Loop Id: 2443 | Module: exec | Source: par_csr_matop.c:263-266 | Coverage: 0.02% |
---|
Loop Id: 2443 | Module: exec | Source: par_csr_matop.c:263-266 | Coverage: 0.02% |
---|
0x543a64 VPADDQ (%RSI,%RAX,1),%YMM9,%YMM11 [2] |
0x543a69 VMOVDQU %YMM11,(%RSI,%RAX,1) [2] |
0x543a6e VPADDQ (%R9,%RAX,1),%YMM10,%YMM12 [1] |
0x543a74 VMOVDQU %YMM12,(%R9,%RAX,1) [1] |
0x543a7a VPADDQ 0x20(%RSI,%RAX,1),%YMM9,%YMM13 [2] |
0x543a80 VMOVDQU %YMM13,0x20(%RSI,%RAX,1) [2] |
0x543a86 VPADDQ 0x20(%R9,%RAX,1),%YMM10,%YMM14 [1] |
0x543a8d VMOVDQU %YMM14,0x20(%R9,%RAX,1) [1] |
0x543a94 VPADDQ 0x40(%RSI,%RAX,1),%YMM9,%YMM15 [2] |
0x543a9a VMOVDQU %YMM15,0x40(%RSI,%RAX,1) [2] |
0x543aa0 VPADDQ 0x40(%R9,%RAX,1),%YMM10,%YMM2 [1] |
0x543aa7 VMOVDQU %YMM2,0x40(%R9,%RAX,1) [1] |
0x543aae VPADDQ 0x60(%RSI,%RAX,1),%YMM9,%YMM0 [2] |
0x543ab4 VMOVDQU %YMM0,0x60(%RSI,%RAX,1) [2] |
0x543aba VPADDQ 0x60(%R9,%RAX,1),%YMM10,%YMM3 [1] |
0x543ac1 VMOVDQU %YMM3,0x60(%R9,%RAX,1) [1] |
0x543ac8 VPADDQ 0x80(%RSI,%RAX,1),%YMM9,%YMM4 [2] |
0x543ad1 VMOVDQU %YMM4,0x80(%RSI,%RAX,1) [2] |
0x543ada VPADDQ 0x80(%R9,%RAX,1),%YMM10,%YMM5 [1] |
0x543ae4 VMOVDQU %YMM5,0x80(%R9,%RAX,1) [1] |
0x543aee VPADDQ 0xa0(%RSI,%RAX,1),%YMM9,%YMM6 [2] |
0x543af7 VMOVDQU %YMM6,0xa0(%RSI,%RAX,1) [2] |
0x543b00 VPADDQ 0xa0(%R9,%RAX,1),%YMM10,%YMM7 [1] |
0x543b0a VMOVDQU %YMM7,0xa0(%R9,%RAX,1) [1] |
0x543b14 VPADDQ 0xc0(%RSI,%RAX,1),%YMM9,%YMM1 [2] |
0x543b1d VMOVDQU %YMM1,0xc0(%RSI,%RAX,1) [2] |
0x543b26 VPADDQ 0xc0(%R9,%RAX,1),%YMM10,%YMM8 [1] |
0x543b30 VMOVDQU %YMM8,0xc0(%R9,%RAX,1) [1] |
0x543b3a VPADDQ 0xe0(%RSI,%RAX,1),%YMM9,%YMM11 [2] |
0x543b43 VMOVDQU %YMM11,0xe0(%RSI,%RAX,1) [2] |
0x543b4c VPADDQ 0xe0(%R9,%RAX,1),%YMM10,%YMM12 [1] |
0x543b56 VMOVDQU %YMM12,0xe0(%R9,%RAX,1) [1] |
0x543b60 ADD $0x100,%RAX |
0x543b66 CMP %RAX,%RDX |
0x543b69 JNE 543a64 |
/scratch_na/users/xoserete/qaas_runs/171-172-8218/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 263 - 266 |
-------------------------------------------------------------------------------- |
263: for (i1 = ns; i1 < ne; i1++) |
264: { |
265: (*C_diag_i)[i1] += jj_count_diag; |
266: (*C_offd_i)[i1] += jj_count_offd; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 2.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.04 |
Bottlenecks | micro-operation queue, |
Function | hypre_ParMatmul_RowSizes._omp_fn.0 |
Source | par_csr_matop.c:263-266 |
Source loop unroll info | unrolled by 4 |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | main |
Unroll factor | 4 |
CQA cycles | 8.33 |
CQA cycles if no scalar integer | 8.33 |
CQA cycles if FP arith vectorized | 8.33 |
CQA cycles if fully vectorized | 4.17 |
Front-end cycles | 8.33 |
DIV/SQRT cycles | 5.50 |
P0 cycles | 5.67 |
P1 cycles | 5.33 |
P2 cycles | 5.33 |
P3 cycles | 8.00 |
P4 cycles | 5.33 |
P5 cycles | 0.70 |
P6 cycles | 8.00 |
P7 cycles | 8.00 |
P8 cycles | 8.00 |
P9 cycles | 0.80 |
P10 cycles | 5.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 8.46 |
Stall cycles (UFS) | 0.00 |
Nb insns | 35.00 |
Nb uops | 34.00 |
Nb loads | 16.00 |
Nb stores | 16.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 122.88 |
Bytes prefetched | 0.00 |
Bytes loaded | 512.00 |
Bytes stored | 512.00 |
Stride 0 | 0.00 |
Stride 1 | 2.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 50.00 |
Vector-efficiency ratio load | 50.00 |
Vector-efficiency ratio store | 50.00 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 50.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | NA |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 2.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.04 |
Bottlenecks | micro-operation queue, |
Function | hypre_ParMatmul_RowSizes._omp_fn.0 |
Source | par_csr_matop.c:263-266 |
Source loop unroll info | unrolled by 4 |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | main |
Unroll factor | 4 |
CQA cycles | 8.33 |
CQA cycles if no scalar integer | 8.33 |
CQA cycles if FP arith vectorized | 8.33 |
CQA cycles if fully vectorized | 4.17 |
Front-end cycles | 8.33 |
DIV/SQRT cycles | 5.50 |
P0 cycles | 5.67 |
P1 cycles | 5.33 |
P2 cycles | 5.33 |
P3 cycles | 8.00 |
P4 cycles | 5.33 |
P5 cycles | 0.70 |
P6 cycles | 8.00 |
P7 cycles | 8.00 |
P8 cycles | 8.00 |
P9 cycles | 0.80 |
P10 cycles | 5.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 8.46 |
Stall cycles (UFS) | 0.00 |
Nb insns | 35.00 |
Nb uops | 34.00 |
Nb loads | 16.00 |
Nb stores | 16.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 122.88 |
Bytes prefetched | 0.00 |
Bytes loaded | 512.00 |
Bytes stored | 512.00 |
Stride 0 | 0.00 |
Stride 1 | 2.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 50.00 |
Vector-efficiency ratio load | 50.00 |
Vector-efficiency ratio store | 50.00 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 50.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | NA |
Path / |
Function | hypre_ParMatmul_RowSizes._omp_fn.0 |
Source file and lines | par_csr_matop.c:263-266 |
Module | exec |
nb instructions | 35 |
nb uops | 34 |
loop length | 267 |
used x86 registers | 4 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 16 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 8.33 cycles |
front end | 8.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.50 | 5.67 | 5.33 | 5.33 | 8.00 | 5.33 | 0.70 | 8.00 | 8.00 | 8.00 | 0.80 | 5.33 |
cycles | 5.50 | 5.67 | 5.33 | 5.33 | 8.00 | 5.33 | 0.70 | 8.00 | 8.00 | 8.00 | 0.80 | 5.33 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 8.46 |
Stall cycles | 0.00 |
Front-end | 8.33 |
Dispatch | 8.00 |
Data deps. | 1.00 |
Overall L1 | 8.33 |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 50% |
load | 50% |
store | 50% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VPADDQ (%RSI,%RAX,1),%YMM9,%YMM11 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VMOVDQU %YMM11,(%RSI,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VPADDQ (%R9,%RAX,1),%YMM10,%YMM12 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VMOVDQU %YMM12,(%R9,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VPADDQ 0x20(%RSI,%RAX,1),%YMM9,%YMM13 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VMOVDQU %YMM13,0x20(%RSI,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VPADDQ 0x20(%R9,%RAX,1),%YMM10,%YMM14 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VMOVDQU %YMM14,0x20(%R9,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VPADDQ 0x40(%RSI,%RAX,1),%YMM9,%YMM15 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VMOVDQU %YMM15,0x40(%RSI,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VPADDQ 0x40(%R9,%RAX,1),%YMM10,%YMM2 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VMOVDQU %YMM2,0x40(%R9,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VPADDQ 0x60(%RSI,%RAX,1),%YMM9,%YMM0 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VMOVDQU %YMM0,0x60(%RSI,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VPADDQ 0x60(%R9,%RAX,1),%YMM10,%YMM3 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VMOVDQU %YMM3,0x60(%R9,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VPADDQ 0x80(%RSI,%RAX,1),%YMM9,%YMM4 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VMOVDQU %YMM4,0x80(%RSI,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VPADDQ 0x80(%R9,%RAX,1),%YMM10,%YMM5 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VMOVDQU %YMM5,0x80(%R9,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VPADDQ 0xa0(%RSI,%RAX,1),%YMM9,%YMM6 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VMOVDQU %YMM6,0xa0(%RSI,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VPADDQ 0xa0(%R9,%RAX,1),%YMM10,%YMM7 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VMOVDQU %YMM7,0xa0(%R9,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VPADDQ 0xc0(%RSI,%RAX,1),%YMM9,%YMM1 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VMOVDQU %YMM1,0xc0(%RSI,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VPADDQ 0xc0(%R9,%RAX,1),%YMM10,%YMM8 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VMOVDQU %YMM8,0xc0(%R9,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VPADDQ 0xe0(%RSI,%RAX,1),%YMM9,%YMM11 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VMOVDQU %YMM11,0xe0(%RSI,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VPADDQ 0xe0(%R9,%RAX,1),%YMM10,%YMM12 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VMOVDQU %YMM12,0xe0(%R9,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
ADD $0x100,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %RAX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 543a64 <hypre_ParMatmul_RowSizes._omp_fn.0+0xc34> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
Function | hypre_ParMatmul_RowSizes._omp_fn.0 |
Source file and lines | par_csr_matop.c:263-266 |
Module | exec |
nb instructions | 35 |
nb uops | 34 |
loop length | 267 |
used x86 registers | 4 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 16 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 8.33 cycles |
front end | 8.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.50 | 5.67 | 5.33 | 5.33 | 8.00 | 5.33 | 0.70 | 8.00 | 8.00 | 8.00 | 0.80 | 5.33 |
cycles | 5.50 | 5.67 | 5.33 | 5.33 | 8.00 | 5.33 | 0.70 | 8.00 | 8.00 | 8.00 | 0.80 | 5.33 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 8.46 |
Stall cycles | 0.00 |
Front-end | 8.33 |
Dispatch | 8.00 |
Data deps. | 1.00 |
Overall L1 | 8.33 |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 50% |
load | 50% |
store | 50% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VPADDQ (%RSI,%RAX,1),%YMM9,%YMM11 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VMOVDQU %YMM11,(%RSI,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VPADDQ (%R9,%RAX,1),%YMM10,%YMM12 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VMOVDQU %YMM12,(%R9,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VPADDQ 0x20(%RSI,%RAX,1),%YMM9,%YMM13 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VMOVDQU %YMM13,0x20(%RSI,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VPADDQ 0x20(%R9,%RAX,1),%YMM10,%YMM14 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VMOVDQU %YMM14,0x20(%R9,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VPADDQ 0x40(%RSI,%RAX,1),%YMM9,%YMM15 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VMOVDQU %YMM15,0x40(%RSI,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VPADDQ 0x40(%R9,%RAX,1),%YMM10,%YMM2 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VMOVDQU %YMM2,0x40(%R9,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VPADDQ 0x60(%RSI,%RAX,1),%YMM9,%YMM0 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VMOVDQU %YMM0,0x60(%RSI,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VPADDQ 0x60(%R9,%RAX,1),%YMM10,%YMM3 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VMOVDQU %YMM3,0x60(%R9,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VPADDQ 0x80(%RSI,%RAX,1),%YMM9,%YMM4 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VMOVDQU %YMM4,0x80(%RSI,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VPADDQ 0x80(%R9,%RAX,1),%YMM10,%YMM5 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VMOVDQU %YMM5,0x80(%R9,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VPADDQ 0xa0(%RSI,%RAX,1),%YMM9,%YMM6 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VMOVDQU %YMM6,0xa0(%RSI,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VPADDQ 0xa0(%R9,%RAX,1),%YMM10,%YMM7 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VMOVDQU %YMM7,0xa0(%R9,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VPADDQ 0xc0(%RSI,%RAX,1),%YMM9,%YMM1 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VMOVDQU %YMM1,0xc0(%RSI,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VPADDQ 0xc0(%R9,%RAX,1),%YMM10,%YMM8 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VMOVDQU %YMM8,0xc0(%R9,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VPADDQ 0xe0(%RSI,%RAX,1),%YMM9,%YMM11 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VMOVDQU %YMM11,0xe0(%RSI,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VPADDQ 0xe0(%R9,%RAX,1),%YMM10,%YMM12 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VMOVDQU %YMM12,0xe0(%R9,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
ADD $0x100,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %RAX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 543a64 <hypre_ParMatmul_RowSizes._omp_fn.0+0xc34> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |