Loop Id: 3004 | Module: exec | Source: csr_matrix.c:145-148 | Coverage: 0.01% |
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Loop Id: 3004 | Module: exec | Source: csr_matrix.c:145-148 | Coverage: 0.01% |
---|
0x57f83f VMOVDQU 0x8(%RAX),%YMM9 [1] |
0x57f844 VMOVDQU 0x28(%RAX),%YMM13 [1] |
0x57f849 ADD $0x100,%RAX |
0x57f84f VMOVDQU -0xb8(%RAX),%YMM2 [2] |
0x57f857 VMOVDQU -0x98(%RAX),%YMM7 [2] |
0x57f85f VPSUBQ -0x100(%RAX),%YMM9,%YMM10 [2] |
0x57f867 VPSUBQ -0xe0(%RAX),%YMM13,%YMM14 [2] |
0x57f86f VPSUBQ -0xc0(%RAX),%YMM2,%YMM4 [2] |
0x57f877 VPSUBQ -0xa0(%RAX),%YMM7,%YMM8 [2] |
0x57f87f VPCMPGTQ %YMM1,%YMM10,%YMM11 |
0x57f884 VPCMPGTQ %YMM1,%YMM14,%YMM15 |
0x57f889 VMOVDQU -0x78(%RAX),%YMM10 [2] |
0x57f88e VMOVDQU -0x58(%RAX),%YMM14 [2] |
0x57f893 VPCMPGTQ %YMM1,%YMM4,%YMM5 |
0x57f898 VMOVDQU -0x38(%RAX),%YMM2 [2] |
0x57f89d VPSUBQ %YMM11,%YMM0,%YMM12 |
0x57f8a2 VPCMPGTQ %YMM1,%YMM8,%YMM0 |
0x57f8a7 VPSUBQ -0x80(%RAX),%YMM10,%YMM11 [2] |
0x57f8ac VMOVDQU -0x18(%RAX),%YMM8 [2] |
0x57f8b1 VPSUBQ %YMM15,%YMM12,%YMM3 |
0x57f8b6 VPSUBQ -0x60(%RAX),%YMM14,%YMM15 [2] |
0x57f8bb VPSUBQ %YMM5,%YMM3,%YMM6 |
0x57f8bf VPSUBQ -0x40(%RAX),%YMM2,%YMM4 [2] |
0x57f8c4 VPCMPGTQ %YMM1,%YMM11,%YMM12 |
0x57f8c9 VPSUBQ %YMM0,%YMM6,%YMM9 |
0x57f8cd VPCMPGTQ %YMM1,%YMM15,%YMM3 |
0x57f8d2 VPSUBQ -0x20(%RAX),%YMM8,%YMM0 [2] |
0x57f8d7 VPCMPGTQ %YMM1,%YMM4,%YMM6 |
0x57f8dc VPSUBQ %YMM12,%YMM9,%YMM13 |
0x57f8e1 VPCMPGTQ %YMM1,%YMM0,%YMM9 |
0x57f8e6 VPSUBQ %YMM3,%YMM13,%YMM5 |
0x57f8ea VPSUBQ %YMM6,%YMM5,%YMM7 |
0x57f8ee VPSUBQ %YMM9,%YMM7,%YMM0 |
0x57f8f3 CMP %RAX,%RSI |
0x57f8f6 JNE 57f83f |
/scratch_na/users/xoserete/qaas_runs/171-172-8218/intel/AMG/build/AMG/AMG/seq_mv/csr_matrix.c: 145 - 148 |
-------------------------------------------------------------------------------- |
145: for (i=0; i < num_rows; i++) |
146: { |
147: adiag = (A_i[i+1] - A_i[i]); |
148: if(adiag > 0) irownnz++; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 2.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.02 |
Bottlenecks | P1, |
Function | hypre_CSRMatrixSetRownnz |
Source | csr_matrix.c:145-148 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 8.33 |
CQA cycles if no scalar integer | 8.33 |
CQA cycles if FP arith vectorized | 8.33 |
CQA cycles if fully vectorized | 4.17 |
Front-end cycles | 5.67 |
DIV/SQRT cycles | 8.17 |
P0 cycles | 8.33 |
P1 cycles | 5.33 |
P2 cycles | 5.33 |
P3 cycles | 0.00 |
P4 cycles | 8.00 |
P5 cycles | 0.70 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 0.80 |
P10 cycles | 5.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 1 - 8 |
FE+BE cycles (UFS) | 8.14 - 8.17 |
Stall cycles (UFS) | 1.98 - 1.99 |
Nb insns | 35.00 |
Nb uops | 34.00 |
Nb loads | 16.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 61.44 |
Bytes prefetched | 0.00 |
Bytes loaded | 512.00 |
Bytes stored | 0.00 |
Stride 0 | 0.00 |
Stride 1 | 0.00 |
Stride n | 1.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 100.00 |
Vector-efficiency ratio all | 50.00 |
Vector-efficiency ratio load | 50.00 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 50.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 50.00 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 2.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.02 |
Bottlenecks | P1, |
Function | hypre_CSRMatrixSetRownnz |
Source | csr_matrix.c:145-148 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 8.33 |
CQA cycles if no scalar integer | 8.33 |
CQA cycles if FP arith vectorized | 8.33 |
CQA cycles if fully vectorized | 4.17 |
Front-end cycles | 5.67 |
DIV/SQRT cycles | 8.17 |
P0 cycles | 8.33 |
P1 cycles | 5.33 |
P2 cycles | 5.33 |
P3 cycles | 0.00 |
P4 cycles | 8.00 |
P5 cycles | 0.70 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 0.80 |
P10 cycles | 5.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 1 - 8 |
FE+BE cycles (UFS) | 8.14 - 8.17 |
Stall cycles (UFS) | 1.98 - 1.99 |
Nb insns | 35.00 |
Nb uops | 34.00 |
Nb loads | 16.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 61.44 |
Bytes prefetched | 0.00 |
Bytes loaded | 512.00 |
Bytes stored | 0.00 |
Stride 0 | 0.00 |
Stride 1 | 0.00 |
Stride n | 1.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 100.00 |
Vector-efficiency ratio all | 50.00 |
Vector-efficiency ratio load | 50.00 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 50.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 50.00 |
Path / |
Function | hypre_CSRMatrixSetRownnz |
Source file and lines | csr_matrix.c:145-148 |
Module | exec |
nb instructions | 35 |
nb uops | 34 |
loop length | 189 |
used x86 registers | 2 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 16 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 5.67 cycles |
front end | 5.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 8.17 | 8.33 | 5.33 | 5.33 | 0.00 | 8.00 | 0.70 | 0.00 | 0.00 | 0.00 | 0.80 | 5.33 |
cycles | 8.17 | 8.33 | 5.33 | 5.33 | 0.00 | 8.00 | 0.70 | 0.00 | 0.00 | 0.00 | 0.80 | 5.33 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00-8.00 |
FE+BE cycles | 8.14-8.17 |
Stall cycles | 1.98-1.99 |
RS full (events) | 6.78-6.82 |
Front-end | 5.67 |
Dispatch | 8.33 |
Data deps. | 1.00-8.00 |
Overall L1 | 8.33 |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 50% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 50% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVDQU 0x8(%RAX),%YMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVDQU 0x28(%RAX),%YMM13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
ADD $0x100,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVDQU -0xb8(%RAX),%YMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVDQU -0x98(%RAX),%YMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VPSUBQ -0x100(%RAX),%YMM9,%YMM10 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.40 |
VPSUBQ -0xe0(%RAX),%YMM13,%YMM14 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.40 |
VPSUBQ -0xc0(%RAX),%YMM2,%YMM4 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.40 |
VPSUBQ -0xa0(%RAX),%YMM7,%YMM8 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.40 |
VPCMPGTQ %YMM1,%YMM10,%YMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0-3 | 1 |
VPCMPGTQ %YMM1,%YMM14,%YMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0-3 | 1 |
VMOVDQU -0x78(%RAX),%YMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVDQU -0x58(%RAX),%YMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VPCMPGTQ %YMM1,%YMM4,%YMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0-3 | 1 |
VMOVDQU -0x38(%RAX),%YMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VPSUBQ %YMM11,%YMM0,%YMM12 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VPCMPGTQ %YMM1,%YMM8,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0-3 | 1 |
VPSUBQ -0x80(%RAX),%YMM10,%YMM11 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.40 |
VMOVDQU -0x18(%RAX),%YMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VPSUBQ %YMM15,%YMM12,%YMM3 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VPSUBQ -0x60(%RAX),%YMM14,%YMM15 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.40 |
VPSUBQ %YMM5,%YMM3,%YMM6 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VPSUBQ -0x40(%RAX),%YMM2,%YMM4 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.40 |
VPCMPGTQ %YMM1,%YMM11,%YMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0-3 | 1 |
VPSUBQ %YMM0,%YMM6,%YMM9 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VPCMPGTQ %YMM1,%YMM15,%YMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0-3 | 1 |
VPSUBQ -0x20(%RAX),%YMM8,%YMM0 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.40 |
VPCMPGTQ %YMM1,%YMM4,%YMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0-3 | 1 |
VPSUBQ %YMM12,%YMM9,%YMM13 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VPCMPGTQ %YMM1,%YMM0,%YMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0-3 | 1 |
VPSUBQ %YMM3,%YMM13,%YMM5 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VPSUBQ %YMM6,%YMM5,%YMM7 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VPSUBQ %YMM9,%YMM7,%YMM0 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
CMP %RAX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 57f83f <hypre_CSRMatrixSetRownnz+0x11f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
Function | hypre_CSRMatrixSetRownnz |
Source file and lines | csr_matrix.c:145-148 |
Module | exec |
nb instructions | 35 |
nb uops | 34 |
loop length | 189 |
used x86 registers | 2 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 16 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 5.67 cycles |
front end | 5.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 8.17 | 8.33 | 5.33 | 5.33 | 0.00 | 8.00 | 0.70 | 0.00 | 0.00 | 0.00 | 0.80 | 5.33 |
cycles | 8.17 | 8.33 | 5.33 | 5.33 | 0.00 | 8.00 | 0.70 | 0.00 | 0.00 | 0.00 | 0.80 | 5.33 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00-8.00 |
FE+BE cycles | 8.14-8.17 |
Stall cycles | 1.98-1.99 |
RS full (events) | 6.78-6.82 |
Front-end | 5.67 |
Dispatch | 8.33 |
Data deps. | 1.00-8.00 |
Overall L1 | 8.33 |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 50% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 50% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVDQU 0x8(%RAX),%YMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVDQU 0x28(%RAX),%YMM13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
ADD $0x100,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVDQU -0xb8(%RAX),%YMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVDQU -0x98(%RAX),%YMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VPSUBQ -0x100(%RAX),%YMM9,%YMM10 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.40 |
VPSUBQ -0xe0(%RAX),%YMM13,%YMM14 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.40 |
VPSUBQ -0xc0(%RAX),%YMM2,%YMM4 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.40 |
VPSUBQ -0xa0(%RAX),%YMM7,%YMM8 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.40 |
VPCMPGTQ %YMM1,%YMM10,%YMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0-3 | 1 |
VPCMPGTQ %YMM1,%YMM14,%YMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0-3 | 1 |
VMOVDQU -0x78(%RAX),%YMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVDQU -0x58(%RAX),%YMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VPCMPGTQ %YMM1,%YMM4,%YMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0-3 | 1 |
VMOVDQU -0x38(%RAX),%YMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VPSUBQ %YMM11,%YMM0,%YMM12 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VPCMPGTQ %YMM1,%YMM8,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0-3 | 1 |
VPSUBQ -0x80(%RAX),%YMM10,%YMM11 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.40 |
VMOVDQU -0x18(%RAX),%YMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VPSUBQ %YMM15,%YMM12,%YMM3 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VPSUBQ -0x60(%RAX),%YMM14,%YMM15 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.40 |
VPSUBQ %YMM5,%YMM3,%YMM6 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VPSUBQ -0x40(%RAX),%YMM2,%YMM4 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.40 |
VPCMPGTQ %YMM1,%YMM11,%YMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0-3 | 1 |
VPSUBQ %YMM0,%YMM6,%YMM9 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VPCMPGTQ %YMM1,%YMM15,%YMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0-3 | 1 |
VPSUBQ -0x20(%RAX),%YMM8,%YMM0 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.40 |
VPCMPGTQ %YMM1,%YMM4,%YMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0-3 | 1 |
VPSUBQ %YMM12,%YMM9,%YMM13 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VPCMPGTQ %YMM1,%YMM0,%YMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0-3 | 1 |
VPSUBQ %YMM3,%YMM13,%YMM5 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VPSUBQ %YMM6,%YMM5,%YMM7 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VPSUBQ %YMM9,%YMM7,%YMM0 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
CMP %RAX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 57f83f <hypre_CSRMatrixSetRownnz+0x11f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |