Loop Id: 2600 | Module: exec | Source: ams.c:3388-3389 | Coverage: 0.13% |
---|
Loop Id: 2600 | Module: exec | Source: ams.c:3388-3389 | Coverage: 0.13% |
---|
0x4b80b0 VMOVSD -0x38(%R8),%XMM1 [1] |
0x4b80b6 VMOVSD -0x30(%R8),%XMM2 [1] |
0x4b80bc VMOVSD -0x28(%R8),%XMM3 [1] |
0x4b80c2 VMOVSD -0x20(%R8),%XMM4 [1] |
0x4b80c8 VANDPD %XMM1,%XMM12,%XMM1 |
0x4b80cc VANDPD %XMM2,%XMM12,%XMM2 |
0x4b80d0 VANDPD %XMM3,%XMM12,%XMM3 |
0x4b80d4 VANDPD %XMM4,%XMM12,%XMM4 |
0x4b80d8 VMOVSD -0x18(%R8),%XMM5 [1] |
0x4b80de VANDPD %XMM5,%XMM12,%XMM5 |
0x4b80e2 VMOVSD -0x10(%R8),%XMM6 [1] |
0x4b80e8 VANDPD %XMM6,%XMM12,%XMM6 |
0x4b80ec VMOVSD -0x8(%R8),%XMM7 [1] |
0x4b80f2 VANDPD %XMM7,%XMM12,%XMM7 |
0x4b80f6 VMOVSD (%R8),%XMM8 [1] |
0x4b80fb VANDPD %XMM12,%XMM8,%XMM8 |
0x4b8100 VADDSD %XMM7,%XMM8,%XMM7 |
0x4b8104 VADDSD %XMM0,%XMM7,%XMM0 |
0x4b8108 VADDSD %XMM5,%XMM4,%XMM4 |
0x4b810c VADDSD %XMM6,%XMM3,%XMM3 |
0x4b8110 VADDSD %XMM4,%XMM3,%XMM3 |
0x4b8114 VADDSD %XMM2,%XMM1,%XMM1 |
0x4b8118 VADDSD %XMM1,%XMM0,%XMM0 |
0x4b811c VADDSD %XMM3,%XMM0,%XMM0 |
0x4b8120 ADD $0x40,%R8 |
0x4b8124 DEC %RDI |
0x4b8127 JNE 4b80b0 |
/scratch_na/users/xoserete/qaas_runs/171-172-8218/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3388 - 3389 |
-------------------------------------------------------------------------------- |
3388: for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++) |
3389: l1_norm[i] += fabs(A_diag_data[j]); |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 2.60 |
CQA speedup if fully vectorized | 8.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.59 |
Bottlenecks | |
Function | hypre_ParCSRComputeL1NormsThreads.extracted |
Source | ams.c:3388-3389 |
Source loop unroll info | unrolled by 8 |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | main |
Unroll factor | 8 |
CQA cycles | 9.00 |
CQA cycles if no scalar integer | 9.00 |
CQA cycles if FP arith vectorized | 3.46 |
CQA cycles if fully vectorized | 1.13 |
Front-end cycles | 4.33 |
DIV/SQRT cycles | 5.50 |
P0 cycles | 5.67 |
P1 cycles | 2.67 |
P2 cycles | 2.67 |
P3 cycles | 0.00 |
P4 cycles | 5.33 |
P5 cycles | 0.50 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 0.00 |
P10 cycles | 2.67 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 9 |
FE+BE cycles (UFS) | 9.16 |
Stall cycles (UFS) | 4.23 |
Nb insns | 27.00 |
Nb uops | 26.00 |
Nb loads | 8.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.89 |
Nb FLOP add-sub | 8.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 7.11 |
Bytes prefetched | 0.00 |
Bytes loaded | 64.00 |
Bytes stored | 0.00 |
Stride 0 | 0.00 |
Stride 1 | 1.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 33.33 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 100.00 |
Vector-efficiency ratio all | 16.67 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 25.00 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 2.60 |
CQA speedup if fully vectorized | 8.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.59 |
Bottlenecks | |
Function | hypre_ParCSRComputeL1NormsThreads.extracted |
Source | ams.c:3388-3389 |
Source loop unroll info | unrolled by 8 |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | main |
Unroll factor | 8 |
CQA cycles | 9.00 |
CQA cycles if no scalar integer | 9.00 |
CQA cycles if FP arith vectorized | 3.46 |
CQA cycles if fully vectorized | 1.13 |
Front-end cycles | 4.33 |
DIV/SQRT cycles | 5.50 |
P0 cycles | 5.67 |
P1 cycles | 2.67 |
P2 cycles | 2.67 |
P3 cycles | 0.00 |
P4 cycles | 5.33 |
P5 cycles | 0.50 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 0.00 |
P10 cycles | 2.67 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 9 |
FE+BE cycles (UFS) | 9.16 |
Stall cycles (UFS) | 4.23 |
Nb insns | 27.00 |
Nb uops | 26.00 |
Nb loads | 8.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.89 |
Nb FLOP add-sub | 8.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 7.11 |
Bytes prefetched | 0.00 |
Bytes loaded | 64.00 |
Bytes stored | 0.00 |
Stride 0 | 0.00 |
Stride 1 | 1.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 33.33 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 100.00 |
Vector-efficiency ratio all | 16.67 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 25.00 |
Path / |
Function | hypre_ParCSRComputeL1NormsThreads.extracted |
Source file and lines | ams.c:3388-3389 |
Module | exec |
nb instructions | 27 |
nb uops | 26 |
loop length | 121 |
used x86 registers | 2 |
used mmx registers | 0 |
used xmm registers | 10 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 4.33 cycles |
front end | 4.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.50 | 5.67 | 2.67 | 2.67 | 0.00 | 5.33 | 0.50 | 0.00 | 0.00 | 0.00 | 0.00 | 2.67 |
cycles | 5.50 | 5.67 | 2.67 | 2.67 | 0.00 | 5.33 | 0.50 | 0.00 | 0.00 | 0.00 | 0.00 | 2.67 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 9.00 |
FE+BE cycles | 9.16 |
Stall cycles | 4.23 |
PRF_FLOAT full (events) | 4.54 |
Front-end | 4.33 |
Dispatch | 5.67 |
Data deps. | 9.00 |
Overall L1 | 9.00 |
all | 33% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 16% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVSD -0x38(%R8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x30(%R8),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x28(%R8),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x20(%R8),%XMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VANDPD %XMM1,%XMM12,%XMM1 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VANDPD %XMM2,%XMM12,%XMM2 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VANDPD %XMM3,%XMM12,%XMM3 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VANDPD %XMM4,%XMM12,%XMM4 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VMOVSD -0x18(%R8),%XMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VANDPD %XMM5,%XMM12,%XMM5 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VMOVSD -0x10(%R8),%XMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VANDPD %XMM6,%XMM12,%XMM6 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VMOVSD -0x8(%R8),%XMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VANDPD %XMM7,%XMM12,%XMM7 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VMOVSD (%R8),%XMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VANDPD %XMM12,%XMM8,%XMM8 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VADDSD %XMM7,%XMM8,%XMM7 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDSD %XMM0,%XMM7,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDSD %XMM5,%XMM4,%XMM4 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDSD %XMM6,%XMM3,%XMM3 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDSD %XMM4,%XMM3,%XMM3 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDSD %XMM2,%XMM1,%XMM1 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDSD %XMM1,%XMM0,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDSD %XMM3,%XMM0,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
ADD $0x40,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
DEC %RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JNE 4b80b0 <hypre_ParCSRComputeL1NormsThreads.extracted+0x1b30> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
Function | hypre_ParCSRComputeL1NormsThreads.extracted |
Source file and lines | ams.c:3388-3389 |
Module | exec |
nb instructions | 27 |
nb uops | 26 |
loop length | 121 |
used x86 registers | 2 |
used mmx registers | 0 |
used xmm registers | 10 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 4.33 cycles |
front end | 4.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.50 | 5.67 | 2.67 | 2.67 | 0.00 | 5.33 | 0.50 | 0.00 | 0.00 | 0.00 | 0.00 | 2.67 |
cycles | 5.50 | 5.67 | 2.67 | 2.67 | 0.00 | 5.33 | 0.50 | 0.00 | 0.00 | 0.00 | 0.00 | 2.67 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 9.00 |
FE+BE cycles | 9.16 |
Stall cycles | 4.23 |
PRF_FLOAT full (events) | 4.54 |
Front-end | 4.33 |
Dispatch | 5.67 |
Data deps. | 9.00 |
Overall L1 | 9.00 |
all | 33% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 16% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVSD -0x38(%R8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x30(%R8),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x28(%R8),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x20(%R8),%XMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VANDPD %XMM1,%XMM12,%XMM1 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VANDPD %XMM2,%XMM12,%XMM2 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VANDPD %XMM3,%XMM12,%XMM3 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VANDPD %XMM4,%XMM12,%XMM4 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VMOVSD -0x18(%R8),%XMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VANDPD %XMM5,%XMM12,%XMM5 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VMOVSD -0x10(%R8),%XMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VANDPD %XMM6,%XMM12,%XMM6 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VMOVSD -0x8(%R8),%XMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VANDPD %XMM7,%XMM12,%XMM7 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VMOVSD (%R8),%XMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VANDPD %XMM12,%XMM8,%XMM8 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VADDSD %XMM7,%XMM8,%XMM7 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDSD %XMM0,%XMM7,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDSD %XMM5,%XMM4,%XMM4 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDSD %XMM6,%XMM3,%XMM3 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDSD %XMM4,%XMM3,%XMM3 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDSD %XMM2,%XMM1,%XMM1 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDSD %XMM1,%XMM0,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDSD %XMM3,%XMM0,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
ADD $0x40,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
DEC %RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JNE 4b80b0 <hypre_ParCSRComputeL1NormsThreads.extracted+0x1b30> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |