Loop Id: 3550 | Module: exec | Source: csr_matvec.c:178-196 [...] | Coverage: 0.01% |
---|
Loop Id: 3550 | Module: exec | Source: csr_matvec.c:178-196 [...] | Coverage: 0.01% |
---|
0x4ef095 MOV -0x60(%RBP),%RAX |
0x4ef099 VADDSD (%RAX,%RSI,8),%XMM0,%XMM0 |
0x4ef09e VMOVSD %XMM0,(%RAX,%RSI,8) |
0x4ef0a3 CMP -0x40(%RBP),%RDX |
0x4ef0a7 LEA 0x1(%RDX),%RDX |
0x4ef0ab JE 4eeff1 |
0x4ef0b1 MOV -0x48(%RBP),%RAX |
0x4ef0b5 ADD %RDX,%RAX |
0x4ef0b8 MOV -0x58(%RBP),%RCX |
0x4ef0bc MOV (%RCX,%RAX,8),%RSI |
0x4ef0c0 MOV -0x50(%RBP),%RAX |
0x4ef0c4 MOV (%RAX,%RSI,8),%RDI |
0x4ef0c8 MOV 0x8(%RAX,%RSI,8),%RAX |
0x4ef0cd VXORPD %XMM0,%XMM0,%XMM0 |
0x4ef0d1 SUB %RDI,%RAX |
0x4ef0d4 JLE 4ef095 |
0x4ef0d6 CMP $0x8,%RAX |
0x4ef0da JB 4ef18b |
0x4ef0e0 MOV %RAX,%R8 |
0x4ef0e3 SHR $0x3,%R8 |
0x4ef0e7 LEA 0x38(,%RDI,8),%RCX |
0x4ef0ef NOP |
(3551) 0x4ef0f0 MOV -0x38(%R14,%RCX,1),%R9 |
(3551) 0x4ef0f5 MOV -0x30(%R14,%RCX,1),%R10 |
(3551) 0x4ef0fa VMOVSD (%RBX,%R9,8),%XMM1 |
(3551) 0x4ef100 VFMADD132SD -0x38(%R12,%RCX,1),%XMM0,%XMM1 |
(3551) 0x4ef107 VMOVSD (%RBX,%R10,8),%XMM0 |
(3551) 0x4ef10d VFMADD132SD -0x30(%R12,%RCX,1),%XMM1,%XMM0 |
(3551) 0x4ef114 MOV -0x28(%R14,%RCX,1),%R9 |
(3551) 0x4ef119 VMOVSD (%RBX,%R9,8),%XMM1 |
(3551) 0x4ef11f VFMADD132SD -0x28(%R12,%RCX,1),%XMM0,%XMM1 |
(3551) 0x4ef126 MOV -0x20(%R14,%RCX,1),%R9 |
(3551) 0x4ef12b VMOVSD (%RBX,%R9,8),%XMM0 |
(3551) 0x4ef131 VFMADD132SD -0x20(%R12,%RCX,1),%XMM1,%XMM0 |
(3551) 0x4ef138 MOV -0x18(%R14,%RCX,1),%R9 |
(3551) 0x4ef13d VMOVSD (%RBX,%R9,8),%XMM1 |
(3551) 0x4ef143 VFMADD132SD -0x18(%R12,%RCX,1),%XMM0,%XMM1 |
(3551) 0x4ef14a MOV -0x10(%R14,%RCX,1),%R9 |
(3551) 0x4ef14f VMOVSD (%RBX,%R9,8),%XMM0 |
(3551) 0x4ef155 VFMADD132SD -0x10(%R12,%RCX,1),%XMM1,%XMM0 |
(3551) 0x4ef15c MOV -0x8(%R14,%RCX,1),%R9 |
(3551) 0x4ef161 VMOVSD (%RBX,%R9,8),%XMM1 |
(3551) 0x4ef167 VFMADD132SD -0x8(%R12,%RCX,1),%XMM0,%XMM1 |
(3551) 0x4ef16e MOV (%R14,%RCX,1),%R9 |
(3551) 0x4ef172 VMOVSD (%RBX,%R9,8),%XMM0 |
(3551) 0x4ef178 VFMADD132SD (%R12,%RCX,1),%XMM1,%XMM0 |
(3551) 0x4ef17e ADD $0x40,%RCX |
(3551) 0x4ef182 DEC %R8 |
(3551) 0x4ef185 JNE 4ef0f0 |
0x4ef18b MOV %EAX,%ECX |
0x4ef18d AND $0x7,%ECX |
0x4ef190 DEC %RCX |
0x4ef193 CMP $0x6,%RCX |
0x4ef197 JA 4ef095 |
/scratch_na/users/xoserete/qaas_runs/171-172-8218/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 178 - 196 |
-------------------------------------------------------------------------------- |
178: #pragma omp parallel for private(i,j,jj,m,tempx) HYPRE_SMP_SCHEDULE |
179: #endif |
180: |
181: for (i = 0; i < num_rownnz; i++) |
182: { |
183: m = A_rownnz[i]; |
[...] |
194: for (jj = A_i[m]; jj < A_i[m+1]; jj++) |
195: tempx += A_data[jj] * x_data[A_j[jj]]; |
196: y_data[m] += tempx; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 2.25 |
CQA speedup if FP arith vectorized | 3.69 |
CQA speedup if fully vectorized | 8.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.50 |
Bottlenecks | micro-operation queue, |
Function | hypre_CSRMatrixMatvecOutOfPlace.extracted.19 |
Source | csr_matvec.c:178-178,csr_matvec.c:181-183,csr_matvec.c:194-196 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 4.50 |
CQA cycles if no scalar integer | 2.00 |
CQA cycles if FP arith vectorized | 1.22 |
CQA cycles if fully vectorized | 0.56 |
Front-end cycles | 4.50 |
DIV/SQRT cycles | 2.50 |
P0 cycles | 2.10 |
P1 cycles | 3.00 |
P2 cycles | 3.00 |
P3 cycles | 0.50 |
P4 cycles | 1.90 |
P5 cycles | 2.50 |
P6 cycles | 0.50 |
P7 cycles | 0.50 |
P8 cycles | 0.50 |
P9 cycles | 2.00 |
P10 cycles | 3.00 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 4.74 |
Stall cycles (UFS) | 0.00 |
Nb insns | 27.00 |
Nb uops | 26.00 |
Nb loads | 9.00 |
Nb stores | 1.00 |
Nb stack references | 5.00 |
FLOP/cycle | 0.22 |
Nb FLOP add-sub | 1.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 17.78 |
Bytes prefetched | 0.00 |
Bytes loaded | 72.00 |
Bytes stored | 8.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 14.29 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 20.00 |
Vector-efficiency ratio all | 14.29 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 15.00 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 2.25 |
CQA speedup if FP arith vectorized | 3.69 |
CQA speedup if fully vectorized | 8.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.50 |
Bottlenecks | micro-operation queue, |
Function | hypre_CSRMatrixMatvecOutOfPlace.extracted.19 |
Source | csr_matvec.c:178-178,csr_matvec.c:181-183,csr_matvec.c:194-196 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 4.50 |
CQA cycles if no scalar integer | 2.00 |
CQA cycles if FP arith vectorized | 1.22 |
CQA cycles if fully vectorized | 0.56 |
Front-end cycles | 4.50 |
DIV/SQRT cycles | 2.50 |
P0 cycles | 2.10 |
P1 cycles | 3.00 |
P2 cycles | 3.00 |
P3 cycles | 0.50 |
P4 cycles | 1.90 |
P5 cycles | 2.50 |
P6 cycles | 0.50 |
P7 cycles | 0.50 |
P8 cycles | 0.50 |
P9 cycles | 2.00 |
P10 cycles | 3.00 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 4.74 |
Stall cycles (UFS) | 0.00 |
Nb insns | 27.00 |
Nb uops | 26.00 |
Nb loads | 9.00 |
Nb stores | 1.00 |
Nb stack references | 5.00 |
FLOP/cycle | 0.22 |
Nb FLOP add-sub | 1.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 17.78 |
Bytes prefetched | 0.00 |
Bytes loaded | 72.00 |
Bytes stored | 8.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 14.29 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 20.00 |
Vector-efficiency ratio all | 14.29 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 15.00 |
Path / |
Function | hypre_CSRMatrixMatvecOutOfPlace.extracted.19 |
Source file and lines | csr_matvec.c:178-196 |
Module | exec |
nb instructions | 27 |
nb uops | 26 |
loop length | 109 |
used x86 registers | 7 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 5 |
micro-operation queue | 4.50 cycles |
front end | 4.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.50 | 2.10 | 3.00 | 3.00 | 0.50 | 1.90 | 2.50 | 0.50 | 0.50 | 0.50 | 2.00 | 3.00 |
cycles | 2.50 | 2.10 | 3.00 | 3.00 | 0.50 | 1.90 | 2.50 | 0.50 | 0.50 | 0.50 | 2.00 | 3.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 4.74 |
Stall cycles | 0.00 |
Front-end | 4.50 |
Dispatch | 3.00 |
Overall L1 | 4.50 |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 33% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 14% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 20% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 16% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 14% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 15% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV -0x60(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VADDSD (%RAX,%RSI,8),%XMM0,%XMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VMOVSD %XMM0,(%RAX,%RSI,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP -0x40(%RBP),%RDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
LEA 0x1(%RDX),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JE 4eeff1 <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0xb1> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x48(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RDX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x58(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RCX,%RAX,8),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x50(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX,%RSI,8),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RAX,%RSI,8),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %RDI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 4ef095 <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0x155> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x8,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 4ef18b <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0x24b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RAX,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SHR $0x3,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA 0x38(,%RDI,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $0x7,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
DEC %RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP $0x6,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JA 4ef095 <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0x155> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
Function | hypre_CSRMatrixMatvecOutOfPlace.extracted.19 |
Source file and lines | csr_matvec.c:178-196 |
Module | exec |
nb instructions | 27 |
nb uops | 26 |
loop length | 109 |
used x86 registers | 7 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 5 |
micro-operation queue | 4.50 cycles |
front end | 4.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.50 | 2.10 | 3.00 | 3.00 | 0.50 | 1.90 | 2.50 | 0.50 | 0.50 | 0.50 | 2.00 | 3.00 |
cycles | 2.50 | 2.10 | 3.00 | 3.00 | 0.50 | 1.90 | 2.50 | 0.50 | 0.50 | 0.50 | 2.00 | 3.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 4.74 |
Stall cycles | 0.00 |
Front-end | 4.50 |
Dispatch | 3.00 |
Overall L1 | 4.50 |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 33% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 14% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 20% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 16% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 14% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 15% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV -0x60(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VADDSD (%RAX,%RSI,8),%XMM0,%XMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VMOVSD %XMM0,(%RAX,%RSI,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP -0x40(%RBP),%RDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
LEA 0x1(%RDX),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JE 4eeff1 <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0xb1> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x48(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RDX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x58(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RCX,%RAX,8),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x50(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX,%RSI,8),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RAX,%RSI,8),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %RDI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 4ef095 <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0x155> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x8,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 4ef18b <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0x24b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RAX,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SHR $0x3,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA 0x38(,%RDI,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $0x7,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
DEC %RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP $0x6,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JA 4ef095 <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0x155> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |