Function: hypre_qsort0 | Module: exec | Source: hypre_qsort.c:31-187 [...] | Coverage: 0.01% |
---|
Function: hypre_qsort0 | Module: exec | Source: hypre_qsort.c:31-187 [...] | Coverage: 0.01% |
---|
/scratch_na/users/xoserete/qaas_runs/171-172-8218/intel/AMG/build/AMG/AMG/utilities/hypre_qsort.c: 31 - 187 |
-------------------------------------------------------------------------------- |
31: temp = v[i]; |
32: v[i] = v[j]; |
33: v[j] = temp; |
[...] |
175: if (left >= right) |
176: return; |
177: hypre_swap( v, left, (left+right)/2); |
178: last = left; |
179: for (i = left+1; i <= right; i++) |
180: if (v[i] < v[left]) |
181: { |
182: hypre_swap(v, ++last, i); |
183: } |
184: hypre_swap(v, left, last); |
185: hypre_qsort0(v, left, last-1); |
186: hypre_qsort0(v, last+1, right); |
187: } |
0x4f8630 CMP %RDX,%RSI |
0x4f8633 JGE 4f87da |
0x4f8639 PUSH %RBP |
0x4f863a MOV %RSP,%RBP |
0x4f863d PUSH %R15 |
0x4f863f PUSH %R14 |
0x4f8641 PUSH %R12 |
0x4f8643 PUSH %RBX |
0x4f8644 MOV %RDX,%RBX |
0x4f8647 MOV %RDI,%R14 |
0x4f864a LEA 0x20(%RDI),%R15 |
0x4f864e MOV %RSI,%R12 |
0x4f8651 JMP 4f868c |
0x4f8653 NOPW %CS:(%RAX,%RAX,1) |
(3649) 0x4f8660 MOV (%R14,%RSI,8),%RAX |
(3649) 0x4f8664 MOV (%R14,%R12,8),%RCX |
(3649) 0x4f8668 MOV %RCX,(%R14,%RSI,8) |
(3649) 0x4f866c MOV %RAX,(%R14,%R12,8) |
(3649) 0x4f8670 LEA -0x1(%R12),%RDX |
(3649) 0x4f8675 MOV %R14,%RDI |
(3649) 0x4f8678 CALL 4f8630 <hypre_qsort0> |
(3649) 0x4f867d INC %R12 |
(3649) 0x4f8680 MOV %R12,%RSI |
(3649) 0x4f8683 CMP %RBX,%R12 |
(3649) 0x4f8686 JGE 4f87d2 |
(3649) 0x4f868c LEA (%RSI,%RBX,1),%RAX |
(3649) 0x4f8690 MOV %RAX,%RCX |
(3649) 0x4f8693 SHR $0x3f,%RCX |
(3649) 0x4f8697 ADD %RAX,%RCX |
(3649) 0x4f869a MOV (%R14,%RSI,8),%RAX |
(3649) 0x4f869e AND $-0x2,%RCX |
(3649) 0x4f86a2 MOV (%R14,%RCX,4),%RDX |
(3649) 0x4f86a6 MOV %RDX,(%R14,%RSI,8) |
(3649) 0x4f86aa MOV %RAX,(%R14,%RCX,4) |
(3649) 0x4f86ae LEA 0x1(%RSI),%RAX |
(3649) 0x4f86b2 CMP %RAX,%RBX |
(3649) 0x4f86b5 CMOVG %RBX,%RAX |
(3649) 0x4f86b9 MOV %RAX,%RCX |
(3649) 0x4f86bc SUB %RSI,%RCX |
(3649) 0x4f86bf CMP $0x4,%RCX |
(3649) 0x4f86c3 JAE 4f8710 |
(3649) 0x4f86c5 MOV %RCX,%RDX |
(3649) 0x4f86c8 AND $-0x4,%RDX |
(3649) 0x4f86cc CMP %RCX,%RDX |
(3649) 0x4f86cf JAE 4f8660 |
(3649) 0x4f86d1 ADD %RSI,%RDX |
(3649) 0x4f86d4 JMP 4f86ec |
0x4f86d6 NOPW %CS:(%RAX,%RAX,1) |
(3650) 0x4f86e0 INC %RDX |
(3650) 0x4f86e3 CMP %RDX,%RAX |
(3650) 0x4f86e6 JE 4f8660 |
(3650) 0x4f86ec MOV 0x8(%R14,%RDX,8),%RCX |
(3650) 0x4f86f1 CMP (%R14,%RSI,8),%RCX |
(3650) 0x4f86f5 JGE 4f86e0 |
(3650) 0x4f86f7 MOV 0x8(%R14,%R12,8),%RDI |
(3650) 0x4f86fc MOV %RCX,0x8(%R14,%R12,8) |
(3650) 0x4f8701 INC %R12 |
(3650) 0x4f8704 MOV %RDI,0x8(%R14,%RDX,8) |
(3650) 0x4f8709 JMP 4f86e0 |
0x4f870b NOPL (%RAX,%RAX,1) |
(3649) 0x4f8710 MOV %RCX,%RDX |
(3649) 0x4f8713 SHR $0x2,%RDX |
(3649) 0x4f8717 LEA (%R15,%RSI,8),%RDI |
(3649) 0x4f871b MOV %RSI,%R12 |
(3649) 0x4f871e JMP 4f8729 |
(3651) 0x4f8720 ADD $0x20,%RDI |
(3651) 0x4f8724 DEC %RDX |
(3651) 0x4f8727 JE 4f86c5 |
(3651) 0x4f8729 MOV -0x18(%RDI),%R9 |
(3651) 0x4f872d MOV (%R14,%RSI,8),%R8 |
(3651) 0x4f8731 CMP %R8,%R9 |
(3651) 0x4f8734 JL 4f8760 |
(3651) 0x4f8736 MOV -0x10(%RDI),%R9 |
(3651) 0x4f873a CMP %R8,%R9 |
(3651) 0x4f873d JL 4f877e |
(3651) 0x4f873f MOV -0x8(%RDI),%R9 |
(3651) 0x4f8743 CMP %R8,%R9 |
(3651) 0x4f8746 JL 4f879c |
(3651) 0x4f8748 MOV (%RDI),%R9 |
(3651) 0x4f874b CMP %R8,%R9 |
(3651) 0x4f874e JGE 4f8720 |
(3651) 0x4f8750 JMP 4f87bd |
0x4f8752 NOPW %CS:(%RAX,%RAX,1) |
(3651) 0x4f8760 MOV 0x8(%R14,%R12,8),%R8 |
(3651) 0x4f8765 MOV %R9,0x8(%R14,%R12,8) |
(3651) 0x4f876a INC %R12 |
(3651) 0x4f876d MOV %R8,-0x18(%RDI) |
(3651) 0x4f8771 MOV (%R14,%RSI,8),%R8 |
(3651) 0x4f8775 MOV -0x10(%RDI),%R9 |
(3651) 0x4f8779 CMP %R8,%R9 |
(3651) 0x4f877c JGE 4f873f |
(3651) 0x4f877e MOV 0x8(%R14,%R12,8),%R8 |
(3651) 0x4f8783 MOV %R9,0x8(%R14,%R12,8) |
(3651) 0x4f8788 INC %R12 |
(3651) 0x4f878b MOV %R8,-0x10(%RDI) |
(3651) 0x4f878f MOV (%R14,%RSI,8),%R8 |
(3651) 0x4f8793 MOV -0x8(%RDI),%R9 |
(3651) 0x4f8797 CMP %R8,%R9 |
(3651) 0x4f879a JGE 4f8748 |
(3651) 0x4f879c MOV 0x8(%R14,%R12,8),%R8 |
(3651) 0x4f87a1 MOV %R9,0x8(%R14,%R12,8) |
(3651) 0x4f87a6 INC %R12 |
(3651) 0x4f87a9 MOV %R8,-0x8(%RDI) |
(3651) 0x4f87ad MOV (%R14,%RSI,8),%R8 |
(3651) 0x4f87b1 MOV (%RDI),%R9 |
(3651) 0x4f87b4 CMP %R8,%R9 |
(3651) 0x4f87b7 JGE 4f8720 |
(3651) 0x4f87bd MOV 0x8(%R14,%R12,8),%R8 |
(3651) 0x4f87c2 MOV %R9,0x8(%R14,%R12,8) |
(3651) 0x4f87c7 INC %R12 |
(3651) 0x4f87ca MOV %R8,(%RDI) |
(3651) 0x4f87cd JMP 4f8720 |
0x4f87d2 POP %RBX |
0x4f87d3 POP %R12 |
0x4f87d5 POP %R14 |
0x4f87d7 POP %R15 |
0x4f87d9 POP %RBP |
0x4f87da RET |
0x4f87db NOPL (%RAX,%RAX,1) |
Path / |
Source file and lines | hypre_qsort.c:31-187 |
Module | exec |
nb instructions | 24 |
nb uops | 24 |
loop length | 91 |
used x86 registers | 10 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 4.00 cycles |
front end | 4.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.00 | 0.40 | 2.00 | 2.00 | 2.50 | 0.40 | 1.00 | 2.50 | 2.50 | 2.50 | 0.20 | 2.00 |
cycles | 1.00 | 0.40 | 2.00 | 2.00 | 2.50 | 0.40 | 1.00 | 2.50 | 2.50 | 2.50 | 0.20 | 2.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 4.10-4.12 |
Stall cycles | 0.00 |
Front-end | 4.00 |
Dispatch | 2.50 |
Overall L1 | 4.00 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CMP %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4f87da <hypre_qsort0+0x1aa> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x20(%RDI),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RSI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JMP 4f868c <hypre_qsort0+0x5c> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | hypre_qsort.c:31-187 |
Module | exec |
nb instructions | 24 |
nb uops | 24 |
loop length | 91 |
used x86 registers | 10 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 4.00 cycles |
front end | 4.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.00 | 0.40 | 2.00 | 2.00 | 2.50 | 0.40 | 1.00 | 2.50 | 2.50 | 2.50 | 0.20 | 2.00 |
cycles | 1.00 | 0.40 | 2.00 | 2.00 | 2.50 | 0.40 | 1.00 | 2.50 | 2.50 | 2.50 | 0.20 | 2.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 4.10-4.12 |
Stall cycles | 0.00 |
Front-end | 4.00 |
Dispatch | 2.50 |
Overall L1 | 4.00 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CMP %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4f87da <hypre_qsort0+0x1aa> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x20(%RDI),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RSI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JMP 4f868c <hypre_qsort0+0x5c> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼hypre_qsort0– | 0.01 | 0 |
▼Loop 3649 - hypre_qsort.c:31-186 - exec– | 0 | 0.01 |
○Loop 3650 - hypre_qsort.c:31-182 - exec | 0 | 0 |
○Loop 3651 - hypre_qsort.c:31-182 - exec | 0 | 0.04 |