Function: hypre_BoomerAMGBuildMultipass._omp_fn.10 | Module: exec | Source: par_multi_interp.c:1737-1881 [...] | Coverage: 1.45% |
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Function: hypre_BoomerAMGBuildMultipass._omp_fn.10 | Module: exec | Source: par_multi_interp.c:1737-1881 [...] | Coverage: 1.45% |
---|
/scratch_na/users/xoserete/qaas_runs/171-172-8218/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1737 - 1881 |
-------------------------------------------------------------------------------- |
1737: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa,tmp_array,tmp_array_offd) |
[...] |
1746: tmp_marker = NULL; |
1747: if (n_fine) |
1748: { tmp_marker = hypre_CTAlloc(HYPRE_Int,n_fine); } |
1749: tmp_marker_offd = NULL; |
1750: if (num_cols_offd) |
1751: { tmp_marker_offd = hypre_CTAlloc(HYPRE_Int,num_cols_offd); } |
1752: tmp_array = NULL; |
1753: if (n_coarse) |
1754: { tmp_array = hypre_CTAlloc(HYPRE_Int,n_coarse); } |
1755: tmp_array_offd = NULL; |
1756: if (new_num_cols_offd > n_coarse_offd) |
1757: { tmp_array_offd = hypre_CTAlloc(HYPRE_Int,new_num_cols_offd); } |
1758: else |
1759: { tmp_array_offd = hypre_CTAlloc(HYPRE_Int,n_coarse_offd);} |
1760: for (i=0; i < n_fine; i++) |
1761: { tmp_marker[i] = -1; } |
1762: for (i=0; i < num_cols_offd; i++) |
1763: { tmp_marker_offd[i] = -1; } |
1764: |
1765: /* Compute this thread's range of pass_length */ |
1766: my_thread_num = hypre_GetThreadNum(); |
1767: num_threads = hypre_NumActiveThreads(); |
1768: thread_start = pass_pointer[pass] + (pass_length/num_threads)*my_thread_num; |
1769: if (my_thread_num == num_threads-1) |
1770: { thread_stop = pass_pointer[pass] + pass_length; } |
1771: else |
1772: { thread_stop = pass_pointer[pass] + (pass_length/num_threads)*(my_thread_num+1); } |
1773: |
1774: for (i=thread_start; i < thread_stop; i++) |
1775: { |
1776: i1 = pass_array[i]; |
1777: sum_C = 0; |
1778: sum_N = 0; |
1779: j_start = P_diag_start[i1]; |
1780: j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1]; |
1781: cnt = P_diag_i[i1]; |
1782: for (j=j_start; j < j_end; j++) |
1783: { |
1784: k1 = P_diag_pass[pass][j]; |
1785: tmp_array[k1] = cnt; |
1786: P_diag_data[cnt] = 0; |
1787: P_diag_j[cnt++] = k1; |
1788: } |
1789: j_start = P_offd_start[i1]; |
1790: j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1]; |
1791: cnt_offd = P_offd_i[i1]; |
1792: for (j=j_start; j < j_end; j++) |
1793: { |
1794: k1 = P_offd_pass[pass][j]; |
1795: tmp_array_offd[k1] = cnt_offd; |
1796: P_offd_data[cnt_offd] = 0; |
1797: P_offd_j[cnt_offd++] = k1; |
1798: } |
1799: for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++) |
1800: { |
1801: j1 = S_diag_j[j]; |
1802: if (assigned[j1] == pass-1) |
1803: tmp_marker[j1] = i1; |
1804: } |
1805: for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++) |
1806: { |
1807: j1 = S_offd_j[j]; |
1808: if (assigned_offd[j1] == pass-1) |
1809: tmp_marker_offd[j1] = i1; |
1810: } |
1811: for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++) |
1812: { |
1813: j1 = A_diag_j[j]; |
1814: if (tmp_marker[j1] == i1) |
1815: { |
1816: for (k=P_diag_i[j1]; k < P_diag_i[j1+1]; k++) |
1817: { |
1818: k1 = P_diag_j[k]; |
1819: alfa = A_diag_data[j]*P_diag_data[k]; |
1820: P_diag_data[tmp_array[k1]] += alfa; |
1821: sum_C += alfa; |
1822: sum_N += alfa; |
1823: } |
1824: for (k=P_offd_i[j1]; k < P_offd_i[j1+1]; k++) |
1825: { |
1826: k1 = P_offd_j[k]; |
1827: alfa = A_diag_data[j]*P_offd_data[k]; |
1828: P_offd_data[tmp_array_offd[k1]] += alfa; |
1829: sum_C += alfa; |
1830: sum_N += alfa; |
1831: } |
1832: } |
1833: else |
1834: { |
1835: if (CF_marker[j1] != -3 && |
1836: (num_functions == 1 || dof_func[i1] == dof_func[j1])) |
1837: sum_N += A_diag_data[j]; |
1838: } |
1839: } |
1840: for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++) |
1841: { |
1842: if (col_offd_S_to_A) |
1843: j1 = map_A_to_S[A_offd_j[j]]; |
1844: else |
1845: j1 = A_offd_j[j]; |
1846: |
1847: if (j1 > -1 && tmp_marker_offd[j1] == i1) |
1848: { |
1849: j_start = Pext_start[j1]; |
1850: j_end = j_start+Pext_i[j1+1]; |
1851: for (k=j_start; k < j_end; k++) |
1852: { |
1853: k1 = Pext_pass[pass][k]; |
1854: alfa = A_offd_data[j]*Pext_data[k]; |
1855: if (k1 < 0) |
1856: P_diag_data[tmp_array[-k1-1]] += alfa; |
1857: else |
1858: P_offd_data[tmp_array_offd[k1]] += alfa; |
1859: sum_C += alfa; |
1860: sum_N += alfa; |
1861: } |
1862: } |
1863: else |
1864: { |
1865: if (CF_marker_offd[j1] != -3 && |
1866: (num_functions == 1 || dof_func_offd[j1] == dof_func[i1])) |
1867: sum_N += A_offd_data[j]; |
1868: } |
1869: } |
1870: diagonal = A_diag_data[A_diag_i[i1]]; |
1871: if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal); |
1872: |
1873: for (j=P_diag_i[i1]; j < P_diag_i[i1+1]; j++) |
1874: P_diag_data[j] *= alfa; |
1875: for (j=P_offd_i[i1]; j < P_offd_i[i1+1]; j++) |
1876: P_offd_data[j] *= alfa; |
1877: } |
1878: hypre_TFree(tmp_marker); |
1879: hypre_TFree(tmp_marker_offd); |
1880: hypre_TFree(tmp_array); |
1881: hypre_TFree(tmp_array_offd); |
0x46e620 PUSH %RBP |
0x46e621 MOV %RSP,%RBP |
0x46e624 PUSH %R15 |
0x46e626 PUSH %R14 |
0x46e628 PUSH %R13 |
0x46e62a PUSH %R12 |
0x46e62c PUSH %RBX |
0x46e62d AND $-0x20,%RSP |
0x46e631 SUB $0x160,%RSP |
0x46e638 MOV 0x148(%RDI),%RAX |
0x46e63f MOV 0x138(%RDI),%RDX |
0x46e646 MOV 0x130(%RDI),%RCX |
0x46e64d MOV 0x128(%RDI),%RBX |
0x46e654 MOV 0x108(%RDI),%R9 |
0x46e65b MOV 0x100(%RDI),%R10 |
0x46e662 MOV %RAX,0x148(%RSP) |
0x46e66a MOV 0xf8(%RDI),%R11 |
0x46e671 MOV 0xf0(%RDI),%R12 |
0x46e678 MOV %RDX,0x88(%RSP) |
0x46e680 MOV 0xe8(%RDI),%R13 |
0x46e687 MOV 0xe0(%RDI),%R14 |
0x46e68e MOV %RCX,0x138(%RSP) |
0x46e696 MOV 0x110(%RDI),%RSI |
0x46e69d MOV 0x140(%RDI),%R8 |
0x46e6a4 MOV %RBX,0x130(%RSP) |
0x46e6ac MOV %R9,0xe8(%RSP) |
0x46e6b4 MOV 0x120(%RDI),%RDX |
0x46e6bb MOV %R10,0x100(%RSP) |
0x46e6c3 MOV 0x118(%RDI),%RCX |
0x46e6ca MOV %R11,0x18(%RSP) |
0x46e6cf MOV %R12,0x8(%RSP) |
0x46e6d4 MOV %R13,0x48(%RSP) |
0x46e6d9 MOV %R14,0x40(%RSP) |
0x46e6de MOV %RSI,0x158(%RSP) |
0x46e6e6 MOV 0xd8(%RDI),%R15 |
0x46e6ed MOV 0xd0(%RDI),%RAX |
0x46e6f4 MOV 0xc8(%RDI),%RBX |
0x46e6fb MOV 0xc0(%RDI),%R9 |
0x46e702 MOV 0xb8(%RDI),%R10 |
0x46e709 MOV %R15,0x80(%RSP) |
0x46e711 MOV 0x68(%RDI),%R15 |
0x46e715 MOV 0xb0(%RDI),%R11 |
0x46e71c MOV %RAX,0x78(%RSP) |
0x46e721 MOV 0xa8(%RDI),%R12 |
0x46e728 MOV 0x98(%RDI),%R13 |
0x46e72f MOV %RBX,0xf8(%RSP) |
0x46e737 MOV 0x80(%RDI),%R14 |
0x46e73e MOV 0x60(%RDI),%RAX |
0x46e742 MOV %R9,0xb0(%RSP) |
0x46e74a MOV 0x58(%RDI),%RBX |
0x46e74e MOV 0x50(%RDI),%R9 |
0x46e752 MOV %R15,0x128(%RSP) |
0x46e75a MOV 0x48(%RDI),%R15 |
0x46e75e MOV %R10,0xf0(%RSP) |
0x46e766 MOV %R11,0x38(%RSP) |
0x46e76b MOV 0xa0(%RDI),%R10 |
0x46e772 MOV %R12,0x10(%RSP) |
0x46e777 MOV 0x90(%RDI),%R11 |
0x46e77e MOV %R13,0xd8(%RSP) |
0x46e786 MOV 0x78(%RDI),%R12 |
0x46e78a MOV %R14,0xd0(%RSP) |
0x46e792 MOV 0x88(%RDI),%R13 |
0x46e799 MOV %RAX,0x70(%RSP) |
0x46e79e MOV 0x70(%RDI),%R14 |
0x46e7a2 MOV %RBX,0x120(%RSP) |
0x46e7aa MOV %R9,0x68(%RSP) |
0x46e7af MOV %R15,0x30(%RSP) |
0x46e7b4 MOV 0x40(%RDI),%RAX |
0x46e7b8 MOV 0x38(%RDI),%RBX |
0x46e7bc MOV 0x30(%RDI),%R9 |
0x46e7c0 MOV 0x28(%RDI),%R15 |
0x46e7c4 MOV %RAX,0x60(%RSP) |
0x46e7c9 MOV %RBX,0x28(%RSP) |
0x46e7ce MOV 0x20(%RDI),%RAX |
0x46e7d2 MOV 0x18(%RDI),%RBX |
0x46e7d6 MOV %R9,0x20(%RSP) |
0x46e7db MOV %R15,0x58(%RSP) |
0x46e7e0 MOV 0x10(%RDI),%R9 |
0x46e7e4 MOV 0x8(%RDI),%R15 |
0x46e7e8 MOV (%RDI),%RDI |
0x46e7eb MOV %RAX,0xc8(%RSP) |
0x46e7f3 MOV %RBX,0xa8(%RSP) |
0x46e7fb MOV %R9,0x108(%RSP) |
0x46e803 MOV %R15,0x140(%RSP) |
0x46e80b MOV %RDI,0x110(%RSP) |
0x46e813 TEST %RSI,%RSI |
0x46e816 JNE 46fc9e |
0x46e81c MOVQ $0,0x150(%RSP) |
0x46e828 TEST %R14,%R14 |
0x46e82b JNE 46fc22 |
0x46e831 MOVQ $0,0x118(%RSP) |
0x46e83d TEST %RCX,%RCX |
0x46e840 JNE 46fbbb |
0x46e846 XOR %R15D,%R15D |
0x46e849 CMP %RDX,%R8 |
0x46e84c JLE 46fb95 |
0x46e852 MOV %R11,0xb8(%RSP) |
0x46e85a MOV $0x8,%ESI |
0x46e85f MOV %R8,%RDI |
0x46e862 MOV %R10,0xc0(%RSP) |
0x46e86a VMOVSD %XMM1,0xe0(%RSP) |
0x46e873 CALL 595800 <hypre_CAlloc> |
0x46e878 CMPQ $0,0x158(%RSP) |
0x46e881 VMOVSD 0xe0(%RSP),%XMM1 |
0x46e88a MOV %RAX,%RBX |
0x46e88d MOV 0xc0(%RSP),%RSI |
0x46e895 MOV 0xb8(%RSP),%RAX |
0x46e89d JLE 46e8ef |
0x46e89f MOV 0x158(%RSP),%RDX |
0x46e8a7 MOV 0x150(%RSP),%RDI |
0x46e8af MOV %RSI,0xc0(%RSP) |
0x46e8b7 MOV $0xff,%ESI |
0x46e8bc VMOVSD %XMM1,0xe0(%RSP) |
0x46e8c5 SAL $0x3,%RDX |
0x46e8c9 MOV %RAX,0xb8(%RSP) |
0x46e8d1 CALL 4110a0 <memset@plt> |
0x46e8d6 VMOVSD 0xe0(%RSP),%XMM1 |
0x46e8df MOV 0xc0(%RSP),%RSI |
0x46e8e7 MOV 0xb8(%RSP),%RAX |
0x46e8ef TEST %R14,%R14 |
0x46e8f2 JLE 46e940 |
0x46e8f4 MOV 0x118(%RSP),%RDI |
0x46e8fc MOV %RSI,0xe0(%RSP) |
0x46e904 LEA (,%R14,8),%RDX |
0x46e90c MOV $0xff,%ESI |
0x46e911 VMOVSD %XMM1,0x158(%RSP) |
0x46e91a MOV %RAX,0xc0(%RSP) |
0x46e922 CALL 4110a0 <memset@plt> |
0x46e927 VMOVSD 0x158(%RSP),%XMM1 |
0x46e930 MOV 0xe0(%RSP),%RSI |
0x46e938 MOV 0xc0(%RSP),%RAX |
0x46e940 MOV %RSI,0xc0(%RSP) |
0x46e948 VMOVSD %XMM1,0x158(%RSP) |
0x46e951 MOV %RAX,0xb8(%RSP) |
0x46e959 CALL 598830 <hypre_GetThreadNum> |
0x46e95e MOV %RAX,%R14 |
0x46e961 CALL 598820 <hypre_NumActiveThreads> |
0x46e966 MOV 0xe8(%RSP),%R8 |
0x46e96e MOV 0xf8(%RSP),%RDX |
0x46e976 MOV %R14,%R10 |
0x46e979 MOV %RAX,%R9 |
0x46e97c MOV 0x148(%RSP),%RAX |
0x46e984 MOV 0x148(%RSP),%R11 |
0x46e98c MOV (%RDX,%R8,8),%RCX |
0x46e990 LEA (,%R8,8),%RDI |
0x46e998 VMOVSD 0x158(%RSP),%XMM12 |
0x46e9a1 CQTO |
0x46e9a3 MOV %RDI,0xe0(%RSP) |
0x46e9ab IDIV %R9 |
0x46e9ae ADD %RCX,%R11 |
0x46e9b1 DEC %R9 |
0x46e9b4 MOV %R11,%R8 |
0x46e9b7 MOV 0xb8(%RSP),%R11 |
0x46e9bf IMUL %RAX,%R10 |
0x46e9c3 ADD %R10,%RAX |
0x46e9c6 LEA (%RCX,%R10,1),%RSI |
0x46e9ca MOV 0xc0(%RSP),%R10 |
0x46e9d2 ADD %RCX,%RAX |
0x46e9d5 CMP %R9,%R14 |
0x46e9d8 CMOVNE %RAX,%R8 |
0x46e9dc CMP %RSI,%R8 |
0x46e9df JLE 46f82e |
0x46e9e5 MOV 0xb0(%RSP),%R14 |
0x46e9ed VMOVQ 0x13034b(%RIP),%XMM4 |
0x46e9f5 VXORPD %XMM3,%XMM3,%XMM3 |
0x46e9f9 LEA (%R14,%R8,8),%RDI |
0x46e9fd LEA (%R14,%RSI,8),%R9 |
0x46ea01 MOV 0xe8(%RSP),%R14 |
0x46ea09 MOV %RDI,0x50(%RSP) |
0x46ea0e MOV %R9,0xf8(%RSP) |
0x46ea16 MOV %R15,%R9 |
0x46ea19 MOV 0xa8(%RSP),%R15 |
0x46ea21 DEC %R14 |
0x46ea24 NOPL (%RAX) |
(648) 0x46ea28 MOV 0xf8(%RSP),%RCX |
(648) 0x46ea30 MOV 0xd0(%RSP),%R8 |
(648) 0x46ea38 MOV 0x78(%RSP),%RDX |
(648) 0x46ea3d MOV (%RCX),%RDI |
(648) 0x46ea40 LEA (,%RDI,8),%RAX |
(648) 0x46ea48 MOV (%RDX,%RDI,8),%RDX |
(648) 0x46ea4c LEA 0x8(%RAX),%RCX |
(648) 0x46ea50 MOV %RAX,0x148(%RSP) |
(648) 0x46ea58 ADD %R8,%RAX |
(648) 0x46ea5b LEA (%R8,%RCX,1),%RSI |
(648) 0x46ea5f MOV %RAX,0xb8(%RSP) |
(648) 0x46ea67 MOV (%RAX),%RAX |
(648) 0x46ea6a MOV (%RSI),%R8 |
(648) 0x46ea6d MOV %RSI,0xc0(%RSP) |
(648) 0x46ea75 ADD %RDX,%R8 |
(648) 0x46ea78 SUB %RAX,%R8 |
(648) 0x46ea7b CMP %R8,%RDX |
(648) 0x46ea7e JGE 46ec83 |
(648) 0x46ea84 MOV %RAX,%RSI |
(648) 0x46ea87 SUB %RDX,%RSI |
(648) 0x46ea8a SUB %RAX,%RDX |
(648) 0x46ea8d MOV %RDX,0x158(%RSP) |
(648) 0x46ea95 ADD %R8,%RSI |
(648) 0x46ea98 MOV 0xe0(%RSP),%RDX |
(648) 0x46eaa0 MOV 0x40(%RSP),%R8 |
(648) 0x46eaa5 MOV (%R8,%RDX,1),%R8 |
(648) 0x46eaa9 MOV 0x158(%RSP),%RDX |
(648) 0x46eab1 LEA (%R8,%RDX,8),%RDX |
(648) 0x46eab5 MOV %RSI,%R8 |
(648) 0x46eab8 SUB %RAX,%R8 |
(648) 0x46eabb AND $0x7,%R8D |
(648) 0x46eabf JE 46eba2 |
(648) 0x46eac5 CMP $0x1,%R8 |
(648) 0x46eac9 JE 46eb81 |
(648) 0x46eacf CMP $0x2,%R8 |
(648) 0x46ead3 JE 46eb69 |
(648) 0x46ead9 CMP $0x3,%R8 |
(648) 0x46eadd JE 46eb51 |
(648) 0x46eadf CMP $0x4,%R8 |
(648) 0x46eae3 JE 46eb39 |
(648) 0x46eae5 CMP $0x5,%R8 |
(648) 0x46eae9 JE 46eb21 |
(648) 0x46eaeb CMP $0x6,%R8 |
(648) 0x46eaef JE 46eb09 |
(648) 0x46eaf1 MOV (%RDX,%RAX,8),%R8 |
(648) 0x46eaf5 MOV %RAX,(%R9,%R8,8) |
(648) 0x46eaf9 MOVQ $0,(%R12,%RAX,8) |
(648) 0x46eb01 INC %RAX |
(648) 0x46eb04 MOV %R8,-0x8(%R13,%RAX,8) |
(648) 0x46eb09 MOV (%RDX,%RAX,8),%R8 |
(648) 0x46eb0d MOV %RAX,(%R9,%R8,8) |
(648) 0x46eb11 MOVQ $0,(%R12,%RAX,8) |
(648) 0x46eb19 INC %RAX |
(648) 0x46eb1c MOV %R8,-0x8(%R13,%RAX,8) |
(648) 0x46eb21 MOV (%RDX,%RAX,8),%R8 |
(648) 0x46eb25 MOV %RAX,(%R9,%R8,8) |
(648) 0x46eb29 MOVQ $0,(%R12,%RAX,8) |
(648) 0x46eb31 INC %RAX |
(648) 0x46eb34 MOV %R8,-0x8(%R13,%RAX,8) |
(648) 0x46eb39 MOV (%RDX,%RAX,8),%R8 |
(648) 0x46eb3d MOV %RAX,(%R9,%R8,8) |
(648) 0x46eb41 MOVQ $0,(%R12,%RAX,8) |
(648) 0x46eb49 INC %RAX |
(648) 0x46eb4c MOV %R8,-0x8(%R13,%RAX,8) |
(648) 0x46eb51 MOV (%RDX,%RAX,8),%R8 |
(648) 0x46eb55 MOV %RAX,(%R9,%R8,8) |
(648) 0x46eb59 MOVQ $0,(%R12,%RAX,8) |
(648) 0x46eb61 INC %RAX |
(648) 0x46eb64 MOV %R8,-0x8(%R13,%RAX,8) |
(648) 0x46eb69 MOV (%RDX,%RAX,8),%R8 |
(648) 0x46eb6d MOV %RAX,(%R9,%R8,8) |
(648) 0x46eb71 MOVQ $0,(%R12,%RAX,8) |
(648) 0x46eb79 INC %RAX |
(648) 0x46eb7c MOV %R8,-0x8(%R13,%RAX,8) |
(648) 0x46eb81 MOV (%RDX,%RAX,8),%R8 |
(648) 0x46eb85 MOV %RAX,(%R9,%R8,8) |
(648) 0x46eb89 MOVQ $0,(%R12,%RAX,8) |
(648) 0x46eb91 INC %RAX |
(648) 0x46eb94 MOV %R8,-0x8(%R13,%RAX,8) |
(648) 0x46eb99 CMP %RSI,%RAX |
(648) 0x46eb9c JE 46ec83 |
(648) 0x46eba2 MOV %RBX,0x158(%RSP) |
(659) 0x46ebaa MOV (%RDX,%RAX,8),%RBX |
(659) 0x46ebae LEA 0x1(%RAX),%R8 |
(659) 0x46ebb2 MOV %RAX,(%R9,%RBX,8) |
(659) 0x46ebb6 MOVQ $0,(%R12,%RAX,8) |
(659) 0x46ebbe MOV %RBX,-0x8(%R13,%R8,8) |
(659) 0x46ebc3 MOV (%RDX,%R8,8),%RBX |
(659) 0x46ebc7 MOV %R8,(%R9,%RBX,8) |
(659) 0x46ebcb MOVQ $0,(%R12,%R8,8) |
(659) 0x46ebd3 LEA 0x2(%RAX),%R8 |
(659) 0x46ebd7 MOV %RBX,-0x8(%R13,%R8,8) |
(659) 0x46ebdc MOV (%RDX,%R8,8),%RBX |
(659) 0x46ebe0 MOV %R8,(%R9,%RBX,8) |
(659) 0x46ebe4 MOVQ $0,(%R12,%R8,8) |
(659) 0x46ebec LEA 0x3(%RAX),%R8 |
(659) 0x46ebf0 MOV %RBX,-0x8(%R13,%R8,8) |
(659) 0x46ebf5 MOV (%RDX,%R8,8),%RBX |
(659) 0x46ebf9 MOV %R8,(%R9,%RBX,8) |
(659) 0x46ebfd MOVQ $0,(%R12,%R8,8) |
(659) 0x46ec05 LEA 0x4(%RAX),%R8 |
(659) 0x46ec09 MOV %RBX,-0x8(%R13,%R8,8) |
(659) 0x46ec0e MOV (%RDX,%R8,8),%RBX |
(659) 0x46ec12 MOV %R8,(%R9,%RBX,8) |
(659) 0x46ec16 MOVQ $0,(%R12,%R8,8) |
(659) 0x46ec1e LEA 0x5(%RAX),%R8 |
(659) 0x46ec22 MOV %RBX,-0x8(%R13,%R8,8) |
(659) 0x46ec27 MOV (%RDX,%R8,8),%RBX |
(659) 0x46ec2b MOV %R8,(%R9,%RBX,8) |
(659) 0x46ec2f MOVQ $0,(%R12,%R8,8) |
(659) 0x46ec37 LEA 0x6(%RAX),%R8 |
(659) 0x46ec3b MOV %RBX,-0x8(%R13,%R8,8) |
(659) 0x46ec40 MOV (%RDX,%R8,8),%RBX |
(659) 0x46ec44 MOV %R8,(%R9,%RBX,8) |
(659) 0x46ec48 MOVQ $0,(%R12,%R8,8) |
(659) 0x46ec50 LEA 0x7(%RAX),%R8 |
(659) 0x46ec54 ADD $0x8,%RAX |
(659) 0x46ec58 MOV %RBX,-0x8(%R13,%R8,8) |
(659) 0x46ec5d MOV (%RDX,%R8,8),%RBX |
(659) 0x46ec61 MOV %R8,(%R9,%RBX,8) |
(659) 0x46ec65 MOVQ $0,(%R12,%R8,8) |
(659) 0x46ec6d MOV %RBX,-0x8(%R13,%RAX,8) |
(659) 0x46ec72 CMP %RSI,%RAX |
(659) 0x46ec75 JNE 46ebaa |
(648) 0x46ec7b MOV 0x158(%RSP),%RBX |
(648) 0x46ec83 MOV 0x80(%RSP),%RAX |
(648) 0x46ec8b MOV 0x148(%RSP),%R8 |
(648) 0x46ec93 MOV (%RAX,%RDI,8),%RDX |
(648) 0x46ec97 MOV 0xd8(%RSP),%RAX |
(648) 0x46ec9f LEA (%RAX,%RCX,1),%RSI |
(648) 0x46eca3 ADD %R8,%RAX |
(648) 0x46eca6 MOV (%RSI),%R8 |
(648) 0x46eca9 MOV %RAX,0xa8(%RSP) |
(648) 0x46ecb1 MOV (%RAX),%RAX |
(648) 0x46ecb4 MOV %RSI,0xb0(%RSP) |
(648) 0x46ecbc ADD %RDX,%R8 |
(648) 0x46ecbf SUB %RAX,%R8 |
(648) 0x46ecc2 CMP %R8,%RDX |
(648) 0x46ecc5 JGE 46eeca |
(648) 0x46eccb MOV %RAX,%RSI |
(648) 0x46ecce SUB %RDX,%RSI |
(648) 0x46ecd1 SUB %RAX,%RDX |
(648) 0x46ecd4 MOV %RDX,0x158(%RSP) |
(648) 0x46ecdc ADD %R8,%RSI |
(648) 0x46ecdf MOV 0xe0(%RSP),%RDX |
(648) 0x46ece7 MOV 0x48(%RSP),%R8 |
(648) 0x46ecec MOV (%R8,%RDX,1),%R8 |
(648) 0x46ecf0 MOV 0x158(%RSP),%RDX |
(648) 0x46ecf8 LEA (%R8,%RDX,8),%RDX |
(648) 0x46ecfc MOV %RSI,%R8 |
(648) 0x46ecff SUB %RAX,%R8 |
(648) 0x46ed02 AND $0x7,%R8D |
(648) 0x46ed06 JE 46ede9 |
(648) 0x46ed0c CMP $0x1,%R8 |
(648) 0x46ed10 JE 46edc8 |
(648) 0x46ed16 CMP $0x2,%R8 |
(648) 0x46ed1a JE 46edb0 |
(648) 0x46ed20 CMP $0x3,%R8 |
(648) 0x46ed24 JE 46ed98 |
(648) 0x46ed26 CMP $0x4,%R8 |
(648) 0x46ed2a JE 46ed80 |
(648) 0x46ed2c CMP $0x5,%R8 |
(648) 0x46ed30 JE 46ed68 |
(648) 0x46ed32 CMP $0x6,%R8 |
(648) 0x46ed36 JE 46ed50 |
(648) 0x46ed38 MOV (%RDX,%RAX,8),%R8 |
(648) 0x46ed3c MOV %RAX,(%RBX,%R8,8) |
(648) 0x46ed40 MOVQ $0,(%R11,%RAX,8) |
(648) 0x46ed48 INC %RAX |
(648) 0x46ed4b MOV %R8,-0x8(%R10,%RAX,8) |
(648) 0x46ed50 MOV (%RDX,%RAX,8),%R8 |
(648) 0x46ed54 MOV %RAX,(%RBX,%R8,8) |
(648) 0x46ed58 MOVQ $0,(%R11,%RAX,8) |
(648) 0x46ed60 INC %RAX |
(648) 0x46ed63 MOV %R8,-0x8(%R10,%RAX,8) |
(648) 0x46ed68 MOV (%RDX,%RAX,8),%R8 |
(648) 0x46ed6c MOV %RAX,(%RBX,%R8,8) |
(648) 0x46ed70 MOVQ $0,(%R11,%RAX,8) |
(648) 0x46ed78 INC %RAX |
(648) 0x46ed7b MOV %R8,-0x8(%R10,%RAX,8) |
(648) 0x46ed80 MOV (%RDX,%RAX,8),%R8 |
(648) 0x46ed84 MOV %RAX,(%RBX,%R8,8) |
(648) 0x46ed88 MOVQ $0,(%R11,%RAX,8) |
(648) 0x46ed90 INC %RAX |
(648) 0x46ed93 MOV %R8,-0x8(%R10,%RAX,8) |
(648) 0x46ed98 MOV (%RDX,%RAX,8),%R8 |
(648) 0x46ed9c MOV %RAX,(%RBX,%R8,8) |
(648) 0x46eda0 MOVQ $0,(%R11,%RAX,8) |
(648) 0x46eda8 INC %RAX |
(648) 0x46edab MOV %R8,-0x8(%R10,%RAX,8) |
(648) 0x46edb0 MOV (%RDX,%RAX,8),%R8 |
(648) 0x46edb4 MOV %RAX,(%RBX,%R8,8) |
(648) 0x46edb8 MOVQ $0,(%R11,%RAX,8) |
(648) 0x46edc0 INC %RAX |
(648) 0x46edc3 MOV %R8,-0x8(%R10,%RAX,8) |
(648) 0x46edc8 MOV (%RDX,%RAX,8),%R8 |
(648) 0x46edcc MOV %RAX,(%RBX,%R8,8) |
(648) 0x46edd0 MOVQ $0,(%R11,%RAX,8) |
(648) 0x46edd8 INC %RAX |
(648) 0x46eddb MOV %R8,-0x8(%R10,%RAX,8) |
(648) 0x46ede0 CMP %RSI,%RAX |
(648) 0x46ede3 JE 46eeca |
(648) 0x46ede9 MOV %R9,0x158(%RSP) |
(658) 0x46edf1 MOV (%RDX,%RAX,8),%R9 |
(658) 0x46edf5 LEA 0x1(%RAX),%R8 |
(658) 0x46edf9 MOV %RAX,(%RBX,%R9,8) |
(658) 0x46edfd MOVQ $0,(%R11,%RAX,8) |
(658) 0x46ee05 MOV %R9,-0x8(%R10,%R8,8) |
(658) 0x46ee0a MOV (%RDX,%R8,8),%R9 |
(658) 0x46ee0e MOV %R8,(%RBX,%R9,8) |
(658) 0x46ee12 MOVQ $0,(%R11,%R8,8) |
(658) 0x46ee1a LEA 0x2(%RAX),%R8 |
(658) 0x46ee1e MOV %R9,-0x8(%R10,%R8,8) |
(658) 0x46ee23 MOV (%RDX,%R8,8),%R9 |
(658) 0x46ee27 MOV %R8,(%RBX,%R9,8) |
(658) 0x46ee2b MOVQ $0,(%R11,%R8,8) |
(658) 0x46ee33 LEA 0x3(%RAX),%R8 |
(658) 0x46ee37 MOV %R9,-0x8(%R10,%R8,8) |
(658) 0x46ee3c MOV (%RDX,%R8,8),%R9 |
(658) 0x46ee40 MOV %R8,(%RBX,%R9,8) |
(658) 0x46ee44 MOVQ $0,(%R11,%R8,8) |
(658) 0x46ee4c LEA 0x4(%RAX),%R8 |
(658) 0x46ee50 MOV %R9,-0x8(%R10,%R8,8) |
(658) 0x46ee55 MOV (%RDX,%R8,8),%R9 |
(658) 0x46ee59 MOV %R8,(%RBX,%R9,8) |
(658) 0x46ee5d MOVQ $0,(%R11,%R8,8) |
(658) 0x46ee65 LEA 0x5(%RAX),%R8 |
(658) 0x46ee69 MOV %R9,-0x8(%R10,%R8,8) |
(658) 0x46ee6e MOV (%RDX,%R8,8),%R9 |
(658) 0x46ee72 MOV %R8,(%RBX,%R9,8) |
(658) 0x46ee76 MOVQ $0,(%R11,%R8,8) |
(658) 0x46ee7e LEA 0x6(%RAX),%R8 |
(658) 0x46ee82 MOV %R9,-0x8(%R10,%R8,8) |
(658) 0x46ee87 MOV (%RDX,%R8,8),%R9 |
(658) 0x46ee8b MOV %R8,(%RBX,%R9,8) |
(658) 0x46ee8f MOVQ $0,(%R11,%R8,8) |
(658) 0x46ee97 LEA 0x7(%RAX),%R8 |
(658) 0x46ee9b ADD $0x8,%RAX |
(658) 0x46ee9f MOV %R9,-0x8(%R10,%R8,8) |
(658) 0x46eea4 MOV (%RDX,%R8,8),%R9 |
(658) 0x46eea8 MOV %R8,(%RBX,%R9,8) |
(658) 0x46eeac MOVQ $0,(%R11,%R8,8) |
(658) 0x46eeb4 MOV %R9,-0x8(%R10,%RAX,8) |
(658) 0x46eeb9 CMP %RSI,%RAX |
(658) 0x46eebc JNE 46edf1 |
(648) 0x46eec2 MOV 0x158(%RSP),%R9 |
(648) 0x46eeca MOV 0x68(%RSP),%RSI |
(648) 0x46eecf LEA (%RSI,%RCX,1),%R8 |
(648) 0x46eed3 MOV (%RSI,%RDI,8),%RAX |
(648) 0x46eed7 MOV (%R8),%RSI |
(648) 0x46eeda CMP %RSI,%RAX |
(648) 0x46eedd JGE 46ef1e |
(648) 0x46eedf MOV %RCX,0x158(%RSP) |
(648) 0x46eee7 NOPW (%RAX,%RAX,1) |
(657) 0x46eef0 MOV 0x120(%RSP),%RCX |
(657) 0x46eef8 MOV (%RCX,%RAX,8),%RDX |
(657) 0x46eefc MOV 0x130(%RSP),%RCX |
(657) 0x46ef04 CMP (%RCX,%RDX,8),%R14 |
(657) 0x46ef08 JE 46f050 |
(657) 0x46ef0e INC %RAX |
(657) 0x46ef11 CMP %RSI,%RAX |
(657) 0x46ef14 JL 46eef0 |
(648) 0x46ef16 MOV 0x158(%RSP),%RCX |
(648) 0x46ef1e MOV 0x70(%RSP),%R8 |
(648) 0x46ef23 ADD %R8,%RCX |
(648) 0x46ef26 MOV (%R8,%RDI,8),%RAX |
(648) 0x46ef2a MOV (%RCX),%RSI |
(648) 0x46ef2d CMP %RSI,%RAX |
(648) 0x46ef30 JGE 46ef5e |
(648) 0x46ef32 NOPW (%RAX,%RAX,1) |
(656) 0x46ef38 MOV 0x128(%RSP),%RDX |
(656) 0x46ef40 MOV 0x138(%RSP),%R8 |
(656) 0x46ef48 MOV (%RDX,%RAX,8),%RDX |
(656) 0x46ef4c CMP (%R8,%RDX,8),%R14 |
(656) 0x46ef50 JE 46f070 |
(656) 0x46ef56 INC %RAX |
(656) 0x46ef59 CMP %RSI,%RAX |
(656) 0x46ef5c JL 46ef38 |
(648) 0x46ef5e MOV 0x58(%RSP),%RCX |
(648) 0x46ef63 MOV 0x148(%RSP),%RDX |
(648) 0x46ef6b MOV (%RCX,%RDI,8),%R8 |
(648) 0x46ef6f MOV 0x8(%RCX,%RDX,1),%RDX |
(648) 0x46ef74 LEA 0x1(%R8),%RAX |
(648) 0x46ef78 CMP %RDX,%RAX |
(648) 0x46ef7b JGE 46fb5c |
(648) 0x46ef81 MOV 0x20(%RSP),%RCX |
(648) 0x46ef86 SAL $0x3,%RAX |
(648) 0x46ef8a VXORPD %XMM0,%XMM0,%XMM0 |
(648) 0x46ef8e MOV %R15,0xa0(%RSP) |
(648) 0x46ef96 MOV %R8,0x98(%RSP) |
(648) 0x46ef9e VMOVSD %XMM0,%XMM0,%XMM2 |
(648) 0x46efa2 LEA (%RCX,%RAX,1),%RSI |
(648) 0x46efa6 LEA (%RCX,%RDX,8),%RDX |
(648) 0x46efaa MOV %RSI,0xe8(%RSP) |
(648) 0x46efb2 MOV 0xc8(%RSP),%RSI |
(648) 0x46efba MOV %RDX,0x158(%RSP) |
(648) 0x46efc2 ADD %RSI,%RAX |
(648) 0x46efc5 MOV 0xe8(%RSP),%RSI |
(648) 0x46efcd MOV %R14,0xe8(%RSP) |
(648) 0x46efd5 JMP 46f010 |
0x46efd7 NOPW (%RAX,%RAX,1) |
(653) 0x46efe0 MOV 0x108(%RSP),%RDX |
(653) 0x46efe8 MOV 0x148(%RSP),%R8 |
(653) 0x46eff0 MOV (%RDX,%RCX,8),%RCX |
(653) 0x46eff4 CMP %RCX,(%RDX,%R8,1) |
(653) 0x46eff8 JE 46f043 |
(653) 0x46effa ADD $0x8,%RSI |
(653) 0x46effe ADD $0x8,%RAX |
(653) 0x46f002 CMP %RSI,0x158(%RSP) |
(653) 0x46f00a JE 46f390 |
(653) 0x46f010 MOV (%RSI),%RCX |
(653) 0x46f013 MOV 0x150(%RSP),%R15 |
(653) 0x46f01b LEA (,%RCX,8),%R8 |
(653) 0x46f023 CMP (%R15,%RCX,8),%RDI |
(653) 0x46f027 JE 46f090 |
(653) 0x46f029 MOV 0x110(%RSP),%R14 |
(653) 0x46f031 CMPQ $-0x3,(%R14,%RCX,8) |
(653) 0x46f036 JE 46effa |
(653) 0x46f038 CMPQ $0x1,0x140(%RSP) |
(653) 0x46f041 JNE 46efe0 |
(653) 0x46f043 VADDSD (%RAX),%XMM0,%XMM0 |
(653) 0x46f047 JMP 46effa |
0x46f049 NOPL (%RAX) |
(657) 0x46f050 MOV 0x150(%RSP),%RSI |
(657) 0x46f058 INC %RAX |
(657) 0x46f05b MOV %RDI,(%RSI,%RDX,8) |
(657) 0x46f05f MOV (%R8),%RSI |
(657) 0x46f062 CMP %RAX,%RSI |
(657) 0x46f065 JG 46eef0 |
(648) 0x46f06b JMP 46ef16 |
(656) 0x46f070 MOV 0x118(%RSP),%RSI |
(656) 0x46f078 INC %RAX |
(656) 0x46f07b MOV %RDI,(%RSI,%RDX,8) |
(656) 0x46f07f MOV (%RCX),%RSI |
(656) 0x46f082 CMP %RAX,%RSI |
(656) 0x46f085 JG 46ef38 |
(648) 0x46f08b JMP 46ef5e |
(653) 0x46f090 MOV 0xd0(%RSP),%R15 |
(653) 0x46f098 MOV (%R15,%RCX,8),%RDX |
(653) 0x46f09c MOV 0x8(%R15,%R8,1),%R15 |
(653) 0x46f0a1 CMP %R15,%RDX |
(653) 0x46f0a4 JGE 46f213 |
(653) 0x46f0aa MOV %R15,%R14 |
(653) 0x46f0ad SUB %RDX,%R14 |
(653) 0x46f0b0 AND $0x3,%R14D |
(653) 0x46f0b4 JE 46f157 |
(653) 0x46f0ba CMP $0x1,%R14 |
(653) 0x46f0be JE 46f120 |
(653) 0x46f0c0 CMP $0x2,%R14 |
(653) 0x46f0c4 JE 46f0f2 |
(653) 0x46f0c6 VMOVSD (%RAX),%XMM5 |
(653) 0x46f0ca MOV (%R13,%RDX,8),%R14 |
(653) 0x46f0cf VMULSD (%R12,%RDX,8),%XMM5,%XMM6 |
(653) 0x46f0d5 MOV (%R9,%R14,8),%R14 |
(653) 0x46f0d9 INC %RDX |
(653) 0x46f0dc LEA (%R12,%R14,8),%R14 |
(653) 0x46f0e0 VADDSD (%R14),%XMM6,%XMM7 |
(653) 0x46f0e5 VADDSD %XMM6,%XMM2,%XMM2 |
(653) 0x46f0e9 VADDSD %XMM6,%XMM0,%XMM0 |
(653) 0x46f0ed VMOVSD %XMM7,(%R14) |
(653) 0x46f0f2 VMOVSD (%RAX),%XMM8 |
(653) 0x46f0f6 MOV (%R13,%RDX,8),%R14 |
(653) 0x46f0fb VMULSD (%R12,%RDX,8),%XMM8,%XMM9 |
(653) 0x46f101 MOV (%R9,%R14,8),%R14 |
(653) 0x46f105 INC %RDX |
(653) 0x46f108 LEA (%R12,%R14,8),%R14 |
(653) 0x46f10c VADDSD (%R14),%XMM9,%XMM10 |
(653) 0x46f111 VADDSD %XMM9,%XMM2,%XMM2 |
(653) 0x46f116 VADDSD %XMM9,%XMM0,%XMM0 |
(653) 0x46f11b VMOVSD %XMM10,(%R14) |
(653) 0x46f120 VMOVSD (%RAX),%XMM11 |
(653) 0x46f124 MOV (%R13,%RDX,8),%R14 |
(653) 0x46f129 VMULSD (%R12,%RDX,8),%XMM11,%XMM12 |
(653) 0x46f12f MOV (%R9,%R14,8),%R14 |
(653) 0x46f133 INC %RDX |
(653) 0x46f136 LEA (%R12,%R14,8),%R14 |
(653) 0x46f13a VADDSD (%R14),%XMM12,%XMM13 |
(653) 0x46f13f VADDSD %XMM12,%XMM2,%XMM2 |
(653) 0x46f144 VADDSD %XMM12,%XMM0,%XMM0 |
(653) 0x46f149 VMOVSD %XMM13,(%R14) |
(653) 0x46f14e CMP %R15,%RDX |
(653) 0x46f151 JE 46f213 |
(655) 0x46f157 VMOVSD (%RAX),%XMM14 |
(655) 0x46f15b MOV (%R13,%RDX,8),%R14 |
(655) 0x46f160 VMULSD (%R12,%RDX,8),%XMM14,%XMM15 |
(655) 0x46f166 MOV (%R9,%R14,8),%R14 |
(655) 0x46f16a LEA (%R12,%R14,8),%R14 |
(655) 0x46f16e VADDSD (%R14),%XMM15,%XMM1 |
(655) 0x46f173 VADDSD %XMM15,%XMM2,%XMM6 |
(655) 0x46f178 VADDSD %XMM15,%XMM0,%XMM7 |
(655) 0x46f17d VMOVSD %XMM1,(%R14) |
(655) 0x46f182 MOV 0x8(%R13,%RDX,8),%R14 |
(655) 0x46f187 VMOVSD (%RAX),%XMM5 |
(655) 0x46f18b MOV (%R9,%R14,8),%R14 |
(655) 0x46f18f VMULSD 0x8(%R12,%RDX,8),%XMM5,%XMM8 |
(655) 0x46f196 LEA (%R12,%R14,8),%R14 |
(655) 0x46f19a VADDSD (%R14),%XMM8,%XMM9 |
(655) 0x46f19f VADDSD %XMM8,%XMM6,%XMM10 |
(655) 0x46f1a4 VADDSD %XMM8,%XMM7,%XMM11 |
(655) 0x46f1a9 VMOVSD %XMM9,(%R14) |
(655) 0x46f1ae MOV 0x10(%R13,%RDX,8),%R14 |
(655) 0x46f1b3 VMOVSD (%RAX),%XMM12 |
(655) 0x46f1b7 MOV (%R9,%R14,8),%R14 |
(655) 0x46f1bb VMULSD 0x10(%R12,%RDX,8),%XMM12,%XMM13 |
(655) 0x46f1c2 LEA (%R12,%R14,8),%R14 |
(655) 0x46f1c6 VADDSD (%R14),%XMM13,%XMM2 |
(655) 0x46f1cb VADDSD %XMM13,%XMM10,%XMM14 |
(655) 0x46f1d0 VADDSD %XMM13,%XMM11,%XMM0 |
(655) 0x46f1d5 VMOVSD %XMM2,(%R14) |
(655) 0x46f1da MOV 0x18(%R13,%RDX,8),%R14 |
(655) 0x46f1df VMOVSD (%RAX),%XMM15 |
(655) 0x46f1e3 MOV (%R9,%R14,8),%R14 |
(655) 0x46f1e7 VMULSD 0x18(%R12,%RDX,8),%XMM15,%XMM12 |
(655) 0x46f1ee ADD $0x4,%RDX |
(655) 0x46f1f2 LEA (%R12,%R14,8),%R14 |
(655) 0x46f1f6 VADDSD (%R14),%XMM12,%XMM1 |
(655) 0x46f1fb VADDSD %XMM12,%XMM14,%XMM2 |
(655) 0x46f200 VADDSD %XMM12,%XMM0,%XMM0 |
(655) 0x46f205 VMOVSD %XMM1,(%R14) |
(655) 0x46f20a CMP %R15,%RDX |
(655) 0x46f20d JNE 46f157 |
(653) 0x46f213 MOV 0xd8(%RSP),%R15 |
(653) 0x46f21b MOV (%R15,%RCX,8),%RDX |
(653) 0x46f21f MOV 0x8(%R15,%R8,1),%R8 |
(653) 0x46f224 CMP %R8,%RDX |
(653) 0x46f227 JGE 46effa |
(653) 0x46f22d MOV %R8,%RCX |
(653) 0x46f230 SUB %RDX,%RCX |
(653) 0x46f233 AND $0x3,%ECX |
(653) 0x46f236 JE 46f2d0 |
(653) 0x46f23c CMP $0x1,%RCX |
(653) 0x46f240 JE 46f29c |
(653) 0x46f242 CMP $0x2,%RCX |
(653) 0x46f246 JE 46f271 |
(653) 0x46f248 VMOVSD (%RAX),%XMM6 |
(653) 0x46f24c MOV (%R10,%RDX,8),%R14 |
(653) 0x46f250 VMULSD (%R11,%RDX,8),%XMM6,%XMM7 |
(653) 0x46f256 MOV (%RBX,%R14,8),%R15 |
(653) 0x46f25a INC %RDX |
(653) 0x46f25d LEA (%R11,%R15,8),%RCX |
(653) 0x46f261 VADDSD (%RCX),%XMM7,%XMM5 |
(653) 0x46f265 VADDSD %XMM7,%XMM2,%XMM2 |
(653) 0x46f269 VADDSD %XMM7,%XMM0,%XMM0 |
(653) 0x46f26d VMOVSD %XMM5,(%RCX) |
(653) 0x46f271 VMOVSD (%RAX),%XMM8 |
(653) 0x46f275 MOV (%R10,%RDX,8),%R14 |
(653) 0x46f279 VMULSD (%R11,%RDX,8),%XMM8,%XMM9 |
(653) 0x46f27f MOV (%RBX,%R14,8),%R15 |
(653) 0x46f283 INC %RDX |
(653) 0x46f286 LEA (%R11,%R15,8),%RCX |
(653) 0x46f28a VADDSD (%RCX),%XMM9,%XMM10 |
(653) 0x46f28e VADDSD %XMM9,%XMM2,%XMM2 |
(653) 0x46f293 VADDSD %XMM9,%XMM0,%XMM0 |
(653) 0x46f298 VMOVSD %XMM10,(%RCX) |
(653) 0x46f29c VMOVSD (%RAX),%XMM11 |
(653) 0x46f2a0 MOV (%R10,%RDX,8),%R14 |
(653) 0x46f2a4 VMULSD (%R11,%RDX,8),%XMM11,%XMM12 |
(653) 0x46f2aa MOV (%RBX,%R14,8),%R15 |
(653) 0x46f2ae INC %RDX |
(653) 0x46f2b1 LEA (%R11,%R15,8),%RCX |
(653) 0x46f2b5 VADDSD (%RCX),%XMM12,%XMM13 |
(653) 0x46f2b9 VADDSD %XMM12,%XMM2,%XMM2 |
(653) 0x46f2be VADDSD %XMM12,%XMM0,%XMM0 |
(653) 0x46f2c3 VMOVSD %XMM13,(%RCX) |
(653) 0x46f2c7 CMP %R8,%RDX |
(653) 0x46f2ca JE 46effa |
(654) 0x46f2d0 VMOVSD (%RAX),%XMM12 |
(654) 0x46f2d4 MOV (%R10,%RDX,8),%R14 |
(654) 0x46f2d8 VMULSD (%R11,%RDX,8),%XMM12,%XMM14 |
(654) 0x46f2de MOV (%RBX,%R14,8),%R15 |
(654) 0x46f2e2 MOV 0x8(%R10,%RDX,8),%R14 |
(654) 0x46f2e7 LEA (%R11,%R15,8),%RCX |
(654) 0x46f2eb MOV (%RBX,%R14,8),%R15 |
(654) 0x46f2ef MOV 0x10(%R10,%RDX,8),%R14 |
(654) 0x46f2f4 VADDSD (%RCX),%XMM14,%XMM15 |
(654) 0x46f2f8 VADDSD %XMM14,%XMM2,%XMM2 |
(654) 0x46f2fd VADDSD %XMM14,%XMM0,%XMM0 |
(654) 0x46f302 VMOVSD %XMM15,(%RCX) |
(654) 0x46f306 LEA (%R11,%R15,8),%RCX |
(654) 0x46f30a MOV (%RBX,%R14,8),%R15 |
(654) 0x46f30e MOV 0x18(%R10,%RDX,8),%R14 |
(654) 0x46f313 VMOVSD (%RAX),%XMM1 |
(654) 0x46f317 VMULSD 0x8(%R11,%RDX,8),%XMM1,%XMM6 |
(654) 0x46f31e VADDSD (%RCX),%XMM6,%XMM7 |
(654) 0x46f322 VADDSD %XMM6,%XMM2,%XMM8 |
(654) 0x46f326 VADDSD %XMM6,%XMM0,%XMM9 |
(654) 0x46f32a VMOVSD %XMM7,(%RCX) |
(654) 0x46f32e LEA (%R11,%R15,8),%RCX |
(654) 0x46f332 MOV (%RBX,%R14,8),%R15 |
(654) 0x46f336 VMOVSD (%RAX),%XMM5 |
(654) 0x46f33a VMULSD 0x10(%R11,%RDX,8),%XMM5,%XMM10 |
(654) 0x46f341 VADDSD (%RCX),%XMM10,%XMM11 |
(654) 0x46f345 VADDSD %XMM10,%XMM8,%XMM13 |
(654) 0x46f34a VADDSD %XMM10,%XMM9,%XMM14 |
(654) 0x46f34f VMOVSD %XMM11,(%RCX) |
(654) 0x46f353 LEA (%R11,%R15,8),%RCX |
(654) 0x46f357 VMOVSD (%RAX),%XMM12 |
(654) 0x46f35b VMULSD 0x18(%R11,%RDX,8),%XMM12,%XMM12 |
(654) 0x46f362 ADD $0x4,%RDX |
(654) 0x46f366 VADDSD (%RCX),%XMM12,%XMM15 |
(654) 0x46f36a VADDSD %XMM12,%XMM13,%XMM2 |
(654) 0x46f36f VADDSD %XMM12,%XMM14,%XMM0 |
(654) 0x46f374 VMOVSD %XMM15,(%RCX) |
(654) 0x46f378 CMP %R8,%RDX |
(654) 0x46f37b JNE 46f2d0 |
(653) 0x46f381 JMP 46effa |
0x46f386 NOPW %CS:(%RAX,%RAX,1) |
(648) 0x46f390 MOV 0xa0(%RSP),%R15 |
(648) 0x46f398 MOV 0x98(%RSP),%R8 |
(648) 0x46f3a0 MOV 0xe8(%RSP),%R14 |
(648) 0x46f3a8 MOV 0x60(%RSP),%RCX |
(648) 0x46f3ad MOV 0x148(%RSP),%RAX |
(648) 0x46f3b5 MOV (%RCX,%RDI,8),%RDX |
(648) 0x46f3b9 MOV 0x8(%RCX,%RAX,1),%RCX |
(648) 0x46f3be CMP %RCX,%RDX |
(648) 0x46f3c1 JGE 46f4c3 |
(648) 0x46f3c7 MOV 0x30(%RSP),%RAX |
(648) 0x46f3cc SAL $0x3,%RDX |
(648) 0x46f3d0 MOV %R10,0xa0(%RSP) |
(648) 0x46f3d8 MOV %R13,0x98(%RSP) |
(648) 0x46f3e0 LEA (%RAX,%RDX,1),%RSI |
(648) 0x46f3e4 MOV %R8,0x90(%RSP) |
(648) 0x46f3ec MOV %RSI,0x158(%RSP) |
(648) 0x46f3f4 MOV 0x28(%RSP),%RSI |
(648) 0x46f3f9 ADD %RSI,%RDX |
(648) 0x46f3fc LEA (%RAX,%RCX,8),%RSI |
(648) 0x46f400 MOV %R14,%RAX |
(648) 0x46f403 MOV 0x38(%RSP),%R14 |
(648) 0x46f408 JMP 46f44c |
0x46f40a NOPW (%RAX,%RAX,1) |
(651) 0x46f410 MOV 0x108(%RSP),%R10 |
(651) 0x46f418 MOV 0x148(%RSP),%R13 |
(651) 0x46f420 MOV 0xf0(%RSP),%RCX |
(651) 0x46f428 MOV (%R10,%R13,1),%R10 |
(651) 0x46f42c CMP %R10,(%RCX,%R8,1) |
(651) 0x46f430 JE 46f49f |
(651) 0x46f432 ADDQ $0x8,0x158(%RSP) |
(651) 0x46f43b ADD $0x8,%RDX |
(651) 0x46f43f MOV 0x158(%RSP),%RCX |
(651) 0x46f447 CMP %RSI,%RCX |
(651) 0x46f44a JE 46f4a8 |
(651) 0x46f44c MOV 0x158(%RSP),%R13 |
(651) 0x46f454 MOV (%R13),%RCX |
(651) 0x46f458 TEST %R15,%R15 |
(651) 0x46f45b JE 46f469 |
(651) 0x46f45d MOV 0x100(%RSP),%R10 |
(651) 0x46f465 MOV (%R10,%RCX,8),%RCX |
(651) 0x46f469 LEA (,%RCX,8),%R8 |
(651) 0x46f471 TEST %RCX,%RCX |
(651) 0x46f474 JS 46f489 |
(651) 0x46f476 MOV 0x118(%RSP),%R13 |
(651) 0x46f47e CMP (%R13,%RCX,8),%RDI |
(651) 0x46f483 JE 46f870 |
(651) 0x46f489 CMPQ $-0x3,(%R14,%R8,1) |
(651) 0x46f48e JE 46f432 |
(651) 0x46f490 CMPQ $0x1,0x140(%RSP) |
(651) 0x46f499 JNE 46f410 |
(651) 0x46f49f VADDSD (%RDX),%XMM0,%XMM0 |
(651) 0x46f4a3 JMP 46f432 |
0x46f4a5 NOPL (%RAX) |
(648) 0x46f4a8 MOV 0xa0(%RSP),%R10 |
(648) 0x46f4b0 MOV 0x98(%RSP),%R13 |
(648) 0x46f4b8 MOV %RAX,%R14 |
(648) 0x46f4bb MOV 0x90(%RSP),%R8 |
(648) 0x46f4c3 MOV 0xc8(%RSP),%RDI |
(648) 0x46f4cb VMULSD (%RDI,%R8,8),%XMM2,%XMM9 |
(648) 0x46f4d1 VCOMISD %XMM3,%XMM9 |
(648) 0x46f4d5 JE 46f4e0 |
(648) 0x46f4d7 VXORPD %XMM4,%XMM0,%XMM10 |
(648) 0x46f4db VDIVSD %XMM9,%XMM10,%XMM12 |
(648) 0x46f4e0 MOV 0xb8(%RSP),%R8 |
(648) 0x46f4e8 MOV 0xc0(%RSP),%RAX |
(648) 0x46f4f0 MOV (%R8),%RSI |
(648) 0x46f4f3 MOV (%RAX),%RCX |
(648) 0x46f4f6 CMP %RCX,%RSI |
(648) 0x46f4f9 JGE 46f676 |
(648) 0x46f4ff SUB %RSI,%RCX |
(648) 0x46f502 MOV %RSI,%RDI |
(648) 0x46f505 LEA -0x1(%RCX),%RDX |
(648) 0x46f509 CMP $0x2,%RDX |
(648) 0x46f50d JBE 46fb69 |
(648) 0x46f513 MOV %RCX,%RDX |
(648) 0x46f516 LEA (%R12,%RSI,8),%RAX |
(648) 0x46f51a VBROADCASTSD %XMM12,%YMM5 |
(648) 0x46f51f SHR $0x2,%RDX |
(648) 0x46f523 SAL $0x5,%RDX |
(648) 0x46f527 LEA (%RDX,%RAX,1),%R8 |
(648) 0x46f52b SUB $0x20,%RDX |
(648) 0x46f52f SHR $0x5,%RDX |
(648) 0x46f533 INC %RDX |
(648) 0x46f536 AND $0x7,%EDX |
(648) 0x46f539 JE 46f5c3 |
(648) 0x46f53f CMP $0x1,%RDX |
(648) 0x46f543 JE 46f5b1 |
(648) 0x46f545 CMP $0x2,%RDX |
(648) 0x46f549 JE 46f5a4 |
(648) 0x46f54b CMP $0x3,%RDX |
(648) 0x46f54f JE 46f597 |
(648) 0x46f551 CMP $0x4,%RDX |
(648) 0x46f555 JE 46f58a |
(648) 0x46f557 CMP $0x5,%RDX |
(648) 0x46f55b JE 46f57d |
(648) 0x46f55d CMP $0x6,%RDX |
(648) 0x46f561 JE 46f570 |
(648) 0x46f563 VMULPD (%RAX),%YMM5,%YMM11 |
(648) 0x46f567 ADD $0x20,%RAX |
(648) 0x46f56b VMOVUPD %YMM11,-0x20(%RAX) |
(648) 0x46f570 VMULPD (%RAX),%YMM5,%YMM13 |
(648) 0x46f574 ADD $0x20,%RAX |
(648) 0x46f578 VMOVUPD %YMM13,-0x20(%RAX) |
(648) 0x46f57d VMULPD (%RAX),%YMM5,%YMM14 |
(648) 0x46f581 ADD $0x20,%RAX |
(648) 0x46f585 VMOVUPD %YMM14,-0x20(%RAX) |
(648) 0x46f58a VMULPD (%RAX),%YMM5,%YMM15 |
(648) 0x46f58e ADD $0x20,%RAX |
(648) 0x46f592 VMOVUPD %YMM15,-0x20(%RAX) |
(648) 0x46f597 VMULPD (%RAX),%YMM5,%YMM1 |
(648) 0x46f59b ADD $0x20,%RAX |
(648) 0x46f59f VMOVUPD %YMM1,-0x20(%RAX) |
(648) 0x46f5a4 VMULPD (%RAX),%YMM5,%YMM6 |
(648) 0x46f5a8 ADD $0x20,%RAX |
(648) 0x46f5ac VMOVUPD %YMM6,-0x20(%RAX) |
(648) 0x46f5b1 VMULPD (%RAX),%YMM5,%YMM7 |
(648) 0x46f5b5 ADD $0x20,%RAX |
(648) 0x46f5b9 VMOVUPD %YMM7,-0x20(%RAX) |
(648) 0x46f5be CMP %R8,%RAX |
(648) 0x46f5c1 JE 46f632 |
(650) 0x46f5c3 VMULPD (%RAX),%YMM5,%YMM2 |
(650) 0x46f5c7 ADD $0x100,%RAX |
(650) 0x46f5cd VMULPD -0xe0(%RAX),%YMM5,%YMM0 |
(650) 0x46f5d5 VMULPD -0xc0(%RAX),%YMM5,%YMM8 |
(650) 0x46f5dd VMULPD -0xa0(%RAX),%YMM5,%YMM9 |
(650) 0x46f5e5 VMULPD -0x80(%RAX),%YMM5,%YMM10 |
(650) 0x46f5ea VMULPD -0x60(%RAX),%YMM5,%YMM11 |
(650) 0x46f5ef VMOVUPD %YMM2,-0x100(%RAX) |
(650) 0x46f5f7 VMULPD -0x40(%RAX),%YMM5,%YMM13 |
(650) 0x46f5fc VMOVUPD %YMM0,-0xe0(%RAX) |
(650) 0x46f604 VMULPD -0x20(%RAX),%YMM5,%YMM14 |
(650) 0x46f609 VMOVUPD %YMM8,-0xc0(%RAX) |
(650) 0x46f611 VMOVUPD %YMM9,-0xa0(%RAX) |
(650) 0x46f619 VMOVUPD %YMM10,-0x80(%RAX) |
(650) 0x46f61e VMOVUPD %YMM11,-0x60(%RAX) |
(650) 0x46f623 VMOVUPD %YMM13,-0x40(%RAX) |
(650) 0x46f628 VMOVUPD %YMM14,-0x20(%RAX) |
(650) 0x46f62d CMP %R8,%RAX |
(650) 0x46f630 JNE 46f5c3 |
(648) 0x46f632 MOV %RCX,%R8 |
(648) 0x46f635 AND $-0x4,%R8 |
(648) 0x46f639 ADD %R8,%RSI |
(648) 0x46f63c TEST $0x3,%CL |
(648) 0x46f63f JE 46f676 |
(648) 0x46f641 SUB %R8,%RCX |
(648) 0x46f644 CMP $0x1,%RCX |
(648) 0x46f648 JE 46f66a |
(648) 0x46f64a ADD %RDI,%R8 |
(648) 0x46f64d VMOVDDUP %XMM12,%XMM5 |
(648) 0x46f652 LEA (%R12,%R8,8),%RDI |
(648) 0x46f656 VMULPD (%RDI),%XMM5,%XMM15 |
(648) 0x46f65a VMOVUPD %XMM15,(%RDI) |
(648) 0x46f65e TEST $0x1,%CL |
(648) 0x46f661 JE 46f676 |
(648) 0x46f663 AND $-0x2,%RCX |
(648) 0x46f667 ADD %RCX,%RSI |
(648) 0x46f66a LEA (%R12,%RSI,8),%RSI |
(648) 0x46f66e VMULSD (%RSI),%XMM12,%XMM1 |
(648) 0x46f672 VMOVSD %XMM1,(%RSI) |
(648) 0x46f676 MOV 0xa8(%RSP),%RCX |
(648) 0x46f67e MOV 0xb0(%RSP),%RAX |
(648) 0x46f686 MOV (%RCX),%RSI |
(648) 0x46f689 MOV (%RAX),%RCX |
(648) 0x46f68c CMP %RSI,%RCX |
(648) 0x46f68f JLE 46f80c |
(648) 0x46f695 SUB %RSI,%RCX |
(648) 0x46f698 MOV %RSI,%RDI |
(648) 0x46f69b LEA -0x1(%RCX),%RDX |
(648) 0x46f69f CMP $0x2,%RDX |
(648) 0x46f6a3 JBE 46fb71 |
(648) 0x46f6a9 MOV %RCX,%RDX |
(648) 0x46f6ac LEA (%R11,%RSI,8),%RAX |
(648) 0x46f6b0 VBROADCASTSD %XMM12,%YMM6 |
(648) 0x46f6b5 SHR $0x2,%RDX |
(648) 0x46f6b9 SAL $0x5,%RDX |
(648) 0x46f6bd LEA (%RDX,%RAX,1),%R8 |
(648) 0x46f6c1 SUB $0x20,%RDX |
(648) 0x46f6c5 SHR $0x5,%RDX |
(648) 0x46f6c9 INC %RDX |
(648) 0x46f6cc AND $0x7,%EDX |
(648) 0x46f6cf JE 46f759 |
(648) 0x46f6d5 CMP $0x1,%RDX |
(648) 0x46f6d9 JE 46f747 |
(648) 0x46f6db CMP $0x2,%RDX |
(648) 0x46f6df JE 46f73a |
(648) 0x46f6e1 CMP $0x3,%RDX |
(648) 0x46f6e5 JE 46f72d |
(648) 0x46f6e7 CMP $0x4,%RDX |
(648) 0x46f6eb JE 46f720 |
(648) 0x46f6ed CMP $0x5,%RDX |
(648) 0x46f6f1 JE 46f713 |
(648) 0x46f6f3 CMP $0x6,%RDX |
(648) 0x46f6f7 JE 46f706 |
(648) 0x46f6f9 VMULPD (%RAX),%YMM6,%YMM7 |
(648) 0x46f6fd ADD $0x20,%RAX |
(648) 0x46f701 VMOVUPD %YMM7,-0x20(%RAX) |
(648) 0x46f706 VMULPD (%RAX),%YMM6,%YMM2 |
(648) 0x46f70a ADD $0x20,%RAX |
(648) 0x46f70e VMOVUPD %YMM2,-0x20(%RAX) |
(648) 0x46f713 VMULPD (%RAX),%YMM6,%YMM0 |
(648) 0x46f717 ADD $0x20,%RAX |
(648) 0x46f71b VMOVUPD %YMM0,-0x20(%RAX) |
(648) 0x46f720 VMULPD (%RAX),%YMM6,%YMM8 |
(648) 0x46f724 ADD $0x20,%RAX |
(648) 0x46f728 VMOVUPD %YMM8,-0x20(%RAX) |
(648) 0x46f72d VMULPD (%RAX),%YMM6,%YMM9 |
(648) 0x46f731 ADD $0x20,%RAX |
(648) 0x46f735 VMOVUPD %YMM9,-0x20(%RAX) |
(648) 0x46f73a VMULPD (%RAX),%YMM6,%YMM10 |
(648) 0x46f73e ADD $0x20,%RAX |
(648) 0x46f742 VMOVUPD %YMM10,-0x20(%RAX) |
(648) 0x46f747 VMULPD (%RAX),%YMM6,%YMM11 |
(648) 0x46f74b ADD $0x20,%RAX |
(648) 0x46f74f VMOVUPD %YMM11,-0x20(%RAX) |
(648) 0x46f754 CMP %R8,%RAX |
(648) 0x46f757 JE 46f7c8 |
(649) 0x46f759 VMULPD (%RAX),%YMM6,%YMM13 |
(649) 0x46f75d ADD $0x100,%RAX |
(649) 0x46f763 VMULPD -0xe0(%RAX),%YMM6,%YMM14 |
(649) 0x46f76b VMULPD -0xc0(%RAX),%YMM6,%YMM5 |
(649) 0x46f773 VMULPD -0xa0(%RAX),%YMM6,%YMM15 |
(649) 0x46f77b VMULPD -0x80(%RAX),%YMM6,%YMM1 |
(649) 0x46f780 VMULPD -0x60(%RAX),%YMM6,%YMM7 |
(649) 0x46f785 VMOVUPD %YMM13,-0x100(%RAX) |
(649) 0x46f78d VMULPD -0x40(%RAX),%YMM6,%YMM2 |
(649) 0x46f792 VMOVUPD %YMM14,-0xe0(%RAX) |
(649) 0x46f79a VMULPD -0x20(%RAX),%YMM6,%YMM0 |
(649) 0x46f79f VMOVUPD %YMM5,-0xc0(%RAX) |
(649) 0x46f7a7 VMOVUPD %YMM15,-0xa0(%RAX) |
(649) 0x46f7af VMOVUPD %YMM1,-0x80(%RAX) |
(649) 0x46f7b4 VMOVUPD %YMM7,-0x60(%RAX) |
(649) 0x46f7b9 VMOVUPD %YMM2,-0x40(%RAX) |
(649) 0x46f7be VMOVUPD %YMM0,-0x20(%RAX) |
(649) 0x46f7c3 CMP %R8,%RAX |
(649) 0x46f7c6 JNE 46f759 |
(648) 0x46f7c8 MOV %RCX,%R8 |
(648) 0x46f7cb AND $-0x4,%R8 |
(648) 0x46f7cf ADD %R8,%RSI |
(648) 0x46f7d2 TEST $0x3,%CL |
(648) 0x46f7d5 JE 46f80c |
(648) 0x46f7d7 SUB %R8,%RCX |
(648) 0x46f7da CMP $0x1,%RCX |
(648) 0x46f7de JE 46f800 |
(648) 0x46f7e0 ADD %RDI,%R8 |
(648) 0x46f7e3 VMOVDDUP %XMM12,%XMM6 |
(648) 0x46f7e8 LEA (%R11,%R8,8),%RDI |
(648) 0x46f7ec VMULPD (%RDI),%XMM6,%XMM8 |
(648) 0x46f7f0 VMOVUPD %XMM8,(%RDI) |
(648) 0x46f7f4 TEST $0x1,%CL |
(648) 0x46f7f7 JE 46f80c |
(648) 0x46f7f9 AND $-0x2,%RCX |
(648) 0x46f7fd ADD %RCX,%RSI |
(648) 0x46f800 LEA (%R11,%RSI,8),%RSI |
(648) 0x46f804 VMULSD (%RSI),%XMM12,%XMM9 |
(648) 0x46f808 VMOVSD %XMM9,(%RSI) |
(648) 0x46f80c ADDQ $0x8,0xf8(%RSP) |
(648) 0x46f815 MOV 0xf8(%RSP),%RCX |
(648) 0x46f81d CMP %RCX,0x50(%RSP) |
(648) 0x46f822 JNE 46ea28 |
0x46f828 MOV %R9,%R15 |
0x46f82b VZEROUPPER |
0x46f82e MOV 0x150(%RSP),%RDI |
0x46f836 CALL 5958c0 <hypre_Free> |
0x46f83b MOV 0x118(%RSP),%RDI |
0x46f843 CALL 5958c0 <hypre_Free> |
0x46f848 MOV %R15,%RDI |
0x46f84b CALL 5958c0 <hypre_Free> |
0x46f850 LEA -0x28(%RBP),%RSP |
0x46f854 MOV %RBX,%RDI |
0x46f857 POP %RBX |
0x46f858 POP %R12 |
0x46f85a POP %R13 |
0x46f85c POP %R14 |
0x46f85e POP %R15 |
0x46f860 POP %RBP |
0x46f861 JMP 5958c0 |
0x46f866 NOPW %CS:(%RAX,%RAX,1) |
(651) 0x46f870 MOV 0x10(%RSP),%RCX |
(651) 0x46f875 MOV 0x18(%RSP),%R13 |
(651) 0x46f87a MOV (%RCX,%R8,1),%RCX |
(651) 0x46f87e MOV 0x8(%R13,%R8,1),%R10 |
(651) 0x46f883 ADD %RCX,%R10 |
(651) 0x46f886 MOV %R10,0xe8(%RSP) |
(651) 0x46f88e CMP %R10,%RCX |
(651) 0x46f891 JGE 46f432 |
(651) 0x46f897 MOV 0x8(%RSP),%R8 |
(651) 0x46f89c MOV 0xe0(%RSP),%R13 |
(651) 0x46f8a4 SUB %RCX,%R10 |
(651) 0x46f8a7 MOV (%R8,%R13,1),%R8 |
(651) 0x46f8ab AND $0x3,%R10D |
(651) 0x46f8af JE 46f994 |
(651) 0x46f8b5 CMP $0x1,%R10 |
(651) 0x46f8b9 JE 46f945 |
(651) 0x46f8bf CMP $0x2,%R10 |
(651) 0x46f8c3 JE 46f904 |
(651) 0x46f8c5 VMOVSD (%RDX),%XMM1 |
(651) 0x46f8c9 MOV 0x88(%RSP),%R13 |
(651) 0x46f8d1 MOV (%R8,%RCX,8),%R10 |
(651) 0x46f8d5 VMULSD (%R13,%RCX,8),%XMM1,%XMM6 |
(651) 0x46f8dc TEST %R10,%R10 |
(651) 0x46f8df JS 46fb79 |
(651) 0x46f8e5 MOV (%RBX,%R10,8),%R10 |
(651) 0x46f8e9 LEA (%R11,%R10,8),%R13 |
(651) 0x46f8ed VADDSD (%R13),%XMM6,%XMM7 |
(651) 0x46f8f3 VMOVSD %XMM7,(%R13) |
(651) 0x46f8f9 VADDSD %XMM6,%XMM2,%XMM2 |
(651) 0x46f8fd VADDSD %XMM6,%XMM0,%XMM0 |
(651) 0x46f901 INC %RCX |
(651) 0x46f904 VMOVSD (%RDX),%XMM9 |
(651) 0x46f908 MOV 0x88(%RSP),%R13 |
(651) 0x46f910 MOV (%R8,%RCX,8),%R10 |
(651) 0x46f914 VMULSD (%R13,%RCX,8),%XMM9,%XMM10 |
(651) 0x46f91b TEST %R10,%R10 |
(651) 0x46f91e JS 46fb40 |
(651) 0x46f924 MOV (%RBX,%R10,8),%R10 |
(651) 0x46f928 LEA (%R11,%R10,8),%R13 |
(651) 0x46f92c VADDSD (%R13),%XMM10,%XMM5 |
(651) 0x46f932 VMOVSD %XMM5,(%R13) |
(651) 0x46f938 VADDSD %XMM10,%XMM2,%XMM2 |
(651) 0x46f93d VADDSD %XMM10,%XMM0,%XMM0 |
(651) 0x46f942 INC %RCX |
(651) 0x46f945 VMOVSD (%RDX),%XMM13 |
(651) 0x46f949 MOV 0x88(%RSP),%R13 |
(651) 0x46f951 MOV (%R8,%RCX,8),%R10 |
(651) 0x46f955 VMULSD (%R13,%RCX,8),%XMM13,%XMM12 |
(651) 0x46f95c TEST %R10,%R10 |
(651) 0x46f95f JS 46fb10 |
(651) 0x46f965 MOV (%RBX,%R10,8),%R10 |
(651) 0x46f969 LEA (%R11,%R10,8),%R13 |
(651) 0x46f96d VADDSD (%R13),%XMM12,%XMM14 |
(651) 0x46f973 VMOVSD %XMM14,(%R13) |
(651) 0x46f979 INC %RCX |
(651) 0x46f97c VADDSD %XMM12,%XMM2,%XMM2 |
(651) 0x46f981 VADDSD %XMM12,%XMM0,%XMM0 |
(651) 0x46f986 CMP %RCX,0xe8(%RSP) |
(651) 0x46f98e JE 46f432 |
(651) 0x46f994 MOV %R14,(%RSP) |
(651) 0x46f998 MOV 0x88(%RSP),%R13 |
(651) 0x46f9a0 JMP 46fa46 |
0x46f9a5 NOPL (%RAX) |
(652) 0x46f9a8 MOV (%RBX,%R10,8),%R14 |
(652) 0x46f9ac LEA (%R11,%R14,8),%R10 |
(652) 0x46f9b0 VADDSD (%R10),%XMM9,%XMM10 |
(652) 0x46f9b5 VMOVSD %XMM10,(%R10) |
(652) 0x46f9ba LEA 0x1(%RCX),%R14 |
(652) 0x46f9be VMOVSD (%RDX),%XMM14 |
(652) 0x46f9c2 VADDSD %XMM9,%XMM2,%XMM11 |
(652) 0x46f9c7 MOV (%R8,%R14,8),%R10 |
(652) 0x46f9cb VADDSD %XMM9,%XMM0,%XMM13 |
(652) 0x46f9d0 VMULSD (%R13,%R14,8),%XMM14,%XMM15 |
(652) 0x46f9d7 TEST %R10,%R10 |
(652) 0x46f9da JS 46faf0 |
(652) 0x46f9e0 MOV (%RBX,%R10,8),%R14 |
(652) 0x46f9e4 LEA (%R11,%R14,8),%R10 |
(652) 0x46f9e8 VADDSD (%R10),%XMM15,%XMM12 |
(652) 0x46f9ed VMOVSD %XMM12,(%R10) |
(652) 0x46f9f2 LEA 0x2(%RCX),%R14 |
(652) 0x46f9f6 VMOVSD (%RDX),%XMM2 |
(652) 0x46f9fa VADDSD %XMM15,%XMM11,%XMM6 |
(652) 0x46f9ff MOV (%R8,%R14,8),%R10 |
(652) 0x46fa03 VADDSD %XMM15,%XMM13,%XMM7 |
(652) 0x46fa08 VMULSD (%R13,%R14,8),%XMM2,%XMM12 |
(652) 0x46fa0f TEST %R10,%R10 |
(652) 0x46fa12 JS 46fad0 |
(652) 0x46fa18 MOV (%RBX,%R10,8),%R14 |
(652) 0x46fa1c LEA (%R11,%R14,8),%R10 |
(652) 0x46fa20 VADDSD (%R10),%XMM12,%XMM0 |
(652) 0x46fa25 VMOVSD %XMM0,(%R10) |
(652) 0x46fa2a ADD $0x3,%RCX |
(652) 0x46fa2e VADDSD %XMM12,%XMM6,%XMM2 |
(652) 0x46fa33 VADDSD %XMM12,%XMM7,%XMM0 |
(652) 0x46fa38 CMP %RCX,0xe8(%RSP) |
(652) 0x46fa40 JE 46fb30 |
(652) 0x46fa46 VMOVSD (%RDX),%XMM12 |
(652) 0x46fa4a MOV (%R8,%RCX,8),%R14 |
(652) 0x46fa4e VMULSD (%R13,%RCX,8),%XMM12,%XMM1 |
(652) 0x46fa55 TEST %R14,%R14 |
(652) 0x46fa58 JS 46fab0 |
(652) 0x46fa5a MOV (%RBX,%R14,8),%R10 |
(652) 0x46fa5e LEA (%R11,%R10,8),%R14 |
(652) 0x46fa62 VADDSD (%R14),%XMM1,%XMM6 |
(652) 0x46fa67 VMOVSD %XMM6,(%R14) |
(652) 0x46fa6c INC %RCX |
(652) 0x46fa6f VMOVSD (%RDX),%XMM8 |
(652) 0x46fa73 VADDSD %XMM1,%XMM2,%XMM2 |
(652) 0x46fa77 VADDSD %XMM1,%XMM0,%XMM0 |
(652) 0x46fa7b MOV (%R8,%RCX,8),%R10 |
(652) 0x46fa7f VMULSD (%R13,%RCX,8),%XMM8,%XMM9 |
(652) 0x46fa86 TEST %R10,%R10 |
(652) 0x46fa89 JNS 46f9a8 |
(652) 0x46fa8f NOT %R10 |
(652) 0x46fa92 MOV (%R9,%R10,8),%R14 |
(652) 0x46fa96 LEA (%R12,%R14,8),%R10 |
(652) 0x46fa9a VADDSD (%R10),%XMM9,%XMM5 |
(652) 0x46fa9f VMOVSD %XMM5,(%R10) |
(652) 0x46faa4 JMP 46f9ba |
0x46faa9 NOPL (%RAX) |
(652) 0x46fab0 NOT %R14 |
(652) 0x46fab3 MOV (%R9,%R14,8),%R10 |
(652) 0x46fab7 LEA (%R12,%R10,8),%R14 |
(652) 0x46fabb VADDSD (%R14),%XMM1,%XMM7 |
(652) 0x46fac0 VMOVSD %XMM7,(%R14) |
(652) 0x46fac5 JMP 46fa6c |
0x46fac7 NOPW (%RAX,%RAX,1) |
(652) 0x46fad0 NOT %R10 |
(652) 0x46fad3 MOV (%R9,%R10,8),%R14 |
(652) 0x46fad7 LEA (%R12,%R14,8),%R10 |
(652) 0x46fadb VADDSD (%R10),%XMM12,%XMM8 |
(652) 0x46fae0 VMOVSD %XMM8,(%R10) |
(652) 0x46fae5 JMP 46fa2a |
0x46faea NOPW (%RAX,%RAX,1) |
(652) 0x46faf0 NOT %R10 |
(652) 0x46faf3 MOV (%R9,%R10,8),%R14 |
(652) 0x46faf7 LEA (%R12,%R14,8),%R10 |
(652) 0x46fafb VADDSD (%R10),%XMM15,%XMM1 |
(652) 0x46fb00 VMOVSD %XMM1,(%R10) |
(652) 0x46fb05 JMP 46f9f2 |
0x46fb0a NOPW (%RAX,%RAX,1) |
(651) 0x46fb10 NOT %R10 |
(651) 0x46fb13 MOV (%R9,%R10,8),%R10 |
(651) 0x46fb17 LEA (%R12,%R10,8),%R13 |
(651) 0x46fb1b VADDSD (%R13),%XMM12,%XMM15 |
(651) 0x46fb21 VMOVSD %XMM15,(%R13) |
(651) 0x46fb27 JMP 46f979 |
0x46fb2c NOPL (%RAX) |
(651) 0x46fb30 MOV (%RSP),%R14 |
(651) 0x46fb34 JMP 46f432 |
0x46fb39 NOPL (%RAX) |
(651) 0x46fb40 NOT %R10 |
(651) 0x46fb43 MOV (%R9,%R10,8),%R10 |
(651) 0x46fb47 LEA (%R12,%R10,8),%R13 |
(651) 0x46fb4b VADDSD (%R13),%XMM10,%XMM11 |
(651) 0x46fb51 VMOVSD %XMM11,(%R13) |
(651) 0x46fb57 JMP 46f938 |
(648) 0x46fb5c VXORPD %XMM0,%XMM0,%XMM0 |
(648) 0x46fb60 VMOVSD %XMM0,%XMM0,%XMM2 |
(648) 0x46fb64 JMP 46f3a8 |
(648) 0x46fb69 XOR %R8D,%R8D |
(648) 0x46fb6c JMP 46f641 |
(648) 0x46fb71 XOR %R8D,%R8D |
(648) 0x46fb74 JMP 46f7d7 |
(651) 0x46fb79 NOT %R10 |
(651) 0x46fb7c MOV (%R9,%R10,8),%R10 |
(651) 0x46fb80 LEA (%R12,%R10,8),%R13 |
(651) 0x46fb84 VADDSD (%R13),%XMM6,%XMM8 |
(651) 0x46fb8a VMOVSD %XMM8,(%R13) |
(651) 0x46fb90 JMP 46f8f9 |
0x46fb95 MOV %R11,0xb8(%RSP) |
0x46fb9d MOV $0x8,%ESI |
0x46fba2 MOV %RDX,%RDI |
0x46fba5 MOV %R10,0xc0(%RSP) |
0x46fbad VMOVSD %XMM1,0xe0(%RSP) |
0x46fbb6 JMP 46e873 |
0x46fbbb MOV $0x8,%ESI |
0x46fbc0 MOV %RCX,%RDI |
0x46fbc3 MOV %R11,0x98(%RSP) |
0x46fbcb MOV %R10,0xa0(%RSP) |
0x46fbd3 MOV %RDX,0xb8(%RSP) |
0x46fbdb MOV %R8,0xc0(%RSP) |
0x46fbe3 VMOVSD %XMM1,0xe0(%RSP) |
0x46fbec CALL 595800 <hypre_CAlloc> |
0x46fbf1 VMOVSD 0xe0(%RSP),%XMM1 |
0x46fbfa MOV 0xc0(%RSP),%R8 |
0x46fc02 MOV 0xb8(%RSP),%RDX |
0x46fc0a MOV 0xa0(%RSP),%R10 |
0x46fc12 MOV %RAX,%R15 |
0x46fc15 MOV 0x98(%RSP),%R11 |
0x46fc1d JMP 46e849 |
0x46fc22 MOV $0x8,%ESI |
0x46fc27 MOV %R14,%RDI |
0x46fc2a MOV %R11,0x90(%RSP) |
0x46fc32 MOV %R10,0x98(%RSP) |
0x46fc3a MOV %RCX,0xa0(%RSP) |
0x46fc42 MOV %RDX,0xb8(%RSP) |
0x46fc4a MOV %R8,0xc0(%RSP) |
0x46fc52 VMOVSD %XMM1,0xe0(%RSP) |
0x46fc5b CALL 595800 <hypre_CAlloc> |
0x46fc60 VMOVSD 0xe0(%RSP),%XMM1 |
0x46fc69 MOV 0xc0(%RSP),%R8 |
0x46fc71 MOV 0xb8(%RSP),%RDX |
0x46fc79 MOV 0xa0(%RSP),%RCX |
0x46fc81 MOV %RAX,0x118(%RSP) |
0x46fc89 MOV 0x98(%RSP),%R10 |
0x46fc91 MOV 0x90(%RSP),%R11 |
0x46fc99 JMP 46e83d |
0x46fc9e MOV %RSI,%RDI |
0x46fca1 MOV $0x8,%ESI |
0x46fca6 MOV %R11,0x98(%RSP) |
0x46fcae MOV %R10,0xa0(%RSP) |
0x46fcb6 MOV %RCX,0xb8(%RSP) |
0x46fcbe MOV %RDX,0xc0(%RSP) |
0x46fcc6 MOV %R8,0xe0(%RSP) |
0x46fcce VMOVSD %XMM1,0x118(%RSP) |
0x46fcd7 CALL 595800 <hypre_CAlloc> |
0x46fcdc VMOVSD 0x118(%RSP),%XMM1 |
0x46fce5 MOV 0xe0(%RSP),%R8 |
0x46fced MOV 0xc0(%RSP),%RDX |
0x46fcf5 MOV 0xb8(%RSP),%RCX |
0x46fcfd MOV %RAX,0x150(%RSP) |
0x46fd05 MOV 0xa0(%RSP),%R10 |
0x46fd0d MOV 0x98(%RSP),%R11 |
0x46fd15 JMP 46e828 |
0x46fd1a NOPW (%RAX,%RAX,1) |
Path / |
Source file and lines | par_multi_interp.c:1737-1881 |
Module | exec |
nb instructions | 260 |
nb uops | 276 |
loop length | 1576 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 4 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 44 |
micro-operation queue | 46.00 cycles |
front end | 46.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.80 | 6.80 | 30.67 | 30.67 | 45.00 | 6.80 | 6.80 | 45.00 | 45.00 | 45.00 | 6.80 | 30.67 |
cycles | 6.80 | 8.00 | 30.67 | 30.67 | 45.00 | 6.80 | 6.80 | 45.00 | 45.00 | 45.00 | 6.80 | 30.67 |
Cycles executing div or sqrt instructions | 10.00 |
FE+BE cycles | 45.09 |
Stall cycles | 0.93 |
RS full (events) | 4.18 |
Front-end | 46.00 |
Dispatch | 45.00 |
DIV/SQRT | 10.00 |
Overall L1 | 46.00 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 5% |
all | 6% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 1% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 11% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 13% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 12% |
other | 13% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x20,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x160,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x148(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x138(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x130(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x128(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x108(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x100(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x148(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xf8(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xf0(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe8(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RDI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x138(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x110(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x140(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RBX,0x130(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x120(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,0x100(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x118(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xd8(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc8(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R15,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x68(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa8(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x98(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RBX,0xf8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x80(%RDI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x60(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x58(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x50(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R15,0x128(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x48(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,0xf0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa0(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R12,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x90(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R13,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x78(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14,0xd0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x88(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x70(%RDI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RBX,0x120(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x40(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x20(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x108(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,0x140(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x110(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RSI,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 46fc9e <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x167e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOVQ $0,0x150(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %R14,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 46fc22 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1602> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOVQ $0,0x118(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 46fbbb <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x159b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %RDX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 46fb95 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1575> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R11,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R10,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 595800 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
CMPQ $0,0x158(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
VMOVSD 0xe0(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xc0(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JLE 46e8ef <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x2cf> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x158(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x150(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVSD %XMM1,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SAL $0x3,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %RAX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4110a0 <memset@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0xe0(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %R14,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 46e940 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x320> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x118(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (,%R14,8),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVSD %XMM1,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4110a0 <memset@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0x158(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 598830 <hypre_GetThreadNum> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 598820 <hypre_NumActiveThreads> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xe8(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xf8(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RAX,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x148(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x148(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX,%R8,8),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (,%R8,8),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD 0x158(%RSP),%XMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CQTO | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
IDIV %R9 | 5 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 10 |
ADD %RCX,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
DEC %R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R11,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xb8(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %RAX,%R10 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %R10,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RCX,%R10,1),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0xc0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R9,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVNE %RAX,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP %RSI,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 46f82e <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x120e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xb0(%RSP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVQ 0x13034b(%RIP),%XMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM3,%XMM3,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R14,%R8,8),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R14,%RSI,8),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0xe8(%RSP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0xf8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xa8(%RSP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DEC %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R9,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
MOV 0x150(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CALL 5958c0 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x118(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CALL 5958c0 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %R15,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 5958c0 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
JMP 5958c0 <hypre_Free> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R11,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R10,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 46e873 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x253> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R11,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 595800 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0xe0(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x98(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 46e849 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x229> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R11,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 595800 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0xe0(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa0(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x118(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x98(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x90(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 46e83d <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x21d> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV %RSI,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R11,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0x118(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 595800 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0x118(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x150(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x98(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 46e828 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x208> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | par_multi_interp.c:1737-1881 |
Module | exec |
nb instructions | 260 |
nb uops | 276 |
loop length | 1576 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 4 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 44 |
micro-operation queue | 46.00 cycles |
front end | 46.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.80 | 6.80 | 30.67 | 30.67 | 45.00 | 6.80 | 6.80 | 45.00 | 45.00 | 45.00 | 6.80 | 30.67 |
cycles | 6.80 | 8.00 | 30.67 | 30.67 | 45.00 | 6.80 | 6.80 | 45.00 | 45.00 | 45.00 | 6.80 | 30.67 |
Cycles executing div or sqrt instructions | 10.00 |
FE+BE cycles | 45.09 |
Stall cycles | 0.93 |
RS full (events) | 4.18 |
Front-end | 46.00 |
Dispatch | 45.00 |
DIV/SQRT | 10.00 |
Overall L1 | 46.00 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 5% |
all | 6% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 1% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 11% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 13% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 12% |
other | 13% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x20,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x160,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x148(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x138(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x130(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x128(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x108(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x100(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x148(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xf8(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xf0(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe8(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RDI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x138(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x110(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x140(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RBX,0x130(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x120(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,0x100(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x118(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xd8(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc8(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R15,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x68(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa8(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x98(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RBX,0xf8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x80(%RDI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x60(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x58(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x50(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R15,0x128(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x48(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,0xf0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa0(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R12,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x90(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R13,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x78(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14,0xd0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x88(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x70(%RDI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RBX,0x120(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x40(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x20(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x108(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,0x140(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x110(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RSI,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 46fc9e <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x167e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOVQ $0,0x150(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %R14,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 46fc22 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1602> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOVQ $0,0x118(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 46fbbb <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x159b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %RDX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 46fb95 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1575> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R11,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R10,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 595800 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
CMPQ $0,0x158(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
VMOVSD 0xe0(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xc0(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JLE 46e8ef <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x2cf> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x158(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x150(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVSD %XMM1,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SAL $0x3,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %RAX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4110a0 <memset@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0xe0(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %R14,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 46e940 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x320> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x118(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (,%R14,8),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVSD %XMM1,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4110a0 <memset@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0x158(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 598830 <hypre_GetThreadNum> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 598820 <hypre_NumActiveThreads> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xe8(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xf8(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RAX,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x148(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x148(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX,%R8,8),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (,%R8,8),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD 0x158(%RSP),%XMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CQTO | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
IDIV %R9 | 5 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 10 |
ADD %RCX,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
DEC %R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R11,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xb8(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %RAX,%R10 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %R10,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RCX,%R10,1),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0xc0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R9,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVNE %RAX,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP %RSI,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 46f82e <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x120e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xb0(%RSP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVQ 0x13034b(%RIP),%XMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM3,%XMM3,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R14,%R8,8),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R14,%RSI,8),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0xe8(%RSP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0xf8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xa8(%RSP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DEC %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R9,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
MOV 0x150(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CALL 5958c0 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x118(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CALL 5958c0 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %R15,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 5958c0 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
JMP 5958c0 <hypre_Free> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R11,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R10,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 46e873 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x253> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R11,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 595800 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0xe0(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x98(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 46e849 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x229> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R11,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 595800 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0xe0(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa0(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x118(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x98(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x90(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 46e83d <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x21d> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV %RSI,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R11,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0x118(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 595800 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0x118(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x150(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x98(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 46e828 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x208> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼hypre_BoomerAMGBuildMultipass._omp_fn.10– | 1.45 | 0.31 |
▼Loop 648 - par_multi_interp.c:1774-1876 - exec– | 0.19 | 0.03 |
▼Loop 653 - par_multi_interp.c:1811-1837 - exec– | 0.8 | 0.12 |
○Loop 654 - par_multi_interp.c:1824-1830 - exec | 0 | 0 |
○Loop 655 - par_multi_interp.c:1816-1822 - exec | 0 | 0 |
○Loop 657 - par_multi_interp.c:1799-1803 - exec | 0.46 | 0.07 |
○Loop 656 - par_multi_interp.c:1805-1809 - exec | 0 | 0 |
○Loop 658 - par_multi_interp.c:1792-1797 - exec | 0 | 0 |
○Loop 649 - par_multi_interp.c:1875-1876 - exec | 0 | 0 |
▼Loop 651 - par_multi_interp.c:1840-1867 - exec– | 0 | 0 |
○Loop 652 - par_multi_interp.c:1851-1860 - exec | 0 | 0 |
○Loop 650 - par_multi_interp.c:1873-1874 - exec | 0 | 0 |
○Loop 659 - par_multi_interp.c:1782-1787 - exec | 0 | 0 |