Function: hypre_ParCSRRelaxThreads.extracted.57 | Module: exec | Source: ams.c:3662-3682 | Coverage: 31.84% |
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Function: hypre_ParCSRRelaxThreads.extracted.57 | Module: exec | Source: ams.c:3662-3682 | Coverage: 31.84% |
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/scratch_na/users/xoserete/qaas_runs/171-172-8218/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3662 - 3682 |
-------------------------------------------------------------------------------- |
3662: #pragma omp parallel for private(i,ii,jj,res) HYPRE_SMP_SCHEDULE |
3663: #endif |
3664: for (i = 0; i < n; i++) |
3665: { |
3666: /*----------------------------------------------------------- |
3667: * If diagonal is nonzero, relax point i; otherwise, skip it. |
3668: *-----------------------------------------------------------*/ |
3669: if (A_diag_data[A_diag_i[i]] != zero) |
3670: { |
3671: res = f_data[i]; |
3672: for (jj = A_diag_i[i]; jj < A_diag_i[i+1]; jj++) |
3673: { |
3674: ii = A_diag_j[jj]; |
3675: res -= A_diag_data[jj] * Vtemp_data[ii]; |
3676: } |
3677: for (jj = A_offd_i[i]; jj < A_offd_i[i+1]; jj++) |
3678: { |
3679: ii = A_offd_j[jj]; |
3680: res -= A_offd_data[jj] * Vext_data[ii]; |
3681: } |
3682: u_data[i] += (relax_weight*res)/l1_norms[i]; |
0x4aa660 PUSH %RBP |
0x4aa661 MOV %RSP,%RBP |
0x4aa664 PUSH %R15 |
0x4aa666 PUSH %R14 |
0x4aa668 PUSH %R13 |
0x4aa66a PUSH %R12 |
0x4aa66c PUSH %RBX |
0x4aa66d SUB $0x68,%RSP |
0x4aa671 MOV 0x48(%RBP),%RBX |
0x4aa675 MOV 0x40(%RBP),%R13 |
0x4aa679 MOV 0x38(%RBP),%RAX |
0x4aa67d MOV %RAX,-0x80(%RBP) |
0x4aa681 MOV 0x30(%RBP),%RAX |
0x4aa685 MOV %RAX,-0x78(%RBP) |
0x4aa689 MOV 0x28(%RBP),%RAX |
0x4aa68d MOV %RAX,-0x38(%RBP) |
0x4aa691 MOV 0x20(%RBP),%R14 |
0x4aa695 MOV 0x18(%RBP),%RAX |
0x4aa699 MOV %RAX,-0x70(%RBP) |
0x4aa69d MOV 0x10(%RBP),%R12 |
0x4aa6a1 MOVL $0,-0x48(%RBP) |
0x4aa6a8 MOV %R9,-0x30(%RBP) |
0x4aa6ac MOV %R8,%R15 |
0x4aa6af MOV %RCX,-0x40(%RBP) |
0x4aa6b3 MOV %RDX,-0x68(%RBP) |
0x4aa6b7 MOV (%RDI),%ESI |
0x4aa6b9 MOVQ $0,-0x58(%RBP) |
0x4aa6c1 MOVQ $0x1,-0x90(%RBP) |
0x4aa6cc SUB $0x8,%RSP |
0x4aa6d0 LEA -0x90(%RBP),%RAX |
0x4aa6d7 LEA -0x48(%RBP),%RCX |
0x4aa6db LEA -0x58(%RBP),%R8 |
0x4aa6df LEA 0x60(%RBP),%R9 |
0x4aa6e3 MOV $0x735b10,%EDI |
0x4aa6e8 MOV %ESI,-0x44(%RBP) |
0x4aa6eb MOV $0x22,%EDX |
0x4aa6f0 PUSH $0x1 |
0x4aa6f2 PUSH $0x1 |
0x4aa6f4 PUSH %RAX |
0x4aa6f5 CALL 40fee0 <__kmpc_for_static_init_8@plt> |
0x4aa6fa MOV -0x30(%RBP),%RCX |
0x4aa6fe ADD $0x20,%RSP |
0x4aa702 MOV -0x58(%RBP),%R11 |
0x4aa706 MOV 0x60(%RBP),%RAX |
0x4aa70a SUB %R11,%RAX |
0x4aa70d MOV %RAX,-0x88(%RBP) |
0x4aa714 JAE 4aa734 |
0x4aa716 MOV $0x735b30,%EDI |
0x4aa71b MOV -0x44(%RBP),%ESI |
0x4aa71e ADD $0x68,%RSP |
0x4aa722 POP %RBX |
0x4aa723 POP %R12 |
0x4aa725 POP %R13 |
0x4aa727 POP %R14 |
0x4aa729 POP %R15 |
0x4aa72b POP %RBP |
0x4aa72c VZEROUPPER |
0x4aa72f JMP 40fc30 |
0x4aa734 VMOVSD -0x40(%RBP),%XMM0 |
0x4aa739 XOR %EDX,%EDX |
0x4aa73b VXORPD %XMM1,%XMM1,%XMM1 |
0x4aa73f MOV %R11,-0x50(%RBP) |
0x4aa743 JMP 4aa77f |
0x4aa745 NOPW %CS:(%RAX,%RAX,1) |
(3223) 0x4aa750 VMULSD %XMM0,%XMM2,%XMM2 |
(3223) 0x4aa754 MOV -0x68(%RBP),%RAX |
(3223) 0x4aa758 VDIVSD (%RAX,%RSI,8),%XMM2,%XMM2 |
(3223) 0x4aa75d MOV -0x78(%RBP),%RAX |
(3223) 0x4aa761 VADDSD (%RAX,%RSI,8),%XMM2,%XMM2 |
(3223) 0x4aa766 VMOVSD %XMM2,(%RAX,%RSI,8) |
(3223) 0x4aa76b MOV -0x40(%RBP),%RDX |
(3223) 0x4aa76f LEA 0x1(%RDX),%RAX |
(3223) 0x4aa773 CMP -0x88(%RBP),%RDX |
(3223) 0x4aa77a MOV %RAX,%RDX |
(3223) 0x4aa77d JE 4aa716 |
(3223) 0x4aa77f LEA (%R11,%RDX,1),%RSI |
(3223) 0x4aa783 MOV (%RCX,%RSI,8),%R9 |
(3223) 0x4aa787 VUCOMISD (%R15,%R9,8),%XMM1 |
(3223) 0x4aa78d JE 4aa76f |
(3223) 0x4aa78f MOV -0x80(%RBP),%RAX |
(3223) 0x4aa793 VMOVSD (%RAX,%RSI,8),%XMM2 |
(3223) 0x4aa798 MOV 0x8(%RCX,%RSI,8),%RDI |
(3223) 0x4aa79d MOV %RDI,%R10 |
(3223) 0x4aa7a0 SUB %R9,%R10 |
(3223) 0x4aa7a3 MOV %RDX,-0x40(%RBP) |
(3223) 0x4aa7a7 JLE 4aa820 |
(3223) 0x4aa7a9 MOV %R10,%R8 |
(3223) 0x4aa7ac AND $-0x4,%R8 |
(3223) 0x4aa7b0 JE 4aa826 |
(3223) 0x4aa7b2 LEA -0x1(%R8),%R11 |
(3223) 0x4aa7b6 LEA (%R15,%R9,8),%RAX |
(3223) 0x4aa7ba LEA (%R12,%R9,8),%RCX |
(3223) 0x4aa7be VXORPD %XMM3,%XMM3,%XMM3 |
(3223) 0x4aa7c2 XOR %EDX,%EDX |
(3223) 0x4aa7c4 NOPW %CS:(%RAX,%RAX,1) |
(3227) 0x4aa7d0 VMOVUPD (%RCX,%RDX,8),%YMM4 |
(3227) 0x4aa7d5 VXORPD %XMM5,%XMM5,%XMM5 |
(3227) 0x4aa7d9 KXNORW %K0,%K0,%K1 |
(3227) 0x4aa7dd VGATHERQPD (%R13,%YMM4,8),%YMM5{%K1} |
(3227) 0x4aa7e5 VFNMADD231PD (%RAX,%RDX,8),%YMM5,%YMM3 |
(3227) 0x4aa7eb ADD $0x4,%RDX |
(3227) 0x4aa7ef CMP %R11,%RDX |
(3227) 0x4aa7f2 JBE 4aa7d0 |
(3223) 0x4aa7f4 VEXTRACTF128 $0x1,%YMM3,%XMM4 |
(3223) 0x4aa7fa VADDPD %XMM4,%XMM3,%XMM3 |
(3223) 0x4aa7fe VSHUFPD $0x1,%XMM3,%XMM3,%XMM4 |
(3223) 0x4aa803 VADDSD %XMM4,%XMM3,%XMM3 |
(3223) 0x4aa807 VADDSD %XMM3,%XMM2,%XMM2 |
(3223) 0x4aa80b CMP %R8,%R10 |
(3223) 0x4aa80e MOV -0x38(%RBP),%RDX |
(3223) 0x4aa812 MOV -0x30(%RBP),%RCX |
(3223) 0x4aa816 MOV -0x50(%RBP),%R11 |
(3223) 0x4aa81a JNE 4aa82d |
(3223) 0x4aa81c JMP 4aa849 |
0x4aa81e XCHG %AX,%AX |
(3223) 0x4aa820 MOV -0x38(%RBP),%RDX |
(3223) 0x4aa824 JMP 4aa849 |
(3223) 0x4aa826 XOR %R8D,%R8D |
(3223) 0x4aa829 MOV -0x38(%RBP),%RDX |
(3223) 0x4aa82d ADD %R9,%R8 |
(3226) 0x4aa830 MOV (%R12,%R8,8),%RAX |
(3226) 0x4aa834 VMOVSD (%R13,%RAX,8),%XMM3 |
(3226) 0x4aa83b VFNMADD231SD (%R15,%R8,8),%XMM3,%XMM2 |
(3226) 0x4aa841 INC %R8 |
(3226) 0x4aa844 CMP %R8,%RDI |
(3226) 0x4aa847 JNE 4aa830 |
(3223) 0x4aa849 MOV -0x70(%RBP),%RAX |
(3223) 0x4aa84d MOV (%RAX,%RSI,8),%R9 |
(3223) 0x4aa851 MOV 0x8(%RAX,%RSI,8),%RDI |
(3223) 0x4aa856 MOV %RDI,%R10 |
(3223) 0x4aa859 SUB %R9,%R10 |
(3223) 0x4aa85c JLE 4aa750 |
(3223) 0x4aa862 MOV %R10,%R8 |
(3223) 0x4aa865 AND $-0x4,%R8 |
(3223) 0x4aa869 JE 4aa8e2 |
(3223) 0x4aa86b LEA -0x1(%R8),%R11 |
(3223) 0x4aa86f LEA (%R14,%R9,8),%RAX |
(3223) 0x4aa873 MOV %R9,-0x60(%RBP) |
(3223) 0x4aa877 LEA (%RDX,%R9,8),%RCX |
(3223) 0x4aa87b VXORPD %XMM3,%XMM3,%XMM3 |
(3223) 0x4aa87f XOR %R9D,%R9D |
(3223) 0x4aa882 NOPW %CS:(%RAX,%RAX,1) |
(3225) 0x4aa890 VMOVUPD (%RCX,%R9,8),%YMM4 |
(3225) 0x4aa896 VXORPD %XMM5,%XMM5,%XMM5 |
(3225) 0x4aa89a KXNORW %K0,%K0,%K1 |
(3225) 0x4aa89e VGATHERQPD (%RBX,%YMM4,8),%YMM5{%K1} |
(3225) 0x4aa8a5 VFNMADD231PD (%RAX,%R9,8),%YMM5,%YMM3 |
(3225) 0x4aa8ab ADD $0x4,%R9 |
(3225) 0x4aa8af CMP %R11,%R9 |
(3225) 0x4aa8b2 JBE 4aa890 |
(3223) 0x4aa8b4 VEXTRACTF128 $0x1,%YMM3,%XMM4 |
(3223) 0x4aa8ba VADDPD %XMM4,%XMM3,%XMM3 |
(3223) 0x4aa8be VSHUFPD $0x1,%XMM3,%XMM3,%XMM4 |
(3223) 0x4aa8c3 VADDSD %XMM4,%XMM3,%XMM3 |
(3223) 0x4aa8c7 VADDSD %XMM3,%XMM2,%XMM2 |
(3223) 0x4aa8cb CMP %R8,%R10 |
(3223) 0x4aa8ce MOV -0x30(%RBP),%RCX |
(3223) 0x4aa8d2 MOV -0x50(%RBP),%R11 |
(3223) 0x4aa8d6 MOV -0x60(%RBP),%R9 |
(3223) 0x4aa8da JE 4aa750 |
(3223) 0x4aa8e0 JMP 4aa8e5 |
(3223) 0x4aa8e2 XOR %R8D,%R8D |
(3223) 0x4aa8e5 ADD %R9,%R8 |
(3223) 0x4aa8e8 NOPL (%RAX,%RAX,1) |
(3224) 0x4aa8f0 MOV (%RDX,%R8,8),%RAX |
(3224) 0x4aa8f4 VMOVSD (%RBX,%RAX,8),%XMM3 |
(3224) 0x4aa8f9 VFNMADD231SD (%R14,%R8,8),%XMM3,%XMM2 |
(3224) 0x4aa8ff INC %R8 |
(3224) 0x4aa902 CMP %R8,%RDI |
(3224) 0x4aa905 JNE 4aa8f0 |
(3223) 0x4aa907 JMP 4aa750 |
0x4aa90c NOPL (%RAX) |
Path / |
Source file and lines | ams.c:3662-3682 |
Module | exec |
nb instructions | 66 |
nb uops | 68 |
loop length | 246 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 22 |
micro-operation queue | 11.33 cycles |
front end | 11.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.10 | 1.00 | 6.67 | 6.67 | 11.50 | 1.00 | 0.90 | 11.50 | 11.50 | 11.50 | 1.00 | 6.67 |
cycles | 1.10 | 1.00 | 6.67 | 6.67 | 11.50 | 1.00 | 0.90 | 11.50 | 11.50 | 11.50 | 1.00 | 6.67 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 11.59 |
Stall cycles | 0.08-0.08 |
RS full (events) | 0.27-0.26 |
Front-end | 11.33 |
Dispatch | 11.50 |
Overall L1 | 11.50 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 25% |
all | 50% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 7% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 40% |
all | 11% |
load | 10% |
store | 10% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 18% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 11% |
load | 11% |
store | 10% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 15% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x68,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x48(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x40(%RBP),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x80(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x30(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x78(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x28(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x20(%RBP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x70(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVL $0,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RCX,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,-0x68(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVQ $0,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVQ $0x1,-0x90(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x90(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x48(%RBP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x58(%RBP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x60(%RBP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x735b10,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,-0x44(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x22,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 40fee0 <__kmpc_for_static_init_8@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x30(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x20,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x58(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x60(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %R11,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RAX,-0x88(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JAE 4aa734 <hypre_ParCSRRelaxThreads.extracted.57+0xd4> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x735b30,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x44(%RBP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x68,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 40fc30 <__kmpc_for_static_fini@plt> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
VMOVSD -0x40(%RBP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VXORPD %XMM1,%XMM1,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R11,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 4aa77f <hypre_ParCSRRelaxThreads.extracted.57+0x11f> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | ams.c:3662-3682 |
Module | exec |
nb instructions | 66 |
nb uops | 68 |
loop length | 246 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 22 |
micro-operation queue | 11.33 cycles |
front end | 11.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.10 | 1.00 | 6.67 | 6.67 | 11.50 | 1.00 | 0.90 | 11.50 | 11.50 | 11.50 | 1.00 | 6.67 |
cycles | 1.10 | 1.00 | 6.67 | 6.67 | 11.50 | 1.00 | 0.90 | 11.50 | 11.50 | 11.50 | 1.00 | 6.67 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 11.59 |
Stall cycles | 0.08-0.08 |
RS full (events) | 0.27-0.26 |
Front-end | 11.33 |
Dispatch | 11.50 |
Overall L1 | 11.50 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 25% |
all | 50% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 7% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 40% |
all | 11% |
load | 10% |
store | 10% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 18% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 11% |
load | 11% |
store | 10% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 15% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x68,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x48(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x40(%RBP),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x80(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x30(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x78(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x28(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x20(%RBP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x70(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVL $0,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RCX,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,-0x68(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVQ $0,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVQ $0x1,-0x90(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x90(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x48(%RBP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x58(%RBP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x60(%RBP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x735b10,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,-0x44(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x22,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 40fee0 <__kmpc_for_static_init_8@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x30(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x20,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x58(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x60(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %R11,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RAX,-0x88(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JAE 4aa734 <hypre_ParCSRRelaxThreads.extracted.57+0xd4> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x735b30,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x44(%RBP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x68,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 40fc30 <__kmpc_for_static_fini@plt> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
VMOVSD -0x40(%RBP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VXORPD %XMM1,%XMM1,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R11,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 4aa77f <hypre_ParCSRRelaxThreads.extracted.57+0x11f> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼hypre_ParCSRRelaxThreads.extracted.57– | 31.84 | 6.89 |
▼Loop 3223 - ams.c:3662-3682 - exec– | 3.84 | 0.75 |
○Loop 3227 - ams.c:3672-3675 - exec | 25.09 | 4.91 |
○Loop 3226 - ams.c:3672-3675 - exec | 2.88 | 0.56 |
○Loop 3225 - ams.c:3677-3680 - exec | 0.03 | 0.01 |
○Loop 3224 - ams.c:3677-3680 - exec | 0 | 0 |