Function: hypre_BoomerAMGBuildMultipass._omp_fn.9 | Module: exec | Source: par_multi_interp.c:1575-1663 [...] | Coverage: 0.33% |
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Function: hypre_BoomerAMGBuildMultipass._omp_fn.9 | Module: exec | Source: par_multi_interp.c:1575-1663 [...] | Coverage: 0.33% |
---|
/scratch_na/users/xoserete/qaas_runs/171-172-8218/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1575 - 1663 |
-------------------------------------------------------------------------------- |
1575: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa) |
[...] |
1584: tmp_marker = NULL; |
1585: if (n_fine) |
1586: { tmp_marker = hypre_CTAlloc(HYPRE_Int,n_fine); } |
1587: tmp_marker_offd = NULL; |
1588: if (num_cols_offd) |
1589: { tmp_marker_offd = hypre_CTAlloc(HYPRE_Int,num_cols_offd); } |
1590: for (i=0; i < n_fine; i++) |
1591: { tmp_marker[i] = -1; } |
1592: for (i=0; i < num_cols_offd; i++) |
1593: { tmp_marker_offd[i] = -1; } |
1594: |
1595: /* Compute this thread's range of pass_length */ |
1596: my_thread_num = hypre_GetThreadNum(); |
1597: num_threads = hypre_NumActiveThreads(); |
1598: thread_start = pass_pointer[1] + (pass_length/num_threads)*my_thread_num; |
1599: if (my_thread_num == num_threads-1) |
1600: { thread_stop = pass_pointer[1] + pass_length; } |
1601: else |
1602: { thread_stop = pass_pointer[1] + (pass_length/num_threads)*(my_thread_num+1); } |
1603: |
1604: /* determine P for points of pass 1, i.e. neighbors of coarse points */ |
1605: for (i=thread_start; i < thread_stop; i++) |
1606: { |
1607: i1 = pass_array[i]; |
1608: sum_C = 0; |
1609: sum_N = 0; |
1610: j_start = P_diag_start[i1]; |
1611: j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1]; |
1612: for (j=j_start; j < j_end; j++) |
1613: { |
1614: k1 = P_diag_pass[1][j]; |
1615: tmp_marker[C_array[k1]] = i1; |
1616: } |
1617: cnt = P_diag_i[i1]; |
1618: for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++) |
1619: { |
1620: j1 = A_diag_j[j]; |
1621: if (CF_marker[j1] != -3 && |
1622: (num_functions == 1 || dof_func[i1] == dof_func[j1])) |
1623: sum_N += A_diag_data[j]; |
1624: if (j1 != -1 && tmp_marker[j1] == i1) |
1625: { |
1626: P_diag_data[cnt] = A_diag_data[j]; |
1627: P_diag_j[cnt++] = fine_to_coarse[j1]; |
1628: sum_C += A_diag_data[j]; |
1629: } |
1630: } |
1631: j_start = P_offd_start[i1]; |
1632: j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1]; |
1633: for (j=j_start; j < j_end; j++) |
1634: { |
1635: k1 = P_offd_pass[1][j]; |
1636: tmp_marker_offd[C_array_offd[k1]] = i1; |
1637: } |
1638: cnt_offd = P_offd_i[i1]; |
1639: for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++) |
1640: { |
1641: if (col_offd_S_to_A) |
1642: j1 = map_A_to_S[A_offd_j[j]]; |
1643: else |
1644: j1 = A_offd_j[j]; |
1645: if (CF_marker_offd[j1] != -3 && |
1646: (num_functions == 1 || dof_func[i1] == dof_func_offd[j1])) |
1647: sum_N += A_offd_data[j]; |
1648: if (j1 != -1 && tmp_marker_offd[j1] == i1) |
1649: { |
1650: P_offd_data[cnt_offd] = A_offd_data[j]; |
1651: P_offd_j[cnt_offd++] = map_S_to_new[j1]; |
1652: sum_C += A_offd_data[j]; |
1653: } |
1654: } |
1655: diagonal = A_diag_data[A_diag_i[i1]]; |
1656: if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal); |
1657: for (j=P_diag_i[i1]; j < cnt; j++) |
1658: P_diag_data[j] *= alfa; |
1659: for (j=P_offd_i[i1]; j < cnt_offd; j++) |
1660: P_offd_data[j] *= alfa; |
1661: } |
1662: hypre_TFree(tmp_marker); |
1663: hypre_TFree(tmp_marker_offd); |
0x46fd20 PUSH %RBP |
0x46fd21 MOV %RSP,%RBP |
0x46fd24 PUSH %R15 |
0x46fd26 PUSH %R14 |
0x46fd28 PUSH %R13 |
0x46fd2a PUSH %R12 |
0x46fd2c PUSH %RBX |
0x46fd2d AND $-0x20,%RSP |
0x46fd31 SUB $0x100,%RSP |
0x46fd38 MOV 0xf8(%RDI),%RAX |
0x46fd3f MOV 0xe0(%RDI),%RCX |
0x46fd46 MOV 0xd8(%RDI),%RSI |
0x46fd4d MOV 0xd0(%RDI),%R8 |
0x46fd54 MOV 0xc8(%RDI),%R9 |
0x46fd5b MOV 0xc0(%RDI),%R10 |
0x46fd62 MOV %RAX,0xe0(%RSP) |
0x46fd6a MOV 0xb8(%RDI),%R11 |
0x46fd71 MOV 0xb0(%RDI),%R12 |
0x46fd78 MOV %RCX,0x8(%RSP) |
0x46fd7d MOV 0xa8(%RDI),%R13 |
0x46fd84 MOV 0x90(%RDI),%RAX |
0x46fd8b MOV %RSI,0xa0(%RSP) |
0x46fd93 MOV 0xf0(%RDI),%RDX |
0x46fd9a MOV 0xe8(%RDI),%RBX |
0x46fda1 MOV %R8,0x38(%RSP) |
0x46fda6 MOV %R9,0x30(%RSP) |
0x46fdab MOV 0xa0(%RDI),%R14 |
0x46fdb2 MOV %R10,0x70(%RSP) |
0x46fdb7 MOV 0x98(%RDI),%R15 |
0x46fdbe MOV %R11,0x68(%RSP) |
0x46fdc3 MOV %R12,0xd8(%RSP) |
0x46fdcb MOV %R13,0x80(%RSP) |
0x46fdd3 MOV %RAX,0xc8(%RSP) |
0x46fddb MOV %RDX,0xa8(%RSP) |
0x46fde3 MOV 0x88(%RDI),%RDX |
0x46fdea MOV 0x80(%RDI),%RCX |
0x46fdf1 MOV 0x78(%RDI),%RSI |
0x46fdf5 MOV 0x68(%RDI),%R8 |
0x46fdf9 MOV 0x60(%RDI),%R9 |
0x46fdfd MOV %RDX,0x28(%RSP) |
0x46fe02 MOV 0x40(%RDI),%RAX |
0x46fe06 MOV 0x38(%RDI),%RDX |
0x46fe0a MOV %RCX,0x98(%RSP) |
0x46fe12 MOV 0x70(%RDI),%R10 |
0x46fe16 MOV 0x30(%RDI),%RCX |
0x46fe1a MOV %RSI,0x60(%RSP) |
0x46fe1f MOV 0x58(%RDI),%R11 |
0x46fe23 MOV 0x28(%RDI),%RSI |
0x46fe27 MOV %R8,0x90(%RSP) |
0x46fe2f MOV 0x50(%RDI),%R12 |
0x46fe33 MOV 0x20(%RDI),%R8 |
0x46fe37 MOV %R9,0x58(%RSP) |
0x46fe3c MOV 0x48(%RDI),%R13 |
0x46fe40 MOV 0x18(%RDI),%R9 |
0x46fe44 MOV %RAX,0x50(%RSP) |
0x46fe49 MOV %RDX,0xe8(%RSP) |
0x46fe51 MOV 0x10(%RDI),%RAX |
0x46fe55 MOV 0x8(%RDI),%RDX |
0x46fe59 MOV (%RDI),%RDI |
0x46fe5c MOV %RCX,0x20(%RSP) |
0x46fe61 MOV %RSI,0x48(%RSP) |
0x46fe66 MOV %R8,0xf8(%RSP) |
0x46fe6e MOV %R9,0x18(%RSP) |
0x46fe73 MOV %RAX,0xd0(%RSP) |
0x46fe7b MOV %RDX,0xf0(%RSP) |
0x46fe83 MOV %RDI,0x10(%RSP) |
0x46fe88 TEST %RBX,%RBX |
0x46fe8b JNE 470a6e |
0x46fe91 TEST %R12,%R12 |
0x46fe94 JNE 470bf0 |
0x46fe9a XOR %EBX,%EBX |
0x46fe9c XOR %R12D,%R12D |
0x46fe9f MOV %R11,0x88(%RSP) |
0x46fea7 MOV %R10,0xb0(%RSP) |
0x46feaf VMOVSD %XMM1,0xb8(%RSP) |
0x46feb8 CALL 598830 <hypre_GetThreadNum> |
0x46febd MOV %RAX,0xc0(%RSP) |
0x46fec5 CALL 598820 <hypre_NumActiveThreads> |
0x46feca MOV 0xc0(%RSP),%R10 |
0x46fed2 MOV 0xd8(%RSP),%R8 |
0x46feda MOV %RAX,%R9 |
0x46fedd MOV 0xe0(%RSP),%RAX |
0x46fee5 MOV 0xe0(%RSP),%RSI |
0x46feed MOV %R10,%R11 |
0x46fef0 MOV 0x8(%R8),%RCX |
0x46fef4 VMOVSD 0xb8(%RSP),%XMM11 |
0x46fefd CQTO |
0x46feff IDIV %R9 |
0x46ff02 ADD %RCX,%RSI |
0x46ff05 DEC %R9 |
0x46ff08 MOV %RSI,%R8 |
0x46ff0b IMUL %RAX,%R11 |
0x46ff0f ADD %R11,%RAX |
0x46ff12 LEA (%RCX,%R11,1),%RDI |
0x46ff16 MOV 0x88(%RSP),%R11 |
0x46ff1e ADD %RCX,%RAX |
0x46ff21 CMP %R9,%R10 |
0x46ff24 MOV 0xb0(%RSP),%R10 |
0x46ff2c CMOVNE %RAX,%R8 |
0x46ff30 CMP %RDI,%R8 |
0x46ff33 JLE 47081e |
0x46ff39 MOV 0x80(%RSP),%R9 |
0x46ff41 VMOVQ 0x12edf7(%RIP),%XMM5 |
0x46ff49 VXORPD %XMM4,%XMM4,%XMM4 |
0x46ff4d LEA (%R9,%RDI,8),%RCX |
0x46ff51 LEA (%R9,%R8,8),%RAX |
0x46ff55 MOV %RCX,0xd8(%RSP) |
0x46ff5d MOV %RAX,0x40(%RSP) |
0x46ff62 NOPW (%RAX,%RAX,1) |
(660) 0x46ff68 MOV 0xd8(%RSP),%RDX |
(660) 0x46ff70 MOV 0x58(%RSP),%RCX |
(660) 0x46ff75 MOV 0x68(%RSP),%RDI |
(660) 0x46ff7a MOV (%RDX),%RDX |
(660) 0x46ff7d LEA (,%RDX,8),%R8 |
(660) 0x46ff85 MOV (%RDI,%RDX,8),%R9 |
(660) 0x46ff89 LEA (%RCX,%R8,1),%RAX |
(660) 0x46ff8d LEA 0x8(%R8),%RSI |
(660) 0x46ff91 MOV (%RAX),%RDI |
(660) 0x46ff94 MOV %RAX,0xc0(%RSP) |
(660) 0x46ff9c MOV 0x8(%RCX,%R8,1),%RAX |
(660) 0x46ffa1 MOV %RSI,0xe0(%RSP) |
(660) 0x46ffa9 ADD %R9,%RAX |
(660) 0x46ffac SUB %RDI,%RAX |
(660) 0x46ffaf CMP %RAX,%R9 |
(660) 0x46ffb2 JGE 4700f9 |
(660) 0x46ffb8 MOV 0x30(%RSP),%RDI |
(660) 0x46ffbd MOV 0x8(%RDI),%RSI |
(660) 0x46ffc1 LEA (%RSI,%RAX,8),%RDI |
(660) 0x46ffc5 LEA (%RSI,%R9,8),%RCX |
(660) 0x46ffc9 MOV %RDI,%R9 |
(660) 0x46ffcc SUB %RCX,%R9 |
(660) 0x46ffcf SUB $0x8,%R9 |
(660) 0x46ffd3 SHR $0x3,%R9 |
(660) 0x46ffd7 INC %R9 |
(660) 0x46ffda AND $0x7,%R9D |
(660) 0x46ffde JE 470076 |
(660) 0x46ffe4 CMP $0x1,%R9 |
(660) 0x46ffe8 JE 470062 |
(660) 0x46ffea CMP $0x2,%R9 |
(660) 0x46ffee JE 470053 |
(660) 0x46fff0 CMP $0x3,%R9 |
(660) 0x46fff4 JE 470044 |
(660) 0x46fff6 CMP $0x4,%R9 |
(660) 0x46fffa JE 470035 |
(660) 0x46fffc CMP $0x5,%R9 |
(660) 0x470000 JE 470026 |
(660) 0x470002 CMP $0x6,%R9 |
(660) 0x470006 JE 470017 |
(660) 0x470008 MOV (%RCX),%RAX |
(660) 0x47000b ADD $0x8,%RCX |
(660) 0x47000f MOV (%R15,%RAX,8),%RSI |
(660) 0x470013 MOV %RDX,(%R12,%RSI,8) |
(660) 0x470017 MOV (%RCX),%R9 |
(660) 0x47001a ADD $0x8,%RCX |
(660) 0x47001e MOV (%R15,%R9,8),%RAX |
(660) 0x470022 MOV %RDX,(%R12,%RAX,8) |
(660) 0x470026 MOV (%RCX),%RSI |
(660) 0x470029 ADD $0x8,%RCX |
(660) 0x47002d MOV (%R15,%RSI,8),%R9 |
(660) 0x470031 MOV %RDX,(%R12,%R9,8) |
(660) 0x470035 MOV (%RCX),%RAX |
(660) 0x470038 ADD $0x8,%RCX |
(660) 0x47003c MOV (%R15,%RAX,8),%RSI |
(660) 0x470040 MOV %RDX,(%R12,%RSI,8) |
(660) 0x470044 MOV (%RCX),%R9 |
(660) 0x470047 ADD $0x8,%RCX |
(660) 0x47004b MOV (%R15,%R9,8),%RAX |
(660) 0x47004f MOV %RDX,(%R12,%RAX,8) |
(660) 0x470053 MOV (%RCX),%RSI |
(660) 0x470056 ADD $0x8,%RCX |
(660) 0x47005a MOV (%R15,%RSI,8),%R9 |
(660) 0x47005e MOV %RDX,(%R12,%R9,8) |
(660) 0x470062 MOV (%RCX),%RAX |
(660) 0x470065 ADD $0x8,%RCX |
(660) 0x470069 MOV (%R15,%RAX,8),%RSI |
(660) 0x47006d MOV %RDX,(%R12,%RSI,8) |
(660) 0x470071 CMP %RCX,%RDI |
(660) 0x470074 JE 4700ee |
(660) 0x470076 MOV 0xe0(%RSP),%R9 |
(669) 0x47007e MOV (%RCX),%RAX |
(669) 0x470081 ADD $0x40,%RCX |
(669) 0x470085 MOV (%R15,%RAX,8),%RSI |
(669) 0x470089 MOV %RDX,(%R12,%RSI,8) |
(669) 0x47008d MOV -0x38(%RCX),%RAX |
(669) 0x470091 MOV (%R15,%RAX,8),%RSI |
(669) 0x470095 MOV %RDX,(%R12,%RSI,8) |
(669) 0x470099 MOV -0x30(%RCX),%RAX |
(669) 0x47009d MOV (%R15,%RAX,8),%RSI |
(669) 0x4700a1 MOV %RDX,(%R12,%RSI,8) |
(669) 0x4700a5 MOV -0x28(%RCX),%RAX |
(669) 0x4700a9 MOV (%R15,%RAX,8),%RSI |
(669) 0x4700ad MOV %RDX,(%R12,%RSI,8) |
(669) 0x4700b1 MOV -0x20(%RCX),%RAX |
(669) 0x4700b5 MOV (%R15,%RAX,8),%RSI |
(669) 0x4700b9 MOV %RDX,(%R12,%RSI,8) |
(669) 0x4700bd MOV -0x18(%RCX),%RAX |
(669) 0x4700c1 MOV (%R15,%RAX,8),%RSI |
(669) 0x4700c5 MOV %RDX,(%R12,%RSI,8) |
(669) 0x4700c9 MOV -0x10(%RCX),%RAX |
(669) 0x4700cd MOV (%R15,%RAX,8),%RSI |
(669) 0x4700d1 MOV %RDX,(%R12,%RSI,8) |
(669) 0x4700d5 MOV -0x8(%RCX),%RAX |
(669) 0x4700d9 MOV (%R15,%RAX,8),%RSI |
(669) 0x4700dd MOV %RDX,(%R12,%RSI,8) |
(669) 0x4700e1 CMP %RCX,%RDI |
(669) 0x4700e4 JNE 47007e |
(660) 0x4700e6 MOV %R9,0xe0(%RSP) |
(660) 0x4700ee MOV 0xc0(%RSP),%RCX |
(660) 0x4700f6 MOV (%RCX),%RDI |
(660) 0x4700f9 MOV 0x48(%RSP),%RSI |
(660) 0x4700fe MOV 0xe0(%RSP),%RCX |
(660) 0x470106 VXORPD %XMM0,%XMM0,%XMM0 |
(660) 0x47010a VMOVSD %XMM0,%XMM0,%XMM2 |
(660) 0x47010e LEA (%RSI,%R8,1),%R9 |
(660) 0x470112 ADD %RCX,%RSI |
(660) 0x470115 MOV (%R9),%RAX |
(660) 0x470118 MOV %R9,0xb0(%RSP) |
(660) 0x470120 MOV %RAX,0xb8(%RSP) |
(660) 0x470128 INC %RAX |
(660) 0x47012b CMP (%RSI),%RAX |
(660) 0x47012e JGE 470207 |
(660) 0x470134 CMPQ $0x1,0xf0(%RSP) |
(660) 0x47013d MOV %RBX,0xb8(%RSP) |
(660) 0x470145 JE 470840 |
(660) 0x47014b MOV %R14,0x88(%RSP) |
(660) 0x470153 MOV 0x20(%RSP),%R9 |
(660) 0x470158 MOV %R10,0x80(%RSP) |
(660) 0x470160 MOV 0xd0(%RSP),%R10 |
(660) 0x470168 MOV %R13,0x78(%RSP) |
(660) 0x47016d MOV 0x10(%RSP),%R13 |
(660) 0x470172 NOPW (%RAX,%RAX,1) |
(668) 0x470178 MOV (%R9,%RAX,8),%RCX |
(668) 0x47017c CMPQ $-0x3,(%R13,%RCX,8) |
(668) 0x470182 JE 47019b |
(668) 0x470184 MOV (%R10,%RCX,8),%R14 |
(668) 0x470188 CMP %R14,(%R10,%R8,1) |
(668) 0x47018c JNE 47019b |
(668) 0x47018e MOV 0xf8(%RSP),%RBX |
(668) 0x470196 VADDSD (%RBX,%RAX,8),%XMM0,%XMM0 |
(668) 0x47019b CMP $-0x1,%RCX |
(668) 0x47019f JE 4701e2 |
(668) 0x4701a1 CMP (%R12,%RCX,8),%RDX |
(668) 0x4701a5 JNE 4701e2 |
(668) 0x4701a7 MOV 0xf8(%RSP),%R14 |
(668) 0x4701af LEA (,%RDI,8),%RBX |
(668) 0x4701b7 VMOVSD (%R14,%RAX,8),%XMM6 |
(668) 0x4701bd MOV 0xa8(%RSP),%R14 |
(668) 0x4701c5 MOV (%R14,%RCX,8),%RCX |
(668) 0x4701c9 MOV 0x90(%RSP),%R14 |
(668) 0x4701d1 VMOVSD %XMM6,(%R11,%RDI,8) |
(668) 0x4701d7 VADDSD %XMM6,%XMM2,%XMM2 |
(668) 0x4701db INC %RDI |
(668) 0x4701de MOV %RCX,(%R14,%RBX,1) |
(668) 0x4701e2 INC %RAX |
(668) 0x4701e5 CMP (%RSI),%RAX |
(668) 0x4701e8 JL 470178 |
(660) 0x4701ea MOV 0xb8(%RSP),%RBX |
(660) 0x4701f2 MOV 0x88(%RSP),%R14 |
(660) 0x4701fa MOV 0x80(%RSP),%R10 |
(660) 0x470202 MOV 0x78(%RSP),%R13 |
(660) 0x470207 MOV 0x60(%RSP),%R9 |
(660) 0x47020c MOV 0x70(%RSP),%RSI |
(660) 0x470211 MOV %R9,%RAX |
(660) 0x470214 MOV (%RSI,%RDX,8),%RCX |
(660) 0x470218 ADD %R8,%RAX |
(660) 0x47021b MOV (%RAX),%RSI |
(660) 0x47021e MOV %RAX,0xb8(%RSP) |
(660) 0x470226 MOV 0x8(%R9,%R8,1),%RAX |
(660) 0x47022b ADD %RCX,%RAX |
(660) 0x47022e SUB %RSI,%RAX |
(660) 0x470231 CMP %RAX,%RCX |
(660) 0x470234 JGE 47037a |
(660) 0x47023a MOV 0x38(%RSP),%RSI |
(660) 0x47023f MOV 0x8(%RSI),%R9 |
(660) 0x470243 LEA (%R9,%RAX,8),%RSI |
(660) 0x470247 LEA (%R9,%RCX,8),%RCX |
(660) 0x47024b MOV %RSI,%RAX |
(660) 0x47024e SUB %RCX,%RAX |
(660) 0x470251 SUB $0x8,%RAX |
(660) 0x470255 SHR $0x3,%RAX |
(660) 0x470259 INC %RAX |
(660) 0x47025c AND $0x7,%EAX |
(660) 0x47025f JE 4702f7 |
(660) 0x470265 CMP $0x1,%RAX |
(660) 0x470269 JE 4702e3 |
(660) 0x47026b CMP $0x2,%RAX |
(660) 0x47026f JE 4702d4 |
(660) 0x470271 CMP $0x3,%RAX |
(660) 0x470275 JE 4702c5 |
(660) 0x470277 CMP $0x4,%RAX |
(660) 0x47027b JE 4702b6 |
(660) 0x47027d CMP $0x5,%RAX |
(660) 0x470281 JE 4702a7 |
(660) 0x470283 CMP $0x6,%RAX |
(660) 0x470287 JE 470298 |
(660) 0x470289 MOV (%RCX),%R9 |
(660) 0x47028c ADD $0x8,%RCX |
(660) 0x470290 MOV (%R14,%R9,8),%RAX |
(660) 0x470294 MOV %RDX,(%RBX,%RAX,8) |
(660) 0x470298 MOV (%RCX),%R9 |
(660) 0x47029b ADD $0x8,%RCX |
(660) 0x47029f MOV (%R14,%R9,8),%RAX |
(660) 0x4702a3 MOV %RDX,(%RBX,%RAX,8) |
(660) 0x4702a7 MOV (%RCX),%R9 |
(660) 0x4702aa ADD $0x8,%RCX |
(660) 0x4702ae MOV (%R14,%R9,8),%RAX |
(660) 0x4702b2 MOV %RDX,(%RBX,%RAX,8) |
(660) 0x4702b6 MOV (%RCX),%R9 |
(660) 0x4702b9 ADD $0x8,%RCX |
(660) 0x4702bd MOV (%R14,%R9,8),%RAX |
(660) 0x4702c1 MOV %RDX,(%RBX,%RAX,8) |
(660) 0x4702c5 MOV (%RCX),%R9 |
(660) 0x4702c8 ADD $0x8,%RCX |
(660) 0x4702cc MOV (%R14,%R9,8),%RAX |
(660) 0x4702d0 MOV %RDX,(%RBX,%RAX,8) |
(660) 0x4702d4 MOV (%RCX),%R9 |
(660) 0x4702d7 ADD $0x8,%RCX |
(660) 0x4702db MOV (%R14,%R9,8),%RAX |
(660) 0x4702df MOV %RDX,(%RBX,%RAX,8) |
(660) 0x4702e3 MOV (%RCX),%R9 |
(660) 0x4702e6 ADD $0x8,%RCX |
(660) 0x4702ea MOV (%R14,%R9,8),%RAX |
(660) 0x4702ee MOV %RDX,(%RBX,%RAX,8) |
(660) 0x4702f2 CMP %RCX,%RSI |
(660) 0x4702f5 JE 47036f |
(660) 0x4702f7 MOV 0xe0(%RSP),%R9 |
(666) 0x4702ff MOV (%RCX),%RAX |
(666) 0x470302 ADD $0x40,%RCX |
(666) 0x470306 MOV (%R14,%RAX,8),%RAX |
(666) 0x47030a MOV %RDX,(%RBX,%RAX,8) |
(666) 0x47030e MOV -0x38(%RCX),%RAX |
(666) 0x470312 MOV (%R14,%RAX,8),%RAX |
(666) 0x470316 MOV %RDX,(%RBX,%RAX,8) |
(666) 0x47031a MOV -0x30(%RCX),%RAX |
(666) 0x47031e MOV (%R14,%RAX,8),%RAX |
(666) 0x470322 MOV %RDX,(%RBX,%RAX,8) |
(666) 0x470326 MOV -0x28(%RCX),%RAX |
(666) 0x47032a MOV (%R14,%RAX,8),%RAX |
(666) 0x47032e MOV %RDX,(%RBX,%RAX,8) |
(666) 0x470332 MOV -0x20(%RCX),%RAX |
(666) 0x470336 MOV (%R14,%RAX,8),%RAX |
(666) 0x47033a MOV %RDX,(%RBX,%RAX,8) |
(666) 0x47033e MOV -0x18(%RCX),%RAX |
(666) 0x470342 MOV (%R14,%RAX,8),%RAX |
(666) 0x470346 MOV %RDX,(%RBX,%RAX,8) |
(666) 0x47034a MOV -0x10(%RCX),%RAX |
(666) 0x47034e MOV (%R14,%RAX,8),%RAX |
(666) 0x470352 MOV %RDX,(%RBX,%RAX,8) |
(666) 0x470356 MOV -0x8(%RCX),%RAX |
(666) 0x47035a MOV (%R14,%RAX,8),%RAX |
(666) 0x47035e MOV %RDX,(%RBX,%RAX,8) |
(666) 0x470362 CMP %RCX,%RSI |
(666) 0x470365 JNE 4702ff |
(660) 0x470367 MOV %R9,0xe0(%RSP) |
(660) 0x47036f MOV 0xb8(%RSP),%RCX |
(660) 0x470377 MOV (%RCX),%RSI |
(660) 0x47037a MOV 0x50(%RSP),%RCX |
(660) 0x47037f MOV 0xe0(%RSP),%R9 |
(660) 0x470387 MOV (%RCX,%RDX,8),%RAX |
(660) 0x47038b ADD %RCX,%R9 |
(660) 0x47038e CMP %RAX,(%R9) |
(660) 0x470391 JLE 4709c0 |
(660) 0x470397 CMPQ $0,0x18(%RSP) |
(660) 0x47039d JE 4708e8 |
(660) 0x4703a3 MOV %R11,0x80(%RSP) |
(660) 0x4703ab MOV 0x28(%RSP),%R11 |
(660) 0x4703b0 MOV %RDI,0x78(%RSP) |
(660) 0x4703b5 MOV 0x8(%RSP),%RDI |
(660) 0x4703ba MOV %R12,0xe0(%RSP) |
(660) 0x4703c2 MOV %R14,0x88(%RSP) |
(660) 0x4703ca JMP 470439 |
0x4703cc NOPL (%RAX) |
(665) 0x4703d0 MOV 0xc8(%RSP),%R14 |
(665) 0x4703d8 MOV 0xd0(%RSP),%R12 |
(665) 0x4703e0 MOV (%R14,%RCX,8),%R14 |
(665) 0x4703e4 CMP %R14,(%R12,%R8,1) |
(665) 0x4703e8 JE 470458 |
(665) 0x4703ea CMP $-0x1,%RCX |
(665) 0x4703ee JE 470431 |
(665) 0x4703f0 CMP (%RBX,%RCX,8),%RDX |
(665) 0x4703f4 JNE 470431 |
(665) 0x4703f6 MOV 0xe8(%RSP),%R14 |
(665) 0x4703fe LEA (,%RSI,8),%R12 |
(665) 0x470406 VMOVSD (%R14,%RAX,8),%XMM7 |
(665) 0x47040c MOV 0xa0(%RSP),%R14 |
(665) 0x470414 MOV (%R14,%RCX,8),%RCX |
(665) 0x470418 MOV 0x98(%RSP),%R14 |
(665) 0x470420 VMOVSD %XMM7,(%R10,%RSI,8) |
(665) 0x470426 VADDSD %XMM7,%XMM2,%XMM2 |
(665) 0x47042a INC %RSI |
(665) 0x47042d MOV %RCX,(%R14,%R12,1) |
(665) 0x470431 INC %RAX |
(665) 0x470434 CMP (%R9),%RAX |
(665) 0x470437 JGE 470470 |
(665) 0x470439 MOV (%R13,%RAX,8),%R12 |
(665) 0x47043e MOV (%RDI,%R12,8),%RCX |
(665) 0x470442 CMPQ $-0x3,(%R11,%RCX,8) |
(665) 0x470447 JE 4703ea |
(665) 0x470449 CMPQ $0x1,0xf0(%RSP) |
(665) 0x470452 JNE 4703d0 |
(665) 0x470458 MOV 0xe8(%RSP),%R12 |
(665) 0x470460 VADDSD (%R12,%RAX,8),%XMM0,%XMM0 |
(665) 0x470466 JMP 4703ea |
0x470468 NOPL (%RAX,%RAX,1) |
(660) 0x470470 MOV 0xe0(%RSP),%R12 |
(660) 0x470478 MOV 0x88(%RSP),%R14 |
(660) 0x470480 MOV 0x80(%RSP),%R11 |
(660) 0x470488 MOV 0x78(%RSP),%RDI |
(660) 0x47048d MOV 0xb8(%RSP),%RDX |
(660) 0x470495 MOV (%RDX),%R8 |
(660) 0x470498 MOV 0xb0(%RSP),%RAX |
(660) 0x4704a0 MOV 0xf8(%RSP),%RCX |
(660) 0x4704a8 MOV (%RAX),%R9 |
(660) 0x4704ab VMULSD (%RCX,%R9,8),%XMM2,%XMM10 |
(660) 0x4704b1 VCOMISD %XMM4,%XMM10 |
(660) 0x4704b5 JE 4704c0 |
(660) 0x4704b7 VXORPD %XMM5,%XMM0,%XMM1 |
(660) 0x4704bb VDIVSD %XMM10,%XMM1,%XMM11 |
(660) 0x4704c0 MOV 0xc0(%RSP),%RDX |
(660) 0x4704c8 MOV (%RDX),%RCX |
(660) 0x4704cb CMP %RDI,%RCX |
(660) 0x4704ce JGE 47065a |
(660) 0x4704d4 SUB %RCX,%RDI |
(660) 0x4704d7 MOV %RCX,0xe0(%RSP) |
(660) 0x4704df LEA -0x1(%RDI),%RAX |
(660) 0x4704e3 CMP $0x2,%RAX |
(660) 0x4704e7 JBE 470a5f |
(660) 0x4704ed MOV %RDI,%RDX |
(660) 0x4704f0 LEA (%R11,%RCX,8),%RAX |
(660) 0x4704f4 VBROADCASTSD %XMM11,%YMM12 |
(660) 0x4704f9 SHR $0x2,%RDX |
(660) 0x4704fd SAL $0x5,%RDX |
(660) 0x470501 LEA (%RDX,%RAX,1),%R9 |
(660) 0x470505 SUB $0x20,%RDX |
(660) 0x470509 SHR $0x5,%RDX |
(660) 0x47050d INC %RDX |
(660) 0x470510 AND $0x7,%EDX |
(660) 0x470513 JE 47059d |
(660) 0x470519 CMP $0x1,%RDX |
(660) 0x47051d JE 47058b |
(660) 0x47051f CMP $0x2,%RDX |
(660) 0x470523 JE 47057e |
(660) 0x470525 CMP $0x3,%RDX |
(660) 0x470529 JE 470571 |
(660) 0x47052b CMP $0x4,%RDX |
(660) 0x47052f JE 470564 |
(660) 0x470531 CMP $0x5,%RDX |
(660) 0x470535 JE 470557 |
(660) 0x470537 CMP $0x6,%RDX |
(660) 0x47053b JE 47054a |
(660) 0x47053d VMULPD (%RAX),%YMM12,%YMM13 |
(660) 0x470541 ADD $0x20,%RAX |
(660) 0x470545 VMOVUPD %YMM13,-0x20(%RAX) |
(660) 0x47054a VMULPD (%RAX),%YMM12,%YMM14 |
(660) 0x47054e ADD $0x20,%RAX |
(660) 0x470552 VMOVUPD %YMM14,-0x20(%RAX) |
(660) 0x470557 VMULPD (%RAX),%YMM12,%YMM15 |
(660) 0x47055b ADD $0x20,%RAX |
(660) 0x47055f VMOVUPD %YMM15,-0x20(%RAX) |
(660) 0x470564 VMULPD (%RAX),%YMM12,%YMM0 |
(660) 0x470568 ADD $0x20,%RAX |
(660) 0x47056c VMOVUPD %YMM0,-0x20(%RAX) |
(660) 0x470571 VMULPD (%RAX),%YMM12,%YMM3 |
(660) 0x470575 ADD $0x20,%RAX |
(660) 0x470579 VMOVUPD %YMM3,-0x20(%RAX) |
(660) 0x47057e VMULPD (%RAX),%YMM12,%YMM2 |
(660) 0x470582 ADD $0x20,%RAX |
(660) 0x470586 VMOVUPD %YMM2,-0x20(%RAX) |
(660) 0x47058b VMULPD (%RAX),%YMM12,%YMM6 |
(660) 0x47058f ADD $0x20,%RAX |
(660) 0x470593 VMOVUPD %YMM6,-0x20(%RAX) |
(660) 0x470598 CMP %RAX,%R9 |
(660) 0x47059b JE 47060c |
(662) 0x47059d VMULPD (%RAX),%YMM12,%YMM7 |
(662) 0x4705a1 ADD $0x100,%RAX |
(662) 0x4705a7 VMULPD -0xe0(%RAX),%YMM12,%YMM8 |
(662) 0x4705af VMULPD -0xc0(%RAX),%YMM12,%YMM9 |
(662) 0x4705b7 VMULPD -0xa0(%RAX),%YMM12,%YMM10 |
(662) 0x4705bf VMULPD -0x80(%RAX),%YMM12,%YMM1 |
(662) 0x4705c4 VMULPD -0x60(%RAX),%YMM12,%YMM13 |
(662) 0x4705c9 VMOVUPD %YMM7,-0x100(%RAX) |
(662) 0x4705d1 VMULPD -0x40(%RAX),%YMM12,%YMM14 |
(662) 0x4705d6 VMOVUPD %YMM8,-0xe0(%RAX) |
(662) 0x4705de VMULPD -0x20(%RAX),%YMM12,%YMM15 |
(662) 0x4705e3 VMOVUPD %YMM9,-0xc0(%RAX) |
(662) 0x4705eb VMOVUPD %YMM10,-0xa0(%RAX) |
(662) 0x4705f3 VMOVUPD %YMM1,-0x80(%RAX) |
(662) 0x4705f8 VMOVUPD %YMM13,-0x60(%RAX) |
(662) 0x4705fd VMOVUPD %YMM14,-0x40(%RAX) |
(662) 0x470602 VMOVUPD %YMM15,-0x20(%RAX) |
(662) 0x470607 CMP %RAX,%R9 |
(662) 0x47060a JNE 47059d |
(660) 0x47060c TEST $0x3,%DIL |
(660) 0x470610 JE 47065a |
(660) 0x470612 MOV %RDI,%R9 |
(660) 0x470615 AND $-0x4,%R9 |
(660) 0x470619 ADD %R9,%RCX |
(660) 0x47061c SUB %R9,%RDI |
(660) 0x47061f CMP $0x1,%RDI |
(660) 0x470623 JE 47064e |
(660) 0x470625 MOV 0xe0(%RSP),%RAX |
(660) 0x47062d VMOVDDUP %XMM11,%XMM12 |
(660) 0x470632 ADD %R9,%RAX |
(660) 0x470635 LEA (%R11,%RAX,8),%RDX |
(660) 0x470639 VMULPD (%RDX),%XMM12,%XMM0 |
(660) 0x47063d VMOVUPD %XMM0,(%RDX) |
(660) 0x470641 TEST $0x1,%DIL |
(660) 0x470645 JE 47065a |
(660) 0x470647 AND $-0x2,%RDI |
(660) 0x47064b ADD %RDI,%RCX |
(660) 0x47064e LEA (%R11,%RCX,8),%RDI |
(660) 0x470652 VMULSD (%RDI),%XMM11,%XMM3 |
(660) 0x470656 VMOVSD %XMM3,(%RDI) |
(660) 0x47065a CMP %R8,%RSI |
(660) 0x47065d JLE 4707ff |
(660) 0x470663 SUB %R8,%RSI |
(660) 0x470666 MOV %R8,%RCX |
(660) 0x470669 LEA -0x1(%RSI),%R9 |
(660) 0x47066d CMP $0x2,%R9 |
(660) 0x470671 JBE 470a67 |
(660) 0x470677 MOV %RSI,%RDX |
(660) 0x47067a LEA (%R10,%R8,8),%R9 |
(660) 0x47067e VBROADCASTSD %XMM11,%YMM6 |
(660) 0x470683 SHR $0x2,%RDX |
(660) 0x470687 SAL $0x5,%RDX |
(660) 0x47068b LEA (%RDX,%R9,1),%RDI |
(660) 0x47068f SUB $0x20,%RDX |
(660) 0x470693 SHR $0x5,%RDX |
(660) 0x470697 INC %RDX |
(660) 0x47069a AND $0x7,%EDX |
(660) 0x47069d JE 470739 |
(660) 0x4706a3 CMP $0x1,%RDX |
(660) 0x4706a7 JE 470721 |
(660) 0x4706a9 CMP $0x2,%RDX |
(660) 0x4706ad JE 470712 |
(660) 0x4706af CMP $0x3,%RDX |
(660) 0x4706b3 JE 470703 |
(660) 0x4706b5 CMP $0x4,%RDX |
(660) 0x4706b9 JE 4706f4 |
(660) 0x4706bb CMP $0x5,%RDX |
(660) 0x4706bf JE 4706e5 |
(660) 0x4706c1 CMP $0x6,%RDX |
(660) 0x4706c5 JE 4706d6 |
(660) 0x4706c7 VMULPD (%R9),%YMM6,%YMM2 |
(660) 0x4706cc ADD $0x20,%R9 |
(660) 0x4706d0 VMOVUPD %YMM2,-0x20(%R9) |
(660) 0x4706d6 VMULPD (%R9),%YMM6,%YMM7 |
(660) 0x4706db ADD $0x20,%R9 |
(660) 0x4706df VMOVUPD %YMM7,-0x20(%R9) |
(660) 0x4706e5 VMULPD (%R9),%YMM6,%YMM8 |
(660) 0x4706ea ADD $0x20,%R9 |
(660) 0x4706ee VMOVUPD %YMM8,-0x20(%R9) |
(660) 0x4706f4 VMULPD (%R9),%YMM6,%YMM9 |
(660) 0x4706f9 ADD $0x20,%R9 |
(660) 0x4706fd VMOVUPD %YMM9,-0x20(%R9) |
(660) 0x470703 VMULPD (%R9),%YMM6,%YMM10 |
(660) 0x470708 ADD $0x20,%R9 |
(660) 0x47070c VMOVUPD %YMM10,-0x20(%R9) |
(660) 0x470712 VMULPD (%R9),%YMM6,%YMM1 |
(660) 0x470717 ADD $0x20,%R9 |
(660) 0x47071b VMOVUPD %YMM1,-0x20(%R9) |
(660) 0x470721 VMULPD (%R9),%YMM6,%YMM13 |
(660) 0x470726 ADD $0x20,%R9 |
(660) 0x47072a VMOVUPD %YMM13,-0x20(%R9) |
(660) 0x470730 CMP %R9,%RDI |
(660) 0x470733 JE 4707b9 |
(661) 0x470739 VMULPD (%R9),%YMM6,%YMM14 |
(661) 0x47073e ADD $0x100,%R9 |
(661) 0x470745 VMULPD -0xe0(%R9),%YMM6,%YMM15 |
(661) 0x47074e VMULPD -0xc0(%R9),%YMM6,%YMM12 |
(661) 0x470757 VMULPD -0xa0(%R9),%YMM6,%YMM0 |
(661) 0x470760 VMULPD -0x80(%R9),%YMM6,%YMM3 |
(661) 0x470766 VMULPD -0x60(%R9),%YMM6,%YMM2 |
(661) 0x47076c VMOVUPD %YMM14,-0x100(%R9) |
(661) 0x470775 VMULPD -0x40(%R9),%YMM6,%YMM7 |
(661) 0x47077b VMOVUPD %YMM15,-0xe0(%R9) |
(661) 0x470784 VMULPD -0x20(%R9),%YMM6,%YMM8 |
(661) 0x47078a VMOVUPD %YMM12,-0xc0(%R9) |
(661) 0x470793 VMOVUPD %YMM0,-0xa0(%R9) |
(661) 0x47079c VMOVUPD %YMM3,-0x80(%R9) |
(661) 0x4707a2 VMOVUPD %YMM2,-0x60(%R9) |
(661) 0x4707a8 VMOVUPD %YMM7,-0x40(%R9) |
(661) 0x4707ae VMOVUPD %YMM8,-0x20(%R9) |
(661) 0x4707b4 CMP %R9,%RDI |
(661) 0x4707b7 JNE 470739 |
(660) 0x4707b9 TEST $0x3,%SIL |
(660) 0x4707bd JE 4707ff |
(660) 0x4707bf MOV %RSI,%RAX |
(660) 0x4707c2 AND $-0x4,%RAX |
(660) 0x4707c6 ADD %RAX,%R8 |
(660) 0x4707c9 SUB %RAX,%RSI |
(660) 0x4707cc CMP $0x1,%RSI |
(660) 0x4707d0 JE 4707f3 |
(660) 0x4707d2 ADD %RCX,%RAX |
(660) 0x4707d5 VMOVDDUP %XMM11,%XMM6 |
(660) 0x4707da LEA (%R10,%RAX,8),%RCX |
(660) 0x4707de VMULPD (%RCX),%XMM6,%XMM9 |
(660) 0x4707e2 VMOVUPD %XMM9,(%RCX) |
(660) 0x4707e6 TEST $0x1,%SIL |
(660) 0x4707ea JE 4707ff |
(660) 0x4707ec AND $-0x2,%RSI |
(660) 0x4707f0 ADD %RSI,%R8 |
(660) 0x4707f3 LEA (%R10,%R8,8),%RSI |
(660) 0x4707f7 VMULSD (%RSI),%XMM11,%XMM10 |
(660) 0x4707fb VMOVSD %XMM10,(%RSI) |
(660) 0x4707ff ADDQ $0x8,0xd8(%RSP) |
(660) 0x470808 MOV 0xd8(%RSP),%R8 |
(660) 0x470810 CMP %R8,0x40(%RSP) |
(660) 0x470815 JNE 46ff68 |
0x47081b VZEROUPPER |
0x47081e MOV %R12,%RDI |
0x470821 CALL 5958c0 <hypre_Free> |
0x470826 LEA -0x28(%RBP),%RSP |
0x47082a MOV %RBX,%RDI |
0x47082d POP %RBX |
0x47082e POP %R12 |
0x470830 POP %R13 |
0x470832 POP %R14 |
0x470834 POP %R15 |
0x470836 POP %RBP |
0x470837 JMP 5958c0 |
0x47083c NOPL (%RAX) |
(660) 0x470840 MOV %R10,0x88(%RSP) |
(660) 0x470848 MOV 0x10(%RSP),%R9 |
(660) 0x47084d MOV %R8,0x80(%RSP) |
(660) 0x470855 MOV 0x20(%RSP),%R8 |
(660) 0x47085a NOPW (%RAX,%RAX,1) |
(667) 0x470860 MOV (%R8,%RAX,8),%RCX |
(667) 0x470864 CMPQ $-0x3,(%R9,%RCX,8) |
(667) 0x470869 JE 470878 |
(667) 0x47086b MOV 0xf8(%RSP),%RBX |
(667) 0x470873 VADDSD (%RBX,%RAX,8),%XMM0,%XMM0 |
(667) 0x470878 CMP $-0x1,%RCX |
(667) 0x47087c JE 4708bf |
(667) 0x47087e CMP (%R12,%RCX,8),%RDX |
(667) 0x470882 JNE 4708bf |
(667) 0x470884 MOV 0xf8(%RSP),%R10 |
(667) 0x47088c LEA (,%RDI,8),%RBX |
(667) 0x470894 VMOVSD (%R10,%RAX,8),%XMM3 |
(667) 0x47089a MOV 0xa8(%RSP),%R10 |
(667) 0x4708a2 MOV (%R10,%RCX,8),%RCX |
(667) 0x4708a6 MOV 0x90(%RSP),%R10 |
(667) 0x4708ae VMOVSD %XMM3,(%R11,%RDI,8) |
(667) 0x4708b4 VADDSD %XMM3,%XMM2,%XMM2 |
(667) 0x4708b8 INC %RDI |
(667) 0x4708bb MOV %RCX,(%R10,%RBX,1) |
(667) 0x4708bf INC %RAX |
(667) 0x4708c2 CMP (%RSI),%RAX |
(667) 0x4708c5 JL 470860 |
(660) 0x4708c7 MOV 0xb8(%RSP),%RBX |
(660) 0x4708cf MOV 0x88(%RSP),%R10 |
(660) 0x4708d7 MOV 0x80(%RSP),%R8 |
(660) 0x4708df JMP 470207 |
0x4708e4 NOPL (%RAX) |
(660) 0x4708e8 CMPQ $0x1,0xf0(%RSP) |
(660) 0x4708f1 JE 4709c8 |
(660) 0x4708f7 MOV %R12,0xe0(%RSP) |
(660) 0x4708ff MOV %R11,0x88(%RSP) |
(660) 0x470907 MOV %RDI,0x80(%RSP) |
(660) 0x47090f MOV 0x28(%RSP),%RDI |
(660) 0x470914 NOPL (%RAX) |
(664) 0x470918 MOV (%R13,%RAX,8),%RCX |
(664) 0x47091d CMPQ $-0x3,(%RDI,%RCX,8) |
(664) 0x470922 JE 47094c |
(664) 0x470924 MOV 0xd0(%RSP),%R11 |
(664) 0x47092c MOV 0xc8(%RSP),%R12 |
(664) 0x470934 MOV (%R11,%R8,1),%R11 |
(664) 0x470938 CMP %R11,(%R12,%RCX,8) |
(664) 0x47093c JNE 47094c |
(664) 0x47093e MOV 0xe8(%RSP),%R12 |
(664) 0x470946 VADDSD (%R12,%RAX,8),%XMM0,%XMM0 |
(664) 0x47094c CMP $-0x1,%RCX |
(664) 0x470950 JE 470994 |
(664) 0x470952 CMP (%RBX,%RCX,8),%RDX |
(664) 0x470956 JNE 470994 |
(664) 0x470958 MOV 0xe8(%RSP),%R11 |
(664) 0x470960 LEA (,%RSI,8),%R12 |
(664) 0x470968 VMOVSD (%R11,%RAX,8),%XMM9 |
(664) 0x47096e MOV 0xa0(%RSP),%R11 |
(664) 0x470976 MOV (%R11,%RCX,8),%RCX |
(664) 0x47097a MOV 0x98(%RSP),%R11 |
(664) 0x470982 VMOVSD %XMM9,(%R10,%RSI,8) |
(664) 0x470988 VADDSD %XMM9,%XMM2,%XMM2 |
(664) 0x47098d INC %RSI |
(664) 0x470990 MOV %RCX,(%R11,%R12,1) |
(664) 0x470994 INC %RAX |
(664) 0x470997 CMP %RAX,(%R9) |
(664) 0x47099a JG 470918 |
(660) 0x4709a0 MOV 0xe0(%RSP),%R12 |
(660) 0x4709a8 MOV 0x88(%RSP),%R11 |
(660) 0x4709b0 MOV 0x80(%RSP),%RDI |
(660) 0x4709b8 JMP 47048d |
0x4709bd NOPL (%RAX) |
(660) 0x4709c0 MOV %RSI,%R8 |
(660) 0x4709c3 JMP 470498 |
(660) 0x4709c8 MOV %R11,0xe0(%RSP) |
(660) 0x4709d0 MOV %RDI,0x88(%RSP) |
(660) 0x4709d8 MOV 0x28(%RSP),%RDI |
(660) 0x4709dd NOPL (%RAX) |
(663) 0x4709e0 MOV (%R13,%RAX,8),%RCX |
(663) 0x4709e5 CMPQ $-0x3,(%RDI,%RCX,8) |
(663) 0x4709ea JE 4709fa |
(663) 0x4709ec MOV 0xe8(%RSP),%R8 |
(663) 0x4709f4 VADDSD (%R8,%RAX,8),%XMM0,%XMM0 |
(663) 0x4709fa CMP $-0x1,%RCX |
(663) 0x4709fe JE 470a42 |
(663) 0x470a00 CMP (%RBX,%RCX,8),%RDX |
(663) 0x470a04 JNE 470a42 |
(663) 0x470a06 MOV 0xe8(%RSP),%R11 |
(663) 0x470a0e LEA (,%RSI,8),%R8 |
(663) 0x470a16 VMOVSD (%R11,%RAX,8),%XMM8 |
(663) 0x470a1c MOV 0xa0(%RSP),%R11 |
(663) 0x470a24 MOV (%R11,%RCX,8),%RCX |
(663) 0x470a28 MOV 0x98(%RSP),%R11 |
(663) 0x470a30 VMOVSD %XMM8,(%R10,%RSI,8) |
(663) 0x470a36 VADDSD %XMM8,%XMM2,%XMM2 |
(663) 0x470a3b INC %RSI |
(663) 0x470a3e MOV %RCX,(%R11,%R8,1) |
(663) 0x470a42 INC %RAX |
(663) 0x470a45 CMP %RAX,(%R9) |
(663) 0x470a48 JG 4709e0 |
(660) 0x470a4a MOV 0xe0(%RSP),%R11 |
(660) 0x470a52 MOV 0x88(%RSP),%RDI |
(660) 0x470a5a JMP 47048d |
(660) 0x470a5f XOR %R9D,%R9D |
(660) 0x470a62 JMP 47061c |
(660) 0x470a67 XOR %EAX,%EAX |
(660) 0x470a69 JMP 4707c9 |
0x470a6e MOV $0x8,%ESI |
0x470a73 MOV %RBX,%RDI |
0x470a76 MOV %R12,0x78(%RSP) |
0x470a7b MOV %R11,0x88(%RSP) |
0x470a83 MOV %R10,0xb0(%RSP) |
0x470a8b VMOVSD %XMM1,0xb8(%RSP) |
0x470a94 MOV %RBX,0xc0(%RSP) |
0x470a9c CALL 595800 <hypre_CAlloc> |
0x470aa1 MOV 0x78(%RSP),%RCX |
0x470aa6 MOV 0xc0(%RSP),%RDX |
0x470aae VMOVSD 0xb8(%RSP),%XMM1 |
0x470ab7 MOV 0xb0(%RSP),%R10 |
0x470abf MOV %RAX,%R12 |
0x470ac2 TEST %RCX,%RCX |
0x470ac5 MOV 0x88(%RSP),%R11 |
0x470acd JNE 470b86 |
0x470ad3 XOR %EBX,%EBX |
0x470ad5 TEST %RDX,%RDX |
0x470ad8 JLE 46fe9f |
0x470ade SAL $0x3,%RDX |
0x470ae2 MOV $0xff,%ESI |
0x470ae7 MOV %R12,%RDI |
0x470aea MOV %RCX,0x88(%RSP) |
0x470af2 MOV %R11,0xb0(%RSP) |
0x470afa MOV %R10,0xb8(%RSP) |
0x470b02 VMOVSD %XMM1,0xc0(%RSP) |
0x470b0b CALL 4110a0 <memset@plt> |
0x470b10 VMOVSD 0xc0(%RSP),%XMM1 |
0x470b19 MOV 0xb8(%RSP),%R10 |
0x470b21 MOV 0xb0(%RSP),%R11 |
0x470b29 MOV 0x88(%RSP),%RCX |
0x470b31 TEST %RCX,%RCX |
0x470b34 JLE 46fe9f |
0x470b3a LEA (,%RCX,8),%RDX |
0x470b42 MOV $0xff,%ESI |
0x470b47 MOV %RBX,%RDI |
0x470b4a MOV %R11,0xb0(%RSP) |
0x470b52 MOV %R10,0xb8(%RSP) |
0x470b5a VMOVSD %XMM1,0xc0(%RSP) |
0x470b63 CALL 4110a0 <memset@plt> |
0x470b68 VMOVSD 0xc0(%RSP),%XMM1 |
0x470b71 MOV 0xb8(%RSP),%R10 |
0x470b79 MOV 0xb0(%RSP),%R11 |
0x470b81 JMP 46fe9f |
0x470b86 MOV %RCX,%RDI |
0x470b89 MOV $0x8,%ESI |
0x470b8e MOV %R11,0x78(%RSP) |
0x470b93 MOV %R10,0x88(%RSP) |
0x470b9b MOV %RDX,0xb0(%RSP) |
0x470ba3 MOV %RCX,0xc0(%RSP) |
0x470bab VMOVSD %XMM1,0xb8(%RSP) |
0x470bb4 CALL 595800 <hypre_CAlloc> |
0x470bb9 MOV 0xb0(%RSP),%RDX |
0x470bc1 MOV 0xc0(%RSP),%RCX |
0x470bc9 VMOVSD 0xb8(%RSP),%XMM1 |
0x470bd2 MOV 0x88(%RSP),%R10 |
0x470bda MOV %RAX,%RBX |
0x470bdd TEST %RDX,%RDX |
0x470be0 MOV 0x78(%RSP),%R11 |
0x470be5 JG 470ade |
0x470beb JMP 470b31 |
0x470bf0 MOV %R12,%RDI |
0x470bf3 MOV $0x8,%ESI |
0x470bf8 MOV %R11,0x88(%RSP) |
0x470c00 MOV %R10,0xb0(%RSP) |
0x470c08 MOV %R12,0xc0(%RSP) |
0x470c10 XOR %R12D,%R12D |
0x470c13 VMOVSD %XMM1,0xb8(%RSP) |
0x470c1c CALL 595800 <hypre_CAlloc> |
0x470c21 MOV 0xc0(%RSP),%RCX |
0x470c29 VMOVSD 0xb8(%RSP),%XMM1 |
0x470c32 MOV 0xb0(%RSP),%R10 |
0x470c3a MOV 0x88(%RSP),%R11 |
0x470c42 MOV %RAX,%RBX |
0x470c45 JMP 470b31 |
0x470c4a NOPW (%RAX,%RAX,1) |
Path / |
Source file and lines | par_multi_interp.c:1575-1663 |
Module | exec |
nb instructions | 202 |
nb uops | 215 |
loop length | 1122 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 4 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 32 |
micro-operation queue | 35.83 cycles |
front end | 35.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.40 | 6.40 | 23.00 | 23.00 | 33.00 | 6.40 | 6.40 | 33.00 | 33.00 | 33.00 | 6.40 | 23.00 |
cycles | 6.40 | 7.60 | 23.00 | 23.00 | 33.00 | 6.40 | 6.40 | 33.00 | 33.00 | 33.00 | 6.40 | 23.00 |
Cycles executing div or sqrt instructions | 10.00 |
FE+BE cycles | 34.11-34.15 |
Stall cycles | 0.00 |
Front-end | 35.83 |
Dispatch | 33.00 |
DIV/SQRT | 10.00 |
Overall L1 | 35.83 |
all | 1% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 4% |
all | 7% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 1% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 9% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 10% |
all | 13% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 12% |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x20,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x100,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0xf8(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd8(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc8(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xb8(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa8(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x90(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xf0(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe8(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa0(%RDI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x98(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x88(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x80(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x68(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x60(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x40(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x70(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x58(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x50(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x48(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0xf8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0xd0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xf0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RBX,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 470a6e <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xd4e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
TEST %R12,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 470bf0 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xed0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EBX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %R12D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R11,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 598830 <hypre_GetThreadNum> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 598820 <hypre_NumActiveThreads> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xc0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd8(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xe0(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R8),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xb8(%RSP),%XMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CQTO | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %R9 | 5 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 10 |
ADD %RCX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
DEC %R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RSI,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %RAX,%R11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %R11,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RCX,%R11,1),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x88(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R9,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0xb0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMOVNE %RAX,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP %RDI,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 47081e <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xafe> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x80(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVQ 0x12edf7(%RIP),%XMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM4,%XMM4,%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R9,%RDI,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R9,%R8,8),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RCX,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 5958c0 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
JMP 5958c0 <hypre_Free> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R12,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 595800 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x78(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xb8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV 0x88(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JNE 470b86 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xe66> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EBX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 46fe9f <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x17f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
SAL $0x3,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RCX,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4110a0 <memset@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0xc0(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x88(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 46fe9f <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x17f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (,%RCX,8),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R11,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4110a0 <memset@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0xc0(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 46fe9f <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x17f> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV %RCX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R11,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 595800 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xb0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xb8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x88(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV 0x78(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JG 470ade <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xdbe> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 470b31 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xe11> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R11,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %R12D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD %XMM1,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 595800 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xc0(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xb8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x88(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JMP 470b31 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xe11> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | par_multi_interp.c:1575-1663 |
Module | exec |
nb instructions | 202 |
nb uops | 215 |
loop length | 1122 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 4 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 32 |
micro-operation queue | 35.83 cycles |
front end | 35.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.40 | 6.40 | 23.00 | 23.00 | 33.00 | 6.40 | 6.40 | 33.00 | 33.00 | 33.00 | 6.40 | 23.00 |
cycles | 6.40 | 7.60 | 23.00 | 23.00 | 33.00 | 6.40 | 6.40 | 33.00 | 33.00 | 33.00 | 6.40 | 23.00 |
Cycles executing div or sqrt instructions | 10.00 |
FE+BE cycles | 34.11-34.15 |
Stall cycles | 0.00 |
Front-end | 35.83 |
Dispatch | 33.00 |
DIV/SQRT | 10.00 |
Overall L1 | 35.83 |
all | 1% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 4% |
all | 7% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 1% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 9% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 10% |
all | 13% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 12% |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x20,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x100,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0xf8(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd8(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc8(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xb8(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa8(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x90(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xf0(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe8(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa0(%RDI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x98(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x88(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x80(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x68(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x60(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x40(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x70(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x58(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x50(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x48(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0xf8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0xd0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xf0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RBX,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 470a6e <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xd4e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
TEST %R12,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 470bf0 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xed0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EBX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %R12D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R11,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 598830 <hypre_GetThreadNum> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 598820 <hypre_NumActiveThreads> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xc0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd8(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xe0(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R8),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xb8(%RSP),%XMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CQTO | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %R9 | 5 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 10 |
ADD %RCX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
DEC %R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RSI,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %RAX,%R11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %R11,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RCX,%R11,1),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x88(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R9,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0xb0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMOVNE %RAX,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP %RDI,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 47081e <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xafe> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x80(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVQ 0x12edf7(%RIP),%XMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM4,%XMM4,%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R9,%RDI,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R9,%R8,8),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RCX,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 5958c0 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
JMP 5958c0 <hypre_Free> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R12,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 595800 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x78(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xb8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV 0x88(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JNE 470b86 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xe66> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EBX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 46fe9f <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x17f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
SAL $0x3,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RCX,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4110a0 <memset@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0xc0(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x88(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 46fe9f <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x17f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (,%RCX,8),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R11,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4110a0 <memset@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0xc0(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 46fe9f <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x17f> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV %RCX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R11,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 595800 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xb0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xb8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x88(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV 0x78(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JG 470ade <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xdbe> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 470b31 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xe11> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R11,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %R12D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD %XMM1,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 595800 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xc0(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xb8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x88(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JMP 470b31 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xe11> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼hypre_BoomerAMGBuildMultipass._omp_fn.9– | 0.33 | 0.07 |
▼Loop 660 - par_multi_interp.c:1605-1660 - exec– | 0.06 | 0.01 |
○Loop 667 - par_multi_interp.c:1618-1628 - exec | 0.26 | 0.04 |
○Loop 668 - par_multi_interp.c:1618-1628 - exec | 0 | 0 |
○Loop 664 - par_multi_interp.c:1639-1652 - exec | 0 | 0 |
○Loop 669 - par_multi_interp.c:1612-1615 - exec | 0 | 0 |
○Loop 666 - par_multi_interp.c:1633-1636 - exec | 0 | 0 |
○Loop 661 - par_multi_interp.c:1659-1660 - exec | 0 | 0 |
○Loop 665 - par_multi_interp.c:1639-1652 - exec | 0 | 0 |
○Loop 663 - par_multi_interp.c:1639-1652 - exec | 0 | 0 |
○Loop 662 - par_multi_interp.c:1657-1658 - exec | 0 | 0 |