Function: hypre_BoomerAMGCorrectCFMarker | Module: exec | Source: par_strength.c:2311-2320 | Coverage: 0.01% |
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Function: hypre_BoomerAMGCorrectCFMarker | Module: exec | Source: par_strength.c:2311-2320 | Coverage: 0.01% |
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/scratch_na/users/xoserete/qaas_runs/171-172-8218/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 2311 - 2320 |
-------------------------------------------------------------------------------- |
2311: for (i=0; i < num_var; i++) |
2312: { |
2313: if (CF_marker[i] > 0 ) |
2314: { |
2315: if (CF_marker[i] == 1) CF_marker[i] = new_CF_marker[cnt++]; |
2316: else { CF_marker[i] = 1; cnt++;} |
2317: } |
2318: } |
2319: |
2320: return 0; |
0x48cec0 TEST %RSI,%RSI |
0x48cec3 JLE 48cfa1 |
0x48cec9 CMP $0x4,%RSI |
0x48cecd JAE 48cee6 |
0x48cecf XOR %EAX,%EAX |
0x48ced1 MOV %RSI,%RCX |
0x48ced4 AND $-0x4,%RCX |
0x48ced8 CMP %RSI,%RCX |
0x48cedb JB 48cfbf |
0x48cee1 JMP 48cfa1 |
0x48cee6 PUSH %RBP |
0x48cee7 MOV %RSP,%RBP |
0x48ceea MOV %RSI,%RCX |
0x48ceed SHR $0x2,%RCX |
0x48cef1 LEA 0x18(%RDI),%R8 |
0x48cef5 XOR %EAX,%EAX |
0x48cef7 JMP 48cf13 |
0x48cef9 NOPL (%RAX) |
(2443) 0x48cf00 INC %RAX |
(2443) 0x48cf03 MOV %R9,(%R8) |
(2443) 0x48cf06 ADD $0x20,%R8 |
(2443) 0x48cf0a DEC %RCX |
(2443) 0x48cf0d JE 48cf94 |
(2443) 0x48cf13 MOV -0x18(%R8),%R10 |
(2443) 0x48cf17 TEST %R10,%R10 |
(2443) 0x48cf1a JLE 48cf33 |
(2443) 0x48cf1c MOV $0x1,%R9D |
(2443) 0x48cf22 CMP $0x1,%R10 |
(2443) 0x48cf26 JNE 48cf2c |
(2443) 0x48cf28 MOV (%RDX,%RAX,8),%R9 |
(2443) 0x48cf2c INC %RAX |
(2443) 0x48cf2f MOV %R9,-0x18(%R8) |
(2443) 0x48cf33 MOV -0x10(%R8),%R10 |
(2443) 0x48cf37 TEST %R10,%R10 |
(2443) 0x48cf3a JLE 48cf53 |
(2443) 0x48cf3c MOV $0x1,%R9D |
(2443) 0x48cf42 CMP $0x1,%R10 |
(2443) 0x48cf46 JNE 48cf4c |
(2443) 0x48cf48 MOV (%RDX,%RAX,8),%R9 |
(2443) 0x48cf4c INC %RAX |
(2443) 0x48cf4f MOV %R9,-0x10(%R8) |
(2443) 0x48cf53 MOV -0x8(%R8),%R10 |
(2443) 0x48cf57 TEST %R10,%R10 |
(2443) 0x48cf5a JLE 48cf73 |
(2443) 0x48cf5c MOV $0x1,%R9D |
(2443) 0x48cf62 CMP $0x1,%R10 |
(2443) 0x48cf66 JNE 48cf6c |
(2443) 0x48cf68 MOV (%RDX,%RAX,8),%R9 |
(2443) 0x48cf6c INC %RAX |
(2443) 0x48cf6f MOV %R9,-0x8(%R8) |
(2443) 0x48cf73 MOV (%R8),%R10 |
(2443) 0x48cf76 TEST %R10,%R10 |
(2443) 0x48cf79 JLE 48cf06 |
(2443) 0x48cf7b MOV $0x1,%R9D |
(2443) 0x48cf81 CMP $0x1,%R10 |
(2443) 0x48cf85 JNE 48cf00 |
(2443) 0x48cf8b MOV (%RDX,%RAX,8),%R9 |
(2443) 0x48cf8f JMP 48cf00 |
0x48cf94 POP %RBP |
0x48cf95 MOV %RSI,%RCX |
0x48cf98 AND $-0x4,%RCX |
0x48cf9c CMP %RSI,%RCX |
0x48cf9f JB 48cfbf |
0x48cfa1 XOR %EAX,%EAX |
0x48cfa3 RET |
0x48cfa4 NOPW %CS:(%RAX,%RAX,1) |
(2442) 0x48cfb0 INC %RAX |
(2442) 0x48cfb3 MOV %R8,(%RDI,%RCX,8) |
(2442) 0x48cfb7 INC %RCX |
(2442) 0x48cfba CMP %RCX,%RSI |
(2442) 0x48cfbd JE 48cfa1 |
(2442) 0x48cfbf MOV (%RDI,%RCX,8),%R9 |
(2442) 0x48cfc3 TEST %R9,%R9 |
(2442) 0x48cfc6 JLE 48cfb7 |
(2442) 0x48cfc8 MOV $0x1,%R8D |
(2442) 0x48cfce CMP $0x1,%R9 |
(2442) 0x48cfd2 JNE 48cfb0 |
(2442) 0x48cfd4 MOV (%RDX,%RAX,8),%R8 |
(2442) 0x48cfd8 JMP 48cfb0 |
0x48cfda NOPW (%RAX,%RAX,1) |
Path / |
Source file and lines | par_strength.c:2311-2320 |
Module | exec |
nb instructions | 27 |
nb uops | 27 |
loop length | 98 |
used x86 registers | 7 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 4.50 cycles |
front end | 4.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.00 | 2.00 | 0.67 | 0.67 | 0.50 | 2.00 | 3.00 | 0.50 | 0.50 | 0.50 | 2.00 | 0.67 |
cycles | 3.00 | 2.00 | 0.67 | 0.67 | 0.50 | 2.00 | 3.00 | 0.50 | 0.50 | 0.50 | 2.00 | 0.67 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 4.59 |
Stall cycles | 0.00 |
Front-end | 4.50 |
Dispatch | 3.00 |
Overall L1 | 4.50 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TEST %RSI,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 48cfa1 <hypre_BoomerAMGCorrectCFMarker+0xe1> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x4,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 48cee6 <hypre_BoomerAMGCorrectCFMarker+0x26> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RSI,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
CMP %RSI,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 48cfbf <hypre_BoomerAMGCorrectCFMarker+0xff> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 48cfa1 <hypre_BoomerAMGCorrectCFMarker+0xe1> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RSI,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SHR $0x2,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA 0x18(%RDI),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 48cf13 <hypre_BoomerAMGCorrectCFMarker+0x53> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
MOV %RSI,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
CMP %RSI,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 48cfbf <hypre_BoomerAMGCorrectCFMarker+0xff> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | par_strength.c:2311-2320 |
Module | exec |
nb instructions | 27 |
nb uops | 27 |
loop length | 98 |
used x86 registers | 7 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 4.50 cycles |
front end | 4.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.00 | 2.00 | 0.67 | 0.67 | 0.50 | 2.00 | 3.00 | 0.50 | 0.50 | 0.50 | 2.00 | 0.67 |
cycles | 3.00 | 2.00 | 0.67 | 0.67 | 0.50 | 2.00 | 3.00 | 0.50 | 0.50 | 0.50 | 2.00 | 0.67 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 4.59 |
Stall cycles | 0.00 |
Front-end | 4.50 |
Dispatch | 3.00 |
Overall L1 | 4.50 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TEST %RSI,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 48cfa1 <hypre_BoomerAMGCorrectCFMarker+0xe1> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x4,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 48cee6 <hypre_BoomerAMGCorrectCFMarker+0x26> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RSI,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
CMP %RSI,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 48cfbf <hypre_BoomerAMGCorrectCFMarker+0xff> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 48cfa1 <hypre_BoomerAMGCorrectCFMarker+0xe1> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RSI,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SHR $0x2,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA 0x18(%RDI),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 48cf13 <hypre_BoomerAMGCorrectCFMarker+0x53> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
MOV %RSI,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
CMP %RSI,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 48cfbf <hypre_BoomerAMGCorrectCFMarker+0xff> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼hypre_BoomerAMGCorrectCFMarker– | 0.01 | 0 |
○Loop 2443 - par_strength.c:2311-2315 - exec | 0.01 | 0.07 |
○Loop 2442 - par_strength.c:2311-2315 - exec | 0 | 0 |