Loop Id: 3150 | Module: exec | Source: par_csr_matop.c:127-242 [...] | Coverage: 0.04% |
---|
Loop Id: 3150 | Module: exec | Source: par_csr_matop.c:127-242 [...] | Coverage: 0.04% |
---|
0x4a9810 MOV -0x78(%RBP),%RSI |
0x4a9814 MOV -0x50(%RBP),%RDI |
0x4a9818 MOV %RBX,(%RSI,%RDI,8) |
0x4a981c MOV -0x70(%RBP),%RSI |
0x4a9820 MOV %R8,(%RSI,%RDI,8) |
0x4a9824 MOV %RDX,%RDI |
0x4a9827 MOV %R13,%R8 |
0x4a982a MOV %RAX,%RBX |
0x4a982d CMP -0x38(%RBP),%RDX |
0x4a9831 JGE 4a99fc |
0x4a9837 CMPQ $0,0x78(%RBP) |
0x4a983c JE 4a9846 |
0x4a983e MOV %RBX,(%R14,%RDI,8) |
0x4a9842 LEA 0x1(%RBX),%RAX |
0x4a9846 CMPQ $0,0x70(%RBP) |
0x4a984b MOV %RDI,-0x50(%RBP) |
0x4a984f JE 4a9920 |
0x4a9855 MOV 0x10(%RBP),%RSI |
0x4a9859 MOV (%RSI,%RDI,8),%R10 |
0x4a985d LEA 0x1(%RDI),%RDX |
0x4a9861 CMP 0x8(%RSI,%RDI,8),%R10 |
0x4a9866 JGE 4a9924 |
0x4a986c MOV %R8,%R13 |
0x4a986f JMP 4a9896 |
(3154) 0x4a9880 INC %R10 |
(3154) 0x4a9883 MOV 0x10(%RBP),%RSI |
(3154) 0x4a9887 MOV -0x50(%RBP),%RDI |
(3154) 0x4a988b CMP 0x8(%RSI,%RDI,8),%R10 |
(3154) 0x4a9890 JGE 4a9927 |
(3154) 0x4a9896 MOV 0x18(%RBP),%RSI |
(3154) 0x4a989a MOV (%RSI,%R10,8),%R12 |
(3154) 0x4a989e MOV 0x50(%RBP),%RDI |
(3154) 0x4a98a2 MOV (%RDI,%R12,8),%RSI |
(3154) 0x4a98a6 MOV 0x8(%RDI,%R12,8),%RDI |
(3154) 0x4a98ab JMP 4a98b3 |
(3156) 0x4a98b0 INC %RSI |
(3156) 0x4a98b3 CMP %RDI,%RSI |
(3156) 0x4a98b6 JGE 4a98e0 |
(3156) 0x4a98b8 MOV 0x58(%RBP),%R9 |
(3156) 0x4a98bc MOV (%R9,%RSI,8),%R9 |
(3156) 0x4a98c0 ADD %R15,%R9 |
(3156) 0x4a98c3 CMP %R8,(%R14,%R9,8) |
(3156) 0x4a98c7 JGE 4a98b0 |
(3156) 0x4a98c9 MOV %R13,(%R14,%R9,8) |
(3156) 0x4a98cd INC %R13 |
(3156) 0x4a98d0 MOV 0x50(%RBP),%RDI |
(3156) 0x4a98d4 MOV 0x8(%RDI,%R12,8),%RDI |
(3156) 0x4a98d9 JMP 4a98b0 |
(3154) 0x4a98e0 MOV 0x40(%RBP),%RDI |
(3154) 0x4a98e4 MOV (%RDI,%R12,8),%RSI |
(3154) 0x4a98e8 MOV 0x8(%RDI,%R12,8),%RDI |
(3154) 0x4a98ed JMP 4a98f3 |
(3155) 0x4a98f0 INC %RSI |
(3155) 0x4a98f3 CMP %RDI,%RSI |
(3155) 0x4a98f6 JGE 4a9880 |
(3155) 0x4a98f8 MOV 0x48(%RBP),%R9 |
(3155) 0x4a98fc MOV (%R9,%RSI,8),%R9 |
(3155) 0x4a9900 CMP %RBX,(%R14,%R9,8) |
(3155) 0x4a9904 JGE 4a98f0 |
(3155) 0x4a9906 MOV %RAX,(%R14,%R9,8) |
(3155) 0x4a990a INC %RAX |
(3155) 0x4a990d MOV 0x40(%RBP),%RDI |
(3155) 0x4a9911 MOV 0x8(%RDI,%R12,8),%RDI |
(3155) 0x4a9916 JMP 4a98f0 |
0x4a9920 LEA 0x1(%RDI),%RDX |
0x4a9924 MOV %R8,%R13 |
0x4a9927 MOV -0x58(%RBP),%RSI |
0x4a992b MOV (%RSI,%RDI,8),%R10 |
0x4a992f JMP 4a9947 |
(3151) 0x4a9940 INC %R10 |
(3151) 0x4a9943 MOV -0x58(%RBP),%RSI |
(3151) 0x4a9947 CMP (%RSI,%RDX,8),%R10 |
(3151) 0x4a994b JGE 4a9810 |
(3151) 0x4a9951 MOV -0x80(%RBP),%RSI |
(3151) 0x4a9955 MOV (%RSI,%R10,8),%R12 |
(3151) 0x4a9959 MOV 0x20(%RBP),%RDI |
(3151) 0x4a995d MOV (%RDI,%R12,8),%RSI |
(3151) 0x4a9961 MOV 0x8(%RDI,%R12,8),%RDI |
(3151) 0x4a9966 JMP 4a9973 |
(3153) 0x4a9970 INC %RSI |
(3153) 0x4a9973 CMP %RDI,%RSI |
(3153) 0x4a9976 JGE 4a99a0 |
(3153) 0x4a9978 MOV (%RCX,%RSI,8),%R9 |
(3153) 0x4a997c CMP %RBX,(%R14,%R9,8) |
(3153) 0x4a9980 JGE 4a9970 |
(3153) 0x4a9982 MOV %RAX,(%R14,%R9,8) |
(3153) 0x4a9986 INC %RAX |
(3153) 0x4a9989 MOV 0x20(%RBP),%RDI |
(3153) 0x4a998d MOV 0x8(%RDI,%R12,8),%RDI |
(3153) 0x4a9992 JMP 4a9970 |
(3151) 0x4a99a0 CMPQ $0,0x88(%RBP) |
(3151) 0x4a99a8 JE 4a9940 |
(3151) 0x4a99aa MOV 0x30(%RBP),%RDI |
(3151) 0x4a99ae MOV (%RDI,%R12,8),%RSI |
(3151) 0x4a99b2 MOV 0x8(%RDI,%R12,8),%RDI |
(3151) 0x4a99b7 JMP 4a99c3 |
(3152) 0x4a99c0 INC %RSI |
(3152) 0x4a99c3 CMP %RDI,%RSI |
(3152) 0x4a99c6 JGE 4a9940 |
(3152) 0x4a99cc MOV 0x38(%RBP),%R9 |
(3152) 0x4a99d0 MOV (%R9,%RSI,8),%R9 |
(3152) 0x4a99d4 MOV 0x60(%RBP),%R11 |
(3152) 0x4a99d8 MOV (%R11,%R9,8),%R9 |
(3152) 0x4a99dc ADD %R15,%R9 |
(3152) 0x4a99df CMP %R8,(%R14,%R9,8) |
(3152) 0x4a99e3 JGE 4a99c0 |
(3152) 0x4a99e5 MOV %R13,(%R14,%R9,8) |
(3152) 0x4a99e9 INC %R13 |
(3152) 0x4a99ec MOV 0x30(%RBP),%RDI |
(3152) 0x4a99f0 MOV 0x8(%RDI,%R12,8),%RDI |
(3152) 0x4a99f5 JMP 4a99c0 |
/home/eoseret/qaas_runs_CPU_9468/171-586-9096/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 127 - 242 |
-------------------------------------------------------------------------------- |
127: for (i1 = ns; i1 < ne; i1++) |
[...] |
135: if ( allsquare ) { |
136: B_marker[i1] = jj_count_diag; |
137: jj_count_diag++; |
[...] |
144: if (num_cols_offd_A) |
145: { |
146: for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++) |
147: { |
148: i2 = A_offd_j[jj2]; |
[...] |
154: for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++) |
155: { |
156: i3 = num_cols_diag_B+B_ext_offd_j[jj3]; |
[...] |
164: if (B_marker[i3] < jj_row_begin_offd) |
165: { |
166: B_marker[i3] = jj_count_offd; |
167: jj_count_offd++; |
168: } |
169: } |
170: for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++) |
171: { |
172: i3 = B_ext_diag_j[jj3]; |
173: |
174: if (B_marker[i3] < jj_row_begin_diag) |
175: { |
176: B_marker[i3] = jj_count_diag; |
177: jj_count_diag++; |
[...] |
187: for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++) |
188: { |
189: i2 = A_diag_j[jj2]; |
[...] |
195: for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++) |
196: { |
197: i3 = B_diag_j[jj3]; |
[...] |
205: if (B_marker[i3] < jj_row_begin_diag) |
206: { |
207: B_marker[i3] = jj_count_diag; |
208: jj_count_diag++; |
[...] |
216: if (num_cols_offd_B) |
217: { |
218: for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++) |
219: { |
220: i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]]; |
[...] |
228: if (B_marker[i3] < jj_row_begin_offd) |
229: { |
230: B_marker[i3] = jj_count_offd; |
231: jj_count_offd++; |
[...] |
241: (*C_diag_i)[i1] = jj_row_begin_diag; |
242: (*C_offd_i)[i1] = jj_row_begin_offd; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 8.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.36 |
Bottlenecks | micro-operation queue, |
Function | hypre_ParMatmul_RowSizes.extracted |
Source | par_csr_matop.c:127-127,par_csr_matop.c:135-137,par_csr_matop.c:144-146,par_csr_matop.c:187-187,par_csr_matop.c:241-242 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 5.00 |
CQA cycles if no scalar integer | 5.00 |
CQA cycles if FP arith vectorized | 5.00 |
CQA cycles if fully vectorized | 0.63 |
Front-end cycles | 5.00 |
DIV/SQRT cycles | 2.00 |
P0 cycles | 1.40 |
P1 cycles | 3.67 |
P2 cycles | 3.67 |
P3 cycles | 2.00 |
P4 cycles | 1.40 |
P5 cycles | 2.00 |
P6 cycles | 2.00 |
P7 cycles | 2.00 |
P8 cycles | 2.00 |
P9 cycles | 1.20 |
P10 cycles | 3.67 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 5.13 |
Stall cycles (UFS) | 0.00 |
Nb insns | 29.00 |
Nb uops | 29.00 |
Nb loads | 11.00 |
Nb stores | 4.00 |
Nb stack references | 8.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 24.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 88.00 |
Bytes stored | 32.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 8.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.36 |
Bottlenecks | micro-operation queue, |
Function | hypre_ParMatmul_RowSizes.extracted |
Source | par_csr_matop.c:127-127,par_csr_matop.c:135-137,par_csr_matop.c:144-146,par_csr_matop.c:187-187,par_csr_matop.c:241-242 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 5.00 |
CQA cycles if no scalar integer | 5.00 |
CQA cycles if FP arith vectorized | 5.00 |
CQA cycles if fully vectorized | 0.63 |
Front-end cycles | 5.00 |
DIV/SQRT cycles | 2.00 |
P0 cycles | 1.40 |
P1 cycles | 3.67 |
P2 cycles | 3.67 |
P3 cycles | 2.00 |
P4 cycles | 1.40 |
P5 cycles | 2.00 |
P6 cycles | 2.00 |
P7 cycles | 2.00 |
P8 cycles | 2.00 |
P9 cycles | 1.20 |
P10 cycles | 3.67 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 5.13 |
Stall cycles (UFS) | 0.00 |
Nb insns | 29.00 |
Nb uops | 29.00 |
Nb loads | 11.00 |
Nb stores | 4.00 |
Nb stack references | 8.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 24.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 88.00 |
Bytes stored | 32.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Path / |
Function | hypre_ParMatmul_RowSizes.extracted |
Source file and lines | par_csr_matop.c:127-242 |
Module | exec |
nb instructions | 29 |
nb uops | 29 |
loop length | 114 |
used x86 registers | 10 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 8 |
micro-operation queue | 5.00 cycles |
front end | 5.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.00 | 1.40 | 3.67 | 3.67 | 2.00 | 1.40 | 2.00 | 2.00 | 2.00 | 2.00 | 1.20 | 3.67 |
cycles | 2.00 | 1.40 | 3.67 | 3.67 | 2.00 | 1.40 | 2.00 | 2.00 | 2.00 | 2.00 | 1.20 | 3.67 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 5.13 |
Stall cycles | 0.00 |
Front-end | 5.00 |
Dispatch | 3.67 |
Overall L1 | 5.00 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV -0x78(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x50(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RBX,(%RSI,%RDI,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x70(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,(%RSI,%RDI,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R13,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP -0x38(%RBP),%RDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JGE 4a99fc <hypre_ParMatmul_RowSizes.extracted+0x2dc> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMPQ $0,0x78(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JE 4a9846 <hypre_ParMatmul_RowSizes.extracted+0x126> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RBX,(%R14,%RDI,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x1(%RBX),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMPQ $0,0x70(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RDI,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JE 4a9920 <hypre_ParMatmul_RowSizes.extracted+0x200> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x10(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RSI,%RDI,8),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x1(%RDI),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP 0x8(%RSI,%RDI,8),%R10 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JGE 4a9924 <hypre_ParMatmul_RowSizes.extracted+0x204> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R8,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JMP 4a9896 <hypre_ParMatmul_RowSizes.extracted+0x176> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
LEA 0x1(%RDI),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R8,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x58(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RSI,%RDI,8),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 4a9947 <hypre_ParMatmul_RowSizes.extracted+0x227> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
Function | hypre_ParMatmul_RowSizes.extracted |
Source file and lines | par_csr_matop.c:127-242 |
Module | exec |
nb instructions | 29 |
nb uops | 29 |
loop length | 114 |
used x86 registers | 10 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 8 |
micro-operation queue | 5.00 cycles |
front end | 5.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.00 | 1.40 | 3.67 | 3.67 | 2.00 | 1.40 | 2.00 | 2.00 | 2.00 | 2.00 | 1.20 | 3.67 |
cycles | 2.00 | 1.40 | 3.67 | 3.67 | 2.00 | 1.40 | 2.00 | 2.00 | 2.00 | 2.00 | 1.20 | 3.67 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 5.13 |
Stall cycles | 0.00 |
Front-end | 5.00 |
Dispatch | 3.67 |
Overall L1 | 5.00 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV -0x78(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x50(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RBX,(%RSI,%RDI,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x70(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,(%RSI,%RDI,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R13,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP -0x38(%RBP),%RDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JGE 4a99fc <hypre_ParMatmul_RowSizes.extracted+0x2dc> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMPQ $0,0x78(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JE 4a9846 <hypre_ParMatmul_RowSizes.extracted+0x126> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RBX,(%R14,%RDI,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x1(%RBX),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMPQ $0,0x70(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RDI,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JE 4a9920 <hypre_ParMatmul_RowSizes.extracted+0x200> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x10(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RSI,%RDI,8),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x1(%RDI),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP 0x8(%RSI,%RDI,8),%R10 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JGE 4a9924 <hypre_ParMatmul_RowSizes.extracted+0x204> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R8,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JMP 4a9896 <hypre_ParMatmul_RowSizes.extracted+0x176> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
LEA 0x1(%RDI),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R8,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x58(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RSI,%RDI,8),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 4a9947 <hypre_ParMatmul_RowSizes.extracted+0x227> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |