Loop Id: 3835 | Module: exec | Source: csr_matvec.c:560-579 [...] | Coverage: 0.01% |
---|
Loop Id: 3835 | Module: exec | Source: csr_matvec.c:560-579 [...] | Coverage: 0.01% |
---|
0x4c9150 MOV -0x60(%RBP),%R11 |
0x4c9154 VMOVSD %XMM4,(%R11,%R10,8) |
0x4c915a LEA 0x1(%R8),%R10 |
0x4c915e INC %R9 |
0x4c9161 CMP %RCX,%R8 |
0x4c9164 MOV %R10,%R8 |
0x4c9167 JE 4c8f63 |
0x4c916d LEA (%RAX,%R8,1),%R10 |
0x4c9171 VMOVSD (%R11,%R10,8),%XMM4 |
0x4c9177 TEST %RDX,%RDX |
0x4c917a JE 4c9260 |
0x4c9180 VMOVQ %R10,%XMM5 |
0x4c9185 VPBROADCASTQ %XMM5,%YMM6 |
0x4c918a VPXOR %XMM5,%XMM5,%XMM5 |
0x4c918e XOR %R11D,%R11D |
0x4c9191 NOPW %CS:(%RAX,%RAX,1) |
(3836) 0x4c91a0 VMOVQ %R11,%XMM7 |
(3836) 0x4c91a5 VPBROADCASTQ %XMM7,%YMM7 |
(3836) 0x4c91aa VPOR %YMM1,%YMM7,%YMM7 |
(3836) 0x4c91ae VPMULUDQ %YMM7,%YMM2,%YMM8 |
(3836) 0x4c91b2 VPSRLQ $0x20,%YMM7,%YMM9 |
(3836) 0x4c91b7 VPMULUDQ %YMM0,%YMM9,%YMM9 |
(3836) 0x4c91bb VPADDQ %YMM8,%YMM9,%YMM8 |
(3836) 0x4c91c0 VPSLLQ $0x20,%YMM8,%YMM8 |
(3836) 0x4c91c6 VPMULUDQ %YMM7,%YMM0,%YMM7 |
(3836) 0x4c91ca VPADDQ %YMM7,%YMM6,%YMM7 |
(3836) 0x4c91ce VPADDQ %YMM7,%YMM8,%YMM7 |
(3836) 0x4c91d2 VPSLLQ $0x3,%YMM7,%YMM7 |
(3836) 0x4c91d7 VPADDQ %YMM7,%YMM3,%YMM7 |
(3836) 0x4c91db VPEXTRQ $0x1,%XMM7,%R15 |
(3836) 0x4c91e1 VEXTRACTI128 $0x1,%YMM7,%XMM8 |
(3836) 0x4c91e7 VPEXTRQ $0x1,%XMM8,%R12 |
(3836) 0x4c91ed VMOVQ %XMM8,%R13 |
(3836) 0x4c91f2 VMOVSD (%R13),%XMM8 |
(3836) 0x4c91f8 VMOVHPD (%R12),%XMM8,%XMM8 |
(3836) 0x4c91fe VMOVQ %XMM7,%R12 |
(3836) 0x4c9203 VMOVSD (%R12),%XMM7 |
(3836) 0x4c9209 VMOVHPD (%R15),%XMM7,%XMM7 |
(3836) 0x4c920e VINSERTF128 $0x1,%XMM8,%YMM7,%YMM7 |
(3836) 0x4c9214 VADDPD %YMM7,%YMM5,%YMM5 |
(3836) 0x4c9218 ADD $0x4,%R11 |
(3836) 0x4c921c CMP %RSI,%R11 |
(3836) 0x4c921f JLE 4c91a0 |
0x4c9225 VEXTRACTF128 $0x1,%YMM5,%XMM6 |
0x4c922b VADDPD %XMM6,%XMM5,%XMM5 |
0x4c922f VSHUFPD $0x1,%XMM5,%XMM5,%XMM6 |
0x4c9234 VADDSD %XMM6,%XMM5,%XMM5 |
0x4c9238 VADDSD %XMM5,%XMM4,%XMM4 |
0x4c923c MOV %RDX,%R15 |
0x4c923f MOV -0x58(%RBP),%R12 |
0x4c9243 CMP %R12,%RDX |
0x4c9246 MOV -0x38(%RBP),%R13 |
0x4c924a JE 4c9150 |
0x4c9250 JMP 4c9263 |
0x4c9260 XOR %R15D,%R15D |
0x4c9263 MOV %R12,%R11 |
0x4c9266 SUB %R15,%R11 |
0x4c9269 IMUL %R13,%R15 |
0x4c926d ADD %R9,%R15 |
0x4c9270 LEA (%RBX,%R15,8),%R15 |
0x4c9274 NOPW %CS:(%RAX,%RAX,1) |
(3834) 0x4c9280 VADDSD (%R15),%XMM4,%XMM4 |
(3834) 0x4c9285 ADD %RDI,%R15 |
(3834) 0x4c9288 DEC %R11 |
(3834) 0x4c928b JNE 4c9280 |
0x4c928d JMP 4c9150 |
/home/eoseret/qaas_runs_CPU_9468/171-586-9096/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 560 - 579 |
-------------------------------------------------------------------------------- |
560: #pragma omp for HYPRE_SMP_SCHEDULE |
[...] |
573: #pragma omp for HYPRE_SMP_SCHEDULE |
574: #endif |
575: for (i = 0; i < y_size; i++) |
576: { |
577: for (j = 0; j < num_threads; j++) |
578: { |
579: y_data[i] += y_data_expand[j*y_size + i]; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.49 |
CQA speedup if FP arith vectorized | 1.76 |
CQA speedup if fully vectorized | 7.35 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.42 |
Bottlenecks | |
Function | hypre_CSRMatrixMatvecT.extracted.49 |
Source | csr_matvec.c:560-560,csr_matvec.c:573-579 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 4.39 |
CQA cycles if no scalar integer | 2.94 |
CQA cycles if FP arith vectorized | 2.49 |
CQA cycles if fully vectorized | 0.60 |
Front-end cycles | 4.39 |
DIV/SQRT cycles | 2.07 |
P0 cycles | 3.10 |
P1 cycles | 1.11 |
P2 cycles | 1.11 |
P3 cycles | 0.50 |
P4 cycles | 2.97 |
P5 cycles | 2.00 |
P6 cycles | 0.50 |
P7 cycles | 0.50 |
P8 cycles | 0.50 |
P9 cycles | 2.00 |
P10 cycles | 1.11 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 4.82 |
Stall cycles (UFS) | 0.03 |
Nb insns | 26.33 |
Nb uops | 26.33 |
Nb loads | 3.33 |
Nb stores | 1.00 |
Nb stack references | 2.33 |
FLOP/cycle | 0.61 |
Nb FLOP add-sub | 2.67 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 7.96 |
Bytes prefetched | 0.00 |
Bytes loaded | 26.67 |
Bytes stored | 8.00 |
Stride 0 | 1.00 |
Stride 1 | 0.00 |
Stride n | 0.00 |
Stride unknown | 2.00 |
Stride indirect | 1.33 |
Vectorization ratio all | 17.78 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 29.17 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 25.00 |
Vector-efficiency ratio all | 14.72 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 16.15 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 15.63 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 2.38 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 8.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.76 |
Bottlenecks | micro-operation queue, |
Function | hypre_CSRMatrixMatvecT.extracted.49 |
Source | csr_matvec.c:560-560,csr_matvec.c:573-579 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 3.17 |
CQA cycles if no scalar integer | 1.33 |
CQA cycles if FP arith vectorized | 3.17 |
CQA cycles if fully vectorized | 0.40 |
Front-end cycles | 3.17 |
DIV/SQRT cycles | 1.40 |
P0 cycles | 1.80 |
P1 cycles | 0.67 |
P2 cycles | 0.67 |
P3 cycles | 0.50 |
P4 cycles | 1.40 |
P5 cycles | 1.40 |
P6 cycles | 0.50 |
P7 cycles | 0.50 |
P8 cycles | 0.50 |
P9 cycles | 1.40 |
P10 cycles | 0.67 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 4.09 |
Stall cycles (UFS) | 0.08 |
Nb insns | 19.00 |
Nb uops | 19.00 |
Nb loads | 2.00 |
Nb stores | 1.00 |
Nb stack references | 1.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 7.58 |
Bytes prefetched | 0.00 |
Bytes loaded | 16.00 |
Bytes stored | 8.00 |
Stride 0 | 1.00 |
Stride 1 | 0.00 |
Stride n | 0.00 |
Stride unknown | 2.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.42 |
CQA speedup if FP arith vectorized | 2.59 |
CQA speedup if fully vectorized | 7.35 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.42 |
Bottlenecks | micro-operation queue, |
Function | hypre_CSRMatrixMatvecT.extracted.49 |
Source | csr_matvec.c:560-560,csr_matvec.c:573-579 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 5.67 |
CQA cycles if no scalar integer | 4.00 |
CQA cycles if FP arith vectorized | 2.19 |
CQA cycles if fully vectorized | 0.77 |
Front-end cycles | 5.67 |
DIV/SQRT cycles | 2.70 |
P0 cycles | 4.00 |
P1 cycles | 1.33 |
P2 cycles | 1.33 |
P3 cycles | 0.50 |
P4 cycles | 4.00 |
P5 cycles | 2.70 |
P6 cycles | 0.50 |
P7 cycles | 0.50 |
P8 cycles | 0.50 |
P9 cycles | 2.60 |
P10 cycles | 1.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 5.84 |
Stall cycles (UFS) | 0.00 |
Nb insns | 34.00 |
Nb uops | 34.00 |
Nb loads | 4.00 |
Nb stores | 1.00 |
Nb stack references | 3.00 |
FLOP/cycle | 0.71 |
Nb FLOP add-sub | 4.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 7.06 |
Bytes prefetched | 0.00 |
Bytes loaded | 32.00 |
Bytes stored | 8.00 |
Stride 0 | 1.00 |
Stride 1 | 0.00 |
Stride n | 0.00 |
Stride unknown | 2.00 |
Stride indirect | 2.00 |
Vectorization ratio all | 26.67 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 33.33 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 37.50 |
Vector-efficiency ratio all | 15.83 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 16.67 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 17.19 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.24 |
CQA speedup if FP arith vectorized | 2.04 |
CQA speedup if fully vectorized | 6.93 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.24 |
Bottlenecks | micro-operation queue, |
Function | hypre_CSRMatrixMatvecT.extracted.49 |
Source | csr_matvec.c:560-560,csr_matvec.c:573-579 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 4.33 |
CQA cycles if no scalar integer | 3.50 |
CQA cycles if FP arith vectorized | 2.13 |
CQA cycles if fully vectorized | 0.63 |
Front-end cycles | 4.33 |
DIV/SQRT cycles | 2.10 |
P0 cycles | 3.50 |
P1 cycles | 1.33 |
P2 cycles | 1.33 |
P3 cycles | 0.50 |
P4 cycles | 3.50 |
P5 cycles | 1.90 |
P6 cycles | 0.50 |
P7 cycles | 0.50 |
P8 cycles | 0.50 |
P9 cycles | 2.00 |
P10 cycles | 1.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 4.54 |
Stall cycles (UFS) | 0.00 |
Nb insns | 26.00 |
Nb uops | 26.00 |
Nb loads | 4.00 |
Nb stores | 1.00 |
Nb stack references | 3.00 |
FLOP/cycle | 0.92 |
Nb FLOP add-sub | 4.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 9.23 |
Bytes prefetched | 0.00 |
Bytes loaded | 32.00 |
Bytes stored | 8.00 |
Stride 0 | 1.00 |
Stride 1 | 0.00 |
Stride n | 0.00 |
Stride unknown | 2.00 |
Stride indirect | 2.00 |
Vectorization ratio all | 26.67 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 25.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 37.50 |
Vector-efficiency ratio all | 15.83 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 15.63 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 17.19 |
Path / |
Function | hypre_CSRMatrixMatvecT.extracted.49 |
Source file and lines | csr_matvec.c:560-579 |
Module | exec |
nb instructions | 26.33 |
nb uops | 26.33 |
loop length | 122.33 |
used x86 registers | 11.67 |
used mmx registers | 0 |
used xmm registers | 2.33 |
used ymm registers | 1.33 |
used zmm registers | 0 |
nb stack references | 2.33 |
micro-operation queue | 4.39 cycles |
front end | 4.39 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.07 | 2.97 | 1.11 | 1.11 | 0.50 | 2.97 | 2.00 | 0.50 | 0.50 | 0.50 | 2.00 | 1.11 |
cycles | 2.07 | 3.10 | 1.11 | 1.11 | 0.50 | 2.97 | 2.00 | 0.50 | 0.50 | 0.50 | 2.00 | 1.11 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 4.82 |
Stall cycles | 0.03 |
ROB full (events) | 0.03 |
Front-end | 4.39 |
Dispatch | 3.10 |
Data deps. | 1.00 |
Overall L1 | 4.39 |
all | 8% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 11% |
all | 28% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 33% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 17% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 29% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 13% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 13% |
all | 16% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 16% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 14% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 16% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 15% |
Function | hypre_CSRMatrixMatvecT.extracted.49 |
Source file and lines | csr_matvec.c:560-579 |
Module | exec |
nb instructions | 19 |
nb uops | 19 |
loop length | 85 |
used x86 registers | 12 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 1 |
micro-operation queue | 3.17 cycles |
front end | 3.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.40 | 1.40 | 0.67 | 0.67 | 0.50 | 1.40 | 1.40 | 0.50 | 0.50 | 0.50 | 1.40 | 0.67 |
cycles | 1.40 | 1.80 | 0.67 | 0.67 | 0.50 | 1.40 | 1.40 | 0.50 | 0.50 | 0.50 | 1.40 | 0.67 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 4.09 |
Stall cycles | 0.08 |
ROB full (events) | 0.10 |
Front-end | 3.17 |
Dispatch | 1.80 |
Data deps. | 1.00 |
Overall L1 | 3.17 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV -0x60(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM4,(%R11,%R10,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x1(%R8),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RCX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R10,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JE 4c8f63 <hypre_CSRMatrixMatvecT.extracted.49+0x1f3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (%RAX,%R8,1),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD (%R11,%R10,8),%XMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 4c9260 <hypre_CSRMatrixMatvecT.extracted.49+0x4f0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R12,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %R15,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
IMUL %R13,%R15 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %R9,%R15 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RBX,%R15,8),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 4c9150 <hypre_CSRMatrixMatvecT.extracted.49+0x3e0> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
Function | hypre_CSRMatrixMatvecT.extracted.49 |
Source file and lines | csr_matvec.c:560-579 |
Module | exec |
nb instructions | 34 |
nb uops | 34 |
loop length | 159 |
used x86 registers | 12 |
used mmx registers | 0 |
used xmm registers | 3 |
used ymm registers | 2 |
used zmm registers | 0 |
nb stack references | 3 |
micro-operation queue | 5.67 cycles |
front end | 5.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.70 | 4.00 | 1.33 | 1.33 | 0.50 | 4.00 | 2.70 | 0.50 | 0.50 | 0.50 | 2.60 | 1.33 |
cycles | 2.70 | 4.00 | 1.33 | 1.33 | 0.50 | 4.00 | 2.70 | 0.50 | 0.50 | 0.50 | 2.60 | 1.33 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 5.84 |
Stall cycles | 0.00 |
Front-end | 5.67 |
Dispatch | 4.00 |
Data deps. | 1.00 |
Overall L1 | 5.67 |
all | 12% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 16% |
all | 42% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 33% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 26% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 33% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 37% |
all | 14% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 14% |
all | 17% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 16% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 15% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 16% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 17% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV -0x60(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM4,(%R11,%R10,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x1(%R8),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RCX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R10,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JE 4c8f63 <hypre_CSRMatrixMatvecT.extracted.49+0x1f3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (%RAX,%R8,1),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD (%R11,%R10,8),%XMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 4c9260 <hypre_CSRMatrixMatvecT.extracted.49+0x4f0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVQ %R10,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VPBROADCASTQ %XMM5,%YMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPXOR %XMM5,%XMM5,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %R11D,%R11D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VEXTRACTF128 $0x1,%YMM5,%XMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD %XMM6,%XMM5,%XMM5 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VSHUFPD $0x1,%XMM5,%XMM5,%XMM6 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VADDSD %XMM6,%XMM5,%XMM5 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDSD %XMM5,%XMM4,%XMM4 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
MOV %RDX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x58(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %R12,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x38(%RBP),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JE 4c9150 <hypre_CSRMatrixMatvecT.extracted.49+0x3e0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 4c9263 <hypre_CSRMatrixMatvecT.extracted.49+0x4f3> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV %R12,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %R15,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
IMUL %R13,%R15 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %R9,%R15 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RBX,%R15,8),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 4c9150 <hypre_CSRMatrixMatvecT.extracted.49+0x3e0> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
Function | hypre_CSRMatrixMatvecT.extracted.49 |
Source file and lines | csr_matvec.c:560-579 |
Module | exec |
nb instructions | 26 |
nb uops | 26 |
loop length | 123 |
used x86 registers | 11 |
used mmx registers | 0 |
used xmm registers | 3 |
used ymm registers | 2 |
used zmm registers | 0 |
nb stack references | 3 |
micro-operation queue | 4.33 cycles |
front end | 4.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.10 | 3.50 | 1.33 | 1.33 | 0.50 | 3.50 | 1.90 | 0.50 | 0.50 | 0.50 | 2.00 | 1.33 |
cycles | 2.10 | 3.50 | 1.33 | 1.33 | 0.50 | 3.50 | 1.90 | 0.50 | 0.50 | 0.50 | 2.00 | 1.33 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 4.54 |
Stall cycles | 0.00 |
Front-end | 4.33 |
Dispatch | 3.50 |
Data deps. | 1.00 |
Overall L1 | 4.33 |
all | 12% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 16% |
all | 42% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 33% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 26% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 25% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 37% |
all | 14% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 14% |
all | 17% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 16% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 15% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 15% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 17% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV -0x60(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM4,(%R11,%R10,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x1(%R8),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RCX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R10,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JE 4c8f63 <hypre_CSRMatrixMatvecT.extracted.49+0x1f3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (%RAX,%R8,1),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD (%R11,%R10,8),%XMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 4c9260 <hypre_CSRMatrixMatvecT.extracted.49+0x4f0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVQ %R10,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VPBROADCASTQ %XMM5,%YMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPXOR %XMM5,%XMM5,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %R11D,%R11D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VEXTRACTF128 $0x1,%YMM5,%XMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD %XMM6,%XMM5,%XMM5 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VSHUFPD $0x1,%XMM5,%XMM5,%XMM6 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VADDSD %XMM6,%XMM5,%XMM5 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDSD %XMM5,%XMM4,%XMM4 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
MOV %RDX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x58(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %R12,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x38(%RBP),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JE 4c9150 <hypre_CSRMatrixMatvecT.extracted.49+0x3e0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |