Loop Id: 3173 | Module: exec | Source: par_csr_matop.c:970-989 [...] | Coverage: 0.03% |
---|
Loop Id: 3173 | Module: exec | Source: par_csr_matop.c:970-989 [...] | Coverage: 0.03% |
---|
0x4aaa90 MOV -0x88(%RBP),%R10 [7] |
0x4aaa97 VMOVSD (%R10,%R8,8),%XMM1 [9] |
0x4aaa9d VFMADD213SD (%RBX,%R11,8),%XMM0,%XMM1 [4] |
0x4aaaa3 VMOVSD %XMM1,(%RBX,%R11,8) [4] |
0x4aaaa9 MOV %R12,%R13 |
0x4aaaac INC %R8 |
0x4aaaaf CMP %R9,%R8 |
0x4aaab2 JGE 4aa9b0 |
0x4aaab8 MOV -0xe8(%RBP),%R10 [7] |
0x4aaabf MOV (%R10,%R8,8),%R10 [1] |
0x4aaac3 MOV -0xf0(%RBP),%R11 [7] |
0x4aaaca MOV (%R11,%R10,8),%R10 [3] |
0x4aaace MOV %R13,%R12 |
0x4aaad1 ADD %R10,%R13 |
0x4aaad4 MOV (%RDI,%R13,8),%R11 [8] |
0x4aaad8 CMP -0x30(%RBP),%R11 [7] |
0x4aaadc JGE 4aaa90 |
0x4aaade MOV %RCX,(%RDI,%R13,8) [8] |
0x4aaae2 MOV -0x88(%RBP),%R9 [7] |
0x4aaae9 VMULSD (%R9,%R8,8),%XMM0,%XMM1 [9] |
0x4aaaef VMOVSD %XMM1,(%RBX,%RCX,8) [6] |
0x4aaaf4 MOV -0x90(%RBP),%R9 [7] |
0x4aaafb MOV %R10,(%R9,%RCX,8) [2] |
0x4aaaff INC %RCX |
0x4aab02 MOV -0x68(%RBP),%R9 [7] |
0x4aab06 MOV 0x8(%R9,%RSI,8),%R9 [5] |
0x4aab0b JMP 4aaaa9 |
/home/eoseret/qaas_runs_CPU_9468/171-586-9096/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 970 - 989 |
-------------------------------------------------------------------------------- |
970: for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++) |
971: { |
972: i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]]; |
[...] |
980: if (B_marker[i3] < jj_row_begin_offd) |
981: { |
982: B_marker[i3] = jj_count_offd; |
983: C_offd_data[jj_count_offd] = a_entry*B_offd_data[jj3]; |
984: C_offd_j[jj_count_offd] = i3-num_cols_diag_B; |
985: jj_count_offd++; |
986: } |
987: else |
988: { |
989: C_offd_data[B_marker[i3]] += a_entry*B_offd_data[jj3]; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.75 |
CQA speedup if FP arith vectorized | 2.85 |
CQA speedup if fully vectorized | 8.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.08 |
Bottlenecks | |
Function | hypre_ParMatmul.extracted.12 |
Source | par_csr_matop.c:970-972,par_csr_matop.c:980-989 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 3.50 |
CQA cycles if no scalar integer | 2.00 |
CQA cycles if FP arith vectorized | 1.23 |
CQA cycles if fully vectorized | 0.44 |
Front-end cycles | 3.42 |
DIV/SQRT cycles | 1.35 |
P0 cycles | 1.05 |
P1 cycles | 3.33 |
P2 cycles | 3.33 |
P3 cycles | 1.00 |
P4 cycles | 1.00 |
P5 cycles | 1.10 |
P6 cycles | 1.00 |
P7 cycles | 1.00 |
P8 cycles | 1.00 |
P9 cycles | 1.00 |
P10 cycles | 3.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 2 |
FE+BE cycles (UFS) | 4.63 |
Stall cycles (UFS) | 0.98 |
Nb insns | 20.00 |
Nb uops | 19.50 |
Nb loads | 10.00 |
Nb stores | 2.00 |
Nb stack references | 5.00 |
FLOP/cycle | 0.43 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.50 |
Nb FLOP fma | 0.50 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 27.33 |
Bytes prefetched | 0.00 |
Bytes loaded | 80.00 |
Bytes stored | 16.00 |
Stride 0 | 1.00 |
Stride 1 | 2.00 |
Stride n | 0.50 |
Stride unknown | 1.00 |
Stride indirect | 2.00 |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | 0.00 |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | 0.00 |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | 12.50 |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | 12.50 |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 2.00 |
CQA speedup if FP arith vectorized | 2.67 |
CQA speedup if fully vectorized | 8.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.09 |
Bottlenecks | micro-operation queue, |
Function | hypre_ParMatmul.extracted.12 |
Source | par_csr_matop.c:970-972,par_csr_matop.c:980-989 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 4.00 |
CQA cycles if no scalar integer | 2.00 |
CQA cycles if FP arith vectorized | 1.50 |
CQA cycles if fully vectorized | 0.50 |
Front-end cycles | 4.00 |
DIV/SQRT cycles | 1.20 |
P0 cycles | 1.20 |
P1 cycles | 3.67 |
P2 cycles | 3.67 |
P3 cycles | 1.50 |
P4 cycles | 1.20 |
P5 cycles | 1.20 |
P6 cycles | 1.50 |
P7 cycles | 1.50 |
P8 cycles | 1.50 |
P9 cycles | 1.20 |
P10 cycles | 3.67 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 2 |
FE+BE cycles (UFS) | 4.74 |
Stall cycles (UFS) | 0.50 |
Nb insns | 23.00 |
Nb uops | 23.00 |
Nb loads | 11.00 |
Nb stores | 3.00 |
Nb stack references | 6.00 |
FLOP/cycle | 0.25 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 1.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 28.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 88.00 |
Bytes stored | 24.00 |
Stride 0 | 1.00 |
Stride 1 | 4.00 |
Stride n | 0.00 |
Stride unknown | 1.00 |
Stride indirect | 2.00 |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | 0.00 |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | 12.50 |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.50 |
CQA speedup if FP arith vectorized | 3.13 |
CQA speedup if fully vectorized | 8.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.06 |
Bottlenecks | P2, P3, P11, |
Function | hypre_ParMatmul.extracted.12 |
Source | par_csr_matop.c:970-972,par_csr_matop.c:980-989 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 3.00 |
CQA cycles if no scalar integer | 2.00 |
CQA cycles if FP arith vectorized | 0.96 |
CQA cycles if fully vectorized | 0.38 |
Front-end cycles | 2.83 |
DIV/SQRT cycles | 1.50 |
P0 cycles | 0.90 |
P1 cycles | 3.00 |
P2 cycles | 3.00 |
P3 cycles | 0.50 |
P4 cycles | 0.80 |
P5 cycles | 1.00 |
P6 cycles | 0.50 |
P7 cycles | 0.50 |
P8 cycles | 0.50 |
P9 cycles | 0.80 |
P10 cycles | 3.00 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 2 |
FE+BE cycles (UFS) | 4.52 |
Stall cycles (UFS) | 1.46 |
Nb insns | 17.00 |
Nb uops | 16.00 |
Nb loads | 9.00 |
Nb stores | 1.00 |
Nb stack references | 4.00 |
FLOP/cycle | 0.67 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 1.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 26.67 |
Bytes prefetched | 0.00 |
Bytes loaded | 72.00 |
Bytes stored | 8.00 |
Stride 0 | 1.00 |
Stride 1 | 0.00 |
Stride n | 1.00 |
Stride unknown | 1.00 |
Stride indirect | 2.00 |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | 0.00 |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | 12.50 |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Path / |
Function | hypre_ParMatmul.extracted.12 |
Source file and lines | par_csr_matop.c:970-989 |
Module | exec |
nb instructions | 20 |
nb uops | 19.50 |
loop length | 89 |
used x86 registers | 10 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 5 |
micro-operation queue | 3.42 cycles |
front end | 3.42 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.35 | 1.05 | 3.33 | 3.33 | 1.00 | 1.00 | 1.10 | 1.00 | 1.00 | 1.00 | 1.00 | 3.33 |
cycles | 1.35 | 1.05 | 3.33 | 3.33 | 1.00 | 1.00 | 1.10 | 1.00 | 1.00 | 1.00 | 1.00 | 3.33 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 2.00 |
FE+BE cycles | 4.63 |
Stall cycles | 0.98 |
LM full (events) | 2.17 |
Front-end | 3.42 |
Dispatch | 3.33 |
Data deps. | 2.00 |
Overall L1 | 3.50 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 12% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 12% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Function | hypre_ParMatmul.extracted.12 |
Source file and lines | par_csr_matop.c:970-989 |
Module | exec |
nb instructions | 23 |
nb uops | 23 |
loop length | 100 |
used x86 registers | 11 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 6 |
micro-operation queue | 4.00 cycles |
front end | 4.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.20 | 1.20 | 3.67 | 3.67 | 1.50 | 1.20 | 1.20 | 1.50 | 1.50 | 1.50 | 1.20 | 3.67 |
cycles | 1.20 | 1.20 | 3.67 | 3.67 | 1.50 | 1.20 | 1.20 | 1.50 | 1.50 | 1.50 | 1.20 | 3.67 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 2.00 |
FE+BE cycles | 4.74 |
Stall cycles | 0.50 |
LM full (events) | 1.52 |
Front-end | 4.00 |
Dispatch | 3.67 |
Data deps. | 2.00 |
Overall L1 | 4.00 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV %R12,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
INC %R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %R9,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4aa9b0 <hypre_ParMatmul.extracted.12+0x420> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0xe8(%RBP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R10,%R8,8),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xf0(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R11,%R10,8),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R13,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD %R10,%R13 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV (%RDI,%R13,8),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP -0x30(%RBP),%R11 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JGE 4aaa90 <hypre_ParMatmul.extracted.12+0x500> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RCX,(%RDI,%R13,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x88(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMULSD (%R9,%R8,8),%XMM0,%XMM1 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM1,(%RBX,%RCX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x90(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,(%R9,%RCX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x68(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R9,%RSI,8),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 4aaaa9 <hypre_ParMatmul.extracted.12+0x519> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
Function | hypre_ParMatmul.extracted.12 |
Source file and lines | par_csr_matop.c:970-989 |
Module | exec |
nb instructions | 17 |
nb uops | 16 |
loop length | 78 |
used x86 registers | 9 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 4 |
micro-operation queue | 2.83 cycles |
front end | 2.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.50 | 0.90 | 3.00 | 3.00 | 0.50 | 0.80 | 1.00 | 0.50 | 0.50 | 0.50 | 0.80 | 3.00 |
cycles | 1.50 | 0.90 | 3.00 | 3.00 | 0.50 | 0.80 | 1.00 | 0.50 | 0.50 | 0.50 | 0.80 | 3.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 2.00 |
FE+BE cycles | 4.52 |
Stall cycles | 1.46 |
LM full (events) | 2.83 |
Front-end | 2.83 |
Dispatch | 3.00 |
Data deps. | 2.00 |
Overall L1 | 3.00 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 12% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 12% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV -0x88(%RBP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD (%R10,%R8,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VFMADD213SD (%RBX,%R11,8),%XMM0,%XMM1 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM1,(%RBX,%R11,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
INC %R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %R9,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4aa9b0 <hypre_ParMatmul.extracted.12+0x420> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0xe8(%RBP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R10,%R8,8),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xf0(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R11,%R10,8),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R13,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD %R10,%R13 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV (%RDI,%R13,8),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP -0x30(%RBP),%R11 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JGE 4aaa90 <hypre_ParMatmul.extracted.12+0x500> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |