Loop Id: 2442 | Module: exec | Source: par_csr_matop.c:263-266 | Coverage: 0.02% |
---|
Loop Id: 2442 | Module: exec | Source: par_csr_matop.c:263-266 | Coverage: 0.02% |
---|
0x559bb3 VPADDQ (%R8,%RCX,1),%ZMM11,%ZMM13 [2] |
0x559bba VMOVDQU64 %ZMM13,(%R8,%RCX,1) [2] |
0x559bc1 VPADDQ (%R14,%RCX,1),%ZMM12,%ZMM14 [1] |
0x559bc8 VMOVDQU64 %ZMM14,(%R14,%RCX,1) [1] |
0x559bcf VPADDQ 0x40(%R8,%RCX,1),%ZMM11,%ZMM15 [2] |
0x559bd7 VMOVDQU64 %ZMM15,0x40(%R8,%RCX,1) [2] |
0x559bdf VPADDQ 0x40(%R14,%RCX,1),%ZMM12,%ZMM2 [1] |
0x559be7 VMOVDQU64 %ZMM2,0x40(%R14,%RCX,1) [1] |
0x559bef VPADDQ 0x80(%R8,%RCX,1),%ZMM11,%ZMM0 [2] |
0x559bf7 VMOVDQU64 %ZMM0,0x80(%R8,%RCX,1) [2] |
0x559bff VPADDQ 0x80(%R14,%RCX,1),%ZMM12,%ZMM4 [1] |
0x559c07 VMOVDQU64 %ZMM4,0x80(%R14,%RCX,1) [1] |
0x559c0f VPADDQ 0xc0(%R8,%RCX,1),%ZMM11,%ZMM3 [2] |
0x559c17 VMOVDQU64 %ZMM3,0xc0(%R8,%RCX,1) [2] |
0x559c1f VPADDQ 0xc0(%R14,%RCX,1),%ZMM12,%ZMM5 [1] |
0x559c27 VMOVDQU64 %ZMM5,0xc0(%R14,%RCX,1) [1] |
0x559c2f VPADDQ 0x100(%R8,%RCX,1),%ZMM11,%ZMM6 [2] |
0x559c37 VMOVDQU64 %ZMM6,0x100(%R8,%RCX,1) [2] |
0x559c3f VPADDQ 0x100(%R14,%RCX,1),%ZMM12,%ZMM7 [1] |
0x559c47 VMOVDQU64 %ZMM7,0x100(%R14,%RCX,1) [1] |
0x559c4f VPADDQ 0x140(%R8,%RCX,1),%ZMM11,%ZMM8 [2] |
0x559c57 VMOVDQU64 %ZMM8,0x140(%R8,%RCX,1) [2] |
0x559c5f VPADDQ 0x140(%R14,%RCX,1),%ZMM12,%ZMM9 [1] |
0x559c67 VMOVDQU64 %ZMM9,0x140(%R14,%RCX,1) [1] |
0x559c6f VPADDQ 0x180(%R8,%RCX,1),%ZMM11,%ZMM10 [2] |
0x559c77 VMOVDQU64 %ZMM10,0x180(%R8,%RCX,1) [2] |
0x559c7f VPADDQ 0x180(%R14,%RCX,1),%ZMM12,%ZMM1 [1] |
0x559c87 VMOVDQU64 %ZMM1,0x180(%R14,%RCX,1) [1] |
0x559c8f VPADDQ 0x1c0(%R8,%RCX,1),%ZMM11,%ZMM13 [2] |
0x559c97 VMOVDQU64 %ZMM13,0x1c0(%R8,%RCX,1) [2] |
0x559c9f VPADDQ 0x1c0(%R14,%RCX,1),%ZMM12,%ZMM14 [1] |
0x559ca7 VMOVDQU64 %ZMM14,0x1c0(%R14,%RCX,1) [1] |
0x559caf ADD $0x200,%RCX |
0x559cb6 CMP %RCX,%RBX |
0x559cb9 JNE 559bb3 |
/home/eoseret/qaas_runs_CPU_9468/171-147-2675/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 263 - 266 |
-------------------------------------------------------------------------------- |
263: for (i1 = ns; i1 < ne; i1++) |
264: { |
265: (*C_diag_i)[i1] += jj_count_diag; |
266: (*C_offd_i)[i1] += jj_count_offd; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.04 |
Bottlenecks | micro-operation queue, |
Function | hypre_ParMatmul_RowSizes._omp_fn.0 |
Source | par_csr_matop.c:263-266 |
Source loop unroll info | unrolled by 8 |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | main |
Unroll factor | 8 |
CQA cycles | 8.33 |
CQA cycles if no scalar integer | 8.33 |
CQA cycles if FP arith vectorized | 8.33 |
CQA cycles if fully vectorized | 8.33 |
Front-end cycles | 8.33 |
DIV/SQRT cycles | 8.00 |
P0 cycles | 0.60 |
P1 cycles | 5.33 |
P2 cycles | 5.33 |
P3 cycles | 8.00 |
P4 cycles | 8.00 |
P5 cycles | 1.00 |
P6 cycles | 8.00 |
P7 cycles | 8.00 |
P8 cycles | 8.00 |
P9 cycles | 0.40 |
P10 cycles | 5.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 8.45 |
Stall cycles (UFS) | 0.00 |
Nb insns | 35.00 |
Nb uops | 34.00 |
Nb loads | 16.00 |
Nb stores | 16.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 245.76 |
Bytes prefetched | 0.00 |
Bytes loaded | 1024.00 |
Bytes stored | 1024.00 |
Stride 0 | 0.00 |
Stride 1 | 2.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 100.00 |
Vector-efficiency ratio load | 100.00 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 100.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | NA |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.04 |
Bottlenecks | micro-operation queue, |
Function | hypre_ParMatmul_RowSizes._omp_fn.0 |
Source | par_csr_matop.c:263-266 |
Source loop unroll info | unrolled by 8 |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | main |
Unroll factor | 8 |
CQA cycles | 8.33 |
CQA cycles if no scalar integer | 8.33 |
CQA cycles if FP arith vectorized | 8.33 |
CQA cycles if fully vectorized | 8.33 |
Front-end cycles | 8.33 |
DIV/SQRT cycles | 8.00 |
P0 cycles | 0.60 |
P1 cycles | 5.33 |
P2 cycles | 5.33 |
P3 cycles | 8.00 |
P4 cycles | 8.00 |
P5 cycles | 1.00 |
P6 cycles | 8.00 |
P7 cycles | 8.00 |
P8 cycles | 8.00 |
P9 cycles | 0.40 |
P10 cycles | 5.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 8.45 |
Stall cycles (UFS) | 0.00 |
Nb insns | 35.00 |
Nb uops | 34.00 |
Nb loads | 16.00 |
Nb stores | 16.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 245.76 |
Bytes prefetched | 0.00 |
Bytes loaded | 1024.00 |
Bytes stored | 1024.00 |
Stride 0 | 0.00 |
Stride 1 | 2.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 100.00 |
Vector-efficiency ratio load | 100.00 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 100.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | NA |
Path / |
Function | hypre_ParMatmul_RowSizes._omp_fn.0 |
Source file and lines | par_csr_matop.c:263-266 |
Module | exec |
nb instructions | 35 |
nb uops | 34 |
loop length | 268 |
used x86 registers | 4 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 16 |
nb stack references | 0 |
micro-operation queue | 8.33 cycles |
front end | 8.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 8.00 | 0.60 | 5.33 | 5.33 | 8.00 | 8.00 | 1.00 | 8.00 | 8.00 | 8.00 | 0.40 | 5.33 |
cycles | 8.00 | 0.60 | 5.33 | 5.33 | 8.00 | 8.00 | 1.00 | 8.00 | 8.00 | 8.00 | 0.40 | 5.33 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 8.45 |
Stall cycles | 0.00 |
Front-end | 8.33 |
Dispatch | 8.00 |
Data deps. | 1.00 |
Overall L1 | 8.33 |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VPADDQ (%R8,%RCX,1),%ZMM11,%ZMM13 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM13,(%R8,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ (%R14,%RCX,1),%ZMM12,%ZMM14 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM14,(%R14,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ 0x40(%R8,%RCX,1),%ZMM11,%ZMM15 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM15,0x40(%R8,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ 0x40(%R14,%RCX,1),%ZMM12,%ZMM2 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM2,0x40(%R14,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ 0x80(%R8,%RCX,1),%ZMM11,%ZMM0 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM0,0x80(%R8,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ 0x80(%R14,%RCX,1),%ZMM12,%ZMM4 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM4,0x80(%R14,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ 0xc0(%R8,%RCX,1),%ZMM11,%ZMM3 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM3,0xc0(%R8,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ 0xc0(%R14,%RCX,1),%ZMM12,%ZMM5 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM5,0xc0(%R14,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ 0x100(%R8,%RCX,1),%ZMM11,%ZMM6 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM6,0x100(%R8,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ 0x100(%R14,%RCX,1),%ZMM12,%ZMM7 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM7,0x100(%R14,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ 0x140(%R8,%RCX,1),%ZMM11,%ZMM8 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM8,0x140(%R8,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ 0x140(%R14,%RCX,1),%ZMM12,%ZMM9 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM9,0x140(%R14,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ 0x180(%R8,%RCX,1),%ZMM11,%ZMM10 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM10,0x180(%R8,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ 0x180(%R14,%RCX,1),%ZMM12,%ZMM1 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM1,0x180(%R14,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ 0x1c0(%R8,%RCX,1),%ZMM11,%ZMM13 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM13,0x1c0(%R8,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ 0x1c0(%R14,%RCX,1),%ZMM12,%ZMM14 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM14,0x1c0(%R14,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
ADD $0x200,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %RCX,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 559bb3 <hypre_ParMatmul_RowSizes._omp_fn.0+0xcf3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
Function | hypre_ParMatmul_RowSizes._omp_fn.0 |
Source file and lines | par_csr_matop.c:263-266 |
Module | exec |
nb instructions | 35 |
nb uops | 34 |
loop length | 268 |
used x86 registers | 4 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 16 |
nb stack references | 0 |
micro-operation queue | 8.33 cycles |
front end | 8.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 8.00 | 0.60 | 5.33 | 5.33 | 8.00 | 8.00 | 1.00 | 8.00 | 8.00 | 8.00 | 0.40 | 5.33 |
cycles | 8.00 | 0.60 | 5.33 | 5.33 | 8.00 | 8.00 | 1.00 | 8.00 | 8.00 | 8.00 | 0.40 | 5.33 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 8.45 |
Stall cycles | 0.00 |
Front-end | 8.33 |
Dispatch | 8.00 |
Data deps. | 1.00 |
Overall L1 | 8.33 |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VPADDQ (%R8,%RCX,1),%ZMM11,%ZMM13 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM13,(%R8,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ (%R14,%RCX,1),%ZMM12,%ZMM14 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM14,(%R14,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ 0x40(%R8,%RCX,1),%ZMM11,%ZMM15 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM15,0x40(%R8,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ 0x40(%R14,%RCX,1),%ZMM12,%ZMM2 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM2,0x40(%R14,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ 0x80(%R8,%RCX,1),%ZMM11,%ZMM0 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM0,0x80(%R8,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ 0x80(%R14,%RCX,1),%ZMM12,%ZMM4 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM4,0x80(%R14,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ 0xc0(%R8,%RCX,1),%ZMM11,%ZMM3 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM3,0xc0(%R8,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ 0xc0(%R14,%RCX,1),%ZMM12,%ZMM5 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM5,0xc0(%R14,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ 0x100(%R8,%RCX,1),%ZMM11,%ZMM6 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM6,0x100(%R8,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ 0x100(%R14,%RCX,1),%ZMM12,%ZMM7 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM7,0x100(%R14,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ 0x140(%R8,%RCX,1),%ZMM11,%ZMM8 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM8,0x140(%R8,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ 0x140(%R14,%RCX,1),%ZMM12,%ZMM9 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM9,0x140(%R14,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ 0x180(%R8,%RCX,1),%ZMM11,%ZMM10 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM10,0x180(%R8,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ 0x180(%R14,%RCX,1),%ZMM12,%ZMM1 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM1,0x180(%R14,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ 0x1c0(%R8,%RCX,1),%ZMM11,%ZMM13 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM13,0x1c0(%R8,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ 0x1c0(%R14,%RCX,1),%ZMM12,%ZMM14 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM14,0x1c0(%R14,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
ADD $0x200,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %RCX,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 559bb3 <hypre_ParMatmul_RowSizes._omp_fn.0+0xcf3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |