Function: hypre_BoomerAMGBuildMultipass._omp_fn.9 | Module: exec | Source: par_multi_interp.c:1575-1663 [...] | Coverage: 0.46% |
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Function: hypre_BoomerAMGBuildMultipass._omp_fn.9 | Module: exec | Source: par_multi_interp.c:1575-1663 [...] | Coverage: 0.46% |
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/home/eoseret/qaas_runs_CPU_9468/171-147-2675/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1575 - 1663 |
-------------------------------------------------------------------------------- |
1575: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa) |
[...] |
1584: tmp_marker = NULL; |
1585: if (n_fine) |
1586: { tmp_marker = hypre_CTAlloc(HYPRE_Int,n_fine); } |
1587: tmp_marker_offd = NULL; |
1588: if (num_cols_offd) |
1589: { tmp_marker_offd = hypre_CTAlloc(HYPRE_Int,num_cols_offd); } |
1590: for (i=0; i < n_fine; i++) |
1591: { tmp_marker[i] = -1; } |
1592: for (i=0; i < num_cols_offd; i++) |
1593: { tmp_marker_offd[i] = -1; } |
1594: |
1595: /* Compute this thread's range of pass_length */ |
1596: my_thread_num = hypre_GetThreadNum(); |
1597: num_threads = hypre_NumActiveThreads(); |
1598: thread_start = pass_pointer[1] + (pass_length/num_threads)*my_thread_num; |
1599: if (my_thread_num == num_threads-1) |
1600: { thread_stop = pass_pointer[1] + pass_length; } |
1601: else |
1602: { thread_stop = pass_pointer[1] + (pass_length/num_threads)*(my_thread_num+1); } |
1603: |
1604: /* determine P for points of pass 1, i.e. neighbors of coarse points */ |
1605: for (i=thread_start; i < thread_stop; i++) |
1606: { |
1607: i1 = pass_array[i]; |
1608: sum_C = 0; |
1609: sum_N = 0; |
1610: j_start = P_diag_start[i1]; |
1611: j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1]; |
1612: for (j=j_start; j < j_end; j++) |
1613: { |
1614: k1 = P_diag_pass[1][j]; |
1615: tmp_marker[C_array[k1]] = i1; |
1616: } |
1617: cnt = P_diag_i[i1]; |
1618: for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++) |
1619: { |
1620: j1 = A_diag_j[j]; |
1621: if (CF_marker[j1] != -3 && |
1622: (num_functions == 1 || dof_func[i1] == dof_func[j1])) |
1623: sum_N += A_diag_data[j]; |
1624: if (j1 != -1 && tmp_marker[j1] == i1) |
1625: { |
1626: P_diag_data[cnt] = A_diag_data[j]; |
1627: P_diag_j[cnt++] = fine_to_coarse[j1]; |
1628: sum_C += A_diag_data[j]; |
1629: } |
1630: } |
1631: j_start = P_offd_start[i1]; |
1632: j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1]; |
1633: for (j=j_start; j < j_end; j++) |
1634: { |
1635: k1 = P_offd_pass[1][j]; |
1636: tmp_marker_offd[C_array_offd[k1]] = i1; |
1637: } |
1638: cnt_offd = P_offd_i[i1]; |
1639: for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++) |
1640: { |
1641: if (col_offd_S_to_A) |
1642: j1 = map_A_to_S[A_offd_j[j]]; |
1643: else |
1644: j1 = A_offd_j[j]; |
1645: if (CF_marker_offd[j1] != -3 && |
1646: (num_functions == 1 || dof_func[i1] == dof_func_offd[j1])) |
1647: sum_N += A_offd_data[j]; |
1648: if (j1 != -1 && tmp_marker_offd[j1] == i1) |
1649: { |
1650: P_offd_data[cnt_offd] = A_offd_data[j]; |
1651: P_offd_j[cnt_offd++] = map_S_to_new[j1]; |
1652: sum_C += A_offd_data[j]; |
1653: } |
1654: } |
1655: diagonal = A_diag_data[A_diag_i[i1]]; |
1656: if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal); |
1657: for (j=P_diag_i[i1]; j < cnt; j++) |
1658: P_diag_data[j] *= alfa; |
1659: for (j=P_offd_i[i1]; j < cnt_offd; j++) |
1660: P_offd_data[j] *= alfa; |
1661: } |
1662: hypre_TFree(tmp_marker); |
1663: hypre_TFree(tmp_marker_offd); |
0x474490 PUSH %RBP |
0x474491 MOV %RSP,%RBP |
0x474494 PUSH %R15 |
0x474496 PUSH %R14 |
0x474498 PUSH %R13 |
0x47449a PUSH %R12 |
0x47449c PUSH %RBX |
0x47449d AND $-0x40,%RSP |
0x4744a1 SUB $0x100,%RSP |
0x4744a8 MOV 0xf8(%RDI),%RAX |
0x4744af MOV 0xf0(%RDI),%RDX |
0x4744b6 MOV 0xe0(%RDI),%RCX |
0x4744bd MOV 0xd8(%RDI),%RSI |
0x4744c4 MOV 0xd0(%RDI),%R8 |
0x4744cb MOV 0xc8(%RDI),%R9 |
0x4744d2 MOV %RAX,0xf8(%RSP) |
0x4744da MOV 0xc0(%RDI),%R10 |
0x4744e1 MOV 0xb0(%RDI),%R12 |
0x4744e8 MOV %RDX,0x98(%RSP) |
0x4744f0 MOV 0xa8(%RDI),%R13 |
0x4744f7 MOV 0x90(%RDI),%RAX |
0x4744fe MOV %RCX,0x8(%RSP) |
0x474503 MOV 0xb8(%RDI),%R11 |
0x47450a MOV 0xe8(%RDI),%RBX |
0x474511 MOV %RSI,0x90(%RSP) |
0x474519 MOV %R8,0x28(%RSP) |
0x47451e MOV 0xa0(%RDI),%R14 |
0x474525 MOV %R9,0x20(%RSP) |
0x47452a MOV 0x98(%RDI),%R15 |
0x474531 MOV %R10,0x60(%RSP) |
0x474536 MOV %R12,0xc8(%RSP) |
0x47453e MOV %R13,0x70(%RSP) |
0x474543 MOV %RAX,0xb0(%RSP) |
0x47454b MOV %R11,0x58(%RSP) |
0x474550 MOV 0x88(%RDI),%R11 |
0x474557 MOV 0x80(%RDI),%RDX |
0x47455e MOV 0x78(%RDI),%RCX |
0x474562 MOV 0x70(%RDI),%RSI |
0x474566 MOV 0x68(%RDI),%R8 |
0x47456a MOV 0x60(%RDI),%R9 |
0x47456e MOV 0x58(%RDI),%R10 |
0x474572 MOV %RDX,0x88(%RSP) |
0x47457a MOV 0x40(%RDI),%RAX |
0x47457e MOV 0x38(%RDI),%RDX |
0x474582 MOV %RCX,0x50(%RSP) |
0x474587 MOV 0x50(%RDI),%R12 |
0x47458b MOV 0x28(%RDI),%RCX |
0x47458f MOV %RSI,0xd8(%RSP) |
0x474597 MOV 0x48(%RDI),%R13 |
0x47459b MOV 0x20(%RDI),%RSI |
0x47459f MOV %R8,0x80(%RSP) |
0x4745a7 MOV %R9,0x48(%RSP) |
0x4745ac MOV 0x18(%RDI),%R8 |
0x4745b0 MOV 0x10(%RDI),%R9 |
0x4745b4 MOV %R10,0xd0(%RSP) |
0x4745bc MOV %RAX,0x40(%RSP) |
0x4745c1 MOV 0x30(%RDI),%R10 |
0x4745c5 MOV 0x8(%RDI),%RAX |
0x4745c9 MOV (%RDI),%RDI |
0x4745cc MOV %RDX,0xe0(%RSP) |
0x4745d4 MOV %RCX,0x38(%RSP) |
0x4745d9 MOV %RSI,0xf0(%RSP) |
0x4745e1 MOV %R8,0x18(%RSP) |
0x4745e6 MOV %R9,0xc0(%RSP) |
0x4745ee MOV %RAX,0xe8(%RSP) |
0x4745f6 MOV %RDI,0x10(%RSP) |
0x4745fb TEST %RBX,%RBX |
0x4745fe JNE 47525f |
0x474604 TEST %R12,%R12 |
0x474607 JNE 4753d0 |
0x47460d XOR %EBX,%EBX |
0x47460f XOR %R12D,%R12D |
0x474612 MOV %R10,0x78(%RSP) |
0x474617 MOV %R11,0xa0(%RSP) |
0x47461f VMOVSD %XMM1,0xa8(%RSP) |
0x474628 CALL 5b3bd0 <hypre_GetThreadNum> |
0x47462d MOV %RAX,0xb8(%RSP) |
0x474635 CALL 5b3bc0 <hypre_NumActiveThreads> |
0x47463a MOV 0xb8(%RSP),%R11 |
0x474642 MOV 0xc8(%RSP),%R8 |
0x47464a MOV %RAX,%RSI |
0x47464d MOV 0xf8(%RSP),%RAX |
0x474655 VMOVSD 0xa8(%RSP),%XMM11 |
0x47465e MOV %R11,%RCX |
0x474661 MOV 0x8(%R8),%R9 |
0x474665 MOV 0x78(%RSP),%R10 |
0x47466a CQTO |
0x47466c MOV 0xa0(%RSP),%R8 |
0x474674 IDIV %RSI |
0x474677 DEC %RSI |
0x47467a IMUL %RAX,%RCX |
0x47467e ADD %RCX,%RAX |
0x474681 LEA (%R9,%RCX,1),%RDI |
0x474685 MOV 0xf8(%RSP),%RCX |
0x47468d ADD %R9,%RAX |
0x474690 ADD %R9,%RCX |
0x474693 CMP %RSI,%R11 |
0x474696 CMOVNE %RAX,%RCX |
0x47469a CMP %RDI,%RCX |
0x47469d JLE 475050 |
0x4746a3 MOV 0x70(%RSP),%R9 |
0x4746a8 VMOVQ 0x145790(%RIP),%XMM5 |
0x4746b0 MOV %R10,%R11 |
0x4746b3 VXORPD %XMM4,%XMM4,%XMM4 |
0x4746b7 MOV %R8,%R10 |
0x4746ba LEA (%R9,%RDI,8),%RSI |
0x4746be LEA (%R9,%RCX,8),%RAX |
0x4746c2 MOV %RSI,0xc8(%RSP) |
0x4746ca MOV %RAX,0x30(%RSP) |
0x4746cf NOP |
(659) 0x4746d0 MOV 0xc8(%RSP),%RDX |
(659) 0x4746d8 MOV 0x58(%RSP),%RDI |
(659) 0x4746dd MOV (%RDX),%RDX |
(659) 0x4746e0 MOV (%RDI,%RDX,8),%RCX |
(659) 0x4746e4 MOV 0x48(%RSP),%RDI |
(659) 0x4746e9 LEA (,%RDX,8),%R8 |
(659) 0x4746f1 LEA 0x8(%R8),%R9 |
(659) 0x4746f5 LEA (%RDI,%R8,1),%RSI |
(659) 0x4746f9 MOV 0x8(%RDI,%R8,1),%RAX |
(659) 0x4746fe MOV %RSI,0xa8(%RSP) |
(659) 0x474706 MOV (%RSI),%RSI |
(659) 0x474709 ADD %RCX,%RAX |
(659) 0x47470c SUB %RSI,%RAX |
(659) 0x47470f MOV %RSI,0xf8(%RSP) |
(659) 0x474717 CMP %RAX,%RCX |
(659) 0x47471a JGE 474858 |
(659) 0x474720 MOV 0x20(%RSP),%RDI |
(659) 0x474725 MOV 0x8(%RDI),%RSI |
(659) 0x474729 LEA (%RSI,%RAX,8),%RDI |
(659) 0x47472d LEA (%RSI,%RCX,8),%RCX |
(659) 0x474731 MOV %RDI,%RAX |
(659) 0x474734 SUB %RCX,%RAX |
(659) 0x474737 SUB $0x8,%RAX |
(659) 0x47473b SHR $0x3,%RAX |
(659) 0x47473f INC %RAX |
(659) 0x474742 AND $0x7,%EAX |
(659) 0x474745 JE 4747dd |
(659) 0x47474b CMP $0x1,%RAX |
(659) 0x47474f JE 4747c9 |
(659) 0x474751 CMP $0x2,%RAX |
(659) 0x474755 JE 4747ba |
(659) 0x474757 CMP $0x3,%RAX |
(659) 0x47475b JE 4747ab |
(659) 0x47475d CMP $0x4,%RAX |
(659) 0x474761 JE 47479c |
(659) 0x474763 CMP $0x5,%RAX |
(659) 0x474767 JE 47478d |
(659) 0x474769 CMP $0x6,%RAX |
(659) 0x47476d JE 47477e |
(659) 0x47476f MOV (%RCX),%RSI |
(659) 0x474772 ADD $0x8,%RCX |
(659) 0x474776 MOV (%R15,%RSI,8),%RAX |
(659) 0x47477a MOV %RDX,(%R12,%RAX,8) |
(659) 0x47477e MOV (%RCX),%RSI |
(659) 0x474781 ADD $0x8,%RCX |
(659) 0x474785 MOV (%R15,%RSI,8),%RAX |
(659) 0x474789 MOV %RDX,(%R12,%RAX,8) |
(659) 0x47478d MOV (%RCX),%RSI |
(659) 0x474790 ADD $0x8,%RCX |
(659) 0x474794 MOV (%R15,%RSI,8),%RAX |
(659) 0x474798 MOV %RDX,(%R12,%RAX,8) |
(659) 0x47479c MOV (%RCX),%RSI |
(659) 0x47479f ADD $0x8,%RCX |
(659) 0x4747a3 MOV (%R15,%RSI,8),%RAX |
(659) 0x4747a7 MOV %RDX,(%R12,%RAX,8) |
(659) 0x4747ab MOV (%RCX),%RSI |
(659) 0x4747ae ADD $0x8,%RCX |
(659) 0x4747b2 MOV (%R15,%RSI,8),%RAX |
(659) 0x4747b6 MOV %RDX,(%R12,%RAX,8) |
(659) 0x4747ba MOV (%RCX),%RSI |
(659) 0x4747bd ADD $0x8,%RCX |
(659) 0x4747c1 MOV (%R15,%RSI,8),%RAX |
(659) 0x4747c5 MOV %RDX,(%R12,%RAX,8) |
(659) 0x4747c9 MOV (%RCX),%RSI |
(659) 0x4747cc ADD $0x8,%RCX |
(659) 0x4747d0 MOV (%R15,%RSI,8),%RAX |
(659) 0x4747d4 MOV %RDX,(%R12,%RAX,8) |
(659) 0x4747d8 CMP %RDI,%RCX |
(659) 0x4747db JE 474845 |
(668) 0x4747dd MOV (%RCX),%RSI |
(668) 0x4747e0 ADD $0x40,%RCX |
(668) 0x4747e4 MOV (%R15,%RSI,8),%RAX |
(668) 0x4747e8 MOV %RDX,(%R12,%RAX,8) |
(668) 0x4747ec MOV -0x38(%RCX),%RSI |
(668) 0x4747f0 MOV (%R15,%RSI,8),%RAX |
(668) 0x4747f4 MOV %RDX,(%R12,%RAX,8) |
(668) 0x4747f8 MOV -0x30(%RCX),%RSI |
(668) 0x4747fc MOV (%R15,%RSI,8),%RAX |
(668) 0x474800 MOV %RDX,(%R12,%RAX,8) |
(668) 0x474804 MOV -0x28(%RCX),%RSI |
(668) 0x474808 MOV (%R15,%RSI,8),%RAX |
(668) 0x47480c MOV %RDX,(%R12,%RAX,8) |
(668) 0x474810 MOV -0x20(%RCX),%RSI |
(668) 0x474814 MOV (%R15,%RSI,8),%RAX |
(668) 0x474818 MOV %RDX,(%R12,%RAX,8) |
(668) 0x47481c MOV -0x18(%RCX),%RSI |
(668) 0x474820 MOV (%R15,%RSI,8),%RAX |
(668) 0x474824 MOV %RDX,(%R12,%RAX,8) |
(668) 0x474828 MOV -0x10(%RCX),%RSI |
(668) 0x47482c MOV (%R15,%RSI,8),%RAX |
(668) 0x474830 MOV %RDX,(%R12,%RAX,8) |
(668) 0x474834 MOV -0x8(%RCX),%RSI |
(668) 0x474838 MOV (%R15,%RSI,8),%RAX |
(668) 0x47483c MOV %RDX,(%R12,%RAX,8) |
(668) 0x474840 CMP %RDI,%RCX |
(668) 0x474843 JNE 4747dd |
(659) 0x474845 MOV 0xa8(%RSP),%RCX |
(659) 0x47484d MOV (%RCX),%RDI |
(659) 0x474850 MOV %RDI,0xf8(%RSP) |
(659) 0x474858 MOV 0x38(%RSP),%RSI |
(659) 0x47485d VXORPD %XMM0,%XMM0,%XMM0 |
(659) 0x474861 VMOVSD %XMM0,%XMM0,%XMM2 |
(659) 0x474865 LEA (%RSI,%R8,1),%RAX |
(659) 0x474869 LEA (%RSI,%R9,1),%RSI |
(659) 0x47486d MOV %RAX,0xa0(%RSP) |
(659) 0x474875 MOV (%RAX),%RAX |
(659) 0x474878 MOV %RAX,0xb8(%RSP) |
(659) 0x474880 INC %RAX |
(659) 0x474883 CMP (%RSI),%RAX |
(659) 0x474886 JGE 47496c |
(659) 0x47488c CMPQ $0x1,0xe8(%RSP) |
(659) 0x474895 JE 475070 |
(659) 0x47489b MOV %R13,0x70(%RSP) |
(659) 0x4748a0 MOV %RBX,0xb8(%RSP) |
(659) 0x4748a8 MOV 0xf8(%RSP),%RBX |
(659) 0x4748b0 MOV %R10,0x78(%RSP) |
(659) 0x4748b5 MOV 0x10(%RSP),%R10 |
(659) 0x4748ba MOV %R9,0x68(%RSP) |
(659) 0x4748bf MOV 0xc0(%RSP),%R9 |
(659) 0x4748c7 NOPW (%RAX,%RAX,1) |
(667) 0x4748d0 MOV (%R11,%RAX,8),%RCX |
(667) 0x4748d4 CMPQ $-0x3,(%R10,%RCX,8) |
(667) 0x4748d9 JE 4748f2 |
(667) 0x4748db MOV (%R9,%RCX,8),%R13 |
(667) 0x4748df CMP %R13,(%R9,%R8,1) |
(667) 0x4748e3 JNE 4748f2 |
(667) 0x4748e5 MOV 0xf0(%RSP),%RDI |
(667) 0x4748ed VADDSD (%RDI,%RAX,8),%XMM0,%XMM0 |
(667) 0x4748f2 CMP $-0x1,%RCX |
(667) 0x4748f6 JE 474945 |
(667) 0x4748f8 CMP (%R12,%RCX,8),%RDX |
(667) 0x4748fc JNE 474945 |
(667) 0x4748fe MOV 0xf0(%RSP),%R13 |
(667) 0x474906 LEA (,%RBX,8),%RDI |
(667) 0x47490e VMOVSD (%R13,%RAX,8),%XMM6 |
(667) 0x474915 MOV 0xd0(%RSP),%R13 |
(667) 0x47491d VMOVSD %XMM6,(%R13,%RBX,8) |
(667) 0x474924 MOV 0x98(%RSP),%R13 |
(667) 0x47492c VADDSD %XMM6,%XMM2,%XMM2 |
(667) 0x474930 INC %RBX |
(667) 0x474933 MOV (%R13,%RCX,8),%RCX |
(667) 0x474938 MOV 0x80(%RSP),%R13 |
(667) 0x474940 MOV %RCX,(%R13,%RDI,1) |
(667) 0x474945 INC %RAX |
(667) 0x474948 CMP (%RSI),%RAX |
(667) 0x47494b JL 4748d0 |
(659) 0x47494d MOV 0x78(%RSP),%R10 |
(659) 0x474952 MOV 0x70(%RSP),%R13 |
(659) 0x474957 MOV %RBX,0xf8(%RSP) |
(659) 0x47495f MOV 0x68(%RSP),%R9 |
(659) 0x474964 MOV 0xb8(%RSP),%RBX |
(659) 0x47496c MOV 0x60(%RSP),%RAX |
(659) 0x474971 MOV 0x50(%RSP),%RDI |
(659) 0x474976 MOV (%RAX,%RDX,8),%RCX |
(659) 0x47497a LEA (%RDI,%R8,1),%RSI |
(659) 0x47497e MOV 0x8(%RDI,%R8,1),%RAX |
(659) 0x474983 MOV %RSI,0xb8(%RSP) |
(659) 0x47498b MOV (%RSI),%RSI |
(659) 0x47498e ADD %RCX,%RAX |
(659) 0x474991 SUB %RSI,%RAX |
(659) 0x474994 CMP %RAX,%RCX |
(659) 0x474997 JGE 474add |
(659) 0x47499d MOV 0x28(%RSP),%RDI |
(659) 0x4749a2 MOV 0x8(%RDI),%RSI |
(659) 0x4749a6 LEA (%RSI,%RCX,8),%RCX |
(659) 0x4749aa LEA (%RSI,%RAX,8),%RSI |
(659) 0x4749ae MOV %RSI,%RAX |
(659) 0x4749b1 SUB %RCX,%RAX |
(659) 0x4749b4 SUB $0x8,%RAX |
(659) 0x4749b8 SHR $0x3,%RAX |
(659) 0x4749bc INC %RAX |
(659) 0x4749bf AND $0x7,%EAX |
(659) 0x4749c2 JE 474a5a |
(659) 0x4749c8 CMP $0x1,%RAX |
(659) 0x4749cc JE 474a46 |
(659) 0x4749ce CMP $0x2,%RAX |
(659) 0x4749d2 JE 474a37 |
(659) 0x4749d4 CMP $0x3,%RAX |
(659) 0x4749d8 JE 474a28 |
(659) 0x4749da CMP $0x4,%RAX |
(659) 0x4749de JE 474a19 |
(659) 0x4749e0 CMP $0x5,%RAX |
(659) 0x4749e4 JE 474a0a |
(659) 0x4749e6 CMP $0x6,%RAX |
(659) 0x4749ea JE 4749fb |
(659) 0x4749ec MOV (%RCX),%RDI |
(659) 0x4749ef ADD $0x8,%RCX |
(659) 0x4749f3 MOV (%R14,%RDI,8),%RAX |
(659) 0x4749f7 MOV %RDX,(%RBX,%RAX,8) |
(659) 0x4749fb MOV (%RCX),%RDI |
(659) 0x4749fe ADD $0x8,%RCX |
(659) 0x474a02 MOV (%R14,%RDI,8),%RAX |
(659) 0x474a06 MOV %RDX,(%RBX,%RAX,8) |
(659) 0x474a0a MOV (%RCX),%RDI |
(659) 0x474a0d ADD $0x8,%RCX |
(659) 0x474a11 MOV (%R14,%RDI,8),%RAX |
(659) 0x474a15 MOV %RDX,(%RBX,%RAX,8) |
(659) 0x474a19 MOV (%RCX),%RDI |
(659) 0x474a1c ADD $0x8,%RCX |
(659) 0x474a20 MOV (%R14,%RDI,8),%RAX |
(659) 0x474a24 MOV %RDX,(%RBX,%RAX,8) |
(659) 0x474a28 MOV (%RCX),%RDI |
(659) 0x474a2b ADD $0x8,%RCX |
(659) 0x474a2f MOV (%R14,%RDI,8),%RAX |
(659) 0x474a33 MOV %RDX,(%RBX,%RAX,8) |
(659) 0x474a37 MOV (%RCX),%RDI |
(659) 0x474a3a ADD $0x8,%RCX |
(659) 0x474a3e MOV (%R14,%RDI,8),%RAX |
(659) 0x474a42 MOV %RDX,(%RBX,%RAX,8) |
(659) 0x474a46 MOV (%RCX),%RDI |
(659) 0x474a49 ADD $0x8,%RCX |
(659) 0x474a4d MOV (%R14,%RDI,8),%RAX |
(659) 0x474a51 MOV %RDX,(%RBX,%RAX,8) |
(659) 0x474a55 CMP %RCX,%RSI |
(659) 0x474a58 JE 474ad2 |
(659) 0x474a5a MOV 0xb8(%RSP),%RDI |
(665) 0x474a62 MOV (%RCX),%RAX |
(665) 0x474a65 ADD $0x40,%RCX |
(665) 0x474a69 MOV (%R14,%RAX,8),%RAX |
(665) 0x474a6d MOV %RDX,(%RBX,%RAX,8) |
(665) 0x474a71 MOV -0x38(%RCX),%RAX |
(665) 0x474a75 MOV (%R14,%RAX,8),%RAX |
(665) 0x474a79 MOV %RDX,(%RBX,%RAX,8) |
(665) 0x474a7d MOV -0x30(%RCX),%RAX |
(665) 0x474a81 MOV (%R14,%RAX,8),%RAX |
(665) 0x474a85 MOV %RDX,(%RBX,%RAX,8) |
(665) 0x474a89 MOV -0x28(%RCX),%RAX |
(665) 0x474a8d MOV (%R14,%RAX,8),%RAX |
(665) 0x474a91 MOV %RDX,(%RBX,%RAX,8) |
(665) 0x474a95 MOV -0x20(%RCX),%RAX |
(665) 0x474a99 MOV (%R14,%RAX,8),%RAX |
(665) 0x474a9d MOV %RDX,(%RBX,%RAX,8) |
(665) 0x474aa1 MOV -0x18(%RCX),%RAX |
(665) 0x474aa5 MOV (%R14,%RAX,8),%RAX |
(665) 0x474aa9 MOV %RDX,(%RBX,%RAX,8) |
(665) 0x474aad MOV -0x10(%RCX),%RAX |
(665) 0x474ab1 MOV (%R14,%RAX,8),%RAX |
(665) 0x474ab5 MOV %RDX,(%RBX,%RAX,8) |
(665) 0x474ab9 MOV -0x8(%RCX),%RAX |
(665) 0x474abd MOV (%R14,%RAX,8),%RAX |
(665) 0x474ac1 MOV %RDX,(%RBX,%RAX,8) |
(665) 0x474ac5 CMP %RCX,%RSI |
(665) 0x474ac8 JNE 474a62 |
(659) 0x474aca MOV %RDI,0xb8(%RSP) |
(659) 0x474ad2 MOV 0xb8(%RSP),%RCX |
(659) 0x474ada MOV (%RCX),%RSI |
(659) 0x474add MOV 0x40(%RSP),%RDI |
(659) 0x474ae2 MOV (%RDI,%RDX,8),%RAX |
(659) 0x474ae6 ADD %RDI,%R9 |
(659) 0x474ae9 CMP %RAX,(%R9) |
(659) 0x474aec JLE 475248 |
(659) 0x474af2 CMPQ $0,0x18(%RSP) |
(659) 0x474af8 JE 475120 |
(659) 0x474afe MOV %R12,0x78(%RSP) |
(659) 0x474b03 MOV 0x8(%RSP),%RDI |
(659) 0x474b08 MOV %R11,0x70(%RSP) |
(659) 0x474b0d JMP 474b81 |
0x474b0f NOP |
(664) 0x474b10 MOV 0xb0(%RSP),%R11 |
(664) 0x474b18 MOV 0xc0(%RSP),%R12 |
(664) 0x474b20 MOV (%R11,%RCX,8),%R11 |
(664) 0x474b24 CMP %R11,(%R12,%R8,1) |
(664) 0x474b28 JE 474ba0 |
(664) 0x474b2a CMP $-0x1,%RCX |
(664) 0x474b2e JE 474b79 |
(664) 0x474b30 CMP (%RBX,%RCX,8),%RDX |
(664) 0x474b34 JNE 474b79 |
(664) 0x474b36 MOV 0xe0(%RSP),%R11 |
(664) 0x474b3e LEA (,%RSI,8),%R12 |
(664) 0x474b46 VMOVSD (%R11,%RAX,8),%XMM7 |
(664) 0x474b4c MOV 0xd8(%RSP),%R11 |
(664) 0x474b54 VMOVSD %XMM7,(%R11,%RSI,8) |
(664) 0x474b5a MOV 0x90(%RSP),%R11 |
(664) 0x474b62 VADDSD %XMM7,%XMM2,%XMM2 |
(664) 0x474b66 INC %RSI |
(664) 0x474b69 MOV (%R11,%RCX,8),%RCX |
(664) 0x474b6d MOV 0x88(%RSP),%R11 |
(664) 0x474b75 MOV %RCX,(%R11,%R12,1) |
(664) 0x474b79 INC %RAX |
(664) 0x474b7c CMP (%R9),%RAX |
(664) 0x474b7f JGE 474bb8 |
(664) 0x474b81 MOV (%R13,%RAX,8),%R12 |
(664) 0x474b86 MOV (%RDI,%R12,8),%RCX |
(664) 0x474b8a CMPQ $-0x3,(%R10,%RCX,8) |
(664) 0x474b8f JE 474b2a |
(664) 0x474b91 CMPQ $0x1,0xe8(%RSP) |
(664) 0x474b9a JNE 474b10 |
(664) 0x474ba0 MOV 0xe0(%RSP),%R12 |
(664) 0x474ba8 VADDSD (%R12,%RAX,8),%XMM0,%XMM0 |
(664) 0x474bae JMP 474b2a |
0x474bb3 NOPL (%RAX,%RAX,1) |
(659) 0x474bb8 MOV 0x78(%RSP),%R12 |
(659) 0x474bbd MOV 0x70(%RSP),%R11 |
(659) 0x474bc2 MOV 0xb8(%RSP),%RDX |
(659) 0x474bca MOV (%RDX),%R8 |
(659) 0x474bcd MOV 0xa0(%RSP),%R9 |
(659) 0x474bd5 MOV 0xf0(%RSP),%RCX |
(659) 0x474bdd MOV (%R9),%RAX |
(659) 0x474be0 VMULSD (%RCX,%RAX,8),%XMM2,%XMM10 |
(659) 0x474be5 VCOMISD %XMM4,%XMM10 |
(659) 0x474be9 JE 474bf4 |
(659) 0x474beb VXORPD %XMM5,%XMM0,%XMM1 |
(659) 0x474bef VDIVSD %XMM10,%XMM1,%XMM11 |
(659) 0x474bf4 MOV 0xa8(%RSP),%RDI |
(659) 0x474bfc MOV 0xf8(%RSP),%RDX |
(659) 0x474c04 MOV (%RDI),%RCX |
(659) 0x474c07 CMP %RDX,%RCX |
(659) 0x474c0a JGE 474e26 |
(659) 0x474c10 MOV %RDX,%R9 |
(659) 0x474c13 MOV %RCX,0xb8(%RSP) |
(659) 0x474c1b SUB %RCX,%R9 |
(659) 0x474c1e LEA -0x1(%R9),%RAX |
(659) 0x474c22 CMP $0x6,%RAX |
(659) 0x474c26 JBE 475250 |
(659) 0x474c2c MOV 0xd0(%RSP),%RDI |
(659) 0x474c34 MOV %R9,%RDX |
(659) 0x474c37 VBROADCASTSD %XMM11,%ZMM12 |
(659) 0x474c3d SHR $0x3,%RDX |
(659) 0x474c41 SAL $0x6,%RDX |
(659) 0x474c45 LEA (%RDI,%RCX,8),%RAX |
(659) 0x474c49 LEA (%RDX,%RAX,1),%RDI |
(659) 0x474c4d SUB $0x40,%RDX |
(659) 0x474c51 SHR $0x6,%RDX |
(659) 0x474c55 INC %RDX |
(659) 0x474c58 AND $0x7,%EDX |
(659) 0x474c5b JE 474d05 |
(659) 0x474c61 CMP $0x1,%RDX |
(659) 0x474c65 JE 474cef |
(659) 0x474c6b CMP $0x2,%RDX |
(659) 0x474c6f JE 474cde |
(659) 0x474c71 CMP $0x3,%RDX |
(659) 0x474c75 JE 474ccd |
(659) 0x474c77 CMP $0x4,%RDX |
(659) 0x474c7b JE 474cbc |
(659) 0x474c7d CMP $0x5,%RDX |
(659) 0x474c81 JE 474cab |
(659) 0x474c83 CMP $0x6,%RDX |
(659) 0x474c87 JE 474c9a |
(659) 0x474c89 VMULPD (%RAX),%ZMM12,%ZMM13 |
(659) 0x474c8f ADD $0x40,%RAX |
(659) 0x474c93 VMOVUPD %ZMM13,-0x40(%RAX) |
(659) 0x474c9a VMULPD (%RAX),%ZMM12,%ZMM14 |
(659) 0x474ca0 ADD $0x40,%RAX |
(659) 0x474ca4 VMOVUPD %ZMM14,-0x40(%RAX) |
(659) 0x474cab VMULPD (%RAX),%ZMM12,%ZMM15 |
(659) 0x474cb1 ADD $0x40,%RAX |
(659) 0x474cb5 VMOVUPD %ZMM15,-0x40(%RAX) |
(659) 0x474cbc VMULPD (%RAX),%ZMM12,%ZMM0 |
(659) 0x474cc2 ADD $0x40,%RAX |
(659) 0x474cc6 VMOVUPD %ZMM0,-0x40(%RAX) |
(659) 0x474ccd VMULPD (%RAX),%ZMM12,%ZMM3 |
(659) 0x474cd3 ADD $0x40,%RAX |
(659) 0x474cd7 VMOVUPD %ZMM3,-0x40(%RAX) |
(659) 0x474cde VMULPD (%RAX),%ZMM12,%ZMM2 |
(659) 0x474ce4 ADD $0x40,%RAX |
(659) 0x474ce8 VMOVUPD %ZMM2,-0x40(%RAX) |
(659) 0x474cef VMULPD (%RAX),%ZMM12,%ZMM6 |
(659) 0x474cf5 ADD $0x40,%RAX |
(659) 0x474cf9 VMOVUPD %ZMM6,-0x40(%RAX) |
(659) 0x474d00 CMP %RAX,%RDI |
(659) 0x474d03 JE 474d7f |
(661) 0x474d05 VMULPD (%RAX),%ZMM12,%ZMM7 |
(661) 0x474d0b ADD $0x200,%RAX |
(661) 0x474d11 VMULPD -0x1c0(%RAX),%ZMM12,%ZMM8 |
(661) 0x474d18 VMULPD -0x180(%RAX),%ZMM12,%ZMM9 |
(661) 0x474d1f VMULPD -0x140(%RAX),%ZMM12,%ZMM10 |
(661) 0x474d26 VMULPD -0x100(%RAX),%ZMM12,%ZMM1 |
(661) 0x474d2d VMULPD -0xc0(%RAX),%ZMM12,%ZMM13 |
(661) 0x474d34 VMOVUPD %ZMM7,-0x200(%RAX) |
(661) 0x474d3b VMULPD -0x80(%RAX),%ZMM12,%ZMM14 |
(661) 0x474d42 VMOVUPD %ZMM8,-0x1c0(%RAX) |
(661) 0x474d49 VMULPD -0x40(%RAX),%ZMM12,%ZMM15 |
(661) 0x474d50 VMOVUPD %ZMM9,-0x180(%RAX) |
(661) 0x474d57 VMOVUPD %ZMM10,-0x140(%RAX) |
(661) 0x474d5e VMOVUPD %ZMM1,-0x100(%RAX) |
(661) 0x474d65 VMOVUPD %ZMM13,-0xc0(%RAX) |
(661) 0x474d6c VMOVUPD %ZMM14,-0x80(%RAX) |
(661) 0x474d73 VMOVUPD %ZMM15,-0x40(%RAX) |
(661) 0x474d7a CMP %RAX,%RDI |
(661) 0x474d7d JNE 474d05 |
(659) 0x474d7f MOV %R9,%RAX |
(659) 0x474d82 AND $-0x8,%RAX |
(659) 0x474d86 ADD %RAX,%RCX |
(659) 0x474d89 TEST $0x7,%R9B |
(659) 0x474d8d JE 474e26 |
(659) 0x474d93 SUB %RAX,%R9 |
(659) 0x474d96 LEA -0x1(%R9),%RDX |
(659) 0x474d9a CMP $0x2,%RDX |
(659) 0x474d9e JBE 474dd4 |
(659) 0x474da0 MOV 0xb8(%RSP),%RDI |
(659) 0x474da8 MOV 0xd0(%RSP),%RDX |
(659) 0x474db0 VBROADCASTSD %XMM11,%YMM12 |
(659) 0x474db5 ADD %RAX,%RDI |
(659) 0x474db8 MOV %R9,%RAX |
(659) 0x474dbb LEA (%RDX,%RDI,8),%RDI |
(659) 0x474dbf AND $-0x4,%RAX |
(659) 0x474dc3 VMULPD (%RDI),%YMM12,%YMM0 |
(659) 0x474dc7 ADD %RAX,%RCX |
(659) 0x474dca AND $0x3,%R9D |
(659) 0x474dce VMOVUPD %YMM0,(%RDI) |
(659) 0x474dd2 JE 474e26 |
(659) 0x474dd4 MOV 0xd0(%RSP),%RDI |
(659) 0x474ddc LEA (,%RCX,8),%RAX |
(659) 0x474de4 LEA 0x1(%RCX),%RDX |
(659) 0x474de8 LEA (%RDI,%RAX,1),%R9 |
(659) 0x474dec VMULSD (%R9),%XMM11,%XMM3 |
(659) 0x474df1 VMOVSD %XMM3,(%R9) |
(659) 0x474df6 MOV 0xf8(%RSP),%R9 |
(659) 0x474dfe CMP %RDX,%R9 |
(659) 0x474e01 JLE 474e26 |
(659) 0x474e03 LEA 0x8(%RDI,%RAX,1),%RDX |
(659) 0x474e08 ADD $0x2,%RCX |
(659) 0x474e0c VMULSD (%RDX),%XMM11,%XMM2 |
(659) 0x474e10 VMOVSD %XMM2,(%RDX) |
(659) 0x474e14 CMP %RCX,%R9 |
(659) 0x474e17 JLE 474e26 |
(659) 0x474e19 LEA 0x10(%RDI,%RAX,1),%RCX |
(659) 0x474e1e VMULSD (%RCX),%XMM11,%XMM6 |
(659) 0x474e22 VMOVSD %XMM6,(%RCX) |
(659) 0x474e26 CMP %R8,%RSI |
(659) 0x474e29 JLE 47502e |
(659) 0x474e2f MOV %RSI,%RCX |
(659) 0x474e32 MOV %R8,%RDI |
(659) 0x474e35 SUB %R8,%RCX |
(659) 0x474e38 LEA -0x1(%RCX),%RAX |
(659) 0x474e3c CMP $0x6,%RAX |
(659) 0x474e40 JBE 475257 |
(659) 0x474e46 MOV 0xd8(%RSP),%RDX |
(659) 0x474e4e VBROADCASTSD %XMM11,%ZMM7 |
(659) 0x474e54 LEA (%RDX,%R8,8),%RAX |
(659) 0x474e58 MOV %RCX,%RDX |
(659) 0x474e5b SHR $0x3,%RDX |
(659) 0x474e5f SAL $0x6,%RDX |
(659) 0x474e63 LEA (%RDX,%RAX,1),%R9 |
(659) 0x474e67 SUB $0x40,%RDX |
(659) 0x474e6b SHR $0x6,%RDX |
(659) 0x474e6f INC %RDX |
(659) 0x474e72 AND $0x7,%EDX |
(659) 0x474e75 JE 474f1f |
(659) 0x474e7b CMP $0x1,%RDX |
(659) 0x474e7f JE 474f09 |
(659) 0x474e85 CMP $0x2,%RDX |
(659) 0x474e89 JE 474ef8 |
(659) 0x474e8b CMP $0x3,%RDX |
(659) 0x474e8f JE 474ee7 |
(659) 0x474e91 CMP $0x4,%RDX |
(659) 0x474e95 JE 474ed6 |
(659) 0x474e97 CMP $0x5,%RDX |
(659) 0x474e9b JE 474ec5 |
(659) 0x474e9d CMP $0x6,%RDX |
(659) 0x474ea1 JE 474eb4 |
(659) 0x474ea3 VMULPD (%RAX),%ZMM7,%ZMM8 |
(659) 0x474ea9 ADD $0x40,%RAX |
(659) 0x474ead VMOVUPD %ZMM8,-0x40(%RAX) |
(659) 0x474eb4 VMULPD (%RAX),%ZMM7,%ZMM9 |
(659) 0x474eba ADD $0x40,%RAX |
(659) 0x474ebe VMOVUPD %ZMM9,-0x40(%RAX) |
(659) 0x474ec5 VMULPD (%RAX),%ZMM7,%ZMM10 |
(659) 0x474ecb ADD $0x40,%RAX |
(659) 0x474ecf VMOVUPD %ZMM10,-0x40(%RAX) |
(659) 0x474ed6 VMULPD (%RAX),%ZMM7,%ZMM1 |
(659) 0x474edc ADD $0x40,%RAX |
(659) 0x474ee0 VMOVUPD %ZMM1,-0x40(%RAX) |
(659) 0x474ee7 VMULPD (%RAX),%ZMM7,%ZMM13 |
(659) 0x474eed ADD $0x40,%RAX |
(659) 0x474ef1 VMOVUPD %ZMM13,-0x40(%RAX) |
(659) 0x474ef8 VMULPD (%RAX),%ZMM7,%ZMM14 |
(659) 0x474efe ADD $0x40,%RAX |
(659) 0x474f02 VMOVUPD %ZMM14,-0x40(%RAX) |
(659) 0x474f09 VMULPD (%RAX),%ZMM7,%ZMM15 |
(659) 0x474f0f ADD $0x40,%RAX |
(659) 0x474f13 VMOVUPD %ZMM15,-0x40(%RAX) |
(659) 0x474f1a CMP %R9,%RAX |
(659) 0x474f1d JE 474f99 |
(660) 0x474f1f VMULPD (%RAX),%ZMM7,%ZMM12 |
(660) 0x474f25 ADD $0x200,%RAX |
(660) 0x474f2b VMULPD -0x1c0(%RAX),%ZMM7,%ZMM0 |
(660) 0x474f32 VMULPD -0x180(%RAX),%ZMM7,%ZMM3 |
(660) 0x474f39 VMULPD -0x140(%RAX),%ZMM7,%ZMM2 |
(660) 0x474f40 VMULPD -0x100(%RAX),%ZMM7,%ZMM6 |
(660) 0x474f47 VMULPD -0xc0(%RAX),%ZMM7,%ZMM8 |
(660) 0x474f4e VMOVUPD %ZMM12,-0x200(%RAX) |
(660) 0x474f55 VMULPD -0x80(%RAX),%ZMM7,%ZMM9 |
(660) 0x474f5c VMOVUPD %ZMM0,-0x1c0(%RAX) |
(660) 0x474f63 VMULPD -0x40(%RAX),%ZMM7,%ZMM10 |
(660) 0x474f6a VMOVUPD %ZMM3,-0x180(%RAX) |
(660) 0x474f71 VMOVUPD %ZMM2,-0x140(%RAX) |
(660) 0x474f78 VMOVUPD %ZMM6,-0x100(%RAX) |
(660) 0x474f7f VMOVUPD %ZMM8,-0xc0(%RAX) |
(660) 0x474f86 VMOVUPD %ZMM9,-0x80(%RAX) |
(660) 0x474f8d VMOVUPD %ZMM10,-0x40(%RAX) |
(660) 0x474f94 CMP %R9,%RAX |
(660) 0x474f97 JNE 474f1f |
(659) 0x474f99 MOV %RCX,%R9 |
(659) 0x474f9c AND $-0x8,%R9 |
(659) 0x474fa0 ADD %R9,%R8 |
(659) 0x474fa3 TEST $0x7,%CL |
(659) 0x474fa6 JE 47502e |
(659) 0x474fac SUB %R9,%RCX |
(659) 0x474faf LEA -0x1(%RCX),%RAX |
(659) 0x474fb3 CMP $0x2,%RAX |
(659) 0x474fb7 JBE 474fe4 |
(659) 0x474fb9 ADD %RDI,%R9 |
(659) 0x474fbc MOV 0xd8(%RSP),%RDI |
(659) 0x474fc4 VBROADCASTSD %XMM11,%YMM7 |
(659) 0x474fc9 LEA (%RDI,%R9,8),%RDX |
(659) 0x474fcd MOV %RCX,%R9 |
(659) 0x474fd0 VMULPD (%RDX),%YMM7,%YMM1 |
(659) 0x474fd4 AND $-0x4,%R9 |
(659) 0x474fd8 ADD %R9,%R8 |
(659) 0x474fdb AND $0x3,%ECX |
(659) 0x474fde VMOVUPD %YMM1,(%RDX) |
(659) 0x474fe2 JE 47502e |
(659) 0x474fe4 MOV 0xd8(%RSP),%RAX |
(659) 0x474fec LEA (,%R8,8),%RCX |
(659) 0x474ff4 LEA 0x1(%R8),%RDX |
(659) 0x474ff8 LEA (%RAX,%RCX,1),%RDI |
(659) 0x474ffc VMULSD (%RDI),%XMM11,%XMM13 |
(659) 0x475000 VMOVSD %XMM13,(%RDI) |
(659) 0x475004 CMP %RDX,%RSI |
(659) 0x475007 JLE 47502e |
(659) 0x475009 LEA 0x8(%RAX,%RCX,1),%R9 |
(659) 0x47500e ADD $0x2,%R8 |
(659) 0x475012 VMULSD (%R9),%XMM11,%XMM14 |
(659) 0x475017 VMOVSD %XMM14,(%R9) |
(659) 0x47501c CMP %R8,%RSI |
(659) 0x47501f JLE 47502e |
(659) 0x475021 LEA 0x10(%RAX,%RCX,1),%RSI |
(659) 0x475026 VMULSD (%RSI),%XMM11,%XMM15 |
(659) 0x47502a VMOVSD %XMM15,(%RSI) |
(659) 0x47502e ADDQ $0x8,0xc8(%RSP) |
(659) 0x475037 MOV 0x30(%RSP),%RCX |
(659) 0x47503c MOV 0xc8(%RSP),%R8 |
(659) 0x475044 CMP %RCX,%R8 |
(659) 0x475047 JNE 4746d0 |
0x47504d VZEROUPPER |
0x475050 MOV %R12,%RDI |
0x475053 CALL 5b0b60 <hypre_Free> |
0x475058 LEA -0x28(%RBP),%RSP |
0x47505c MOV %RBX,%RDI |
0x47505f POP %RBX |
0x475060 POP %R12 |
0x475062 POP %R13 |
0x475064 POP %R14 |
0x475066 POP %R15 |
0x475068 POP %RBP |
0x475069 JMP 5b0b60 |
0x47506e XCHG %AX,%AX |
(659) 0x475070 MOV %R10,0xb8(%RSP) |
(659) 0x475078 MOV %R8,0x78(%RSP) |
(659) 0x47507d MOV 0x10(%RSP),%R8 |
(659) 0x475082 MOV %R9,0x70(%RSP) |
(659) 0x475087 MOV 0xf8(%RSP),%R9 |
(659) 0x47508f NOP |
(666) 0x475090 MOV (%R11,%RAX,8),%RCX |
(666) 0x475094 CMPQ $-0x3,(%R8,%RCX,8) |
(666) 0x475099 JE 4750a9 |
(666) 0x47509b MOV 0xf0(%RSP),%R10 |
(666) 0x4750a3 VADDSD (%R10,%RAX,8),%XMM0,%XMM0 |
(666) 0x4750a9 CMP $-0x1,%RCX |
(666) 0x4750ad JE 4750f8 |
(666) 0x4750af CMP (%R12,%RCX,8),%RDX |
(666) 0x4750b3 JNE 4750f8 |
(666) 0x4750b5 MOV 0xf0(%RSP),%R10 |
(666) 0x4750bd LEA (,%R9,8),%RDI |
(666) 0x4750c5 VMOVSD (%R10,%RAX,8),%XMM3 |
(666) 0x4750cb MOV 0xd0(%RSP),%R10 |
(666) 0x4750d3 VMOVSD %XMM3,(%R10,%R9,8) |
(666) 0x4750d9 MOV 0x98(%RSP),%R10 |
(666) 0x4750e1 VADDSD %XMM3,%XMM2,%XMM2 |
(666) 0x4750e5 INC %R9 |
(666) 0x4750e8 MOV (%R10,%RCX,8),%RCX |
(666) 0x4750ec MOV 0x80(%RSP),%R10 |
(666) 0x4750f4 MOV %RCX,(%R10,%RDI,1) |
(666) 0x4750f8 INC %RAX |
(666) 0x4750fb CMP (%RSI),%RAX |
(666) 0x4750fe JL 475090 |
(659) 0x475100 MOV 0xb8(%RSP),%R10 |
(659) 0x475108 MOV 0x78(%RSP),%R8 |
(659) 0x47510d MOV %R9,0xf8(%RSP) |
(659) 0x475115 MOV 0x70(%RSP),%R9 |
(659) 0x47511a JMP 47496c |
0x47511f NOP |
(659) 0x475120 CMPQ $0x1,0xe8(%RSP) |
(659) 0x475129 JE 4751d0 |
(659) 0x47512f MOV %R12,0x78(%RSP) |
(659) 0x475134 NOPL (%RAX) |
(663) 0x475138 MOV (%R13,%RAX,8),%RCX |
(663) 0x47513d CMPQ $-0x3,(%R10,%RCX,8) |
(663) 0x475142 JE 47516c |
(663) 0x475144 MOV 0xc0(%RSP),%RDI |
(663) 0x47514c MOV 0xb0(%RSP),%R12 |
(663) 0x475154 MOV (%RDI,%R8,1),%RDI |
(663) 0x475158 CMP %RDI,(%R12,%RCX,8) |
(663) 0x47515c JNE 47516c |
(663) 0x47515e MOV 0xe0(%RSP),%R12 |
(663) 0x475166 VADDSD (%R12,%RAX,8),%XMM0,%XMM0 |
(663) 0x47516c CMP $-0x1,%RCX |
(663) 0x475170 JE 4751ba |
(663) 0x475172 CMP (%RBX,%RCX,8),%RDX |
(663) 0x475176 JNE 4751ba |
(663) 0x475178 MOV 0xe0(%RSP),%RDI |
(663) 0x475180 LEA (,%RSI,8),%R12 |
(663) 0x475188 VMOVSD (%RDI,%RAX,8),%XMM9 |
(663) 0x47518d MOV 0xd8(%RSP),%RDI |
(663) 0x475195 VMOVSD %XMM9,(%RDI,%RSI,8) |
(663) 0x47519a MOV 0x90(%RSP),%RDI |
(663) 0x4751a2 VADDSD %XMM9,%XMM2,%XMM2 |
(663) 0x4751a7 INC %RSI |
(663) 0x4751aa MOV (%RDI,%RCX,8),%RCX |
(663) 0x4751ae MOV 0x88(%RSP),%RDI |
(663) 0x4751b6 MOV %RCX,(%RDI,%R12,1) |
(663) 0x4751ba INC %RAX |
(663) 0x4751bd CMP %RAX,(%R9) |
(663) 0x4751c0 JG 475138 |
(659) 0x4751c6 MOV 0x78(%RSP),%R12 |
(659) 0x4751cb JMP 474bc2 |
(662) 0x4751d0 MOV (%R13,%RAX,8),%RCX |
(662) 0x4751d5 CMPQ $-0x3,(%R10,%RCX,8) |
(662) 0x4751da JE 4751ea |
(662) 0x4751dc MOV 0xe0(%RSP),%R8 |
(662) 0x4751e4 VADDSD (%R8,%RAX,8),%XMM0,%XMM0 |
(662) 0x4751ea CMP $-0x1,%RCX |
(662) 0x4751ee JE 475238 |
(662) 0x4751f0 CMP (%RBX,%RCX,8),%RDX |
(662) 0x4751f4 JNE 475238 |
(662) 0x4751f6 MOV 0xe0(%RSP),%RDI |
(662) 0x4751fe LEA (,%RSI,8),%R8 |
(662) 0x475206 VMOVSD (%RDI,%RAX,8),%XMM8 |
(662) 0x47520b MOV 0xd8(%RSP),%RDI |
(662) 0x475213 VMOVSD %XMM8,(%RDI,%RSI,8) |
(662) 0x475218 MOV 0x90(%RSP),%RDI |
(662) 0x475220 VADDSD %XMM8,%XMM2,%XMM2 |
(662) 0x475225 INC %RSI |
(662) 0x475228 MOV (%RDI,%RCX,8),%RCX |
(662) 0x47522c MOV 0x88(%RSP),%RDI |
(662) 0x475234 MOV %RCX,(%RDI,%R8,1) |
(662) 0x475238 INC %RAX |
(662) 0x47523b CMP %RAX,(%R9) |
(662) 0x47523e JG 4751d0 |
(659) 0x475240 JMP 474bc2 |
0x475245 NOPL (%RAX) |
(659) 0x475248 MOV %RSI,%R8 |
(659) 0x47524b JMP 474bcd |
(659) 0x475250 XOR %EAX,%EAX |
(659) 0x475252 JMP 474d93 |
(659) 0x475257 XOR %R9D,%R9D |
(659) 0x47525a JMP 474fac |
0x47525f MOV $0x8,%ESI |
0x475264 MOV %RBX,%RDI |
0x475267 MOV %R10,0x68(%RSP) |
0x47526c MOV %R12,0x78(%RSP) |
0x475271 MOV %R11,0xa0(%RSP) |
0x475279 VMOVSD %XMM1,0xa8(%RSP) |
0x475282 MOV %RBX,0xb8(%RSP) |
0x47528a CALL 5b0aa0 <hypre_CAlloc> |
0x47528f MOV 0x78(%RSP),%RCX |
0x475294 MOV 0xb8(%RSP),%RDX |
0x47529c VMOVSD 0xa8(%RSP),%XMM1 |
0x4752a5 MOV 0xa0(%RSP),%R11 |
0x4752ad MOV %RAX,%R12 |
0x4752b0 TEST %RCX,%RCX |
0x4752b3 MOV 0x68(%RSP),%R10 |
0x4752b8 JNE 47536b |
0x4752be XOR %EBX,%EBX |
0x4752c0 TEST %RDX,%RDX |
0x4752c3 JLE 474612 |
0x4752c9 SAL $0x3,%RDX |
0x4752cd MOV $0xff,%ESI |
0x4752d2 MOV %R12,%RDI |
0x4752d5 MOV %R10,0x78(%RSP) |
0x4752da MOV %RCX,0xa0(%RSP) |
0x4752e2 MOV %R11,0xa8(%RSP) |
0x4752ea VMOVSD %XMM1,0xb8(%RSP) |
0x4752f3 CALL 4110a0 <memset@plt> |
0x4752f8 VMOVSD 0xb8(%RSP),%XMM1 |
0x475301 MOV 0xa8(%RSP),%R11 |
0x475309 MOV 0xa0(%RSP),%RCX |
0x475311 MOV 0x78(%RSP),%R10 |
0x475316 TEST %RCX,%RCX |
0x475319 JLE 474612 |
0x47531f LEA (,%RCX,8),%RDX |
0x475327 MOV $0xff,%ESI |
0x47532c MOV %RBX,%RDI |
0x47532f MOV %R10,0xa0(%RSP) |
0x475337 MOV %R11,0xa8(%RSP) |
0x47533f VMOVSD %XMM1,0xb8(%RSP) |
0x475348 CALL 4110a0 <memset@plt> |
0x47534d VMOVSD 0xb8(%RSP),%XMM1 |
0x475356 MOV 0xa8(%RSP),%R11 |
0x47535e MOV 0xa0(%RSP),%R10 |
0x475366 JMP 474612 |
0x47536b MOV %RCX,%RDI |
0x47536e MOV $0x8,%ESI |
0x475373 MOV %R10,0x68(%RSP) |
0x475378 MOV %R11,0x78(%RSP) |
0x47537d MOV %RDX,0xa0(%RSP) |
0x475385 MOV %RCX,0xb8(%RSP) |
0x47538d VMOVSD %XMM1,0xa8(%RSP) |
0x475396 CALL 5b0aa0 <hypre_CAlloc> |
0x47539b MOV 0xa0(%RSP),%RDX |
0x4753a3 MOV 0xb8(%RSP),%RCX |
0x4753ab VMOVSD 0xa8(%RSP),%XMM1 |
0x4753b4 MOV 0x78(%RSP),%R11 |
0x4753b9 MOV %RAX,%RBX |
0x4753bc TEST %RDX,%RDX |
0x4753bf MOV 0x68(%RSP),%R10 |
0x4753c4 JG 4752c9 |
0x4753ca JMP 475316 |
0x4753cf NOP |
0x4753d0 MOV %R12,%RDI |
0x4753d3 MOV $0x8,%ESI |
0x4753d8 MOV %R10,0x78(%RSP) |
0x4753dd MOV %R11,0xa0(%RSP) |
0x4753e5 MOV %R12,0xb8(%RSP) |
0x4753ed XOR %R12D,%R12D |
0x4753f0 VMOVSD %XMM1,0xa8(%RSP) |
0x4753f9 CALL 5b0aa0 <hypre_CAlloc> |
0x4753fe MOV 0xb8(%RSP),%RCX |
0x475406 VMOVSD 0xa8(%RSP),%XMM1 |
0x47540f MOV 0xa0(%RSP),%R11 |
0x475417 MOV 0x78(%RSP),%R10 |
0x47541c MOV %RAX,%RBX |
0x47541f JMP 475316 |
0x475424 NOPW %CS:(%RAX,%RAX,1) |
0x47542f NOP |
Path / |
Source file and lines | par_multi_interp.c:1575-1663 |
Module | exec |
nb instructions | 205 |
nb uops | 218 |
loop length | 1086 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 4 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 32 |
micro-operation queue | 36.33 cycles |
front end | 36.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.40 | 6.40 | 23.00 | 23.00 | 33.00 | 6.40 | 6.40 | 33.00 | 33.00 | 33.00 | 6.40 | 23.00 |
cycles | 6.40 | 7.60 | 23.00 | 23.00 | 33.00 | 6.40 | 6.40 | 33.00 | 33.00 | 33.00 | 6.40 | 23.00 |
Cycles executing div or sqrt instructions | 10.00 |
FE+BE cycles | 34.61-34.66 |
Stall cycles | 0.00 |
Front-end | 36.33 |
Dispatch | 33.00 |
DIV/SQRT | 10.00 |
Overall L1 | 36.33 |
all | 1% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 4% |
all | 7% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 1% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 8% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 10% |
all | 13% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 12% |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x100,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0xf8(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xf0(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd8(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc8(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0xf8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xc0(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa8(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x90(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xb8(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe8(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa0(%RDI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x98(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x88(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x80(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x70(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x68(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x60(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x40(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x50(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x48(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,0xd0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x30(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0xf0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RBX,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 47525f <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xdcf> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
TEST %R12,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 4753d0 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xf40> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EBX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %R12D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R10,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b3bd0 <hypre_GetThreadNum> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b3bc0 <hypre_NumActiveThreads> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xb8(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc8(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xf8(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xa8(%RSP),%XMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R8),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CQTO | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV 0xa0(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IDIV %RSI | 5 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 10 |
DEC %RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %RAX,%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%R9,%RCX,1),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0xf8(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R9,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R9,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %RSI,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVNE %RAX,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP %RDI,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 475050 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xbc0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x70(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVQ 0x145790(%RIP),%XMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VXORPD %XMM4,%XMM4,%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R8,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (%R9,%RDI,8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R9,%RCX,8),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RSI,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 5b0b60 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
JMP 5b0b60 <hypre_Free> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R10,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b0aa0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x78(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xa8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa0(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV 0x68(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JNE 47536b <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xedb> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EBX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 474612 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x182> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
SAL $0x3,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R10,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4110a0 <memset@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0xb8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa8(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa0(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 474612 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x182> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (,%RCX,8),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R10,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4110a0 <memset@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0xb8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa8(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 474612 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x182> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV %RCX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R10,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b0aa0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xa0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xa8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV 0x68(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JG 4752c9 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xe39> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 475316 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xe86> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R10,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %R12D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD %XMM1,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b0aa0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xb8(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xa8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa0(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JMP 475316 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xe86> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | par_multi_interp.c:1575-1663 |
Module | exec |
nb instructions | 205 |
nb uops | 218 |
loop length | 1086 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 4 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 32 |
micro-operation queue | 36.33 cycles |
front end | 36.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.40 | 6.40 | 23.00 | 23.00 | 33.00 | 6.40 | 6.40 | 33.00 | 33.00 | 33.00 | 6.40 | 23.00 |
cycles | 6.40 | 7.60 | 23.00 | 23.00 | 33.00 | 6.40 | 6.40 | 33.00 | 33.00 | 33.00 | 6.40 | 23.00 |
Cycles executing div or sqrt instructions | 10.00 |
FE+BE cycles | 34.61-34.66 |
Stall cycles | 0.00 |
Front-end | 36.33 |
Dispatch | 33.00 |
DIV/SQRT | 10.00 |
Overall L1 | 36.33 |
all | 1% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 4% |
all | 7% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 1% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 8% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 10% |
all | 13% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 12% |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x100,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0xf8(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xf0(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd8(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc8(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0xf8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xc0(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa8(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x90(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xb8(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe8(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa0(%RDI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x98(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x88(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x80(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x70(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x68(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x60(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x40(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x50(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x48(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,0xd0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x30(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0xf0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RBX,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 47525f <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xdcf> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
TEST %R12,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 4753d0 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xf40> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EBX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %R12D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R10,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b3bd0 <hypre_GetThreadNum> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b3bc0 <hypre_NumActiveThreads> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xb8(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc8(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xf8(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xa8(%RSP),%XMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R8),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CQTO | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV 0xa0(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IDIV %RSI | 5 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 10 |
DEC %RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %RAX,%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%R9,%RCX,1),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0xf8(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R9,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R9,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %RSI,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVNE %RAX,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP %RDI,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 475050 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xbc0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x70(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVQ 0x145790(%RIP),%XMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VXORPD %XMM4,%XMM4,%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R8,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (%R9,%RDI,8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R9,%RCX,8),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RSI,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 5b0b60 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
JMP 5b0b60 <hypre_Free> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R10,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b0aa0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x78(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xa8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa0(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV 0x68(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JNE 47536b <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xedb> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EBX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 474612 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x182> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
SAL $0x3,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R10,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4110a0 <memset@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0xb8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa8(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa0(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 474612 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x182> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (,%RCX,8),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R10,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4110a0 <memset@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0xb8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa8(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 474612 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x182> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV %RCX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R10,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b0aa0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xa0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xa8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV 0x68(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JG 4752c9 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xe39> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 475316 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xe86> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R10,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %R12D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD %XMM1,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b0aa0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xb8(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xa8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa0(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JMP 475316 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xe86> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼hypre_BoomerAMGBuildMultipass._omp_fn.9– | 0.46 | 0.09 |
▼Loop 659 - par_multi_interp.c:1605-1660 - exec– | 0.08 | 0.01 |
○Loop 666 - par_multi_interp.c:1618-1628 - exec | 0.38 | 0.06 |
○Loop 663 - par_multi_interp.c:1639-1652 - exec | 0 | 0 |
○Loop 664 - par_multi_interp.c:1639-1652 - exec | 0 | 0 |
○Loop 660 - par_multi_interp.c:1659-1660 - exec | 0 | 0 |
○Loop 661 - par_multi_interp.c:1657-1658 - exec | 0 | 0 |
○Loop 667 - par_multi_interp.c:1618-1628 - exec | 0 | 0 |
○Loop 665 - par_multi_interp.c:1633-1636 - exec | 0 | 0 |
○Loop 668 - par_multi_interp.c:1612-1615 - exec | 0 | 0 |
○Loop 662 - par_multi_interp.c:1639-1652 - exec | 0 | 0 |