Loop Id: 3589 | Module: exec | Source: par_csr_matop.c:946-965 [...] | Coverage: 1.05% |
---|
Loop Id: 3589 | Module: exec | Source: par_csr_matop.c:946-965 [...] | Coverage: 1.05% |
---|
0x4bdf60 MOV %RAX,(%RDI,%R10,8) [3] |
0x4bdf64 VMOVSD %XMM1,(%R12,%RAX,8) [4] |
0x4bdf6a MOV -0x50(%RBP),%R9 [6] |
0x4bdf6e MOV %R10,(%R9,%RAX,8) [8] |
0x4bdf72 INC %RAX |
0x4bdf75 MOV -0x80(%RBP),%RDX [6] |
0x4bdf79 MOV 0x8(%RDX,%RSI,8),%R9 [2] |
0x4bdf7e INC %R8 |
0x4bdf81 CMP %R9,%R8 |
0x4bdf84 JGE 4bdfbb |
0x4bdf86 MOV -0x110(%RBP),%RDX [6] |
0x4bdf8d MOV (%RDX,%R8,8),%R10 [5] |
0x4bdf91 MOV (%RDI,%R10,8),%R11 [3] |
0x4bdf95 MOV -0x108(%RBP),%RDX [6] |
0x4bdf9c VMULSD (%RDX,%R8,8),%XMM0,%XMM1 [7] |
0x4bdfa2 CMP %RBX,%R11 |
0x4bdfa5 JL 4bdf60 |
0x4bdfa7 VADDSD (%R12,%R11,8),%XMM1,%XMM1 [1] |
0x4bdfad VMOVSD %XMM1,(%R12,%R11,8) [1] |
0x4bdfb3 INC %R8 |
0x4bdfb6 CMP %R9,%R8 |
0x4bdfb9 JL 4bdf86 |
/home/eoseret/qaas_runs_CPU_9468/171-147-2675/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 946 - 965 |
-------------------------------------------------------------------------------- |
946: for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++) |
947: { |
948: i3 = B_diag_j[jj3]; |
[...] |
956: if (B_marker[i3] < jj_row_begin_diag) |
957: { |
958: B_marker[i3] = jj_count_diag; |
959: C_diag_data[jj_count_diag] = a_entry*B_diag_data[jj3]; |
960: C_diag_j[jj_count_diag] = i3; |
961: jj_count_diag++; |
962: } |
963: else |
964: { |
965: C_diag_data[B_marker[i3]] += a_entry*B_diag_data[jj3]; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.67 |
CQA speedup if FP arith vectorized | 2.14 |
CQA speedup if fully vectorized | 8.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.07 |
Bottlenecks | |
Function | hypre_ParMatmul.extracted.12 |
Source | par_csr_matop.c:946-948,par_csr_matop.c:956-965 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 2.50 |
CQA cycles if no scalar integer | 1.50 |
CQA cycles if FP arith vectorized | 1.17 |
CQA cycles if fully vectorized | 0.31 |
Front-end cycles | 2.50 |
DIV/SQRT cycles | 1.50 |
P0 cycles | 0.75 |
P1 cycles | 2.33 |
P2 cycles | 2.33 |
P3 cycles | 1.00 |
P4 cycles | 0.65 |
P5 cycles | 1.00 |
P6 cycles | 1.00 |
P7 cycles | 1.00 |
P8 cycles | 1.00 |
P9 cycles | 0.60 |
P10 cycles | 2.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 3.27 |
Stall cycles (UFS) | 0.57 |
Nb insns | 14.50 |
Nb uops | 13.50 |
Nb loads | 7.00 |
Nb stores | 2.00 |
Nb stack references | 3.00 |
FLOP/cycle | 0.60 |
Nb FLOP add-sub | 0.50 |
Nb FLOP mul | 1.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 28.45 |
Bytes prefetched | 0.00 |
Bytes loaded | 56.00 |
Bytes stored | 16.00 |
Stride 0 | 1.00 |
Stride 1 | 1.00 |
Stride n | 1.00 |
Stride unknown | 0.00 |
Stride indirect | 2.00 |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | 0.00 |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | 12.50 |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.44 |
CQA speedup if FP arith vectorized | 2.60 |
CQA speedup if fully vectorized | 8.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.08 |
Bottlenecks | micro-operation queue, |
Function | hypre_ParMatmul.extracted.12 |
Source | par_csr_matop.c:946-948,par_csr_matop.c:956-965 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 2.17 |
CQA cycles if no scalar integer | 1.50 |
CQA cycles if FP arith vectorized | 0.83 |
CQA cycles if fully vectorized | 0.27 |
Front-end cycles | 2.17 |
DIV/SQRT cycles | 1.50 |
P0 cycles | 1.00 |
P1 cycles | 2.00 |
P2 cycles | 2.00 |
P3 cycles | 0.50 |
P4 cycles | 0.70 |
P5 cycles | 1.00 |
P6 cycles | 0.50 |
P7 cycles | 0.50 |
P8 cycles | 0.50 |
P9 cycles | 0.80 |
P10 cycles | 2.00 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 3.08 |
Stall cycles (UFS) | 0.69 |
Nb insns | 12.00 |
Nb uops | 11.00 |
Nb loads | 6.00 |
Nb stores | 1.00 |
Nb stack references | 2.00 |
FLOP/cycle | 0.92 |
Nb FLOP add-sub | 1.00 |
Nb FLOP mul | 1.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 25.85 |
Bytes prefetched | 0.00 |
Bytes loaded | 48.00 |
Bytes stored | 8.00 |
Stride 0 | 1.00 |
Stride 1 | 0.00 |
Stride n | 1.00 |
Stride unknown | 0.00 |
Stride indirect | 2.00 |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | 0.00 |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | 12.50 |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.89 |
CQA speedup if FP arith vectorized | 1.89 |
CQA speedup if fully vectorized | 8.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.06 |
Bottlenecks | micro-operation queue, |
Function | hypre_ParMatmul.extracted.12 |
Source | par_csr_matop.c:946-948,par_csr_matop.c:956-965 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 2.83 |
CQA cycles if no scalar integer | 1.50 |
CQA cycles if FP arith vectorized | 1.50 |
CQA cycles if fully vectorized | 0.35 |
Front-end cycles | 2.83 |
DIV/SQRT cycles | 1.50 |
P0 cycles | 0.50 |
P1 cycles | 2.67 |
P2 cycles | 2.67 |
P3 cycles | 1.50 |
P4 cycles | 0.60 |
P5 cycles | 1.00 |
P6 cycles | 1.50 |
P7 cycles | 1.50 |
P8 cycles | 1.50 |
P9 cycles | 0.40 |
P10 cycles | 2.67 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 3.47 |
Stall cycles (UFS) | 0.45 |
Nb insns | 17.00 |
Nb uops | 16.00 |
Nb loads | 8.00 |
Nb stores | 3.00 |
Nb stack references | 4.00 |
FLOP/cycle | 0.35 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 1.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 31.06 |
Bytes prefetched | 0.00 |
Bytes loaded | 64.00 |
Bytes stored | 24.00 |
Stride 0 | 1.00 |
Stride 1 | 2.00 |
Stride n | 1.00 |
Stride unknown | 0.00 |
Stride indirect | 2.00 |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | 0.00 |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | 12.50 |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Path / |
Function | hypre_ParMatmul.extracted.12 |
Source file and lines | par_csr_matop.c:946-965 |
Module | exec |
nb instructions | 14.50 |
nb uops | 13.50 |
loop length | 62 |
used x86 registers | 10 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 3 |
ADD-SUB / MUL ratio | 1.00 |
micro-operation queue | 2.50 cycles |
front end | 2.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.50 | 0.75 | 2.33 | 2.33 | 1.00 | 0.65 | 1.00 | 1.00 | 1.00 | 1.00 | 0.60 | 2.33 |
cycles | 1.50 | 0.75 | 2.33 | 2.33 | 1.00 | 0.65 | 1.00 | 1.00 | 1.00 | 1.00 | 0.60 | 2.33 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 3.28 |
Stall cycles | 0.57 |
LM full (events) | 1.25 |
Front-end | 2.50 |
Dispatch | 2.33 |
Data deps. | 1.00 |
Overall L1 | 2.50 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | NA (no load vectorizable/vectorized instructions) |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Function | hypre_ParMatmul.extracted.12 |
Source file and lines | par_csr_matop.c:946-965 |
Module | exec |
nb instructions | 12 |
nb uops | 11 |
loop length | 53 |
used x86 registers | 9 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 2 |
ADD-SUB / MUL ratio | 1.00 |
micro-operation queue | 2.17 cycles |
front end | 2.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.50 | 1.00 | 2.00 | 2.00 | 0.50 | 0.70 | 1.00 | 0.50 | 0.50 | 0.50 | 0.80 | 2.00 |
cycles | 1.50 | 1.00 | 2.00 | 2.00 | 0.50 | 0.70 | 1.00 | 0.50 | 0.50 | 0.50 | 0.80 | 2.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 3.08 |
Stall cycles | 0.69 |
LM full (events) | 1.38 |
Front-end | 2.17 |
Dispatch | 2.00 |
Data deps. | 1.00 |
Overall L1 | 2.17 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV -0x110(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX,%R8,8),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI,%R10,8),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x108(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMULSD (%RDX,%R8,8),%XMM0,%XMM1 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
CMP %RBX,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 4bdf60 <hypre_ParMatmul.extracted.12+0x490> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VADDSD (%R12,%R11,8),%XMM1,%XMM1 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VMOVSD %XMM1,(%R12,%R11,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %R9,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 4bdf86 <hypre_ParMatmul.extracted.12+0x4b6> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
Function | hypre_ParMatmul.extracted.12 |
Source file and lines | par_csr_matop.c:946-965 |
Module | exec |
nb instructions | 17 |
nb uops | 16 |
loop length | 71 |
used x86 registers | 11 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 4 |
micro-operation queue | 2.83 cycles |
front end | 2.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.50 | 0.50 | 2.67 | 2.67 | 1.50 | 0.60 | 1.00 | 1.50 | 1.50 | 1.50 | 0.40 | 2.67 |
cycles | 1.50 | 0.50 | 2.67 | 2.67 | 1.50 | 0.60 | 1.00 | 1.50 | 1.50 | 1.50 | 0.40 | 2.67 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 3.47 |
Stall cycles | 0.45 |
LM full (events) | 1.11 |
Front-end | 2.83 |
Dispatch | 2.67 |
Data deps. | 1.00 |
Overall L1 | 2.83 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | NA (no load vectorizable/vectorized instructions) |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV %RAX,(%RDI,%R10,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,(%R12,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x50(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,(%R9,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x80(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RDX,%RSI,8),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %R9,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4bdfbb <hypre_ParMatmul.extracted.12+0x4eb> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x110(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX,%R8,8),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI,%R10,8),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x108(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMULSD (%RDX,%R8,8),%XMM0,%XMM1 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
CMP %RBX,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 4bdf60 <hypre_ParMatmul.extracted.12+0x490> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |