Function: hypre_BoomerAMGBuildMultipass._omp_fn.10 | Module: exec | Source: par_multi_interp.c:1737-1881 [...] | Coverage: 1.62% |
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Function: hypre_BoomerAMGBuildMultipass._omp_fn.10 | Module: exec | Source: par_multi_interp.c:1737-1881 [...] | Coverage: 1.62% |
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/home/eoseret/qaas_runs_CPU_9468/171-147-2675/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1737 - 1881 |
-------------------------------------------------------------------------------- |
1737: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa,tmp_array,tmp_array_offd) |
[...] |
1746: tmp_marker = NULL; |
1747: if (n_fine) |
1748: { tmp_marker = hypre_CTAlloc(HYPRE_Int,n_fine); } |
1749: tmp_marker_offd = NULL; |
1750: if (num_cols_offd) |
1751: { tmp_marker_offd = hypre_CTAlloc(HYPRE_Int,num_cols_offd); } |
1752: tmp_array = NULL; |
1753: if (n_coarse) |
1754: { tmp_array = hypre_CTAlloc(HYPRE_Int,n_coarse); } |
1755: tmp_array_offd = NULL; |
1756: if (new_num_cols_offd > n_coarse_offd) |
1757: { tmp_array_offd = hypre_CTAlloc(HYPRE_Int,new_num_cols_offd); } |
1758: else |
1759: { tmp_array_offd = hypre_CTAlloc(HYPRE_Int,n_coarse_offd);} |
1760: for (i=0; i < n_fine; i++) |
1761: { tmp_marker[i] = -1; } |
1762: for (i=0; i < num_cols_offd; i++) |
1763: { tmp_marker_offd[i] = -1; } |
1764: |
1765: /* Compute this thread's range of pass_length */ |
1766: my_thread_num = hypre_GetThreadNum(); |
1767: num_threads = hypre_NumActiveThreads(); |
1768: thread_start = pass_pointer[pass] + (pass_length/num_threads)*my_thread_num; |
1769: if (my_thread_num == num_threads-1) |
1770: { thread_stop = pass_pointer[pass] + pass_length; } |
1771: else |
1772: { thread_stop = pass_pointer[pass] + (pass_length/num_threads)*(my_thread_num+1); } |
1773: |
1774: for (i=thread_start; i < thread_stop; i++) |
1775: { |
1776: i1 = pass_array[i]; |
1777: sum_C = 0; |
1778: sum_N = 0; |
1779: j_start = P_diag_start[i1]; |
1780: j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1]; |
1781: cnt = P_diag_i[i1]; |
1782: for (j=j_start; j < j_end; j++) |
1783: { |
1784: k1 = P_diag_pass[pass][j]; |
1785: tmp_array[k1] = cnt; |
1786: P_diag_data[cnt] = 0; |
1787: P_diag_j[cnt++] = k1; |
1788: } |
1789: j_start = P_offd_start[i1]; |
1790: j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1]; |
1791: cnt_offd = P_offd_i[i1]; |
1792: for (j=j_start; j < j_end; j++) |
1793: { |
1794: k1 = P_offd_pass[pass][j]; |
1795: tmp_array_offd[k1] = cnt_offd; |
1796: P_offd_data[cnt_offd] = 0; |
1797: P_offd_j[cnt_offd++] = k1; |
1798: } |
1799: for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++) |
1800: { |
1801: j1 = S_diag_j[j]; |
1802: if (assigned[j1] == pass-1) |
1803: tmp_marker[j1] = i1; |
1804: } |
1805: for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++) |
1806: { |
1807: j1 = S_offd_j[j]; |
1808: if (assigned_offd[j1] == pass-1) |
1809: tmp_marker_offd[j1] = i1; |
1810: } |
1811: for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++) |
1812: { |
1813: j1 = A_diag_j[j]; |
1814: if (tmp_marker[j1] == i1) |
1815: { |
1816: for (k=P_diag_i[j1]; k < P_diag_i[j1+1]; k++) |
1817: { |
1818: k1 = P_diag_j[k]; |
1819: alfa = A_diag_data[j]*P_diag_data[k]; |
1820: P_diag_data[tmp_array[k1]] += alfa; |
1821: sum_C += alfa; |
1822: sum_N += alfa; |
1823: } |
1824: for (k=P_offd_i[j1]; k < P_offd_i[j1+1]; k++) |
1825: { |
1826: k1 = P_offd_j[k]; |
1827: alfa = A_diag_data[j]*P_offd_data[k]; |
1828: P_offd_data[tmp_array_offd[k1]] += alfa; |
1829: sum_C += alfa; |
1830: sum_N += alfa; |
1831: } |
1832: } |
1833: else |
1834: { |
1835: if (CF_marker[j1] != -3 && |
1836: (num_functions == 1 || dof_func[i1] == dof_func[j1])) |
1837: sum_N += A_diag_data[j]; |
1838: } |
1839: } |
1840: for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++) |
1841: { |
1842: if (col_offd_S_to_A) |
1843: j1 = map_A_to_S[A_offd_j[j]]; |
1844: else |
1845: j1 = A_offd_j[j]; |
1846: |
1847: if (j1 > -1 && tmp_marker_offd[j1] == i1) |
1848: { |
1849: j_start = Pext_start[j1]; |
1850: j_end = j_start+Pext_i[j1+1]; |
1851: for (k=j_start; k < j_end; k++) |
1852: { |
1853: k1 = Pext_pass[pass][k]; |
1854: alfa = A_offd_data[j]*Pext_data[k]; |
1855: if (k1 < 0) |
1856: P_diag_data[tmp_array[-k1-1]] += alfa; |
1857: else |
1858: P_offd_data[tmp_array_offd[k1]] += alfa; |
1859: sum_C += alfa; |
1860: sum_N += alfa; |
1861: } |
1862: } |
1863: else |
1864: { |
1865: if (CF_marker_offd[j1] != -3 && |
1866: (num_functions == 1 || dof_func_offd[j1] == dof_func[i1])) |
1867: sum_N += A_offd_data[j]; |
1868: } |
1869: } |
1870: diagonal = A_diag_data[A_diag_i[i1]]; |
1871: if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal); |
1872: |
1873: for (j=P_diag_i[i1]; j < P_diag_i[i1+1]; j++) |
1874: P_diag_data[j] *= alfa; |
1875: for (j=P_offd_i[i1]; j < P_offd_i[i1+1]; j++) |
1876: P_offd_data[j] *= alfa; |
1877: } |
1878: hypre_TFree(tmp_marker); |
1879: hypre_TFree(tmp_marker_offd); |
1880: hypre_TFree(tmp_array); |
1881: hypre_TFree(tmp_array_offd); |
0x472c60 PUSH %RBP |
0x472c61 MOV %RSP,%RBP |
0x472c64 PUSH %R15 |
0x472c66 PUSH %R14 |
0x472c68 PUSH %R13 |
0x472c6a PUSH %R12 |
0x472c6c PUSH %RBX |
0x472c6d AND $-0x40,%RSP |
0x472c71 SUB $0x180,%RSP |
0x472c78 MOV 0x148(%RDI),%RAX |
0x472c7f MOV 0x138(%RDI),%RDX |
0x472c86 MOV 0x130(%RDI),%RCX |
0x472c8d MOV 0x128(%RDI),%RBX |
0x472c94 MOV 0x108(%RDI),%R9 |
0x472c9b MOV 0x100(%RDI),%R10 |
0x472ca2 MOV %RAX,0x168(%RSP) |
0x472caa MOV 0xf8(%RDI),%R11 |
0x472cb1 MOV 0xf0(%RDI),%R12 |
0x472cb8 MOV %RDX,0xa8(%RSP) |
0x472cc0 MOV 0xe8(%RDI),%R13 |
0x472cc7 MOV 0xe0(%RDI),%R14 |
0x472cce MOV %RCX,0x158(%RSP) |
0x472cd6 MOV 0x110(%RDI),%RSI |
0x472cdd MOV 0x140(%RDI),%R8 |
0x472ce4 MOV %RBX,0x150(%RSP) |
0x472cec MOV %R9,0x130(%RSP) |
0x472cf4 MOV 0x120(%RDI),%RDX |
0x472cfb MOV %R10,0x118(%RSP) |
0x472d03 MOV 0x118(%RDI),%RCX |
0x472d0a MOV %R11,0x38(%RSP) |
0x472d0f MOV %R12,0x28(%RSP) |
0x472d14 MOV %R13,0x68(%RSP) |
0x472d19 MOV %R14,0x60(%RSP) |
0x472d1e MOV %RSI,0x178(%RSP) |
0x472d26 MOV 0xd8(%RDI),%R15 |
0x472d2d MOV 0xd0(%RDI),%RAX |
0x472d34 MOV 0xc8(%RDI),%RBX |
0x472d3b MOV 0xc0(%RDI),%R9 |
0x472d42 MOV 0xb8(%RDI),%R10 |
0x472d49 MOV %R15,0xa0(%RSP) |
0x472d51 MOV 0x68(%RDI),%R15 |
0x472d55 MOV 0xb0(%RDI),%R11 |
0x472d5c MOV %RAX,0x98(%RSP) |
0x472d64 MOV 0xa8(%RDI),%R12 |
0x472d6b MOV 0x98(%RDI),%R13 |
0x472d72 MOV %RBX,0x110(%RSP) |
0x472d7a MOV 0x80(%RDI),%R14 |
0x472d81 MOV 0x60(%RDI),%RAX |
0x472d85 MOV %R9,0xd0(%RSP) |
0x472d8d MOV 0x58(%RDI),%RBX |
0x472d91 MOV 0x50(%RDI),%R9 |
0x472d95 MOV %R15,0x148(%RSP) |
0x472d9d MOV 0x48(%RDI),%R15 |
0x472da1 MOV %R10,0x108(%RSP) |
0x472da9 MOV %R11,0x58(%RSP) |
0x472dae MOV 0xa0(%RDI),%R10 |
0x472db5 MOV %R12,0x30(%RSP) |
0x472dba MOV 0x90(%RDI),%R11 |
0x472dc1 MOV %R13,0xf8(%RSP) |
0x472dc9 MOV 0x78(%RDI),%R12 |
0x472dcd MOV %R14,0xf0(%RSP) |
0x472dd5 MOV 0x88(%RDI),%R13 |
0x472ddc MOV %RAX,0x90(%RSP) |
0x472de4 MOV 0x70(%RDI),%R14 |
0x472de8 MOV %RBX,0x140(%RSP) |
0x472df0 MOV %R9,0x88(%RSP) |
0x472df8 MOV %R15,0x50(%RSP) |
0x472dfd MOV 0x40(%RDI),%RAX |
0x472e01 MOV 0x38(%RDI),%RBX |
0x472e05 MOV 0x30(%RDI),%R9 |
0x472e09 MOV 0x28(%RDI),%R15 |
0x472e0d MOV %RAX,0x80(%RSP) |
0x472e15 MOV %RBX,0x48(%RSP) |
0x472e1a MOV 0x20(%RDI),%RAX |
0x472e1e MOV 0x18(%RDI),%RBX |
0x472e22 MOV %R9,0x40(%RSP) |
0x472e27 MOV %R15,0x78(%RSP) |
0x472e2c MOV 0x10(%RDI),%R9 |
0x472e30 MOV 0x8(%RDI),%R15 |
0x472e34 MOV (%RDI),%RDI |
0x472e37 MOV %RAX,0xe8(%RSP) |
0x472e3f MOV %RBX,0xc8(%RSP) |
0x472e47 MOV %R9,0x120(%RSP) |
0x472e4f MOV %R15,0x160(%RSP) |
0x472e57 MOV %RDI,0x128(%RSP) |
0x472e5f TEST %RSI,%RSI |
0x472e62 JNE 474407 |
0x472e68 MOVQ $0,0x170(%RSP) |
0x472e74 TEST %R14,%R14 |
0x472e77 JNE 47438b |
0x472e7d MOVQ $0,0x138(%RSP) |
0x472e89 TEST %RCX,%RCX |
0x472e8c JNE 474324 |
0x472e92 XOR %R15D,%R15D |
0x472e95 CMP %RDX,%R8 |
0x472e98 JLE 4742fe |
0x472e9e MOV %R11,0xd8(%RSP) |
0x472ea6 MOV $0x8,%ESI |
0x472eab MOV %R8,%RDI |
0x472eae MOV %R10,0xe0(%RSP) |
0x472eb6 VMOVSD %XMM2,0x100(%RSP) |
0x472ebf CALL 5b0aa0 <hypre_CAlloc> |
0x472ec4 CMPQ $0,0x178(%RSP) |
0x472ecd VMOVSD 0x100(%RSP),%XMM2 |
0x472ed6 MOV %RAX,%RBX |
0x472ed9 MOV 0xe0(%RSP),%RSI |
0x472ee1 MOV 0xd8(%RSP),%RAX |
0x472ee9 JLE 472f3b |
0x472eeb MOV 0x178(%RSP),%RDX |
0x472ef3 MOV 0x170(%RSP),%RDI |
0x472efb MOV %RSI,0xe0(%RSP) |
0x472f03 MOV $0xff,%ESI |
0x472f08 VMOVSD %XMM2,0x100(%RSP) |
0x472f11 SAL $0x3,%RDX |
0x472f15 MOV %RAX,0xd8(%RSP) |
0x472f1d CALL 4110a0 <memset@plt> |
0x472f22 VMOVSD 0x100(%RSP),%XMM2 |
0x472f2b MOV 0xe0(%RSP),%RSI |
0x472f33 MOV 0xd8(%RSP),%RAX |
0x472f3b TEST %R14,%R14 |
0x472f3e JLE 472f8c |
0x472f40 MOV 0x138(%RSP),%RDI |
0x472f48 MOV %RSI,0x100(%RSP) |
0x472f50 LEA (,%R14,8),%RDX |
0x472f58 MOV $0xff,%ESI |
0x472f5d VMOVSD %XMM2,0x178(%RSP) |
0x472f66 MOV %RAX,0xe0(%RSP) |
0x472f6e CALL 4110a0 <memset@plt> |
0x472f73 VMOVSD 0x178(%RSP),%XMM2 |
0x472f7c MOV 0x100(%RSP),%RSI |
0x472f84 MOV 0xe0(%RSP),%RAX |
0x472f8c MOV %RSI,0xe0(%RSP) |
0x472f94 VMOVSD %XMM2,0x178(%RSP) |
0x472f9d MOV %RAX,0xd8(%RSP) |
0x472fa5 CALL 5b3bd0 <hypre_GetThreadNum> |
0x472faa MOV %RAX,%R14 |
0x472fad CALL 5b3bc0 <hypre_NumActiveThreads> |
0x472fb2 MOV 0x130(%RSP),%R8 |
0x472fba MOV 0x110(%RSP),%RDX |
0x472fc2 MOV %R14,%R10 |
0x472fc5 MOV %RAX,%R9 |
0x472fc8 MOV 0x168(%RSP),%RAX |
0x472fd0 MOV 0x168(%RSP),%R11 |
0x472fd8 MOV (%RDX,%R8,8),%RCX |
0x472fdc LEA (,%R8,8),%RDI |
0x472fe4 VMOVSD 0x178(%RSP),%XMM12 |
0x472fed CQTO |
0x472fef MOV %RDI,0x100(%RSP) |
0x472ff7 IDIV %R9 |
0x472ffa ADD %RCX,%R11 |
0x472ffd DEC %R9 |
0x473000 MOV %R11,%R8 |
0x473003 MOV 0xd8(%RSP),%R11 |
0x47300b IMUL %RAX,%R10 |
0x47300f ADD %R10,%RAX |
0x473012 LEA (%RCX,%R10,1),%RSI |
0x473016 MOV 0xe0(%RSP),%R10 |
0x47301e ADD %RCX,%RAX |
0x473021 CMP %R9,%R14 |
0x473024 CMOVNE %RAX,%R8 |
0x473028 CMP %RSI,%R8 |
0x47302b JLE 473f6c |
0x473031 MOV 0xd0(%RSP),%R14 |
0x473039 VMOVQ 0x146dff(%RIP),%XMM4 |
0x473041 VXORPD %XMM3,%XMM3,%XMM3 |
0x473045 LEA (%R14,%RSI,8),%R9 |
0x473049 LEA (%R14,%R8,8),%RDI |
0x47304d MOV 0x130(%RSP),%R14 |
0x473055 MOV %R15,0x130(%RSP) |
0x47305d MOV %R9,0x110(%RSP) |
0x473065 MOV 0xc8(%RSP),%R15 |
0x47306d MOV %RDI,0x70(%RSP) |
0x473072 DEC %R14 |
0x473075 NOPL (%RAX) |
(647) 0x473078 MOV 0x110(%RSP),%RCX |
(647) 0x473080 MOV 0xf0(%RSP),%R8 |
(647) 0x473088 MOV 0x98(%RSP),%RDX |
(647) 0x473090 MOV (%RCX),%RDI |
(647) 0x473093 LEA (,%RDI,8),%RAX |
(647) 0x47309b MOV (%RDX,%RDI,8),%RDX |
(647) 0x47309f LEA 0x8(%RAX),%RCX |
(647) 0x4730a3 MOV %RAX,0x168(%RSP) |
(647) 0x4730ab ADD %R8,%RAX |
(647) 0x4730ae LEA (%R8,%RCX,1),%RSI |
(647) 0x4730b2 MOV %RAX,0xd8(%RSP) |
(647) 0x4730ba MOV (%RAX),%RAX |
(647) 0x4730bd MOV (%RSI),%R9 |
(647) 0x4730c0 MOV %RSI,0xe0(%RSP) |
(647) 0x4730c8 ADD %RDX,%R9 |
(647) 0x4730cb SUB %RAX,%R9 |
(647) 0x4730ce CMP %R9,%RDX |
(647) 0x4730d1 JGE 473305 |
(647) 0x4730d7 MOV %RAX,%RSI |
(647) 0x4730da MOV 0x60(%RSP),%R8 |
(647) 0x4730df SUB %RDX,%RSI |
(647) 0x4730e2 SUB %RAX,%RDX |
(647) 0x4730e5 ADD %R9,%RSI |
(647) 0x4730e8 MOV 0x100(%RSP),%R9 |
(647) 0x4730f0 MOV (%R8,%R9,1),%R8 |
(647) 0x4730f4 MOV %RSI,%R9 |
(647) 0x4730f7 SUB %RAX,%R9 |
(647) 0x4730fa LEA (%R8,%RDX,8),%RDX |
(647) 0x4730fe AND $0x7,%R9D |
(647) 0x473102 JE 4742aa |
(647) 0x473108 CMP $0x1,%R9 |
(647) 0x47310c JE 4731f8 |
(647) 0x473112 CMP $0x2,%R9 |
(647) 0x473116 JE 4731d8 |
(647) 0x47311c CMP $0x3,%R9 |
(647) 0x473120 JE 4731b8 |
(647) 0x473126 CMP $0x4,%R9 |
(647) 0x47312a JE 473198 |
(647) 0x47312c CMP $0x5,%R9 |
(647) 0x473130 JE 473178 |
(647) 0x473132 CMP $0x6,%R9 |
(647) 0x473136 JE 473158 |
(647) 0x473138 MOV (%RDX,%RAX,8),%R8 |
(647) 0x47313c MOV 0x130(%RSP),%R9 |
(647) 0x473144 MOV %RAX,(%R9,%R8,8) |
(647) 0x473148 MOVQ $0,(%R12,%RAX,8) |
(647) 0x473150 INC %RAX |
(647) 0x473153 MOV %R8,-0x8(%R13,%RAX,8) |
(647) 0x473158 MOV (%RDX,%RAX,8),%R8 |
(647) 0x47315c MOV 0x130(%RSP),%R9 |
(647) 0x473164 MOV %RAX,(%R9,%R8,8) |
(647) 0x473168 MOVQ $0,(%R12,%RAX,8) |
(647) 0x473170 INC %RAX |
(647) 0x473173 MOV %R8,-0x8(%R13,%RAX,8) |
(647) 0x473178 MOV (%RDX,%RAX,8),%R8 |
(647) 0x47317c MOV 0x130(%RSP),%R9 |
(647) 0x473184 MOV %RAX,(%R9,%R8,8) |
(647) 0x473188 MOVQ $0,(%R12,%RAX,8) |
(647) 0x473190 INC %RAX |
(647) 0x473193 MOV %R8,-0x8(%R13,%RAX,8) |
(647) 0x473198 MOV (%RDX,%RAX,8),%R8 |
(647) 0x47319c MOV 0x130(%RSP),%R9 |
(647) 0x4731a4 MOV %RAX,(%R9,%R8,8) |
(647) 0x4731a8 MOVQ $0,(%R12,%RAX,8) |
(647) 0x4731b0 INC %RAX |
(647) 0x4731b3 MOV %R8,-0x8(%R13,%RAX,8) |
(647) 0x4731b8 MOV (%RDX,%RAX,8),%R8 |
(647) 0x4731bc MOV 0x130(%RSP),%R9 |
(647) 0x4731c4 MOV %RAX,(%R9,%R8,8) |
(647) 0x4731c8 MOVQ $0,(%R12,%RAX,8) |
(647) 0x4731d0 INC %RAX |
(647) 0x4731d3 MOV %R8,-0x8(%R13,%RAX,8) |
(647) 0x4731d8 MOV (%RDX,%RAX,8),%R8 |
(647) 0x4731dc MOV 0x130(%RSP),%R9 |
(647) 0x4731e4 MOV %RAX,(%R9,%R8,8) |
(647) 0x4731e8 MOVQ $0,(%R12,%RAX,8) |
(647) 0x4731f0 INC %RAX |
(647) 0x4731f3 MOV %R8,-0x8(%R13,%RAX,8) |
(647) 0x4731f8 MOV (%RDX,%RAX,8),%R8 |
(647) 0x4731fc MOV 0x130(%RSP),%R9 |
(647) 0x473204 MOV %RAX,(%R9,%R8,8) |
(647) 0x473208 MOVQ $0,(%R12,%RAX,8) |
(647) 0x473210 INC %RAX |
(647) 0x473213 MOV %R8,-0x8(%R13,%RAX,8) |
(647) 0x473218 CMP %RAX,%RSI |
(647) 0x47321b JE 473305 |
(647) 0x473221 MOV %RBX,0x178(%RSP) |
(647) 0x473229 MOV %R9,%R8 |
(658) 0x47322c MOV (%RDX,%RAX,8),%RBX |
(658) 0x473230 LEA 0x1(%RAX),%R9 |
(658) 0x473234 MOV %RAX,(%R8,%RBX,8) |
(658) 0x473238 MOVQ $0,(%R12,%RAX,8) |
(658) 0x473240 MOV %RBX,-0x8(%R13,%R9,8) |
(658) 0x473245 MOV (%RDX,%R9,8),%RBX |
(658) 0x473249 MOV %R9,(%R8,%RBX,8) |
(658) 0x47324d MOVQ $0,(%R12,%R9,8) |
(658) 0x473255 LEA 0x2(%RAX),%R9 |
(658) 0x473259 MOV %RBX,-0x8(%R13,%R9,8) |
(658) 0x47325e MOV (%RDX,%R9,8),%RBX |
(658) 0x473262 MOV %R9,(%R8,%RBX,8) |
(658) 0x473266 MOVQ $0,(%R12,%R9,8) |
(658) 0x47326e LEA 0x3(%RAX),%R9 |
(658) 0x473272 MOV %RBX,-0x8(%R13,%R9,8) |
(658) 0x473277 MOV (%RDX,%R9,8),%RBX |
(658) 0x47327b MOV %R9,(%R8,%RBX,8) |
(658) 0x47327f MOVQ $0,(%R12,%R9,8) |
(658) 0x473287 LEA 0x4(%RAX),%R9 |
(658) 0x47328b MOV %RBX,-0x8(%R13,%R9,8) |
(658) 0x473290 MOV (%RDX,%R9,8),%RBX |
(658) 0x473294 MOV %R9,(%R8,%RBX,8) |
(658) 0x473298 MOVQ $0,(%R12,%R9,8) |
(658) 0x4732a0 LEA 0x5(%RAX),%R9 |
(658) 0x4732a4 MOV %RBX,-0x8(%R13,%R9,8) |
(658) 0x4732a9 MOV (%RDX,%R9,8),%RBX |
(658) 0x4732ad MOV %R9,(%R8,%RBX,8) |
(658) 0x4732b1 MOVQ $0,(%R12,%R9,8) |
(658) 0x4732b9 LEA 0x6(%RAX),%R9 |
(658) 0x4732bd MOV %RBX,-0x8(%R13,%R9,8) |
(658) 0x4732c2 MOV (%RDX,%R9,8),%RBX |
(658) 0x4732c6 MOV %R9,(%R8,%RBX,8) |
(658) 0x4732ca MOVQ $0,(%R12,%R9,8) |
(658) 0x4732d2 LEA 0x7(%RAX),%R9 |
(658) 0x4732d6 ADD $0x8,%RAX |
(658) 0x4732da MOV %RBX,-0x8(%R13,%R9,8) |
(658) 0x4732df MOV (%RDX,%R9,8),%RBX |
(658) 0x4732e3 MOV %R9,(%R8,%RBX,8) |
(658) 0x4732e7 MOVQ $0,(%R12,%R9,8) |
(658) 0x4732ef MOV %RBX,-0x8(%R13,%RAX,8) |
(658) 0x4732f4 CMP %RAX,%RSI |
(658) 0x4732f7 JNE 47322c |
(647) 0x4732fd MOV 0x178(%RSP),%RBX |
(647) 0x473305 MOV 0xf8(%RSP),%R8 |
(647) 0x47330d MOV 0x168(%RSP),%R9 |
(647) 0x473315 MOV 0xa0(%RSP),%RAX |
(647) 0x47331d LEA (%R8,%RCX,1),%RSI |
(647) 0x473321 ADD %R9,%R8 |
(647) 0x473324 MOV (%RAX,%RDI,8),%RDX |
(647) 0x473328 MOV (%R8),%RAX |
(647) 0x47332b MOV %R8,0xc8(%RSP) |
(647) 0x473333 MOV (%RSI),%R8 |
(647) 0x473336 MOV %RSI,0xd0(%RSP) |
(647) 0x47333e ADD %RDX,%R8 |
(647) 0x473341 SUB %RAX,%R8 |
(647) 0x473344 CMP %R8,%RDX |
(647) 0x473347 JGE 47352c |
(647) 0x47334d MOV %RAX,%RSI |
(647) 0x473350 MOV 0x100(%RSP),%R9 |
(647) 0x473358 SUB %RDX,%RSI |
(647) 0x47335b SUB %RAX,%RDX |
(647) 0x47335e ADD %R8,%RSI |
(647) 0x473361 MOV 0x68(%RSP),%R8 |
(647) 0x473366 MOV (%R8,%R9,1),%R8 |
(647) 0x47336a MOV %RSI,%R9 |
(647) 0x47336d SUB %RAX,%R9 |
(647) 0x473370 LEA (%R8,%RDX,8),%RDX |
(647) 0x473374 AND $0x7,%R9D |
(647) 0x473378 JE 47345b |
(647) 0x47337e CMP $0x1,%R9 |
(647) 0x473382 JE 47343a |
(647) 0x473388 CMP $0x2,%R9 |
(647) 0x47338c JE 473422 |
(647) 0x473392 CMP $0x3,%R9 |
(647) 0x473396 JE 47340a |
(647) 0x473398 CMP $0x4,%R9 |
(647) 0x47339c JE 4733f2 |
(647) 0x47339e CMP $0x5,%R9 |
(647) 0x4733a2 JE 4733da |
(647) 0x4733a4 CMP $0x6,%R9 |
(647) 0x4733a8 JE 4733c2 |
(647) 0x4733aa MOV (%RDX,%RAX,8),%R8 |
(647) 0x4733ae MOV %RAX,(%RBX,%R8,8) |
(647) 0x4733b2 MOVQ $0,(%R11,%RAX,8) |
(647) 0x4733ba INC %RAX |
(647) 0x4733bd MOV %R8,-0x8(%R10,%RAX,8) |
(647) 0x4733c2 MOV (%RDX,%RAX,8),%R9 |
(647) 0x4733c6 MOV %RAX,(%RBX,%R9,8) |
(647) 0x4733ca MOVQ $0,(%R11,%RAX,8) |
(647) 0x4733d2 INC %RAX |
(647) 0x4733d5 MOV %R9,-0x8(%R10,%RAX,8) |
(647) 0x4733da MOV (%RDX,%RAX,8),%R8 |
(647) 0x4733de MOV %RAX,(%RBX,%R8,8) |
(647) 0x4733e2 MOVQ $0,(%R11,%RAX,8) |
(647) 0x4733ea INC %RAX |
(647) 0x4733ed MOV %R8,-0x8(%R10,%RAX,8) |
(647) 0x4733f2 MOV (%RDX,%RAX,8),%R9 |
(647) 0x4733f6 MOV %RAX,(%RBX,%R9,8) |
(647) 0x4733fa MOVQ $0,(%R11,%RAX,8) |
(647) 0x473402 INC %RAX |
(647) 0x473405 MOV %R9,-0x8(%R10,%RAX,8) |
(647) 0x47340a MOV (%RDX,%RAX,8),%R8 |
(647) 0x47340e MOV %RAX,(%RBX,%R8,8) |
(647) 0x473412 MOVQ $0,(%R11,%RAX,8) |
(647) 0x47341a INC %RAX |
(647) 0x47341d MOV %R8,-0x8(%R10,%RAX,8) |
(647) 0x473422 MOV (%RDX,%RAX,8),%R9 |
(647) 0x473426 MOV %RAX,(%RBX,%R9,8) |
(647) 0x47342a MOVQ $0,(%R11,%RAX,8) |
(647) 0x473432 INC %RAX |
(647) 0x473435 MOV %R9,-0x8(%R10,%RAX,8) |
(647) 0x47343a MOV (%RDX,%RAX,8),%R8 |
(647) 0x47343e MOV %RAX,(%RBX,%R8,8) |
(647) 0x473442 MOVQ $0,(%R11,%RAX,8) |
(647) 0x47344a INC %RAX |
(647) 0x47344d MOV %R8,-0x8(%R10,%RAX,8) |
(647) 0x473452 CMP %RAX,%RSI |
(647) 0x473455 JE 47352c |
(657) 0x47345b MOV (%RDX,%RAX,8),%R9 |
(657) 0x47345f LEA 0x1(%RAX),%R8 |
(657) 0x473463 MOV %RAX,(%RBX,%R9,8) |
(657) 0x473467 MOVQ $0,(%R11,%RAX,8) |
(657) 0x47346f MOV %R9,-0x8(%R10,%R8,8) |
(657) 0x473474 MOV (%RDX,%R8,8),%R9 |
(657) 0x473478 MOV %R8,(%RBX,%R9,8) |
(657) 0x47347c MOVQ $0,(%R11,%R8,8) |
(657) 0x473484 LEA 0x2(%RAX),%R8 |
(657) 0x473488 MOV %R9,-0x8(%R10,%R8,8) |
(657) 0x47348d MOV (%RDX,%R8,8),%R9 |
(657) 0x473491 MOV %R8,(%RBX,%R9,8) |
(657) 0x473495 MOVQ $0,(%R11,%R8,8) |
(657) 0x47349d LEA 0x3(%RAX),%R8 |
(657) 0x4734a1 MOV %R9,-0x8(%R10,%R8,8) |
(657) 0x4734a6 MOV (%RDX,%R8,8),%R9 |
(657) 0x4734aa MOV %R8,(%RBX,%R9,8) |
(657) 0x4734ae MOVQ $0,(%R11,%R8,8) |
(657) 0x4734b6 LEA 0x4(%RAX),%R8 |
(657) 0x4734ba MOV %R9,-0x8(%R10,%R8,8) |
(657) 0x4734bf MOV (%RDX,%R8,8),%R9 |
(657) 0x4734c3 MOV %R8,(%RBX,%R9,8) |
(657) 0x4734c7 MOVQ $0,(%R11,%R8,8) |
(657) 0x4734cf LEA 0x5(%RAX),%R8 |
(657) 0x4734d3 MOV %R9,-0x8(%R10,%R8,8) |
(657) 0x4734d8 MOV (%RDX,%R8,8),%R9 |
(657) 0x4734dc MOV %R8,(%RBX,%R9,8) |
(657) 0x4734e0 MOVQ $0,(%R11,%R8,8) |
(657) 0x4734e8 LEA 0x6(%RAX),%R8 |
(657) 0x4734ec MOV %R9,-0x8(%R10,%R8,8) |
(657) 0x4734f1 MOV (%RDX,%R8,8),%R9 |
(657) 0x4734f5 MOV %R8,(%RBX,%R9,8) |
(657) 0x4734f9 MOVQ $0,(%R11,%R8,8) |
(657) 0x473501 LEA 0x7(%RAX),%R8 |
(657) 0x473505 ADD $0x8,%RAX |
(657) 0x473509 MOV %R9,-0x8(%R10,%R8,8) |
(657) 0x47350e MOV (%RDX,%R8,8),%R9 |
(657) 0x473512 MOV %R8,(%RBX,%R9,8) |
(657) 0x473516 MOVQ $0,(%R11,%R8,8) |
(657) 0x47351e MOV %R9,-0x8(%R10,%RAX,8) |
(657) 0x473523 CMP %RAX,%RSI |
(657) 0x473526 JNE 47345b |
(647) 0x47352c MOV 0x88(%RSP),%RSI |
(647) 0x473534 LEA (%RSI,%RCX,1),%R8 |
(647) 0x473538 MOV (%RSI,%RDI,8),%RAX |
(647) 0x47353c MOV (%R8),%RSI |
(647) 0x47353f CMP %RSI,%RAX |
(647) 0x473542 JGE 47356e |
(647) 0x473544 NOPL (%RAX) |
(656) 0x473548 MOV 0x140(%RSP),%RDX |
(656) 0x473550 MOV 0x150(%RSP),%R9 |
(656) 0x473558 MOV (%RDX,%RAX,8),%RDX |
(656) 0x47355c CMP (%R9,%RDX,8),%R14 |
(656) 0x473560 JE 4737d0 |
(656) 0x473566 INC %RAX |
(656) 0x473569 CMP %RSI,%RAX |
(656) 0x47356c JL 473548 |
(647) 0x47356e MOV 0x90(%RSP),%R8 |
(647) 0x473576 ADD %R8,%RCX |
(647) 0x473579 MOV (%R8,%RDI,8),%RAX |
(647) 0x47357d MOV (%RCX),%RSI |
(647) 0x473580 CMP %RSI,%RAX |
(647) 0x473583 JGE 4735ae |
(647) 0x473585 NOPL (%RAX) |
(655) 0x473588 MOV 0x148(%RSP),%RDX |
(655) 0x473590 MOV 0x158(%RSP),%R9 |
(655) 0x473598 MOV (%RDX,%RAX,8),%R8 |
(655) 0x47359c CMP (%R9,%R8,8),%R14 |
(655) 0x4735a0 JE 4737b0 |
(655) 0x4735a6 INC %RAX |
(655) 0x4735a9 CMP %RSI,%RAX |
(655) 0x4735ac JL 473588 |
(647) 0x4735ae MOV 0x78(%RSP),%RCX |
(647) 0x4735b3 MOV 0x168(%RSP),%RDX |
(647) 0x4735bb MOV (%RCX,%RDI,8),%R8 |
(647) 0x4735bf MOV 0x8(%RCX,%RDX,1),%RDX |
(647) 0x4735c4 LEA 0x1(%R8),%RAX |
(647) 0x4735c8 CMP %RDX,%RAX |
(647) 0x4735cb JGE 4742bf |
(647) 0x4735d1 MOV 0x40(%RSP),%RCX |
(647) 0x4735d6 MOV 0xe8(%RSP),%R9 |
(647) 0x4735de SAL $0x3,%RAX |
(647) 0x4735e2 VXORPD %XMM0,%XMM0,%XMM0 |
(647) 0x4735e6 MOV %R15,0xc0(%RSP) |
(647) 0x4735ee VMOVSD %XMM0,%XMM0,%XMM1 |
(647) 0x4735f2 MOV 0x130(%RSP),%R15 |
(647) 0x4735fa LEA (%RCX,%RAX,1),%RSI |
(647) 0x4735fe MOV %R8,0xb8(%RSP) |
(647) 0x473606 ADD %R9,%RAX |
(647) 0x473609 LEA (%RCX,%RDX,8),%R9 |
(647) 0x47360d MOV %R14,0xb0(%RSP) |
(647) 0x473615 JMP 473647 |
0x473617 NOPW (%RAX,%RAX,1) |
(652) 0x473620 MOV 0x120(%RSP),%R8 |
(652) 0x473628 MOV 0x168(%RSP),%R14 |
(652) 0x473630 MOV (%R8,%RCX,8),%RCX |
(652) 0x473634 CMP %RCX,(%R8,%R14,1) |
(652) 0x473638 JE 47367e |
(652) 0x47363a ADD $0x8,%RSI |
(652) 0x47363e ADD $0x8,%RAX |
(652) 0x473642 CMP %RSI,%R9 |
(652) 0x473645 JE 47368f |
(652) 0x473647 MOV (%RSI),%RCX |
(652) 0x47364a MOV 0x170(%RSP),%R14 |
(652) 0x473652 LEA (,%RCX,8),%R8 |
(652) 0x47365a CMP (%R14,%RCX,8),%RDI |
(652) 0x47365e JE 4737f0 |
(652) 0x473664 MOV 0x128(%RSP),%RDX |
(652) 0x47366c CMPQ $-0x3,(%RDX,%RCX,8) |
(652) 0x473671 JE 47363a |
(652) 0x473673 CMPQ $0x1,0x160(%RSP) |
(652) 0x47367c JNE 473620 |
(652) 0x47367e ADD $0x8,%RSI |
(652) 0x473682 VADDSD (%RAX),%XMM0,%XMM0 |
(652) 0x473686 ADD $0x8,%RAX |
(652) 0x47368a CMP %RSI,%R9 |
(652) 0x47368d JNE 473647 |
(647) 0x47368f MOV 0xc0(%RSP),%R15 |
(647) 0x473697 MOV 0xb8(%RSP),%R8 |
(647) 0x47369f MOV 0xb0(%RSP),%R14 |
(647) 0x4736a7 MOV 0x80(%RSP),%RCX |
(647) 0x4736af MOV 0x168(%RSP),%RAX |
(647) 0x4736b7 MOV (%RCX,%RDI,8),%RDX |
(647) 0x4736bb MOV 0x8(%RCX,%RAX,1),%RCX |
(647) 0x4736c0 CMP %RCX,%RDX |
(647) 0x4736c3 JGE 473b23 |
(647) 0x4736c9 MOV 0x50(%RSP),%RSI |
(647) 0x4736ce SAL $0x3,%RDX |
(647) 0x4736d2 MOV 0x48(%RSP),%R9 |
(647) 0x4736d7 MOV %R13,0xb8(%RSP) |
(647) 0x4736df MOV %R10,0xc0(%RSP) |
(647) 0x4736e7 MOV 0x58(%RSP),%R13 |
(647) 0x4736ec LEA (%RSI,%RDX,1),%RAX |
(647) 0x4736f0 MOV %R14,0xb0(%RSP) |
(647) 0x4736f8 ADD %R9,%RDX |
(647) 0x4736fb LEA (%RSI,%RCX,8),%RSI |
(647) 0x4736ff MOV %RAX,0x178(%RSP) |
(647) 0x473707 MOV %R8,%RAX |
(647) 0x47370a JMP 473750 |
0x47370c NOPL (%RAX) |
(650) 0x473710 MOV 0x120(%RSP),%R10 |
(650) 0x473718 MOV 0x168(%RSP),%R14 |
(650) 0x473720 MOV 0x108(%RSP),%RCX |
(650) 0x473728 MOV (%R10,%R14,1),%R9 |
(650) 0x47372c CMP %R9,(%RCX,%R8,1) |
(650) 0x473730 JE 4737a2 |
(650) 0x473732 ADDQ $0x8,0x178(%RSP) |
(650) 0x47373b ADD $0x8,%RDX |
(650) 0x47373f MOV 0x178(%RSP),%RCX |
(650) 0x473747 CMP %RSI,%RCX |
(650) 0x47374a JE 473b08 |
(650) 0x473750 MOV 0x178(%RSP),%R10 |
(650) 0x473758 MOV (%R10),%RCX |
(650) 0x47375b TEST %R15,%R15 |
(650) 0x47375e JE 47376c |
(650) 0x473760 MOV 0x118(%RSP),%R14 |
(650) 0x473768 MOV (%R14,%RCX,8),%RCX |
(650) 0x47376c LEA (,%RCX,8),%R8 |
(650) 0x473774 TEST %RCX,%RCX |
(650) 0x473777 JS 47378b |
(650) 0x473779 MOV 0x138(%RSP),%R9 |
(650) 0x473781 CMP (%R9,%RCX,8),%RDI |
(650) 0x473785 JE 473fa8 |
(650) 0x47378b CMPQ $-0x3,(%R13,%R8,1) |
(650) 0x473791 JE 473732 |
(650) 0x473793 CMPQ $0x1,0x160(%RSP) |
(650) 0x47379c JNE 473710 |
(650) 0x4737a2 VADDSD (%RDX),%XMM0,%XMM0 |
(650) 0x4737a6 JMP 473732 |
0x4737a8 NOPL (%RAX,%RAX,1) |
(655) 0x4737b0 MOV 0x138(%RSP),%RSI |
(655) 0x4737b8 INC %RAX |
(655) 0x4737bb MOV %RDI,(%RSI,%R8,8) |
(655) 0x4737bf MOV (%RCX),%RSI |
(655) 0x4737c2 CMP %RAX,%RSI |
(655) 0x4737c5 JG 473588 |
(647) 0x4737cb JMP 4735ae |
(656) 0x4737d0 MOV 0x170(%RSP),%RSI |
(656) 0x4737d8 INC %RAX |
(656) 0x4737db MOV %RDI,(%RSI,%RDX,8) |
(656) 0x4737df MOV (%R8),%RSI |
(656) 0x4737e2 CMP %RAX,%RSI |
(656) 0x4737e5 JG 473548 |
(647) 0x4737eb JMP 47356e |
(652) 0x4737f0 MOV 0xf0(%RSP),%R14 |
(652) 0x4737f8 MOV (%R14,%RCX,8),%RDX |
(652) 0x4737fc MOV 0x8(%R14,%R8,1),%R14 |
(652) 0x473801 MOV %R14,0x178(%RSP) |
(652) 0x473809 CMP %R14,%RDX |
(652) 0x47380c JGE 473988 |
(652) 0x473812 SUB %RDX,%R14 |
(652) 0x473815 AND $0x3,%R14D |
(652) 0x473819 JE 4738c4 |
(652) 0x47381f CMP $0x1,%R14 |
(652) 0x473823 JE 473885 |
(652) 0x473825 CMP $0x2,%R14 |
(652) 0x473829 JE 473857 |
(652) 0x47382b VMOVSD (%RAX),%XMM5 |
(652) 0x47382f MOV (%R13,%RDX,8),%R14 |
(652) 0x473834 VMULSD (%R12,%RDX,8),%XMM5,%XMM6 |
(652) 0x47383a MOV (%R15,%R14,8),%R14 |
(652) 0x47383e INC %RDX |
(652) 0x473841 LEA (%R12,%R14,8),%R14 |
(652) 0x473845 VADDSD (%R14),%XMM6,%XMM7 |
(652) 0x47384a VADDSD %XMM6,%XMM1,%XMM1 |
(652) 0x47384e VADDSD %XMM6,%XMM0,%XMM0 |
(652) 0x473852 VMOVSD %XMM7,(%R14) |
(652) 0x473857 VMOVSD (%RAX),%XMM8 |
(652) 0x47385b MOV (%R13,%RDX,8),%R14 |
(652) 0x473860 VMULSD (%R12,%RDX,8),%XMM8,%XMM9 |
(652) 0x473866 MOV (%R15,%R14,8),%R14 |
(652) 0x47386a INC %RDX |
(652) 0x47386d LEA (%R12,%R14,8),%R14 |
(652) 0x473871 VADDSD (%R14),%XMM9,%XMM10 |
(652) 0x473876 VADDSD %XMM9,%XMM1,%XMM1 |
(652) 0x47387b VADDSD %XMM9,%XMM0,%XMM0 |
(652) 0x473880 VMOVSD %XMM10,(%R14) |
(652) 0x473885 VMOVSD (%RAX),%XMM11 |
(652) 0x473889 MOV (%R13,%RDX,8),%R14 |
(652) 0x47388e VMULSD (%R12,%RDX,8),%XMM11,%XMM12 |
(652) 0x473894 MOV (%R15,%R14,8),%R14 |
(652) 0x473898 INC %RDX |
(652) 0x47389b LEA (%R12,%R14,8),%R14 |
(652) 0x47389f VADDSD (%R14),%XMM12,%XMM13 |
(652) 0x4738a4 VADDSD %XMM12,%XMM1,%XMM1 |
(652) 0x4738a9 VADDSD %XMM12,%XMM0,%XMM0 |
(652) 0x4738ae VMOVSD %XMM13,(%R14) |
(652) 0x4738b3 MOV 0x178(%RSP),%R14 |
(652) 0x4738bb CMP %R14,%RDX |
(652) 0x4738be JE 473988 |
(654) 0x4738c4 VMOVSD (%RAX),%XMM14 |
(654) 0x4738c8 MOV (%R13,%RDX,8),%R14 |
(654) 0x4738cd VMULSD (%R12,%RDX,8),%XMM14,%XMM15 |
(654) 0x4738d3 MOV (%R15,%R14,8),%R14 |
(654) 0x4738d7 LEA (%R12,%R14,8),%R14 |
(654) 0x4738db VADDSD (%R14),%XMM15,%XMM2 |
(654) 0x4738e0 VADDSD %XMM15,%XMM1,%XMM6 |
(654) 0x4738e5 VADDSD %XMM15,%XMM0,%XMM7 |
(654) 0x4738ea VMOVSD %XMM2,(%R14) |
(654) 0x4738ef MOV 0x8(%R13,%RDX,8),%R14 |
(654) 0x4738f4 VMOVSD (%RAX),%XMM5 |
(654) 0x4738f8 MOV (%R15,%R14,8),%R14 |
(654) 0x4738fc VMULSD 0x8(%R12,%RDX,8),%XMM5,%XMM8 |
(654) 0x473903 LEA (%R12,%R14,8),%R14 |
(654) 0x473907 VADDSD (%R14),%XMM8,%XMM9 |
(654) 0x47390c VADDSD %XMM8,%XMM6,%XMM10 |
(654) 0x473911 VADDSD %XMM8,%XMM7,%XMM11 |
(654) 0x473916 VMOVSD %XMM9,(%R14) |
(654) 0x47391b MOV 0x10(%R13,%RDX,8),%R14 |
(654) 0x473920 VMOVSD (%RAX),%XMM12 |
(654) 0x473924 MOV (%R15,%R14,8),%R14 |
(654) 0x473928 VMULSD 0x10(%R12,%RDX,8),%XMM12,%XMM13 |
(654) 0x47392f LEA (%R12,%R14,8),%R14 |
(654) 0x473933 VADDSD (%R14),%XMM13,%XMM1 |
(654) 0x473938 VADDSD %XMM13,%XMM10,%XMM14 |
(654) 0x47393d VADDSD %XMM13,%XMM11,%XMM0 |
(654) 0x473942 VMOVSD %XMM1,(%R14) |
(654) 0x473947 MOV 0x18(%R13,%RDX,8),%R14 |
(654) 0x47394c VMOVSD (%RAX),%XMM15 |
(654) 0x473950 MOV (%R15,%R14,8),%R14 |
(654) 0x473954 VMULSD 0x18(%R12,%RDX,8),%XMM15,%XMM12 |
(654) 0x47395b ADD $0x4,%RDX |
(654) 0x47395f LEA (%R12,%R14,8),%R14 |
(654) 0x473963 VADDSD (%R14),%XMM12,%XMM2 |
(654) 0x473968 VADDSD %XMM12,%XMM14,%XMM1 |
(654) 0x47396d VADDSD %XMM12,%XMM0,%XMM0 |
(654) 0x473972 VMOVSD %XMM2,(%R14) |
(654) 0x473977 MOV 0x178(%RSP),%R14 |
(654) 0x47397f CMP %R14,%RDX |
(654) 0x473982 JNE 4738c4 |
(652) 0x473988 MOV 0xf8(%RSP),%R14 |
(652) 0x473990 MOV (%R14,%RCX,8),%RDX |
(652) 0x473994 MOV 0x8(%R14,%R8,1),%R8 |
(652) 0x473999 CMP %R8,%RDX |
(652) 0x47399c JGE 47363a |
(652) 0x4739a2 MOV %R8,%RCX |
(652) 0x4739a5 SUB %RDX,%RCX |
(652) 0x4739a8 AND $0x3,%ECX |
(652) 0x4739ab JE 473a49 |
(652) 0x4739b1 CMP $0x1,%RCX |
(652) 0x4739b5 JE 473a13 |
(652) 0x4739b7 CMP $0x2,%RCX |
(652) 0x4739bb JE 4739e8 |
(652) 0x4739bd VMOVSD (%RAX),%XMM6 |
(652) 0x4739c1 MOV (%R10,%RDX,8),%R14 |
(652) 0x4739c5 VMULSD (%R11,%RDX,8),%XMM6,%XMM7 |
(652) 0x4739cb MOV (%RBX,%R14,8),%RCX |
(652) 0x4739cf INC %RDX |
(652) 0x4739d2 LEA (%R11,%RCX,8),%R14 |
(652) 0x4739d6 VADDSD (%R14),%XMM7,%XMM5 |
(652) 0x4739db VADDSD %XMM7,%XMM1,%XMM1 |
(652) 0x4739df VADDSD %XMM7,%XMM0,%XMM0 |
(652) 0x4739e3 VMOVSD %XMM5,(%R14) |
(652) 0x4739e8 VMOVSD (%RAX),%XMM8 |
(652) 0x4739ec MOV (%R10,%RDX,8),%RCX |
(652) 0x4739f0 VMULSD (%R11,%RDX,8),%XMM8,%XMM9 |
(652) 0x4739f6 MOV (%RBX,%RCX,8),%R14 |
(652) 0x4739fa INC %RDX |
(652) 0x4739fd LEA (%R11,%R14,8),%RCX |
(652) 0x473a01 VADDSD (%RCX),%XMM9,%XMM10 |
(652) 0x473a05 VADDSD %XMM9,%XMM1,%XMM1 |
(652) 0x473a0a VADDSD %XMM9,%XMM0,%XMM0 |
(652) 0x473a0f VMOVSD %XMM10,(%RCX) |
(652) 0x473a13 VMOVSD (%RAX),%XMM11 |
(652) 0x473a17 MOV (%R10,%RDX,8),%R14 |
(652) 0x473a1b VMULSD (%R11,%RDX,8),%XMM11,%XMM12 |
(652) 0x473a21 MOV (%RBX,%R14,8),%RCX |
(652) 0x473a25 INC %RDX |
(652) 0x473a28 LEA (%R11,%RCX,8),%R14 |
(652) 0x473a2c VADDSD (%R14),%XMM12,%XMM13 |
(652) 0x473a31 VADDSD %XMM12,%XMM1,%XMM1 |
(652) 0x473a36 VADDSD %XMM12,%XMM0,%XMM0 |
(652) 0x473a3b VMOVSD %XMM13,(%R14) |
(652) 0x473a40 CMP %R8,%RDX |
(652) 0x473a43 JE 47363a |
(653) 0x473a49 VMOVSD (%RAX),%XMM12 |
(653) 0x473a4d MOV (%R10,%RDX,8),%RCX |
(653) 0x473a51 VMULSD (%R11,%RDX,8),%XMM12,%XMM14 |
(653) 0x473a57 MOV (%RBX,%RCX,8),%R14 |
(653) 0x473a5b LEA (%R11,%R14,8),%RCX |
(653) 0x473a5f MOV 0x8(%R10,%RDX,8),%R14 |
(653) 0x473a64 VADDSD (%RCX),%XMM14,%XMM15 |
(653) 0x473a68 VADDSD %XMM14,%XMM1,%XMM1 |
(653) 0x473a6d VADDSD %XMM14,%XMM0,%XMM0 |
(653) 0x473a72 VMOVSD %XMM15,(%RCX) |
(653) 0x473a76 MOV (%RBX,%R14,8),%RCX |
(653) 0x473a7a VMOVSD (%RAX),%XMM2 |
(653) 0x473a7e LEA (%R11,%RCX,8),%R14 |
(653) 0x473a82 MOV 0x10(%R10,%RDX,8),%RCX |
(653) 0x473a87 VMULSD 0x8(%R11,%RDX,8),%XMM2,%XMM6 |
(653) 0x473a8e VADDSD (%R14),%XMM6,%XMM7 |
(653) 0x473a93 VADDSD %XMM6,%XMM1,%XMM8 |
(653) 0x473a97 VADDSD %XMM6,%XMM0,%XMM9 |
(653) 0x473a9b VMOVSD %XMM7,(%R14) |
(653) 0x473aa0 MOV (%RBX,%RCX,8),%R14 |
(653) 0x473aa4 VMOVSD (%RAX),%XMM5 |
(653) 0x473aa8 LEA (%R11,%R14,8),%RCX |
(653) 0x473aac MOV 0x18(%R10,%RDX,8),%R14 |
(653) 0x473ab1 VMULSD 0x10(%R11,%RDX,8),%XMM5,%XMM10 |
(653) 0x473ab8 VADDSD (%RCX),%XMM10,%XMM11 |
(653) 0x473abc VADDSD %XMM10,%XMM8,%XMM13 |
(653) 0x473ac1 VADDSD %XMM10,%XMM9,%XMM14 |
(653) 0x473ac6 VMOVSD %XMM11,(%RCX) |
(653) 0x473aca MOV (%RBX,%R14,8),%RCX |
(653) 0x473ace VMOVSD (%RAX),%XMM12 |
(653) 0x473ad2 LEA (%R11,%RCX,8),%R14 |
(653) 0x473ad6 VMULSD 0x18(%R11,%RDX,8),%XMM12,%XMM12 |
(653) 0x473add ADD $0x4,%RDX |
(653) 0x473ae1 VADDSD (%R14),%XMM12,%XMM15 |
(653) 0x473ae6 VADDSD %XMM12,%XMM13,%XMM1 |
(653) 0x473aeb VADDSD %XMM12,%XMM14,%XMM0 |
(653) 0x473af0 VMOVSD %XMM15,(%R14) |
(653) 0x473af5 CMP %R8,%RDX |
(653) 0x473af8 JNE 473a49 |
(652) 0x473afe JMP 47363a |
0x473b03 NOPL (%RAX,%RAX,1) |
(647) 0x473b08 MOV 0xc0(%RSP),%R10 |
(647) 0x473b10 MOV 0xb8(%RSP),%R13 |
(647) 0x473b18 MOV %RAX,%R8 |
(647) 0x473b1b MOV 0xb0(%RSP),%R14 |
(647) 0x473b23 MOV 0xe8(%RSP),%RDI |
(647) 0x473b2b VMULSD (%RDI,%R8,8),%XMM1,%XMM9 |
(647) 0x473b31 VCOMISD %XMM3,%XMM9 |
(647) 0x473b35 JE 473b40 |
(647) 0x473b37 VXORPD %XMM4,%XMM0,%XMM10 |
(647) 0x473b3b VDIVSD %XMM9,%XMM10,%XMM12 |
(647) 0x473b40 MOV 0xd8(%RSP),%R8 |
(647) 0x473b48 MOV 0xe0(%RSP),%R9 |
(647) 0x473b50 MOV (%R8),%RCX |
(647) 0x473b53 MOV (%R9),%RDI |
(647) 0x473b56 CMP %RDI,%RCX |
(647) 0x473b59 JGE 473d41 |
(647) 0x473b5f MOV %RDI,%RSI |
(647) 0x473b62 MOV %RCX,%R8 |
(647) 0x473b65 SUB %RCX,%RSI |
(647) 0x473b68 LEA -0x1(%RSI),%RAX |
(647) 0x473b6c CMP $0x6,%RAX |
(647) 0x473b70 JBE 4742d4 |
(647) 0x473b76 MOV %RSI,%RDX |
(647) 0x473b79 LEA (%R12,%RCX,8),%RAX |
(647) 0x473b7d VBROADCASTSD %XMM12,%ZMM5 |
(647) 0x473b83 SHR $0x3,%RDX |
(647) 0x473b87 SAL $0x6,%RDX |
(647) 0x473b8b LEA (%RDX,%RAX,1),%R9 |
(647) 0x473b8f SUB $0x40,%RDX |
(647) 0x473b93 SHR $0x6,%RDX |
(647) 0x473b97 INC %RDX |
(647) 0x473b9a AND $0x7,%EDX |
(647) 0x473b9d JE 473c47 |
(647) 0x473ba3 CMP $0x1,%RDX |
(647) 0x473ba7 JE 473c31 |
(647) 0x473bad CMP $0x2,%RDX |
(647) 0x473bb1 JE 473c20 |
(647) 0x473bb3 CMP $0x3,%RDX |
(647) 0x473bb7 JE 473c0f |
(647) 0x473bb9 CMP $0x4,%RDX |
(647) 0x473bbd JE 473bfe |
(647) 0x473bbf CMP $0x5,%RDX |
(647) 0x473bc3 JE 473bed |
(647) 0x473bc5 CMP $0x6,%RDX |
(647) 0x473bc9 JE 473bdc |
(647) 0x473bcb VMULPD (%RAX),%ZMM5,%ZMM11 |
(647) 0x473bd1 ADD $0x40,%RAX |
(647) 0x473bd5 VMOVUPD %ZMM11,-0x40(%RAX) |
(647) 0x473bdc VMULPD (%RAX),%ZMM5,%ZMM13 |
(647) 0x473be2 ADD $0x40,%RAX |
(647) 0x473be6 VMOVUPD %ZMM13,-0x40(%RAX) |
(647) 0x473bed VMULPD (%RAX),%ZMM5,%ZMM14 |
(647) 0x473bf3 ADD $0x40,%RAX |
(647) 0x473bf7 VMOVUPD %ZMM14,-0x40(%RAX) |
(647) 0x473bfe VMULPD (%RAX),%ZMM5,%ZMM15 |
(647) 0x473c04 ADD $0x40,%RAX |
(647) 0x473c08 VMOVUPD %ZMM15,-0x40(%RAX) |
(647) 0x473c0f VMULPD (%RAX),%ZMM5,%ZMM2 |
(647) 0x473c15 ADD $0x40,%RAX |
(647) 0x473c19 VMOVUPD %ZMM2,-0x40(%RAX) |
(647) 0x473c20 VMULPD (%RAX),%ZMM5,%ZMM6 |
(647) 0x473c26 ADD $0x40,%RAX |
(647) 0x473c2a VMOVUPD %ZMM6,-0x40(%RAX) |
(647) 0x473c31 VMULPD (%RAX),%ZMM5,%ZMM7 |
(647) 0x473c37 ADD $0x40,%RAX |
(647) 0x473c3b VMOVUPD %ZMM7,-0x40(%RAX) |
(647) 0x473c42 CMP %R9,%RAX |
(647) 0x473c45 JE 473cc1 |
(649) 0x473c47 VMULPD (%RAX),%ZMM5,%ZMM1 |
(649) 0x473c4d ADD $0x200,%RAX |
(649) 0x473c53 VMULPD -0x1c0(%RAX),%ZMM5,%ZMM0 |
(649) 0x473c5a VMULPD -0x180(%RAX),%ZMM5,%ZMM8 |
(649) 0x473c61 VMULPD -0x140(%RAX),%ZMM5,%ZMM9 |
(649) 0x473c68 VMULPD -0x100(%RAX),%ZMM5,%ZMM10 |
(649) 0x473c6f VMULPD -0xc0(%RAX),%ZMM5,%ZMM11 |
(649) 0x473c76 VMOVUPD %ZMM1,-0x200(%RAX) |
(649) 0x473c7d VMULPD -0x80(%RAX),%ZMM5,%ZMM13 |
(649) 0x473c84 VMOVUPD %ZMM0,-0x1c0(%RAX) |
(649) 0x473c8b VMULPD -0x40(%RAX),%ZMM5,%ZMM14 |
(649) 0x473c92 VMOVUPD %ZMM8,-0x180(%RAX) |
(649) 0x473c99 VMOVUPD %ZMM9,-0x140(%RAX) |
(649) 0x473ca0 VMOVUPD %ZMM10,-0x100(%RAX) |
(649) 0x473ca7 VMOVUPD %ZMM11,-0xc0(%RAX) |
(649) 0x473cae VMOVUPD %ZMM13,-0x80(%RAX) |
(649) 0x473cb5 VMOVUPD %ZMM14,-0x40(%RAX) |
(649) 0x473cbc CMP %R9,%RAX |
(649) 0x473cbf JNE 473c47 |
(647) 0x473cc1 MOV %RSI,%R9 |
(647) 0x473cc4 AND $-0x8,%R9 |
(647) 0x473cc8 ADD %R9,%RCX |
(647) 0x473ccb TEST $0x7,%SIL |
(647) 0x473ccf JE 473d41 |
(647) 0x473cd1 SUB %R9,%RSI |
(647) 0x473cd4 LEA -0x1(%RSI),%RAX |
(647) 0x473cd8 CMP $0x2,%RAX |
(647) 0x473cdc JBE 473d01 |
(647) 0x473cde ADD %R8,%R9 |
(647) 0x473ce1 VBROADCASTSD %XMM12,%YMM5 |
(647) 0x473ce6 LEA (%R12,%R9,8),%R8 |
(647) 0x473cea VMULPD (%R8),%YMM5,%YMM15 |
(647) 0x473cef VMOVUPD %YMM15,(%R8) |
(647) 0x473cf4 TEST $0x3,%SIL |
(647) 0x473cf8 JE 473d41 |
(647) 0x473cfa AND $-0x4,%RSI |
(647) 0x473cfe ADD %RSI,%RCX |
(647) 0x473d01 LEA (,%RCX,8),%RSI |
(647) 0x473d09 LEA 0x1(%RCX),%R9 |
(647) 0x473d0d LEA (%R12,%RSI,1),%RDX |
(647) 0x473d11 VMULSD (%RDX),%XMM12,%XMM2 |
(647) 0x473d15 VMOVSD %XMM2,(%RDX) |
(647) 0x473d19 CMP %RDI,%R9 |
(647) 0x473d1c JGE 473d41 |
(647) 0x473d1e LEA 0x8(%R12,%RSI,1),%RAX |
(647) 0x473d23 ADD $0x2,%RCX |
(647) 0x473d27 VMULSD (%RAX),%XMM12,%XMM6 |
(647) 0x473d2b VMOVSD %XMM6,(%RAX) |
(647) 0x473d2f CMP %RCX,%RDI |
(647) 0x473d32 JLE 473d41 |
(647) 0x473d34 LEA 0x10(%R12,%RSI,1),%RCX |
(647) 0x473d39 VMULSD (%RCX),%XMM12,%XMM7 |
(647) 0x473d3d VMOVSD %XMM7,(%RCX) |
(647) 0x473d41 MOV 0xc8(%RSP),%RDI |
(647) 0x473d49 MOV 0xd0(%RSP),%R8 |
(647) 0x473d51 MOV (%RDI),%RCX |
(647) 0x473d54 MOV (%R8),%RDI |
(647) 0x473d57 CMP %RCX,%RDI |
(647) 0x473d5a JLE 473f42 |
(647) 0x473d60 MOV %RDI,%RSI |
(647) 0x473d63 MOV %RCX,%R8 |
(647) 0x473d66 SUB %RCX,%RSI |
(647) 0x473d69 LEA -0x1(%RSI),%RDX |
(647) 0x473d6d CMP $0x6,%RDX |
(647) 0x473d71 JBE 4742cc |
(647) 0x473d77 MOV %RSI,%RDX |
(647) 0x473d7a LEA (%R11,%RCX,8),%RAX |
(647) 0x473d7e VBROADCASTSD %XMM12,%ZMM0 |
(647) 0x473d84 SHR $0x3,%RDX |
(647) 0x473d88 SAL $0x6,%RDX |
(647) 0x473d8c LEA (%RDX,%RAX,1),%R9 |
(647) 0x473d90 SUB $0x40,%RDX |
(647) 0x473d94 SHR $0x6,%RDX |
(647) 0x473d98 INC %RDX |
(647) 0x473d9b AND $0x7,%EDX |
(647) 0x473d9e JE 473e48 |
(647) 0x473da4 CMP $0x1,%RDX |
(647) 0x473da8 JE 473e32 |
(647) 0x473dae CMP $0x2,%RDX |
(647) 0x473db2 JE 473e21 |
(647) 0x473db4 CMP $0x3,%RDX |
(647) 0x473db8 JE 473e10 |
(647) 0x473dba CMP $0x4,%RDX |
(647) 0x473dbe JE 473dff |
(647) 0x473dc0 CMP $0x5,%RDX |
(647) 0x473dc4 JE 473dee |
(647) 0x473dc6 CMP $0x6,%RDX |
(647) 0x473dca JE 473ddd |
(647) 0x473dcc VMULPD (%RAX),%ZMM0,%ZMM1 |
(647) 0x473dd2 ADD $0x40,%RAX |
(647) 0x473dd6 VMOVUPD %ZMM1,-0x40(%RAX) |
(647) 0x473ddd VMULPD (%RAX),%ZMM0,%ZMM8 |
(647) 0x473de3 ADD $0x40,%RAX |
(647) 0x473de7 VMOVUPD %ZMM8,-0x40(%RAX) |
(647) 0x473dee VMULPD (%RAX),%ZMM0,%ZMM9 |
(647) 0x473df4 ADD $0x40,%RAX |
(647) 0x473df8 VMOVUPD %ZMM9,-0x40(%RAX) |
(647) 0x473dff VMULPD (%RAX),%ZMM0,%ZMM10 |
(647) 0x473e05 ADD $0x40,%RAX |
(647) 0x473e09 VMOVUPD %ZMM10,-0x40(%RAX) |
(647) 0x473e10 VMULPD (%RAX),%ZMM0,%ZMM11 |
(647) 0x473e16 ADD $0x40,%RAX |
(647) 0x473e1a VMOVUPD %ZMM11,-0x40(%RAX) |
(647) 0x473e21 VMULPD (%RAX),%ZMM0,%ZMM13 |
(647) 0x473e27 ADD $0x40,%RAX |
(647) 0x473e2b VMOVUPD %ZMM13,-0x40(%RAX) |
(647) 0x473e32 VMULPD (%RAX),%ZMM0,%ZMM14 |
(647) 0x473e38 ADD $0x40,%RAX |
(647) 0x473e3c VMOVUPD %ZMM14,-0x40(%RAX) |
(647) 0x473e43 CMP %RAX,%R9 |
(647) 0x473e46 JE 473ec2 |
(648) 0x473e48 VMULPD (%RAX),%ZMM0,%ZMM5 |
(648) 0x473e4e ADD $0x200,%RAX |
(648) 0x473e54 VMULPD -0x1c0(%RAX),%ZMM0,%ZMM15 |
(648) 0x473e5b VMULPD -0x180(%RAX),%ZMM0,%ZMM2 |
(648) 0x473e62 VMULPD -0x140(%RAX),%ZMM0,%ZMM6 |
(648) 0x473e69 VMULPD -0x100(%RAX),%ZMM0,%ZMM7 |
(648) 0x473e70 VMULPD -0xc0(%RAX),%ZMM0,%ZMM1 |
(648) 0x473e77 VMOVUPD %ZMM5,-0x200(%RAX) |
(648) 0x473e7e VMULPD -0x80(%RAX),%ZMM0,%ZMM8 |
(648) 0x473e85 VMOVUPD %ZMM15,-0x1c0(%RAX) |
(648) 0x473e8c VMULPD -0x40(%RAX),%ZMM0,%ZMM9 |
(648) 0x473e93 VMOVUPD %ZMM2,-0x180(%RAX) |
(648) 0x473e9a VMOVUPD %ZMM6,-0x140(%RAX) |
(648) 0x473ea1 VMOVUPD %ZMM7,-0x100(%RAX) |
(648) 0x473ea8 VMOVUPD %ZMM1,-0xc0(%RAX) |
(648) 0x473eaf VMOVUPD %ZMM8,-0x80(%RAX) |
(648) 0x473eb6 VMOVUPD %ZMM9,-0x40(%RAX) |
(648) 0x473ebd CMP %RAX,%R9 |
(648) 0x473ec0 JNE 473e48 |
(647) 0x473ec2 MOV %RSI,%R9 |
(647) 0x473ec5 AND $-0x8,%R9 |
(647) 0x473ec9 ADD %R9,%RCX |
(647) 0x473ecc TEST $0x7,%SIL |
(647) 0x473ed0 JE 473f42 |
(647) 0x473ed2 SUB %R9,%RSI |
(647) 0x473ed5 LEA -0x1(%RSI),%RAX |
(647) 0x473ed9 CMP $0x2,%RAX |
(647) 0x473edd JBE 473f02 |
(647) 0x473edf ADD %R8,%R9 |
(647) 0x473ee2 VBROADCASTSD %XMM12,%YMM0 |
(647) 0x473ee7 LEA (%R11,%R9,8),%R8 |
(647) 0x473eeb VMULPD (%R8),%YMM0,%YMM10 |
(647) 0x473ef0 VMOVUPD %YMM10,(%R8) |
(647) 0x473ef5 TEST $0x3,%SIL |
(647) 0x473ef9 JE 473f42 |
(647) 0x473efb AND $-0x4,%RSI |
(647) 0x473eff ADD %RSI,%RCX |
(647) 0x473f02 LEA (,%RCX,8),%RSI |
(647) 0x473f0a LEA 0x1(%RCX),%R9 |
(647) 0x473f0e LEA (%R11,%RSI,1),%RDX |
(647) 0x473f12 VMULSD (%RDX),%XMM12,%XMM11 |
(647) 0x473f16 VMOVSD %XMM11,(%RDX) |
(647) 0x473f1a CMP %R9,%RDI |
(647) 0x473f1d JLE 473f42 |
(647) 0x473f1f LEA 0x8(%R11,%RSI,1),%RAX |
(647) 0x473f24 ADD $0x2,%RCX |
(647) 0x473f28 VMULSD (%RAX),%XMM12,%XMM13 |
(647) 0x473f2c VMOVSD %XMM13,(%RAX) |
(647) 0x473f30 CMP %RCX,%RDI |
(647) 0x473f33 JLE 473f42 |
(647) 0x473f35 LEA 0x10(%R11,%RSI,1),%RCX |
(647) 0x473f3a VMULSD (%RCX),%XMM12,%XMM14 |
(647) 0x473f3e VMOVSD %XMM14,(%RCX) |
(647) 0x473f42 ADDQ $0x8,0x110(%RSP) |
(647) 0x473f4b MOV 0x70(%RSP),%RDI |
(647) 0x473f50 MOV 0x110(%RSP),%R8 |
(647) 0x473f58 CMP %RDI,%R8 |
(647) 0x473f5b JNE 473078 |
0x473f61 MOV 0x130(%RSP),%R15 |
0x473f69 VZEROUPPER |
0x473f6c MOV 0x170(%RSP),%RDI |
0x473f74 CALL 5b0b60 <hypre_Free> |
0x473f79 MOV 0x138(%RSP),%RDI |
0x473f81 CALL 5b0b60 <hypre_Free> |
0x473f86 MOV %R15,%RDI |
0x473f89 CALL 5b0b60 <hypre_Free> |
0x473f8e LEA -0x28(%RBP),%RSP |
0x473f92 MOV %RBX,%RDI |
0x473f95 POP %RBX |
0x473f96 POP %R12 |
0x473f98 POP %R13 |
0x473f9a POP %R14 |
0x473f9c POP %R15 |
0x473f9e POP %RBP |
0x473f9f JMP 5b0b60 |
0x473fa4 NOPL (%RAX) |
(650) 0x473fa8 MOV 0x30(%RSP),%RCX |
(650) 0x473fad MOV 0x38(%RSP),%R10 |
(650) 0x473fb2 MOV (%RCX,%R8,1),%RCX |
(650) 0x473fb6 MOV 0x8(%R10,%R8,1),%R10 |
(650) 0x473fbb ADD %RCX,%R10 |
(650) 0x473fbe CMP %R10,%RCX |
(650) 0x473fc1 JGE 473732 |
(650) 0x473fc7 MOV 0x28(%RSP),%R8 |
(650) 0x473fcc MOV 0x100(%RSP),%R14 |
(650) 0x473fd4 MOV %R10,%R9 |
(650) 0x473fd7 SUB %RCX,%R9 |
(650) 0x473fda MOV (%R8,%R14,1),%R8 |
(650) 0x473fde AND $0x3,%R9D |
(650) 0x473fe2 JE 4740b9 |
(650) 0x473fe8 CMP $0x1,%R9 |
(650) 0x473fec JE 474072 |
(650) 0x473ff2 CMP $0x2,%R9 |
(650) 0x473ff6 JE 474034 |
(650) 0x473ff8 VMOVSD (%RDX),%XMM2 |
(650) 0x473ffc MOV 0xa8(%RSP),%R14 |
(650) 0x474004 MOV (%R8,%RCX,8),%R9 |
(650) 0x474008 VMULSD (%R14,%RCX,8),%XMM2,%XMM6 |
(650) 0x47400e TEST %R9,%R9 |
(650) 0x474011 JS 4742dc |
(650) 0x474017 MOV (%RBX,%R9,8),%R9 |
(650) 0x47401b LEA (%R11,%R9,8),%R14 |
(650) 0x47401f VADDSD (%R14),%XMM6,%XMM7 |
(650) 0x474024 VMOVSD %XMM7,(%R14) |
(650) 0x474029 VADDSD %XMM6,%XMM1,%XMM1 |
(650) 0x47402d VADDSD %XMM6,%XMM0,%XMM0 |
(650) 0x474031 INC %RCX |
(650) 0x474034 VMOVSD (%RDX),%XMM9 |
(650) 0x474038 MOV 0xa8(%RSP),%R14 |
(650) 0x474040 MOV (%R8,%RCX,8),%R9 |
(650) 0x474044 VMULSD (%R14,%RCX,8),%XMM9,%XMM10 |
(650) 0x47404a TEST %R9,%R9 |
(650) 0x47404d JS 474288 |
(650) 0x474053 MOV (%RBX,%R9,8),%R9 |
(650) 0x474057 LEA (%R11,%R9,8),%R14 |
(650) 0x47405b VADDSD (%R14),%XMM10,%XMM5 |
(650) 0x474060 VMOVSD %XMM5,(%R14) |
(650) 0x474065 VADDSD %XMM10,%XMM1,%XMM1 |
(650) 0x47406a VADDSD %XMM10,%XMM0,%XMM0 |
(650) 0x47406f INC %RCX |
(650) 0x474072 VMOVSD (%RDX),%XMM13 |
(650) 0x474076 MOV 0xa8(%RSP),%R14 |
(650) 0x47407e MOV (%R8,%RCX,8),%R9 |
(650) 0x474082 VMULSD (%R14,%RCX,8),%XMM13,%XMM12 |
(650) 0x474088 TEST %R9,%R9 |
(650) 0x47408b JS 474250 |
(650) 0x474091 MOV (%RBX,%R9,8),%R9 |
(650) 0x474095 LEA (%R11,%R9,8),%R14 |
(650) 0x474099 VADDSD (%R14),%XMM12,%XMM14 |
(650) 0x47409e VMOVSD %XMM14,(%R14) |
(650) 0x4740a3 INC %RCX |
(650) 0x4740a6 VADDSD %XMM12,%XMM1,%XMM1 |
(650) 0x4740ab VADDSD %XMM12,%XMM0,%XMM0 |
(650) 0x4740b0 CMP %RCX,%R10 |
(650) 0x4740b3 JE 473732 |
(650) 0x4740b9 MOV %R13,0x20(%RSP) |
(650) 0x4740be MOV 0xa8(%RSP),%R14 |
(650) 0x4740c6 JMP 474167 |
0x4740cb NOPL (%RAX,%RAX,1) |
(651) 0x4740d0 MOV (%RBX,%R9,8),%R13 |
(651) 0x4740d4 LEA (%R11,%R13,8),%R9 |
(651) 0x4740d8 VADDSD (%R9),%XMM9,%XMM10 |
(651) 0x4740dd VMOVSD %XMM10,(%R9) |
(651) 0x4740e2 LEA 0x1(%RCX),%R13 |
(651) 0x4740e6 VMOVSD (%RDX),%XMM14 |
(651) 0x4740ea VADDSD %XMM9,%XMM1,%XMM11 |
(651) 0x4740ef MOV (%R8,%R13,8),%R9 |
(651) 0x4740f3 VADDSD %XMM9,%XMM0,%XMM13 |
(651) 0x4740f8 VMULSD (%R14,%R13,8),%XMM14,%XMM15 |
(651) 0x4740fe TEST %R9,%R9 |
(651) 0x474101 JS 474228 |
(651) 0x474107 MOV (%RBX,%R9,8),%R13 |
(651) 0x47410b LEA (%R11,%R13,8),%R9 |
(651) 0x47410f VADDSD (%R9),%XMM15,%XMM12 |
(651) 0x474114 VMOVSD %XMM12,(%R9) |
(651) 0x474119 LEA 0x2(%RCX),%R13 |
(651) 0x47411d VMOVSD (%RDX),%XMM1 |
(651) 0x474121 VADDSD %XMM15,%XMM11,%XMM6 |
(651) 0x474126 MOV (%R8,%R13,8),%R9 |
(651) 0x47412a VADDSD %XMM15,%XMM13,%XMM7 |
(651) 0x47412f VMULSD (%R14,%R13,8),%XMM1,%XMM12 |
(651) 0x474135 TEST %R9,%R9 |
(651) 0x474138 JS 474200 |
(651) 0x47413e MOV (%RBX,%R9,8),%R13 |
(651) 0x474142 LEA (%R11,%R13,8),%R9 |
(651) 0x474146 VADDSD (%R9),%XMM12,%XMM0 |
(651) 0x47414b VMOVSD %XMM0,(%R9) |
(651) 0x474150 ADD $0x3,%RCX |
(651) 0x474154 VADDSD %XMM12,%XMM6,%XMM1 |
(651) 0x474159 VADDSD %XMM12,%XMM7,%XMM0 |
(651) 0x47415e CMP %RCX,%R10 |
(651) 0x474161 JE 474278 |
(651) 0x474167 VMOVSD (%RDX),%XMM12 |
(651) 0x47416b MOV (%R8,%RCX,8),%R9 |
(651) 0x47416f VMULSD (%R14,%RCX,8),%XMM12,%XMM2 |
(651) 0x474175 TEST %R9,%R9 |
(651) 0x474178 JS 4741d8 |
(651) 0x47417a MOV (%RBX,%R9,8),%R13 |
(651) 0x47417e LEA (%R11,%R13,8),%R9 |
(651) 0x474182 VADDSD (%R9),%XMM2,%XMM6 |
(651) 0x474187 VMOVSD %XMM6,(%R9) |
(651) 0x47418c INC %RCX |
(651) 0x47418f VMOVSD (%RDX),%XMM8 |
(651) 0x474193 VADDSD %XMM2,%XMM1,%XMM1 |
(651) 0x474197 VADDSD %XMM2,%XMM0,%XMM0 |
(651) 0x47419b MOV (%R8,%RCX,8),%R9 |
(651) 0x47419f VMULSD (%R14,%RCX,8),%XMM8,%XMM9 |
(651) 0x4741a5 TEST %R9,%R9 |
(651) 0x4741a8 JNS 4740d0 |
(651) 0x4741ae MOV 0x130(%RSP),%R13 |
(651) 0x4741b6 NOT %R9 |
(651) 0x4741b9 MOV (%R13,%R9,8),%R9 |
(651) 0x4741be LEA (%R12,%R9,8),%R13 |
(651) 0x4741c2 VADDSD (%R13),%XMM9,%XMM5 |
(651) 0x4741c8 VMOVSD %XMM5,(%R13) |
(651) 0x4741ce JMP 4740e2 |
0x4741d3 NOPL (%RAX,%RAX,1) |
(651) 0x4741d8 MOV 0x130(%RSP),%R13 |
(651) 0x4741e0 NOT %R9 |
(651) 0x4741e3 MOV (%R13,%R9,8),%R9 |
(651) 0x4741e8 LEA (%R12,%R9,8),%R13 |
(651) 0x4741ec VADDSD (%R13),%XMM2,%XMM7 |
(651) 0x4741f2 VMOVSD %XMM7,(%R13) |
(651) 0x4741f8 JMP 47418c |
0x4741fa NOPW (%RAX,%RAX,1) |
(651) 0x474200 MOV 0x130(%RSP),%R13 |
(651) 0x474208 NOT %R9 |
(651) 0x47420b MOV (%R13,%R9,8),%R9 |
(651) 0x474210 LEA (%R12,%R9,8),%R13 |
(651) 0x474214 VADDSD (%R13),%XMM12,%XMM8 |
(651) 0x47421a VMOVSD %XMM8,(%R13) |
(651) 0x474220 JMP 474150 |
0x474225 NOPL (%RAX) |
(651) 0x474228 MOV 0x130(%RSP),%R13 |
(651) 0x474230 NOT %R9 |
(651) 0x474233 MOV (%R13,%R9,8),%R9 |
(651) 0x474238 LEA (%R12,%R9,8),%R13 |
(651) 0x47423c VADDSD (%R13),%XMM15,%XMM2 |
(651) 0x474242 VMOVSD %XMM2,(%R13) |
(651) 0x474248 JMP 474119 |
0x47424d NOPL (%RAX) |
(650) 0x474250 MOV 0x130(%RSP),%R14 |
(650) 0x474258 NOT %R9 |
(650) 0x47425b MOV (%R14,%R9,8),%R9 |
(650) 0x47425f LEA (%R12,%R9,8),%R14 |
(650) 0x474263 VADDSD (%R14),%XMM12,%XMM15 |
(650) 0x474268 VMOVSD %XMM15,(%R14) |
(650) 0x47426d JMP 4740a3 |
0x474272 NOPW (%RAX,%RAX,1) |
(650) 0x474278 MOV 0x20(%RSP),%R13 |
(650) 0x47427d JMP 473732 |
0x474282 NOPW (%RAX,%RAX,1) |
(650) 0x474288 MOV 0x130(%RSP),%R14 |
(650) 0x474290 NOT %R9 |
(650) 0x474293 MOV (%R14,%R9,8),%R9 |
(650) 0x474297 LEA (%R12,%R9,8),%R14 |
(650) 0x47429b VADDSD (%R14),%XMM10,%XMM11 |
(650) 0x4742a0 VMOVSD %XMM11,(%R14) |
(650) 0x4742a5 JMP 474065 |
(647) 0x4742aa MOV %RBX,0x178(%RSP) |
(647) 0x4742b2 MOV 0x130(%RSP),%R8 |
(647) 0x4742ba JMP 47322c |
(647) 0x4742bf VXORPD %XMM0,%XMM0,%XMM0 |
(647) 0x4742c3 VMOVSD %XMM0,%XMM0,%XMM1 |
(647) 0x4742c7 JMP 4736a7 |
(647) 0x4742cc XOR %R9D,%R9D |
(647) 0x4742cf JMP 473ed2 |
(647) 0x4742d4 XOR %R9D,%R9D |
(647) 0x4742d7 JMP 473cd1 |
(650) 0x4742dc MOV 0x130(%RSP),%R14 |
(650) 0x4742e4 NOT %R9 |
(650) 0x4742e7 MOV (%R14,%R9,8),%R9 |
(650) 0x4742eb LEA (%R12,%R9,8),%R14 |
(650) 0x4742ef VADDSD (%R14),%XMM6,%XMM8 |
(650) 0x4742f4 VMOVSD %XMM8,(%R14) |
(650) 0x4742f9 JMP 474029 |
0x4742fe MOV %R11,0xd8(%RSP) |
0x474306 MOV $0x8,%ESI |
0x47430b MOV %RDX,%RDI |
0x47430e MOV %R10,0xe0(%RSP) |
0x474316 VMOVSD %XMM2,0x100(%RSP) |
0x47431f JMP 472ebf |
0x474324 MOV $0x8,%ESI |
0x474329 MOV %RCX,%RDI |
0x47432c MOV %R11,0xb8(%RSP) |
0x474334 MOV %R10,0xc0(%RSP) |
0x47433c MOV %RDX,0xd8(%RSP) |
0x474344 MOV %R8,0xe0(%RSP) |
0x47434c VMOVSD %XMM2,0x100(%RSP) |
0x474355 CALL 5b0aa0 <hypre_CAlloc> |
0x47435a VMOVSD 0x100(%RSP),%XMM2 |
0x474363 MOV 0xe0(%RSP),%R8 |
0x47436b MOV 0xd8(%RSP),%RDX |
0x474373 MOV 0xc0(%RSP),%R10 |
0x47437b MOV %RAX,%R15 |
0x47437e MOV 0xb8(%RSP),%R11 |
0x474386 JMP 472e95 |
0x47438b MOV $0x8,%ESI |
0x474390 MOV %R14,%RDI |
0x474393 MOV %R11,0xb0(%RSP) |
0x47439b MOV %R10,0xb8(%RSP) |
0x4743a3 MOV %RCX,0xc0(%RSP) |
0x4743ab MOV %RDX,0xd8(%RSP) |
0x4743b3 MOV %R8,0xe0(%RSP) |
0x4743bb VMOVSD %XMM2,0x100(%RSP) |
0x4743c4 CALL 5b0aa0 <hypre_CAlloc> |
0x4743c9 VMOVSD 0x100(%RSP),%XMM2 |
0x4743d2 MOV 0xe0(%RSP),%R8 |
0x4743da MOV 0xd8(%RSP),%RDX |
0x4743e2 MOV 0xc0(%RSP),%RCX |
0x4743ea MOV %RAX,0x138(%RSP) |
0x4743f2 MOV 0xb8(%RSP),%R10 |
0x4743fa MOV 0xb0(%RSP),%R11 |
0x474402 JMP 472e89 |
0x474407 MOV %RSI,%RDI |
0x47440a MOV $0x8,%ESI |
0x47440f MOV %R11,0xb8(%RSP) |
0x474417 MOV %R10,0xc0(%RSP) |
0x47441f MOV %RCX,0xd8(%RSP) |
0x474427 MOV %RDX,0xe0(%RSP) |
0x47442f MOV %R8,0x100(%RSP) |
0x474437 VMOVSD %XMM2,0x138(%RSP) |
0x474440 CALL 5b0aa0 <hypre_CAlloc> |
0x474445 VMOVSD 0x138(%RSP),%XMM2 |
0x47444e MOV 0x100(%RSP),%R8 |
0x474456 MOV 0xe0(%RSP),%RDX |
0x47445e MOV 0xd8(%RSP),%RCX |
0x474466 MOV %RAX,0x170(%RSP) |
0x47446e MOV 0xc0(%RSP),%R10 |
0x474476 MOV 0xb8(%RSP),%R11 |
0x47447e JMP 472e74 |
0x474483 NOPW %CS:(%RAX,%RAX,1) |
0x47448e XCHG %AX,%AX |
Path / |
Source file and lines | par_multi_interp.c:1737-1881 |
Module | exec |
nb instructions | 260 |
nb uops | 276 |
loop length | 1581 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 4 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 44 |
micro-operation queue | 46.00 cycles |
front end | 46.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.80 | 6.80 | 31.00 | 31.00 | 45.50 | 6.80 | 6.80 | 45.50 | 45.50 | 45.50 | 6.80 | 31.00 |
cycles | 6.80 | 8.00 | 31.00 | 31.00 | 45.50 | 6.80 | 6.80 | 45.50 | 45.50 | 45.50 | 6.80 | 31.00 |
Cycles executing div or sqrt instructions | 10.00 |
FE+BE cycles | 45.58 |
Stall cycles | 1.42 |
RS full (events) | 6.22 |
Front-end | 46.00 |
Dispatch | 45.50 |
DIV/SQRT | 10.00 |
Overall L1 | 46.00 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 6% |
all | 6% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 1% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 13% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 13% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 12% |
other | 13% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x180,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x148(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x138(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x130(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x128(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x108(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x100(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x168(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xf8(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xf0(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe8(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RDI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x110(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x140(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RBX,0x150(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x130(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x120(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,0x118(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x118(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xd8(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc8(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R15,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x68(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa8(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x98(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RBX,0x110(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x80(%RDI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x60(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,0xd0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x58(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x50(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R15,0x148(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x48(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,0x108(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa0(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R12,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x90(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R13,0xf8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x78(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14,0xf0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x88(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x70(%RDI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RBX,0x140(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x40(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x20(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x120(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,0x160(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x128(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RSI,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 474407 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x17a7> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOVQ $0,0x170(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %R14,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 47438b <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x172b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOVQ $0,0x138(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 474324 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x16c4> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %RDX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 4742fe <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x169e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R11,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R10,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM2,0x100(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b0aa0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
CMPQ $0,0x178(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
VMOVSD 0x100(%RSP),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xe0(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd8(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JLE 472f3b <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x2db> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x178(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x170(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVSD %XMM2,0x100(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SAL $0x3,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %RAX,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4110a0 <memset@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0x100(%RSP),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd8(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %R14,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 472f8c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x32c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x138(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x100(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (,%R14,8),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVSD %XMM2,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4110a0 <memset@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0x178(%RSP),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x100(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM2,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b3bd0 <hypre_GetThreadNum> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 5b3bc0 <hypre_NumActiveThreads> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x130(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x110(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RAX,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x168(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x168(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX,%R8,8),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (,%R8,8),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD 0x178(%RSP),%XMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CQTO | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x100(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
IDIV %R9 | 5 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 10 |
ADD %RCX,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
DEC %R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R11,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xd8(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %RAX,%R10 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %R10,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RCX,%R10,1),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0xe0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R9,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVNE %RAX,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP %RSI,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 473f6c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x130c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xd0(%RSP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVQ 0x146dff(%RIP),%XMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM3,%XMM3,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R14,%RSI,8),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R14,%R8,8),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x130(%RSP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R15,0x130(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x110(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xc8(%RSP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
DEC %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x130(%RSP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
MOV 0x170(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CALL 5b0b60 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x138(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CALL 5b0b60 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %R15,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 5b0b60 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
JMP 5b0b60 <hypre_Free> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R11,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R10,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM2,0x100(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 472ebf <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x25f> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R11,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM2,0x100(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b0aa0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0x100(%RSP),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd8(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xb8(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 472e95 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x235> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R11,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM2,0x100(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b0aa0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0x100(%RSP),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd8(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x138(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xb8(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 472e89 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x229> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV %RSI,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R11,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0x100(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM2,0x138(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b0aa0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0x138(%RSP),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x100(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd8(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x170(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xc0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 472e74 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x214> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | par_multi_interp.c:1737-1881 |
Module | exec |
nb instructions | 260 |
nb uops | 276 |
loop length | 1581 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 4 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 44 |
micro-operation queue | 46.00 cycles |
front end | 46.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.80 | 6.80 | 31.00 | 31.00 | 45.50 | 6.80 | 6.80 | 45.50 | 45.50 | 45.50 | 6.80 | 31.00 |
cycles | 6.80 | 8.00 | 31.00 | 31.00 | 45.50 | 6.80 | 6.80 | 45.50 | 45.50 | 45.50 | 6.80 | 31.00 |
Cycles executing div or sqrt instructions | 10.00 |
FE+BE cycles | 45.58 |
Stall cycles | 1.42 |
RS full (events) | 6.22 |
Front-end | 46.00 |
Dispatch | 45.50 |
DIV/SQRT | 10.00 |
Overall L1 | 46.00 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 6% |
all | 6% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 1% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 13% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 13% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 12% |
other | 13% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x180,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x148(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x138(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x130(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x128(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x108(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x100(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x168(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xf8(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xf0(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe8(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RDI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x110(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x140(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RBX,0x150(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x130(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x120(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,0x118(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x118(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xd8(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc8(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R15,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x68(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa8(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x98(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RBX,0x110(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x80(%RDI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x60(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,0xd0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x58(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x50(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R15,0x148(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x48(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,0x108(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa0(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R12,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x90(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R13,0xf8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x78(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14,0xf0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x88(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x70(%RDI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RBX,0x140(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x40(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x20(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x120(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,0x160(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x128(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RSI,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 474407 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x17a7> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOVQ $0,0x170(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %R14,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 47438b <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x172b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOVQ $0,0x138(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 474324 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x16c4> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %RDX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 4742fe <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x169e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R11,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R10,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM2,0x100(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b0aa0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
CMPQ $0,0x178(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
VMOVSD 0x100(%RSP),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xe0(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd8(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JLE 472f3b <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x2db> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x178(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x170(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVSD %XMM2,0x100(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SAL $0x3,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %RAX,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4110a0 <memset@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0x100(%RSP),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd8(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %R14,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 472f8c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x32c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x138(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x100(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (,%R14,8),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVSD %XMM2,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4110a0 <memset@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0x178(%RSP),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x100(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM2,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b3bd0 <hypre_GetThreadNum> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 5b3bc0 <hypre_NumActiveThreads> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x130(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x110(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RAX,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x168(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x168(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX,%R8,8),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (,%R8,8),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD 0x178(%RSP),%XMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CQTO | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x100(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
IDIV %R9 | 5 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 10 |
ADD %RCX,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
DEC %R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R11,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xd8(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %RAX,%R10 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %R10,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RCX,%R10,1),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0xe0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R9,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVNE %RAX,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP %RSI,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 473f6c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x130c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xd0(%RSP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVQ 0x146dff(%RIP),%XMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM3,%XMM3,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R14,%RSI,8),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R14,%R8,8),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x130(%RSP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R15,0x130(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x110(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xc8(%RSP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
DEC %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x130(%RSP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
MOV 0x170(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CALL 5b0b60 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x138(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CALL 5b0b60 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %R15,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 5b0b60 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
JMP 5b0b60 <hypre_Free> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R11,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R10,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM2,0x100(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 472ebf <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x25f> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R11,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM2,0x100(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b0aa0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0x100(%RSP),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd8(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xb8(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 472e95 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x235> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R11,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM2,0x100(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b0aa0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0x100(%RSP),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd8(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x138(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xb8(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 472e89 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x229> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV %RSI,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R11,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0x100(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM2,0x138(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b0aa0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0x138(%RSP),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x100(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd8(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x170(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xc0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 472e74 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x214> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼hypre_BoomerAMGBuildMultipass._omp_fn.10– | 1.62 | 0.31 |
▼Loop 647 - par_multi_interp.c:1774-1876 - exec– | 0.22 | 0.03 |
▼Loop 652 - par_multi_interp.c:1811-1837 - exec– | 0.89 | 0.14 |
○Loop 654 - par_multi_interp.c:1816-1822 - exec | 0 | 0 |
○Loop 653 - par_multi_interp.c:1824-1830 - exec | 0 | 0 |
○Loop 656 - par_multi_interp.c:1799-1803 - exec | 0.51 | 0.08 |
▼Loop 650 - par_multi_interp.c:1840-1867 - exec– | 0 | 0 |
○Loop 651 - par_multi_interp.c:1851-1860 - exec | 0 | 0 |
○Loop 657 - par_multi_interp.c:1792-1797 - exec | 0 | 0 |
○Loop 658 - par_multi_interp.c:1782-1787 - exec | 0 | 0 |
○Loop 655 - par_multi_interp.c:1805-1809 - exec | 0 | 0 |
○Loop 648 - par_multi_interp.c:1875-1876 - exec | 0 | 0 |
○Loop 649 - par_multi_interp.c:1873-1874 - exec | 0 | 0 |