Loop Id: 840 | Module: libparcsr_ls.so | Source: par_coarsen.c:2528-2540 | Coverage: 0.08% |
---|
Loop Id: 840 | Module: libparcsr_ls.so | Source: par_coarsen.c:2528-2540 | Coverage: 0.08% |
---|
0x36df0 VPTESTMQ %YMM7,%YMM7,%K1 |
0x36df6 KMOVQ %K1,%K2 |
0x36dfb VSCATTERQPD %YMM0,(%R11,%YMM6,8){%K2} [3] |
0x36e02 VPTESTMQ %YMM5,%YMM5,%K2 |
0x36e08 KMOVQ %K2,%K3 |
0x36e0d VSCATTERQPD %YMM0,(%R11,%YMM4,8){%K3} [5] |
0x36e14 VPSUBQ %YMM1,%YMM2,%YMM4 |
0x36e18 VMOVDQA64 %YMM2,%YMM4{%K1} |
0x36e1e VPSUBQ %YMM1,%YMM3,%YMM5 |
0x36e22 VMOVDQA64 %YMM3,%YMM5{%K2} |
0x36e28 ADD $0x8,%R10 |
0x36e2c VMOVDQA %YMM4,%YMM2 |
0x36e30 VMOVDQA %YMM5,%YMM3 |
0x36e34 CMP %R8,%R10 |
0x36e37 JA 36e7d |
0x36e39 VMOVDQU 0x20(%R9,%R10,8),%YMM4 [1] |
0x36e40 KXNORW %K0,%K0,%K1 |
0x36e44 VPXOR %XMM5,%XMM5,%XMM5 |
0x36e48 VPGATHERQQ (%RCX,%YMM4,8),%YMM5{%K1} [6] |
0x36e4f VMOVDQU (%R9,%R10,8),%YMM6 [1] |
0x36e55 KXNORW %K0,%K0,%K1 |
0x36e59 VPXOR %XMM7,%XMM7,%XMM7 |
0x36e5d VPGATHERQQ (%RCX,%YMM6,8),%YMM7{%K1} [4] |
0x36e64 VPOR %YMM5,%YMM7,%YMM8 |
0x36e68 VPTEST %YMM8,%YMM8 |
0x36e6d JE 36df0 |
0x36e6f MOV (%R13),%R11 [2] |
0x36e73 JMP 36df0 |
/home/eoseret/qaas_runs_CPU_9468/171-147-2675/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c: 2528 - 2540 |
-------------------------------------------------------------------------------- |
2528: for (ig = ig_begin; ig < ig_end; ig++) |
2529: { |
2530: i = graph_array[ig]; |
2531: |
2532: if (CF_marker[i]!=0) /* C or F point */ |
2533: { |
2534: /* the independent set subroutine needs measure 0 for |
2535: removed nodes */ |
2536: measure_array[i] = 0; |
2537: } |
2538: else |
2539: { |
2540: private_graph_size_cnt++; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.09 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 2.76 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.07 |
Bottlenecks | |
Function | hypre_BoomerAMGCoarsenPMIS.extracted |
Source | par_coarsen.c:2528-2540 |
Source loop unroll info | multi-versionned |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 9.67 |
CQA cycles if no scalar integer | 8.83 |
CQA cycles if FP arith vectorized | 9.67 |
CQA cycles if fully vectorized | 3.51 |
Front-end cycles | 9.67 |
DIV/SQRT cycles | 9.00 |
P0 cycles | 6.17 |
P1 cycles | 3.50 |
P2 cycles | 3.50 |
P3 cycles | 4.00 |
P4 cycles | 5.83 |
P5 cycles | 2.40 |
P6 cycles | 4.00 |
P7 cycles | 4.00 |
P8 cycles | 4.00 |
P9 cycles | 2.60 |
P10 cycles | 3.50 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 1 - 2 |
FE+BE cycles (UFS) | 9.23 - 87.32 |
Stall cycles (UFS) | 0.73 - 78.80 |
Nb insns | 27.00 |
Nb uops | 58.00 |
Nb loads | 4.50 |
Nb stores | 2.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 20.27 |
Bytes prefetched | 0.00 |
Bytes loaded | 132.00 |
Bytes stored | 64.00 |
Stride 0 | 0.50 |
Stride 1 | 1.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 4.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 100.00 |
Vector-efficiency ratio all | 47.22 |
Vector-efficiency ratio load | 50.00 |
Vector-efficiency ratio store | 50.00 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 50.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 45.83 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.11 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 2.80 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.09 |
Bottlenecks | micro-operation queue, |
Function | hypre_BoomerAMGCoarsenPMIS.extracted |
Source | par_coarsen.c:2528-2540 |
Source loop unroll info | multi-versionned |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 9.83 |
CQA cycles if no scalar integer | 8.83 |
CQA cycles if FP arith vectorized | 9.83 |
CQA cycles if fully vectorized | 3.51 |
Front-end cycles | 9.83 |
DIV/SQRT cycles | 9.00 |
P0 cycles | 6.17 |
P1 cycles | 3.67 |
P2 cycles | 3.67 |
P3 cycles | 4.00 |
P4 cycles | 5.83 |
P5 cycles | 2.40 |
P6 cycles | 4.00 |
P7 cycles | 4.00 |
P8 cycles | 4.00 |
P9 cycles | 2.60 |
P10 cycles | 3.67 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 1 - 2 |
FE+BE cycles (UFS) | 9.23 - 87.32 |
Stall cycles (UFS) | 0.55 - 78.64 |
Nb insns | 28.00 |
Nb uops | 59.00 |
Nb loads | 5.00 |
Nb stores | 2.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 20.34 |
Bytes prefetched | 0.00 |
Bytes loaded | 136.00 |
Bytes stored | 64.00 |
Stride 0 | 1.00 |
Stride 1 | 1.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 4.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 100.00 |
Vector-efficiency ratio all | 47.22 |
Vector-efficiency ratio load | 50.00 |
Vector-efficiency ratio store | 50.00 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 50.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 45.83 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.08 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 2.71 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.06 |
Bottlenecks | micro-operation queue, |
Function | hypre_BoomerAMGCoarsenPMIS.extracted |
Source | par_coarsen.c:2528-2540 |
Source loop unroll info | multi-versionned |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 9.50 |
CQA cycles if no scalar integer | 8.83 |
CQA cycles if FP arith vectorized | 9.50 |
CQA cycles if fully vectorized | 3.50 |
Front-end cycles | 9.50 |
DIV/SQRT cycles | 9.00 |
P0 cycles | 6.17 |
P1 cycles | 3.33 |
P2 cycles | 3.33 |
P3 cycles | 4.00 |
P4 cycles | 5.83 |
P5 cycles | 2.40 |
P6 cycles | 4.00 |
P7 cycles | 4.00 |
P8 cycles | 4.00 |
P9 cycles | 2.60 |
P10 cycles | 3.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 1 - 2 |
FE+BE cycles (UFS) | 9.23 - 87.32 |
Stall cycles (UFS) | 0.91 - 78.97 |
Nb insns | 26.00 |
Nb uops | 57.00 |
Nb loads | 4.00 |
Nb stores | 2.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 20.21 |
Bytes prefetched | 0.00 |
Bytes loaded | 128.00 |
Bytes stored | 64.00 |
Stride 0 | 0.00 |
Stride 1 | 1.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 4.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 100.00 |
Vector-efficiency ratio all | 47.22 |
Vector-efficiency ratio load | 50.00 |
Vector-efficiency ratio store | 50.00 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 50.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 45.83 |
Path / |
Function | hypre_BoomerAMGCoarsenPMIS.extracted |
Source file and lines | par_coarsen.c:2528-2540 |
Module | libparcsr_ls.so |
nb instructions | 27 |
nb uops | 58 |
loop length | 131.50 |
used x86 registers | 5.50 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 9 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 9.67 cycles |
front end | 9.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 9.00 | 6.17 | 3.50 | 3.50 | 4.00 | 5.83 | 2.40 | 4.00 | 4.00 | 4.00 | 2.60 | 3.50 |
cycles | 9.00 | 6.17 | 3.50 | 3.50 | 4.00 | 5.83 | 2.40 | 4.00 | 4.00 | 4.00 | 2.60 | 3.50 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00-2.00 |
FE+BE cycles | 9.23-87.32 |
Stall cycles | 0.73-78.80 |
ROB full (events) | 0.07-79.97 |
RS full (events) | 1.89-0.00 |
Front-end | 9.67 |
Dispatch | 9.00 |
Data deps. | 1.00-2.00 |
Overall L1 | 9.67 |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 100% |
all | 100% |
load | NA (no load vectorizable/vectorized instructions) |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 46% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 45% |
all | 50% |
load | NA (no load vectorizable/vectorized instructions) |
store | 50% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 47% |
load | 50% |
store | 50% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 45% |
Function | hypre_BoomerAMGCoarsenPMIS.extracted |
Source file and lines | par_coarsen.c:2528-2540 |
Module | libparcsr_ls.so |
nb instructions | 28 |
nb uops | 59 |
loop length | 136 |
used x86 registers | 6 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 9 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 9.83 cycles |
front end | 9.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 9.00 | 6.17 | 3.67 | 3.67 | 4.00 | 5.83 | 2.40 | 4.00 | 4.00 | 4.00 | 2.60 | 3.67 |
cycles | 9.00 | 6.17 | 3.67 | 3.67 | 4.00 | 5.83 | 2.40 | 4.00 | 4.00 | 4.00 | 2.60 | 3.67 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00-2.00 |
FE+BE cycles | 9.23-87.32 |
Stall cycles | 0.55-78.64 |
ROB full (events) | 0.15-79.47 |
RS full (events) | 1.23-0.00 |
Front-end | 9.83 |
Dispatch | 9.00 |
Data deps. | 1.00-2.00 |
Overall L1 | 9.83 |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 100% |
all | 100% |
load | NA (no load vectorizable/vectorized instructions) |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 46% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 45% |
all | 50% |
load | NA (no load vectorizable/vectorized instructions) |
store | 50% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 47% |
load | 50% |
store | 50% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 45% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VPTESTMQ %YMM7,%YMM7,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
KMOVQ %K1,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
VSCATTERQPD %YMM0,(%R11,%YMM6,8){%K2} | 12 | 1.70 | 0.70 | 0 | 0 | 2 | 0.20 | 0.20 | 2 | 2 | 2 | 0.20 | 0 | 2-12 | 5 |
VPTESTMQ %YMM5,%YMM5,%K2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
KMOVQ %K2,%K3 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
VSCATTERQPD %YMM0,(%R11,%YMM4,8){%K3} | 12 | 1.70 | 0.70 | 0 | 0 | 2 | 0.20 | 0.20 | 2 | 2 | 2 | 0.20 | 0 | 2-12 | 5 |
VPSUBQ %YMM1,%YMM2,%YMM4 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VMOVDQA64 %YMM2,%YMM4{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VPSUBQ %YMM1,%YMM3,%YMM5 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VMOVDQA64 %YMM3,%YMM5{%K2} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
ADD $0x8,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVDQA %YMM4,%YMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VMOVDQA %YMM5,%YMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
CMP %R8,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JA 36e7d <hypre_BoomerAMGCoarsenPMIS.extracted+0x11d> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVDQU 0x20(%R9,%R10,8),%YMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
KXNORW %K0,%K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VPXOR %XMM5,%XMM5,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPGATHERQQ (%RCX,%YMM4,8),%YMM5{%K1} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VMOVDQU (%R9,%R10,8),%YMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
KXNORW %K0,%K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VPXOR %XMM7,%XMM7,%XMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPGATHERQQ (%RCX,%YMM6,8),%YMM7{%K1} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VPOR %YMM5,%YMM7,%YMM8 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VPTEST %YMM8,%YMM8 | 2 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 6 | 1 |
JE 36df0 <hypre_BoomerAMGCoarsenPMIS.extracted+0x90> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV (%R13),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 36df0 <hypre_BoomerAMGCoarsenPMIS.extracted+0x90> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
Function | hypre_BoomerAMGCoarsenPMIS.extracted |
Source file and lines | par_coarsen.c:2528-2540 |
Module | libparcsr_ls.so |
nb instructions | 26 |
nb uops | 57 |
loop length | 127 |
used x86 registers | 5 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 9 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 9.50 cycles |
front end | 9.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 9.00 | 6.17 | 3.33 | 3.33 | 4.00 | 5.83 | 2.40 | 4.00 | 4.00 | 4.00 | 2.60 | 3.33 |
cycles | 9.00 | 6.17 | 3.33 | 3.33 | 4.00 | 5.83 | 2.40 | 4.00 | 4.00 | 4.00 | 2.60 | 3.33 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00-2.00 |
FE+BE cycles | 9.23-87.32 |
Stall cycles | 0.91-78.97 |
RS full (events) | 2.55-0.00 |
Front-end | 9.50 |
Dispatch | 9.00 |
Data deps. | 1.00-2.00 |
Overall L1 | 9.50 |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 100% |
all | 100% |
load | NA (no load vectorizable/vectorized instructions) |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 46% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 45% |
all | 50% |
load | NA (no load vectorizable/vectorized instructions) |
store | 50% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 47% |
load | 50% |
store | 50% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 45% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VPTESTMQ %YMM7,%YMM7,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
KMOVQ %K1,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
VSCATTERQPD %YMM0,(%R11,%YMM6,8){%K2} | 12 | 1.70 | 0.70 | 0 | 0 | 2 | 0.20 | 0.20 | 2 | 2 | 2 | 0.20 | 0 | 2-12 | 5 |
VPTESTMQ %YMM5,%YMM5,%K2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
KMOVQ %K2,%K3 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
VSCATTERQPD %YMM0,(%R11,%YMM4,8){%K3} | 12 | 1.70 | 0.70 | 0 | 0 | 2 | 0.20 | 0.20 | 2 | 2 | 2 | 0.20 | 0 | 2-12 | 5 |
VPSUBQ %YMM1,%YMM2,%YMM4 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VMOVDQA64 %YMM2,%YMM4{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VPSUBQ %YMM1,%YMM3,%YMM5 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VMOVDQA64 %YMM3,%YMM5{%K2} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
ADD $0x8,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVDQA %YMM4,%YMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VMOVDQA %YMM5,%YMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
CMP %R8,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JA 36e7d <hypre_BoomerAMGCoarsenPMIS.extracted+0x11d> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVDQU 0x20(%R9,%R10,8),%YMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
KXNORW %K0,%K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VPXOR %XMM5,%XMM5,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPGATHERQQ (%RCX,%YMM4,8),%YMM5{%K1} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VMOVDQU (%R9,%R10,8),%YMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
KXNORW %K0,%K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VPXOR %XMM7,%XMM7,%XMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPGATHERQQ (%RCX,%YMM6,8),%YMM7{%K1} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VPOR %YMM5,%YMM7,%YMM8 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VPTEST %YMM8,%YMM8 | 2 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 6 | 1 |
JE 36df0 <hypre_BoomerAMGCoarsenPMIS.extracted+0x90> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |