Function: hypre_BoomerAMGBuildExtPIInterp._omp_fn.0 | Module: exec | Source: par_lr_interp.c:1196-1757 [...] | Coverage: 0.25% |
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Function: hypre_BoomerAMGBuildExtPIInterp._omp_fn.0 | Module: exec | Source: par_lr_interp.c:1196-1757 [...] | Coverage: 0.25% |
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/home/eoseret/qaas_runs_CPU_9468/171-147-2675/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c: 1196 - 1757 |
-------------------------------------------------------------------------------- |
1196: #pragma omp parallel private(i,my_thread_num,num_threads,start,stop,coarse_counter,jj_counter,jj_counter_offd, P_marker, P_marker_offd,jj,kk,i1,k1,loc_col,jj_begin_row,jj_begin_row_offd,jj_end_row,jj_end_row_offd,diagonal,sum,sgn,jj1,i2,distribute,strong_f_marker) |
[...] |
1217: strong_f_marker = -2; |
1218: coarse_counter = 0; |
1219: jj_counter = start_indexing; |
1220: jj_counter_offd = start_indexing; |
1221: if (n_fine) |
1222: { |
1223: P_marker = hypre_CTAlloc(HYPRE_Int, n_fine); |
1224: for (i = 0; i < n_fine; i++) |
1225: { P_marker[i] = -1; } |
1226: } |
1227: if (full_off_procNodes) |
1228: { |
1229: P_marker_offd = hypre_CTAlloc(HYPRE_Int, full_off_procNodes); |
1230: for (i = 0; i < full_off_procNodes; i++) |
1231: { P_marker_offd[i] = -1;} |
1232: } |
1233: |
1234: /* this thread's row range */ |
1235: my_thread_num = hypre_GetThreadNum(); |
1236: num_threads = hypre_NumActiveThreads(); |
1237: start = (n_fine/num_threads)*my_thread_num; |
1238: if (my_thread_num == num_threads-1) |
1239: { stop = n_fine; } |
1240: else |
1241: { stop = (n_fine/num_threads)*(my_thread_num+1); } |
1242: |
1243: /* loop over rows */ |
1244: for (i = start; i < stop; i++) |
1245: { |
1246: P_diag_i[i] = jj_counter; |
1247: if (num_procs > 1) |
1248: P_offd_i[i] = jj_counter_offd; |
1249: |
1250: if (CF_marker[i] >= 0) |
1251: { |
1252: jj_counter++; |
1253: fine_to_coarse[i] = coarse_counter; |
1254: coarse_counter++; |
[...] |
1262: else if (CF_marker[i] != -3) |
1263: { |
1264: for (jj = S_diag_i[i]; jj < S_diag_i[i+1]; jj++) |
1265: { |
1266: i1 = S_diag_j[jj]; |
1267: if (CF_marker[i1] >= 0) |
1268: { /* i1 is a C point */ |
1269: if (P_marker[i1] < P_diag_i[i]) |
1270: { |
1271: P_marker[i1] = jj_counter; |
1272: jj_counter++; |
1273: } |
1274: } |
1275: else if (CF_marker[i1] != -3) |
1276: { /* i1 is a F point, loop through it's strong neighbors */ |
1277: for (kk = S_diag_i[i1]; kk < S_diag_i[i1+1]; kk++) |
1278: { |
1279: k1 = S_diag_j[kk]; |
1280: if (CF_marker[k1] >= 0) |
1281: { |
1282: if(P_marker[k1] < P_diag_i[i]) |
1283: { |
1284: P_marker[k1] = jj_counter; |
1285: jj_counter++; |
1286: } |
1287: } |
1288: } |
1289: if(num_procs > 1) |
1290: { |
1291: for (kk = S_offd_i[i1]; kk < S_offd_i[i1+1]; kk++) |
1292: { |
1293: if(col_offd_S_to_A) |
1294: k1 = col_offd_S_to_A[S_offd_j[kk]]; |
1295: else |
1296: k1 = S_offd_j[kk]; |
1297: if (CF_marker_offd[k1] >= 0) |
1298: { |
1299: if(P_marker_offd[k1] < P_offd_i[i]) |
1300: { |
1301: tmp_CF_marker_offd[k1] = 1; |
1302: P_marker_offd[k1] = jj_counter_offd; |
1303: jj_counter_offd++; |
[...] |
1311: if (num_procs > 1) |
1312: { |
1313: for (jj = S_offd_i[i]; jj < S_offd_i[i+1]; jj++) |
1314: { |
1315: i1 = S_offd_j[jj]; |
1316: if(col_offd_S_to_A) |
1317: i1 = col_offd_S_to_A[i1]; |
1318: if (CF_marker_offd[i1] >= 0) |
1319: { |
1320: if(P_marker_offd[i1] < P_offd_i[i]) |
1321: { |
1322: tmp_CF_marker_offd[i1] = 1; |
1323: P_marker_offd[i1] = jj_counter_offd; |
1324: jj_counter_offd++; |
1325: } |
1326: } |
1327: else if (CF_marker_offd[i1] != -3) |
1328: { /* F point; look at neighbors of i1. Sop contains global col |
1329: * numbers and entries that could be in S_diag or S_offd or |
1330: * neither. */ |
1331: for(kk = Sop_i[i1]; kk < Sop_i[i1+1]; kk++) |
1332: { |
1333: k1 = Sop_j[kk]; |
1334: if(k1 >= col_1 && k1 < col_n) |
1335: { /* In S_diag */ |
1336: loc_col = k1-col_1; |
1337: if(P_marker[loc_col] < P_diag_i[i]) |
1338: { |
1339: P_marker[loc_col] = jj_counter; |
1340: jj_counter++; |
1341: } |
1342: } |
1343: else |
1344: { |
1345: loc_col = -k1 - 1; |
1346: if(P_marker_offd[loc_col] < P_offd_i[i]) |
1347: { |
1348: P_marker_offd[loc_col] = jj_counter_offd; |
1349: tmp_CF_marker_offd[loc_col] = 1; |
1350: jj_counter_offd++; |
[...] |
1363: #pragma omp barrier |
1364: #endif |
1365: P_diag_i[stop] = jj_counter; |
1366: P_offd_i[stop] = jj_counter_offd; |
1367: fine_to_coarse_offset[my_thread_num] = coarse_counter; |
1368: diag_offset[my_thread_num] = jj_counter; |
1369: offd_offset[my_thread_num] = jj_counter_offd; |
1370: |
1371: /* Stitch P_diag_i, P_offd_i and fine_to_coarse together */ |
1372: #ifdef HYPRE_USING_OPENMP |
1373: #pragma omp barrier |
1374: #endif |
1375: if(my_thread_num == 0) |
1376: { |
1377: /* Calculate the offset for P_diag_i and P_offd_i for each thread */ |
1378: for (i = 1; i < num_threads; i++) |
1379: { |
1380: diag_offset[i] = diag_offset[i-1] + diag_offset[i]; |
1381: fine_to_coarse_offset[i] = fine_to_coarse_offset[i-1] + fine_to_coarse_offset[i]; |
1382: offd_offset[i] = offd_offset[i-1] + offd_offset[i]; |
1383: } |
1384: } |
1385: #ifdef HYPRE_USING_OPENMP |
1386: #pragma omp barrier |
1387: #endif |
1388: |
1389: if(my_thread_num > 0) |
1390: { |
1391: /* update row pointer array with offset, |
1392: * making sure to update the row stop index */ |
1393: for (i = start+1; i <= stop; i++) |
1394: { |
1395: P_diag_i[i] += diag_offset[my_thread_num-1]; |
1396: P_offd_i[i] += offd_offset[my_thread_num-1]; |
1397: } |
1398: /* update fine_to_coarse by offsetting with the offset |
1399: * from the preceding thread */ |
1400: for (i = start; i < stop; i++) |
1401: { |
1402: if(fine_to_coarse[i] >= 0) |
1403: { fine_to_coarse[i] += fine_to_coarse_offset[my_thread_num-1]; } |
1404: } |
1405: } |
1406: #ifdef HYPRE_USING_OPENMP |
1407: #pragma omp barrier |
1408: #endif |
1409: |
1410: if(my_thread_num == 0) |
1411: { |
1412: if (debug_flag==4) |
1413: { |
1414: wall_time = time_getWallclockSeconds() - wall_time; |
1415: hypre_printf("Proc = %d determine structure %f\n", |
1416: my_id, wall_time); |
1417: fflush(NULL); |
[...] |
1423: if (debug_flag== 4) wall_time = time_getWallclockSeconds(); |
1424: |
1425: P_diag_size = P_diag_i[n_fine]; |
1426: P_offd_size = P_offd_i[n_fine]; |
1427: |
1428: if (P_diag_size) |
1429: { |
1430: P_diag_j = hypre_CTAlloc(HYPRE_Int, P_diag_size); |
1431: P_diag_data = hypre_CTAlloc(HYPRE_Real, P_diag_size); |
1432: } |
1433: |
1434: if (P_offd_size) |
1435: { |
1436: P_offd_j = hypre_CTAlloc(HYPRE_Int, P_offd_size); |
1437: P_offd_data = hypre_CTAlloc(HYPRE_Real, P_offd_size); |
1438: } |
1439: } |
1440: |
1441: /* Fine to coarse mapping */ |
1442: if(num_procs > 1 && my_thread_num == 0) |
1443: { |
1444: for (i = 0; i < n_fine; i++) |
1445: fine_to_coarse[i] += my_first_cpt; |
1446: |
1447: hypre_alt_insert_new_nodes(comm_pkg, extend_comm_pkg, fine_to_coarse, |
1448: full_off_procNodes, |
1449: fine_to_coarse_offd); |
1450: |
1451: for (i = 0; i < n_fine; i++) |
1452: fine_to_coarse[i] -= my_first_cpt; |
1453: } |
1454: |
1455: for (i = 0; i < n_fine; i++) |
1456: P_marker[i] = -1; |
1457: |
1458: for (i = 0; i < full_off_procNodes; i++) |
1459: P_marker_offd[i] = -1; |
[...] |
1467: #pragma omp barrier |
1468: #endif |
1469: for (i = start; i < stop; i++) |
1470: { |
1471: jj_begin_row = P_diag_i[i]; |
1472: jj_begin_row_offd = P_offd_i[i]; |
1473: jj_counter = jj_begin_row; |
1474: jj_counter_offd = jj_begin_row_offd; |
[...] |
1480: if (CF_marker[i] >= 0) |
1481: { |
1482: P_diag_j[jj_counter] = fine_to_coarse[i]; |
1483: P_diag_data[jj_counter] = one; |
[...] |
1491: else if (CF_marker[i] != -3) |
1492: { |
1493: strong_f_marker--; |
1494: for (jj = S_diag_i[i]; jj < S_diag_i[i+1]; jj++) |
[...] |
1503: if (CF_marker[i1] >= 0) |
1504: { |
1505: if (P_marker[i1] < jj_begin_row) |
1506: { |
1507: P_marker[i1] = jj_counter; |
1508: P_diag_j[jj_counter] = fine_to_coarse[i1]; |
1509: P_diag_data[jj_counter] = zero; |
1510: jj_counter++; |
1511: } |
1512: } |
1513: else if (CF_marker[i1] != -3) |
1514: { |
1515: P_marker[i1] = strong_f_marker; |
1516: for (kk = S_diag_i[i1]; kk < S_diag_i[i1+1]; kk++) |
1517: { |
1518: k1 = S_diag_j[kk]; |
1519: if (CF_marker[k1] >= 0) |
1520: { |
1521: if(P_marker[k1] < jj_begin_row) |
1522: { |
1523: P_marker[k1] = jj_counter; |
1524: P_diag_j[jj_counter] = fine_to_coarse[k1]; |
1525: P_diag_data[jj_counter] = zero; |
1526: jj_counter++; |
1527: } |
1528: } |
1529: } |
1530: if(num_procs > 1) |
1531: { |
1532: for (kk = S_offd_i[i1]; kk < S_offd_i[i1+1]; kk++) |
1533: { |
1534: if(col_offd_S_to_A) |
1535: k1 = col_offd_S_to_A[S_offd_j[kk]]; |
1536: else |
1537: k1 = S_offd_j[kk]; |
1538: if(CF_marker_offd[k1] >= 0) |
1539: { |
1540: if(P_marker_offd[k1] < jj_begin_row_offd) |
1541: { |
1542: P_marker_offd[k1] = jj_counter_offd; |
1543: P_offd_j[jj_counter_offd] = k1; |
1544: P_offd_data[jj_counter_offd] = zero; |
1545: jj_counter_offd++; |
[...] |
1553: if ( num_procs > 1) |
1554: { |
1555: for (jj=S_offd_i[i]; jj < S_offd_i[i+1]; jj++) |
1556: { |
1557: i1 = S_offd_j[jj]; |
1558: if(col_offd_S_to_A) |
1559: i1 = col_offd_S_to_A[i1]; |
1560: if ( CF_marker_offd[i1] >= 0) |
1561: { |
1562: if(P_marker_offd[i1] < jj_begin_row_offd) |
1563: { |
1564: P_marker_offd[i1] = jj_counter_offd; |
1565: P_offd_j[jj_counter_offd] = i1; |
1566: P_offd_data[jj_counter_offd] = zero; |
1567: jj_counter_offd++; |
1568: } |
1569: } |
1570: else if (CF_marker_offd[i1] != -3) |
1571: { |
1572: P_marker_offd[i1] = strong_f_marker; |
1573: for(kk = Sop_i[i1]; kk < Sop_i[i1+1]; kk++) |
1574: { |
1575: k1 = Sop_j[kk]; |
1576: /* Find local col number */ |
1577: if(k1 >= col_1 && k1 < col_n) |
1578: { |
1579: loc_col = k1-col_1; |
1580: if(P_marker[loc_col] < jj_begin_row) |
1581: { |
1582: P_marker[loc_col] = jj_counter; |
1583: P_diag_j[jj_counter] = fine_to_coarse[loc_col]; |
1584: P_diag_data[jj_counter] = zero; |
1585: jj_counter++; |
1586: } |
1587: } |
1588: else |
1589: { |
1590: loc_col = -k1 - 1; |
1591: if(P_marker_offd[loc_col] < jj_begin_row_offd) |
1592: { |
1593: P_marker_offd[loc_col] = jj_counter_offd; |
1594: P_offd_j[jj_counter_offd]=loc_col; |
1595: P_offd_data[jj_counter_offd] = zero; |
1596: jj_counter_offd++; |
[...] |
1607: diagonal = A_diag_data[A_diag_i[i]]; |
1608: |
1609: for (jj = A_diag_i[i]+1; jj < A_diag_i[i+1]; jj++) |
1610: { /* i1 is a c-point and strongly influences i, accumulate |
1611: * a_(i,i1) into interpolation weight */ |
1612: i1 = A_diag_j[jj]; |
1613: if (P_marker[i1] >= jj_begin_row) |
1614: { |
1615: P_diag_data[P_marker[i1]] += A_diag_data[jj]; |
1616: } |
1617: else if(P_marker[i1] == strong_f_marker) |
1618: { |
1619: sum = zero; |
1620: sgn = 1; |
1621: if(A_diag_data[A_diag_i[i1]] < 0) sgn = -1; |
1622: /* Loop over row of A for point i1 and calculate the sum |
1623: * of the connections to c-points that strongly influence i. */ |
1624: for(jj1 = A_diag_i[i1]+1; jj1 < A_diag_i[i1+1]; jj1++) |
1625: { |
1626: i2 = A_diag_j[jj1]; |
1627: if((P_marker[i2] >= jj_begin_row || i2 == i) && (sgn*A_diag_data[jj1]) < 0) |
1628: sum += A_diag_data[jj1]; |
1629: } |
1630: if(num_procs > 1) |
1631: { |
1632: for(jj1 = A_offd_i[i1]; jj1< A_offd_i[i1+1]; jj1++) |
1633: { |
1634: i2 = A_offd_j[jj1]; |
1635: if(P_marker_offd[i2] >= jj_begin_row_offd && |
1636: (sgn*A_offd_data[jj1]) < 0) |
1637: sum += A_offd_data[jj1]; |
1638: } |
1639: } |
1640: if(sum != 0) |
1641: { |
1642: distribute = A_diag_data[jj]/sum; |
1643: /* Loop over row of A for point i1 and do the distribution */ |
1644: for(jj1 = A_diag_i[i1]+1; jj1 < A_diag_i[i1+1]; jj1++) |
1645: { |
1646: i2 = A_diag_j[jj1]; |
1647: if(P_marker[i2] >= jj_begin_row && (sgn*A_diag_data[jj1]) < 0) |
1648: P_diag_data[P_marker[i2]] += |
1649: distribute*A_diag_data[jj1]; |
1650: if(i2 == i && (sgn*A_diag_data[jj1]) < 0) |
1651: diagonal += distribute*A_diag_data[jj1]; |
1652: } |
1653: if(num_procs > 1) |
1654: { |
1655: for(jj1 = A_offd_i[i1]; jj1 < A_offd_i[i1+1]; jj1++) |
1656: { |
1657: i2 = A_offd_j[jj1]; |
1658: if(P_marker_offd[i2] >= jj_begin_row_offd && |
1659: (sgn*A_offd_data[jj1]) < 0) |
1660: P_offd_data[P_marker_offd[i2]] += |
[...] |
1667: diagonal += A_diag_data[jj]; |
1668: } |
1669: } |
1670: /* neighbor i1 weakly influences i, accumulate a_(i,i1) into |
1671: * diagonal */ |
1672: else if (CF_marker[i1] != -3) |
1673: { |
1674: if(num_functions == 1 || dof_func[i] == dof_func[i1]) |
1675: diagonal += A_diag_data[jj]; |
1676: } |
1677: } |
1678: if(num_procs > 1) |
1679: { |
1680: for(jj = A_offd_i[i]; jj < A_offd_i[i+1]; jj++) |
1681: { |
1682: i1 = A_offd_j[jj]; |
1683: if(P_marker_offd[i1] >= jj_begin_row_offd) |
1684: P_offd_data[P_marker_offd[i1]] += A_offd_data[jj]; |
1685: else if(P_marker_offd[i1] == strong_f_marker) |
1686: { |
1687: sum = zero; |
1688: for(jj1 = A_ext_i[i1]; jj1 < A_ext_i[i1+1]; jj1++) |
1689: { |
1690: k1 = A_ext_j[jj1]; |
1691: if(k1 >= col_1 && k1 < col_n) |
1692: { /* diag */ |
1693: loc_col = k1 - col_1; |
1694: if(P_marker[loc_col] >= jj_begin_row || loc_col == i) |
1695: sum += A_ext_data[jj1]; |
1696: } |
1697: else |
1698: { |
1699: loc_col = -k1 - 1; |
1700: if(P_marker_offd[loc_col] >= jj_begin_row_offd) |
1701: sum += A_ext_data[jj1]; |
1702: } |
1703: } |
1704: if(sum != 0) |
1705: { |
1706: distribute = A_offd_data[jj] / sum; |
1707: for(jj1 = A_ext_i[i1]; jj1 < A_ext_i[i1+1]; jj1++) |
1708: { |
1709: k1 = A_ext_j[jj1]; |
1710: if(k1 >= col_1 && k1 < col_n) |
1711: { /* diag */ |
1712: loc_col = k1 - col_1; |
1713: if(P_marker[loc_col] >= jj_begin_row) |
1714: P_diag_data[P_marker[loc_col]] += distribute* |
1715: A_ext_data[jj1]; |
1716: if(loc_col == i) |
1717: diagonal += distribute*A_ext_data[jj1]; |
1718: } |
1719: else |
1720: { |
1721: loc_col = -k1 - 1; |
1722: if(P_marker_offd[loc_col] >= jj_begin_row_offd) |
1723: P_offd_data[P_marker_offd[loc_col]] += distribute* |
[...] |
1730: diagonal += A_offd_data[jj]; |
1731: } |
1732: } |
1733: else if (CF_marker_offd[i1] != -3) |
1734: { |
1735: if(num_functions == 1 || dof_func[i] == dof_func_offd[i1]) |
1736: diagonal += A_offd_data[jj]; |
1737: } |
1738: } |
1739: } |
1740: if (diagonal) |
1741: { |
1742: for(jj = jj_begin_row; jj < jj_end_row; jj++) |
1743: P_diag_data[jj] /= -diagonal; |
1744: for(jj = jj_begin_row_offd; jj < jj_end_row_offd; jj++) |
1745: P_offd_data[jj] /= -diagonal; |
1746: } |
1747: } |
1748: strong_f_marker--; |
[...] |
1754: if (n_fine) |
1755: { hypre_TFree(P_marker); } |
1756: if (full_off_procNodes) |
1757: { hypre_TFree(P_marker_offd); } |
0x47ca60 PUSH %R13 |
0x47ca62 MOV %RDI,%RAX |
0x47ca65 LEA 0x10(%RSP),%R13 |
0x47ca6a AND $-0x40,%RSP |
0x47ca6e PUSHQ -0x8(%R13) |
0x47ca72 PUSH %RBP |
0x47ca73 MOV %RSP,%RBP |
0x47ca76 PUSH %R15 |
0x47ca78 PUSH %R14 |
0x47ca7a PUSH %R13 |
0x47ca7c PUSH %R12 |
0x47ca7e PUSH %RBX |
0x47ca7f SUB $0x308,%RSP |
0x47ca86 MOV %RDI,-0x70(%RBP) |
0x47ca8a MOV 0x158(%RDI),%RBX |
0x47ca91 MOV 0x140(%RDI),%RSI |
0x47ca98 MOV 0x138(%RDI),%RDX |
0x47ca9f MOV 0x128(%RDI),%R9 |
0x47caa6 MOV 0x120(%RDI),%R10 |
0x47caad MOV 0x118(%RDI),%R11 |
0x47cab4 MOV %RBX,-0xb0(%RBP) |
0x47cabb MOV 0x110(%RDI),%R12 |
0x47cac2 VMOVSD 0x170(%RDI),%XMM6 |
0x47caca MOV %RSI,-0x210(%RBP) |
0x47cad1 MOV 0x108(%RDI),%R14 |
0x47cad8 VMOVSD 0x168(%RDI),%XMM3 |
0x47cae0 MOV %RDX,-0x1f8(%RBP) |
0x47cae7 MOV 0x160(%RDI),%RCX |
0x47caee MOV 0x150(%RDI),%R8 |
0x47caf5 MOV %R9,-0x260(%RBP) |
0x47cafc MOV %R10,-0x48(%RBP) |
0x47cb00 MOV 0x148(%RDI),%RBX |
0x47cb07 MOV %R11,-0x240(%RBP) |
0x47cb0e MOV %R12,-0x258(%RBP) |
0x47cb15 VMOVSD %XMM6,-0x1d0(%RBP) |
0x47cb1d MOV %R14,-0x248(%RBP) |
0x47cb24 MOV 0xf8(%RDI),%R15 |
0x47cb2b MOV 0xd0(%RDI),%RSI |
0x47cb32 MOV 0xa8(%RAX),%RDX |
0x47cb39 MOV 0xb8(%RDI),%RDI |
0x47cb40 MOV 0xa0(%RAX),%R9 |
0x47cb47 MOV %R15,-0xf0(%RBP) |
0x47cb4e MOV 0x98(%RAX),%R10 |
0x47cb55 MOV 0x90(%RAX),%R11 |
0x47cb5c MOV %RSI,-0x38(%RBP) |
0x47cb60 MOV 0x80(%RAX),%R14 |
0x47cb67 MOV 0x78(%RAX),%R15 |
0x47cb6b MOV %RDI,-0x58(%RBP) |
0x47cb6f MOV 0x88(%RAX),%R12 |
0x47cb76 MOV 0x68(%RAX),%RDI |
0x47cb7a MOV %RDX,-0xf8(%RBP) |
0x47cb81 MOV 0x70(%RAX),%RSI |
0x47cb85 MOV 0x60(%RAX),%RDX |
0x47cb89 MOV %R9,-0x68(%RBP) |
0x47cb8d MOV %R10,-0x198(%RBP) |
0x47cb94 MOV 0x58(%RAX),%R9 |
0x47cb98 MOV %R11,-0x50(%RBP) |
0x47cb9c MOV 0x50(%RAX),%R10 |
0x47cba0 MOV 0x48(%RAX),%R11 |
0x47cba4 MOV %R14,-0x1a8(%RBP) |
0x47cbab MOV %R15,-0x1c0(%RBP) |
0x47cbb2 MOV %RDI,-0x1b0(%RBP) |
0x47cbb9 MOV %RDX,-0x238(%RBP) |
0x47cbc0 MOV %R9,-0x1b8(%RBP) |
0x47cbc7 MOV %R12,-0x190(%RBP) |
0x47cbce MOV %RSI,-0x100(%RBP) |
0x47cbd5 MOV %R10,-0x200(%RBP) |
0x47cbdc MOV %R11,-0x120(%RBP) |
0x47cbe3 MOV 0x40(%RAX),%R12 |
0x47cbe7 MOV 0x28(%RAX),%R14 |
0x47cbeb MOV 0x20(%RAX),%R15 |
0x47cbef MOV 0x18(%RAX),%RDI |
0x47cbf3 MOV 0x10(%RAX),%RDX |
0x47cbf7 MOV %R12,-0x188(%RBP) |
0x47cbfe MOV 0x8(%RAX),%R9 |
0x47cc02 MOV %R14,-0x268(%RBP) |
0x47cc09 MOV %R15,-0x178(%RBP) |
0x47cc10 MOV (%RAX),%R14 |
0x47cc13 MOV %RDI,-0x250(%RBP) |
0x47cc1a MOV %RDX,-0x180(%RBP) |
0x47cc21 MOV %R9,-0x110(%RBP) |
0x47cc28 TEST %RSI,%RSI |
0x47cc2b JNE 47f300 |
0x47cc31 MOV -0x70(%RBP),%RSI |
0x47cc35 MOV 0x130(%RSI),%R10 |
0x47cc3c MOV (%R10),%RDI |
0x47cc3f TEST %RDI,%RDI |
0x47cc42 JNE 47f3d0 |
0x47cc48 MOV %R8,-0x1a0(%RBP) |
0x47cc4f MOV %RCX,-0x130(%RBP) |
0x47cc56 VMOVSD %XMM3,-0x128(%RBP) |
0x47cc5e CALL 5b3bd0 <hypre_GetThreadNum> |
0x47cc63 MOV %RAX,%R12 |
0x47cc66 MOV %RAX,-0x118(%RBP) |
0x47cc6d CALL 5b3bc0 <hypre_NumActiveThreads> |
0x47cc72 MOV %R12,%R9 |
0x47cc75 VMOVSD -0x128(%RBP),%XMM0 |
0x47cc7d MOV -0x1a0(%RBP),%R8 |
0x47cc84 MOV %RAX,%RSI |
0x47cc87 MOV -0x100(%RBP),%RAX |
0x47cc8e LEA -0x1(%RSI),%RCX |
0x47cc92 CQTO |
0x47cc94 IDIV %RSI |
0x47cc97 IMUL %RAX,%R9 |
0x47cc9b ADD %R9,%RAX |
0x47cc9e CMP %RCX,%R12 |
0x47cca1 MOV %R9,-0x108(%RBP) |
0x47cca8 MOV -0x130(%RBP),%RCX |
0x47ccaf CMOVE -0x100(%RBP),%RAX |
0x47ccb7 CMP %R9,%RAX |
0x47ccba MOV %RAX,-0x40(%RBP) |
0x47ccbe JLE 48099f |
0x47ccc4 MOV -0x70(%RBP),%R10 |
0x47ccc8 MOV -0x108(%RBP),%RAX |
0x47cccf MOV %RCX,-0x1c8(%RBP) |
0x47ccd6 XOR %R15D,%R15D |
0x47ccd9 MOV %R8,-0x208(%RBP) |
0x47cce0 MOV %RBX,%RCX |
0x47cce3 MOV 0x38(%R10),%R11 |
0x47cce7 MOV %RSI,-0x230(%RBP) |
0x47ccee MOV %R11,%R8 |
0x47ccf1 MOV -0x58(%RBP),%R11 |
0x47ccf5 JMP 47cd1b |
0x47ccf7 NOPW (%RAX,%RAX,1) |
(759) 0x47cd00 MOV -0x48(%RBP),%R12 |
(759) 0x47cd04 INC %RBX |
(759) 0x47cd07 MOV %R15,(%R12,%RAX,8) |
(759) 0x47cd0b INC %R15 |
(759) 0x47cd0e INC %RAX |
(759) 0x47cd11 CMP %RAX,-0x40(%RBP) |
(759) 0x47cd15 JE 47d008 |
(759) 0x47cd1b MOV %RBX,(%R11,%RAX,8) |
(759) 0x47cd1f CMPQ $0x1,(%R8) |
(759) 0x47cd23 JLE 47cd2d |
(759) 0x47cd25 MOV -0x38(%RBP),%RSI |
(759) 0x47cd29 MOV %RCX,(%RSI,%RAX,8) |
(759) 0x47cd2d MOV (%R14,%RAX,8),%R12 |
(759) 0x47cd31 TEST %R12,%R12 |
(759) 0x47cd34 JNS 47cd00 |
(759) 0x47cd36 CMP $-0x3,%R12 |
(759) 0x47cd3a JE 47cd0e |
(759) 0x47cd3c MOV -0x50(%RBP),%RDX |
(759) 0x47cd40 MOV (%RDX,%RAX,8),%RSI |
(759) 0x47cd44 MOV 0x8(%RDX,%RAX,8),%R12 |
(759) 0x47cd49 CMP %R12,%RSI |
(759) 0x47cd4c JGE 47ce37 |
(759) 0x47cd52 MOV %R15,-0x1a0(%RBP) |
(759) 0x47cd59 MOV -0x198(%RBP),%R10 |
(759) 0x47cd60 JMP 47cd8f |
0x47cd62 NOPW (%RAX,%RAX,1) |
(762) 0x47cd68 MOV (%R11,%RAX,8),%RDX |
(762) 0x47cd6c ADD %R13,%RDI |
(762) 0x47cd6f CMP %RDX,(%RDI) |
(762) 0x47cd72 JGE 47cd83 |
(762) 0x47cd74 MOV %RBX,(%RDI) |
(762) 0x47cd77 MOV -0x50(%RBP),%R15 |
(762) 0x47cd7b INC %RBX |
(762) 0x47cd7e MOV 0x8(%R15,%RAX,8),%R12 |
(762) 0x47cd83 INC %RSI |
(762) 0x47cd86 CMP %R12,%RSI |
(762) 0x47cd89 JGE 47ce30 |
(762) 0x47cd8f MOV (%R10,%RSI,8),%R9 |
(762) 0x47cd93 MOV (%R14,%R9,8),%R15 |
(762) 0x47cd97 LEA (,%R9,8),%RDI |
(762) 0x47cd9f TEST %R15,%R15 |
(762) 0x47cda2 JNS 47cd68 |
(762) 0x47cda4 CMP $-0x3,%R15 |
(762) 0x47cda8 JE 47cd83 |
(762) 0x47cdaa MOV -0x50(%RBP),%R15 |
(762) 0x47cdae ADD $0x8,%RDI |
(762) 0x47cdb2 MOV (%R15,%R9,8),%RDX |
(762) 0x47cdb6 ADD %RDI,%R15 |
(762) 0x47cdb9 MOV (%R15),%R12 |
(762) 0x47cdbc CMP %R12,%RDX |
(762) 0x47cdbf JGE 47ce0e |
(762) 0x47cdc1 MOV %R8,-0x128(%RBP) |
(762) 0x47cdc8 MOV %RSI,-0x130(%RBP) |
(762) 0x47cdcf NOP |
(765) 0x47cdd0 MOV (%R10,%RDX,8),%R8 |
(765) 0x47cdd4 CMPQ $0,(%R14,%R8,8) |
(765) 0x47cdd9 LEA (,%R8,8),%RSI |
(765) 0x47cde1 JS 47cdf8 |
(765) 0x47cde3 ADD %R13,%RSI |
(765) 0x47cde6 MOV (%RSI),%R8 |
(765) 0x47cde9 CMP %R8,(%R11,%RAX,8) |
(765) 0x47cded JLE 47cdf8 |
(765) 0x47cdef MOV %RBX,(%RSI) |
(765) 0x47cdf2 INC %RBX |
(765) 0x47cdf5 MOV (%R15),%R12 |
(765) 0x47cdf8 INC %RDX |
(765) 0x47cdfb CMP %R12,%RDX |
(765) 0x47cdfe JL 47cdd0 |
(762) 0x47ce00 MOV -0x128(%RBP),%R8 |
(762) 0x47ce07 MOV -0x130(%RBP),%RSI |
(762) 0x47ce0e CMPQ $0x1,(%R8) |
(762) 0x47ce12 JG 47e750 |
(762) 0x47ce18 MOV -0x50(%RBP),%RDI |
(762) 0x47ce1c INC %RSI |
(762) 0x47ce1f MOV 0x8(%RDI,%RAX,8),%R12 |
(762) 0x47ce24 CMP %R12,%RSI |
(762) 0x47ce27 JL 47cd8f |
(759) 0x47ce2d NOPL (%RAX) |
(759) 0x47ce30 MOV -0x1a0(%RBP),%R15 |
(759) 0x47ce37 CMPQ $0x1,(%R8) |
(759) 0x47ce3b JLE 47cd0e |
(759) 0x47ce41 MOV -0x68(%RBP),%RSI |
(759) 0x47ce45 MOV (%RSI,%RAX,8),%RDI |
(759) 0x47ce49 CMP 0x8(%RSI,%RAX,8),%RDI |
(759) 0x47ce4e JGE 47cd0e |
(759) 0x47ce54 MOV -0x70(%RBP),%R9 |
(759) 0x47ce58 MOV -0x178(%RBP),%R12 |
(759) 0x47ce5f MOV %R15,-0x270(%RBP) |
(759) 0x47ce66 MOV %R14,-0x318(%RBP) |
(759) 0x47ce6d MOV -0x210(%RBP),%R15 |
(759) 0x47ce74 MOV 0xf0(%R9),%R10 |
(759) 0x47ce7b MOV %R8,-0x320(%RBP) |
(759) 0x47ce82 MOV (%R10),%R9 |
(759) 0x47ce85 MOV -0x1c0(%RBP),%R10 |
(759) 0x47ce8c JMP 47cecb |
0x47ce8e XCHG %AX,%AX |
(760) 0x47ce90 MOV -0x38(%RBP),%R14 |
(760) 0x47ce94 MOV -0x60(%RBP),%RSI |
(760) 0x47ce98 MOV (%R14,%RAX,8),%R8 |
(760) 0x47ce9c ADD %RDX,%RSI |
(760) 0x47ce9f CMP %R8,(%RSI) |
(760) 0x47cea2 JGE 47ceb9 |
(760) 0x47cea4 MOV -0xf0(%RBP),%R14 |
(760) 0x47ceab MOVQ $0x1,(%R14,%RDX,1) |
(760) 0x47ceb3 MOV %RCX,(%RSI) |
(760) 0x47ceb6 INC %RCX |
(760) 0x47ceb9 MOV -0x68(%RBP),%RDX |
(760) 0x47cebd INC %RDI |
(760) 0x47cec0 CMP %RDI,0x8(%RDX,%RAX,8) |
(760) 0x47cec5 JLE 47cfe0 |
(760) 0x47cecb MOV -0xf8(%RBP),%R8 |
(760) 0x47ced2 MOV (%R8,%RDI,8),%R14 |
(760) 0x47ced6 TEST %R12,%R12 |
(760) 0x47ced9 JE 47cedf |
(760) 0x47cedb MOV (%R12,%R14,8),%R14 |
(760) 0x47cedf MOV (%R9,%R14,8),%RSI |
(760) 0x47cee3 LEA (,%R14,8),%RDX |
(760) 0x47ceeb TEST %RSI,%RSI |
(760) 0x47ceee JNS 47ce90 |
(760) 0x47cef0 CMP $-0x3,%RSI |
(760) 0x47cef4 JE 47ceb9 |
(760) 0x47cef6 MOV -0x1f8(%RBP),%R8 |
(760) 0x47cefd LEA 0x8(%R8,%RDX,1),%R14 |
(760) 0x47cf02 MOV (%R8,%RDX,1),%RSI |
(760) 0x47cf06 MOV (%R14),%R8 |
(760) 0x47cf09 CMP %R8,%RSI |
(760) 0x47cf0c JGE 47ceb9 |
(760) 0x47cf0e MOV %RDI,-0x2f0(%RBP) |
(760) 0x47cf15 MOV -0x1a8(%RBP),%RDI |
(760) 0x47cf1c MOV %R12,-0x130(%RBP) |
(760) 0x47cf23 MOV %R9,-0x1a0(%RBP) |
(760) 0x47cf2a MOV %R14,-0x128(%RBP) |
(760) 0x47cf31 JMP 47cf68 |
0x47cf33 NOPL (%RAX,%RAX,1) |
(761) 0x47cf38 CMP %RDX,%R10 |
(761) 0x47cf3b JG 47cf71 |
(761) 0x47cf3d SUB %R10,%RDX |
(761) 0x47cf40 LEA (%R13,%RDX,8),%R12 |
(761) 0x47cf45 MOV (%R12),%R9 |
(761) 0x47cf49 CMP %R9,(%R11,%RAX,8) |
(761) 0x47cf4d JLE 47cf60 |
(761) 0x47cf4f MOV %RBX,(%R12) |
(761) 0x47cf53 MOV -0x128(%RBP),%R8 |
(761) 0x47cf5a INC %RBX |
(761) 0x47cf5d MOV (%R8),%R8 |
(761) 0x47cf60 INC %RSI |
(761) 0x47cf63 CMP %R8,%RSI |
(761) 0x47cf66 JGE 47cfb2 |
(761) 0x47cf68 MOV (%R15,%RSI,8),%RDX |
(761) 0x47cf6c CMP %RDX,%RDI |
(761) 0x47cf6f JG 47cf38 |
(761) 0x47cf71 MOV -0x60(%RBP),%R14 |
(761) 0x47cf75 NOT %RDX |
(761) 0x47cf78 MOV -0x38(%RBP),%R9 |
(761) 0x47cf7c LEA (%R14,%RDX,8),%R12 |
(761) 0x47cf80 MOV (%R12),%R14 |
(761) 0x47cf84 CMP %R14,(%R9,%RAX,8) |
(761) 0x47cf88 JLE 47cf60 |
(761) 0x47cf8a MOV -0xf0(%RBP),%R8 |
(761) 0x47cf91 MOV %RCX,(%R12) |
(761) 0x47cf95 INC %RSI |
(761) 0x47cf98 INC %RCX |
(761) 0x47cf9b MOVQ $0x1,(%R8,%RDX,8) |
(761) 0x47cfa3 MOV -0x128(%RBP),%RDX |
(761) 0x47cfaa MOV (%RDX),%R8 |
(761) 0x47cfad CMP %R8,%RSI |
(761) 0x47cfb0 JL 47cf68 |
(760) 0x47cfb2 MOV -0x2f0(%RBP),%RDI |
(760) 0x47cfb9 MOV -0x68(%RBP),%RDX |
(760) 0x47cfbd MOV -0x130(%RBP),%R12 |
(760) 0x47cfc4 MOV -0x1a0(%RBP),%R9 |
(760) 0x47cfcb INC %RDI |
(760) 0x47cfce CMP %RDI,0x8(%RDX,%RAX,8) |
(760) 0x47cfd3 JG 47cecb |
(759) 0x47cfd9 NOPL (%RAX) |
(759) 0x47cfe0 INC %RAX |
(759) 0x47cfe3 MOV -0x270(%RBP),%R15 |
(759) 0x47cfea MOV -0x318(%RBP),%R14 |
(759) 0x47cff1 MOV -0x320(%RBP),%R8 |
(759) 0x47cff8 CMP %RAX,-0x40(%RBP) |
(759) 0x47cffc JNE 47cd1b |
0x47d002 NOPW (%RAX,%RAX,1) |
0x47d008 MOV %RCX,%RAX |
0x47d00b MOV -0x208(%RBP),%R8 |
0x47d012 MOV -0x230(%RBP),%RSI |
0x47d019 MOV -0x1c8(%RBP),%RCX |
0x47d020 MOV %RCX,-0xf0(%RBP) |
0x47d027 MOV %RAX,-0x1c8(%RBP) |
0x47d02e MOV %RSI,-0x1a0(%RBP) |
0x47d035 MOV %R8,-0x128(%RBP) |
0x47d03c VMOVSD %XMM0,-0x130(%RBP) |
0x47d044 CALL 411290 <GOMP_barrier@plt> |
0x47d049 MOV -0x40(%RBP),%R11 |
0x47d04d MOV -0x1c8(%RBP),%RDX |
0x47d054 MOV -0x118(%RBP),%R8 |
0x47d05b MOV -0x58(%RBP),%R9 |
0x47d05f MOV -0x38(%RBP),%RDI |
0x47d063 MOV -0xb0(%RBP),%RSI |
0x47d06a LEA (,%R11,8),%R12 |
0x47d072 MOV %RBX,(%R9,%R11,8) |
0x47d076 LEA (,%R8,8),%R10 |
0x47d07e MOV %RDX,(%RDI,%R11,8) |
0x47d082 MOV %R15,(%RSI,%R8,8) |
0x47d086 MOV -0x128(%RBP),%R15 |
0x47d08d MOV %R10,-0x1c8(%RBP) |
0x47d094 LEA (%R15,%R10,1),%RAX |
0x47d098 MOV %RBX,(%RAX) |
0x47d09b MOV -0xf0(%RBP),%RBX |
0x47d0a2 MOV %RAX,-0x208(%RBP) |
0x47d0a9 LEA (%RBX,%R10,1),%RBX |
0x47d0ad MOV %RDX,(%RBX) |
0x47d0b0 CALL 411290 <GOMP_barrier@plt> |
0x47d0b5 MOV -0x118(%RBP),%R15 |
0x47d0bc MOV -0xf0(%RBP),%RCX |
0x47d0c3 MOV -0x128(%RBP),%R11 |
0x47d0ca VMOVSD -0x130(%RBP),%XMM1 |
0x47d0d2 TEST %R15,%R15 |
0x47d0d5 MOV -0x1a0(%RBP),%R8 |
0x47d0dc JE 47e820 |
0x47d0e2 MOV %RCX,-0x118(%RBP) |
0x47d0e9 VMOVSD %XMM1,-0xf0(%RBP) |
0x47d0f1 CALL 411290 <GOMP_barrier@plt> |
0x47d0f6 TEST %R15,%R15 |
0x47d0f9 VMOVSD -0xf0(%RBP),%XMM3 |
0x47d101 MOV -0x118(%RBP),%R9 |
0x47d108 MOV -0x128(%RBP),%RDI |
0x47d10f MOV -0x1c8(%RBP),%R10 |
0x47d116 JLE 47d7d0 |
0x47d11c MOV -0x108(%RBP),%RAX |
0x47d123 INC %RAX |
0x47d126 CMP %RAX,-0x40(%RBP) |
0x47d12a JL 480ca1 |
0x47d130 MOV -0x40(%RBP),%R15 |
0x47d134 MOV -0x108(%RBP),%RSI |
0x47d13b LEA -0x8(%R10),%RDX |
0x47d13f LEA (%RDI,%RDX,1),%R11 |
0x47d143 ADD %R9,%RDX |
0x47d146 SUB %RSI,%R15 |
0x47d149 LEA -0x1(%R15),%RCX |
0x47d14d MOV %R15,-0x118(%RBP) |
0x47d154 MOV %RCX,-0x130(%RBP) |
0x47d15b CMP $0x2,%RCX |
0x47d15f JBE 480640 |
0x47d165 MOV -0x38(%RBP),%R8 |
0x47d169 LEA (,%RAX,8),%RSI |
0x47d171 MOV -0x58(%RBP),%RCX |
0x47d175 LEA 0x8(%R12),%RDI |
0x47d17a MOV %RAX,-0x128(%RBP) |
0x47d181 LEA (%R8,%RSI,1),%R9 |
0x47d185 LEA (%R8,%RDI,1),%R15 |
0x47d189 LEA (%RCX,%RDI,1),%R12 |
0x47d18d LEA (%RCX,%RSI,1),%RCX |
0x47d191 ADD $0x40,%RSI |
0x47d195 CMP %RBX,%R9 |
0x47d198 SETAE %R8B |
0x47d19c CMP %R15,%RDX |
0x47d19f MOV %RCX,-0xf0(%RBP) |
0x47d1a6 SETAE %DIL |
0x47d1aa OR %EDI,%R8D |
0x47d1ad CMP %R12,%RDX |
0x47d1b0 SETAE %DIL |
0x47d1b4 CMP %RBX,%RCX |
0x47d1b7 MOV -0x58(%RBP),%RCX |
0x47d1bb SETAE %BL |
0x47d1be OR %EBX,%EDI |
0x47d1c0 ADD %RSI,%RCX |
0x47d1c3 MOV -0x38(%RBP),%RBX |
0x47d1c7 AND %R8D,%EDI |
0x47d1ca CMP %RCX,%R9 |
0x47d1cd MOV -0x208(%RBP),%RCX |
0x47d1d4 SETAE %R8B |
0x47d1d8 ADD %RBX,%RSI |
0x47d1db MOV -0xf0(%RBP),%RBX |
0x47d1e2 CMP %RSI,%RBX |
0x47d1e5 SETAE %SIL |
0x47d1e9 OR %ESI,%R8D |
0x47d1ec AND %EDI,%R8D |
0x47d1ef CMP %RCX,%R9 |
0x47d1f2 SETAE %SIL |
0x47d1f6 CMP %R15,%R11 |
0x47d1f9 SETAE %R15B |
0x47d1fd OR %R15D,%ESI |
0x47d200 TEST %SIL,%R8B |
0x47d203 JE 480640 |
0x47d209 CMP %RCX,%RBX |
0x47d20c SETAE %R8B |
0x47d210 CMP %R12,%R11 |
0x47d213 SETAE %R12B |
0x47d217 OR %R8B,%R12B |
0x47d21a JE 480640 |
0x47d220 CMPQ $0x6,-0x130(%RBP) |
0x47d228 JBE 480d98 |
0x47d22e MOV -0x118(%RBP),%R8 |
0x47d235 VPBROADCASTQ (%R11),%ZMM4 |
0x47d23b XOR %ESI,%ESI |
0x47d23d VPBROADCASTQ (%RDX),%ZMM5 |
0x47d243 SHR $0x3,%R8 |
0x47d247 SAL $0x6,%R8 |
0x47d24b LEA -0x40(%R8),%RDI |
0x47d24f SHR $0x6,%RDI |
0x47d253 INC %RDI |
0x47d256 AND $0x7,%EDI |
0x47d259 JE 47d39f |
0x47d25f CMP $0x1,%RDI |
0x47d263 JE 47d36f |
0x47d269 CMP $0x2,%RDI |
0x47d26d JE 47d348 |
0x47d273 CMP $0x3,%RDI |
0x47d277 JE 47d321 |
0x47d27d CMP $0x4,%RDI |
0x47d281 JE 47d2fa |
0x47d283 CMP $0x5,%RDI |
0x47d287 JE 47d2d3 |
0x47d289 CMP $0x6,%RDI |
0x47d28d JE 47d2ac |
0x47d28f VPADDQ (%RBX),%ZMM4,%ZMM2 |
0x47d295 MOV $0x40,%ESI |
0x47d29a VMOVDQU64 %ZMM2,(%RBX) |
0x47d2a0 VPADDQ (%R9),%ZMM5,%ZMM7 |
0x47d2a6 VMOVDQU64 %ZMM7,(%R9) |
0x47d2ac MOV -0xf0(%RBP),%RBX |
0x47d2b3 VPADDQ (%RBX,%RSI,1),%ZMM4,%ZMM8 |
0x47d2ba VMOVDQU64 %ZMM8,(%RBX,%RSI,1) |
0x47d2c1 VPADDQ (%R9,%RSI,1),%ZMM5,%ZMM9 |
0x47d2c8 VMOVDQU64 %ZMM9,(%R9,%RSI,1) |
0x47d2cf ADD $0x40,%RSI |
0x47d2d3 MOV -0xf0(%RBP),%R15 |
0x47d2da VPADDQ (%R15,%RSI,1),%ZMM4,%ZMM10 |
0x47d2e1 VMOVDQU64 %ZMM10,(%R15,%RSI,1) |
0x47d2e8 VPADDQ (%R9,%RSI,1),%ZMM5,%ZMM11 |
0x47d2ef VMOVDQU64 %ZMM11,(%R9,%RSI,1) |
0x47d2f6 ADD $0x40,%RSI |
0x47d2fa MOV -0xf0(%RBP),%RCX |
0x47d301 VPADDQ (%RCX,%RSI,1),%ZMM4,%ZMM12 |
0x47d308 VMOVDQU64 %ZMM12,(%RCX,%RSI,1) |
0x47d30f VPADDQ (%R9,%RSI,1),%ZMM5,%ZMM13 |
0x47d316 VMOVDQU64 %ZMM13,(%R9,%RSI,1) |
0x47d31d ADD $0x40,%RSI |
0x47d321 MOV -0xf0(%RBP),%R12 |
0x47d328 VPADDQ (%R12,%RSI,1),%ZMM4,%ZMM14 |
0x47d32f VMOVDQU64 %ZMM14,(%R12,%RSI,1) |
0x47d336 VPADDQ (%R9,%RSI,1),%ZMM5,%ZMM15 |
0x47d33d VMOVDQU64 %ZMM15,(%R9,%RSI,1) |
0x47d344 ADD $0x40,%RSI |
0x47d348 MOV -0xf0(%RBP),%RDI |
0x47d34f VPADDQ (%RDI,%RSI,1),%ZMM4,%ZMM6 |
0x47d356 VMOVDQU64 %ZMM6,(%RDI,%RSI,1) |
0x47d35d VPADDQ (%R9,%RSI,1),%ZMM5,%ZMM0 |
0x47d364 VMOVDQU64 %ZMM0,(%R9,%RSI,1) |
0x47d36b ADD $0x40,%RSI |
0x47d36f MOV -0xf0(%RBP),%RBX |
0x47d376 VPADDQ (%RBX,%RSI,1),%ZMM4,%ZMM1 |
0x47d37d VMOVDQU64 %ZMM1,(%RBX,%RSI,1) |
0x47d384 VPADDQ (%R9,%RSI,1),%ZMM5,%ZMM2 |
0x47d38b VMOVDQU64 %ZMM2,(%R9,%RSI,1) |
0x47d392 ADD $0x40,%RSI |
0x47d396 CMP %R8,%RSI |
0x47d399 JE 47d4ab |
(758) 0x47d39f VPADDQ (%RBX,%RSI,1),%ZMM4,%ZMM7 |
(758) 0x47d3a6 VMOVDQU64 %ZMM7,(%RBX,%RSI,1) |
(758) 0x47d3ad VPADDQ (%R9,%RSI,1),%ZMM5,%ZMM8 |
(758) 0x47d3b4 VMOVDQU64 %ZMM8,(%R9,%RSI,1) |
(758) 0x47d3bb VPADDQ 0x40(%RBX,%RSI,1),%ZMM4,%ZMM9 |
(758) 0x47d3c3 VMOVDQU64 %ZMM9,0x40(%RBX,%RSI,1) |
(758) 0x47d3cb VPADDQ 0x40(%R9,%RSI,1),%ZMM5,%ZMM10 |
(758) 0x47d3d3 VMOVDQU64 %ZMM10,0x40(%R9,%RSI,1) |
(758) 0x47d3db VPADDQ 0x80(%RBX,%RSI,1),%ZMM4,%ZMM11 |
(758) 0x47d3e3 VMOVDQU64 %ZMM11,0x80(%RBX,%RSI,1) |
(758) 0x47d3eb VPADDQ 0x80(%R9,%RSI,1),%ZMM5,%ZMM12 |
(758) 0x47d3f3 VMOVDQU64 %ZMM12,0x80(%R9,%RSI,1) |
(758) 0x47d3fb VPADDQ 0xc0(%RBX,%RSI,1),%ZMM4,%ZMM13 |
(758) 0x47d403 VMOVDQU64 %ZMM13,0xc0(%RBX,%RSI,1) |
(758) 0x47d40b VPADDQ 0xc0(%R9,%RSI,1),%ZMM5,%ZMM14 |
(758) 0x47d413 VMOVDQU64 %ZMM14,0xc0(%R9,%RSI,1) |
(758) 0x47d41b VPADDQ 0x100(%RBX,%RSI,1),%ZMM4,%ZMM15 |
(758) 0x47d423 VMOVDQU64 %ZMM15,0x100(%RBX,%RSI,1) |
(758) 0x47d42b VPADDQ 0x100(%R9,%RSI,1),%ZMM5,%ZMM6 |
(758) 0x47d433 VMOVDQU64 %ZMM6,0x100(%R9,%RSI,1) |
(758) 0x47d43b VPADDQ 0x140(%RBX,%RSI,1),%ZMM4,%ZMM0 |
(758) 0x47d443 VMOVDQU64 %ZMM0,0x140(%RBX,%RSI,1) |
(758) 0x47d44b VPADDQ 0x140(%R9,%RSI,1),%ZMM5,%ZMM1 |
(758) 0x47d453 VMOVDQU64 %ZMM1,0x140(%R9,%RSI,1) |
(758) 0x47d45b VPADDQ 0x180(%RBX,%RSI,1),%ZMM4,%ZMM2 |
(758) 0x47d463 VMOVDQU64 %ZMM2,0x180(%RBX,%RSI,1) |
(758) 0x47d46b VPADDQ 0x180(%R9,%RSI,1),%ZMM5,%ZMM7 |
(758) 0x47d473 VMOVDQU64 %ZMM7,0x180(%R9,%RSI,1) |
(758) 0x47d47b VPADDQ 0x1c0(%RBX,%RSI,1),%ZMM4,%ZMM8 |
(758) 0x47d483 VMOVDQU64 %ZMM8,0x1c0(%RBX,%RSI,1) |
(758) 0x47d48b VPADDQ 0x1c0(%R9,%RSI,1),%ZMM5,%ZMM9 |
(758) 0x47d493 VMOVDQU64 %ZMM9,0x1c0(%R9,%RSI,1) |
(758) 0x47d49b ADD $0x200,%RSI |
(758) 0x47d4a2 CMP %R8,%RSI |
(758) 0x47d4a5 JNE 47d39f |
0x47d4ab MOV -0x118(%RBP),%R8 |
0x47d4b2 MOV %R8,%R9 |
0x47d4b5 AND $-0x8,%R9 |
0x47d4b9 ADD %R9,%RAX |
0x47d4bc TEST $0x7,%R8B |
0x47d4c0 JE 480a6d |
0x47d4c6 SUB %R9,%R8 |
0x47d4c9 LEA -0x1(%R8),%RSI |
0x47d4cd MOV %R8,-0x118(%RBP) |
0x47d4d4 CMP $0x2,%RSI |
0x47d4d8 JBE 47d536 |
0x47d4da MOV -0x128(%RBP),%R15 |
0x47d4e1 MOV -0x58(%RBP),%RCX |
0x47d4e5 VPBROADCASTQ (%R11),%YMM4 |
0x47d4ea MOV (%RDX),%RBX |
0x47d4ed ADD %R15,%R9 |
0x47d4f0 MOV -0x38(%RBP),%RDI |
0x47d4f4 SAL $0x3,%R9 |
0x47d4f8 VPBROADCASTQ %RBX,%YMM10 |
0x47d4fe LEA (%RCX,%R9,1),%R12 |
0x47d502 ADD %RDI,%R9 |
0x47d505 VPADDQ (%R12),%YMM4,%YMM5 |
0x47d50b VMOVDQU %YMM5,(%R12) |
0x47d511 VPADDQ (%R9),%YMM10,%YMM11 |
0x47d516 VMOVDQU %YMM11,(%R9) |
0x47d51b MOV -0x118(%RBP),%R9 |
0x47d522 MOV %R9,%R8 |
0x47d525 AND $-0x4,%R8 |
0x47d529 ADD %R8,%RAX |
0x47d52c AND $0x3,%R9D |
0x47d530 JE 480a6d |
0x47d536 MOV (%R11),%R15 |
0x47d539 MOV -0x58(%RBP),%R12 |
0x47d53d LEA (,%RAX,8),%RSI |
0x47d545 MOV -0x38(%RBP),%RCX |
0x47d549 MOV -0x40(%RBP),%RBX |
0x47d54d ADD %R15,(%R12,%RSI,1) |
0x47d551 MOV (%RDX),%RDI |
0x47d554 ADD %RDI,(%RCX,%RSI,1) |
0x47d558 CMP %RAX,%RBX |
0x47d55b JLE 480a6d |
0x47d561 MOV (%R11),%R8 |
0x47d564 LEA 0x8(%RSI),%R9 |
0x47d568 ADD $0x2,%RAX |
0x47d56c ADD %R8,(%R12,%R9,1) |
0x47d570 MOV (%RDX),%R15 |
0x47d573 ADD %R15,(%RCX,%R9,1) |
0x47d577 CMP %RAX,%RBX |
0x47d57a JL 480a6d |
0x47d580 MOV (%R11),%RAX |
0x47d583 ADD $0x10,%RSI |
0x47d587 ADD %RAX,(%R12,%RSI,1) |
0x47d58b MOV (%RDX),%RDX |
0x47d58e ADD %RDX,(%RCX,%RSI,1) |
0x47d592 VZEROUPPER |
0x47d595 MOV -0x108(%RBP),%RAX |
0x47d59c MOV -0x48(%RBP),%R11 |
0x47d5a0 MOV -0x40(%RBP),%RDI |
0x47d5a4 MOV %RAX,%RDX |
0x47d5a7 MOV (%R11,%RAX,8),%R12 |
0x47d5ab NOT %RDX |
0x47d5ae ADD %RDI,%RDX |
0x47d5b1 AND $0x7,%EDX |
0x47d5b4 TEST %R12,%R12 |
0x47d5b7 JS 47d5d4 |
0x47d5b9 MOV -0xb0(%RBP),%RBX |
0x47d5c0 MOV -0x48(%RBP),%R9 |
0x47d5c4 MOV -0x108(%RBP),%R8 |
0x47d5cb ADD -0x8(%RBX,%R10,1),%R12 |
0x47d5d0 MOV %R12,(%R9,%R8,8) |
0x47d5d4 MOV -0x108(%RBP),%R15 |
0x47d5db INC %R15 |
0x47d5de CMP %R15,-0x40(%RBP) |
0x47d5e2 JLE 47d7d0 |
0x47d5e8 TEST %RDX,%RDX |
0x47d5eb JE 47d70b |
0x47d5f1 CMP $0x1,%RDX |
0x47d5f5 JE 47d6e1 |
0x47d5fb CMP $0x2,%RDX |
0x47d5ff JE 47d6c1 |
0x47d605 CMP $0x3,%RDX |
0x47d609 JE 47d6a1 |
0x47d60f CMP $0x4,%RDX |
0x47d613 JE 47d681 |
0x47d615 CMP $0x5,%RDX |
0x47d619 JE 47d661 |
0x47d61b CMP $0x6,%RDX |
0x47d61f JE 47d641 |
0x47d621 MOV -0x48(%RBP),%RSI |
0x47d625 MOV (%RSI,%R15,8),%RAX |
0x47d629 TEST %RAX,%RAX |
0x47d62c JS 47d63e |
0x47d62e MOV -0xb0(%RBP),%RCX |
0x47d635 ADD -0x8(%RCX,%R10,1),%RAX |
0x47d63a MOV %RAX,(%RSI,%R15,8) |
0x47d63e INC %R15 |
0x47d641 MOV -0x48(%RBP),%RDI |
0x47d645 MOV (%RDI,%R15,8),%RDX |
0x47d649 TEST %RDX,%RDX |
0x47d64c JS 47d65e |
0x47d64e MOV -0xb0(%RBP),%R11 |
0x47d655 ADD -0x8(%R11,%R10,1),%RDX |
0x47d65a MOV %RDX,(%RDI,%R15,8) |
0x47d65e INC %R15 |
0x47d661 MOV -0x48(%RBP),%R12 |
0x47d665 MOV (%R12,%R15,8),%RBX |
0x47d669 TEST %RBX,%RBX |
0x47d66c JS 47d67e |
0x47d66e MOV -0xb0(%RBP),%R9 |
0x47d675 ADD -0x8(%R9,%R10,1),%RBX |
0x47d67a MOV %RBX,(%R12,%R15,8) |
0x47d67e INC %R15 |
0x47d681 MOV -0x48(%RBP),%R8 |
0x47d685 MOV (%R8,%R15,8),%RSI |
0x47d689 TEST %RSI,%RSI |
0x47d68c JS 47d69e |
0x47d68e MOV -0xb0(%RBP),%RAX |
0x47d695 ADD -0x8(%RAX,%R10,1),%RSI |
0x47d69a MOV %RSI,(%R8,%R15,8) |
0x47d69e INC %R15 |
0x47d6a1 MOV -0x48(%RBP),%RDI |
0x47d6a5 MOV (%RDI,%R15,8),%RDX |
0x47d6a9 TEST %RDX,%RDX |
0x47d6ac JS 47d6be |
0x47d6ae MOV -0xb0(%RBP),%RCX |
0x47d6b5 ADD -0x8(%RCX,%R10,1),%RDX |
0x47d6ba MOV %RDX,(%RDI,%R15,8) |
0x47d6be INC %R15 |
0x47d6c1 MOV -0x48(%RBP),%R11 |
0x47d6c5 MOV (%R11,%R15,8),%R12 |
0x47d6c9 TEST %R12,%R12 |
0x47d6cc JS 47d6de |
0x47d6ce MOV -0xb0(%RBP),%RBX |
0x47d6d5 ADD -0x8(%RBX,%R10,1),%R12 |
0x47d6da MOV %R12,(%R11,%R15,8) |
0x47d6de INC %R15 |
0x47d6e1 MOV -0x48(%RBP),%R9 |
0x47d6e5 MOV (%R9,%R15,8),%R8 |
0x47d6e9 TEST %R8,%R8 |
0x47d6ec JS 47d6fe |
0x47d6ee MOV -0xb0(%RBP),%RSI |
0x47d6f5 ADD -0x8(%RSI,%R10,1),%R8 |
0x47d6fa MOV %R8,(%R9,%R15,8) |
0x47d6fe INC %R15 |
0x47d701 CMP %R15,-0x40(%RBP) |
0x47d705 JLE 47d7d0 |
0x47d70b MOV -0xb0(%RBP),%RAX |
0x47d712 MOV -0x48(%RBP),%RDX |
(756) 0x47d716 MOV (%RDX,%R15,8),%RDI |
(756) 0x47d71a TEST %RDI,%RDI |
(756) 0x47d71d JS 47d728 |
(756) 0x47d71f ADD -0x8(%RAX,%R10,1),%RDI |
(756) 0x47d724 MOV %RDI,(%RDX,%R15,8) |
(756) 0x47d728 INC %R15 |
(756) 0x47d72b MOV (%RDX,%R15,8),%RCX |
(756) 0x47d72f TEST %RCX,%RCX |
(756) 0x47d732 JS 47d73d |
(756) 0x47d734 ADD -0x8(%RAX,%R10,1),%RCX |
(756) 0x47d739 MOV %RCX,(%RDX,%R15,8) |
(756) 0x47d73d LEA 0x1(%R15),%R11 |
(756) 0x47d741 MOV (%RDX,%R11,8),%R12 |
(756) 0x47d745 TEST %R12,%R12 |
(756) 0x47d748 JS 47d753 |
(756) 0x47d74a ADD -0x8(%RAX,%R10,1),%R12 |
(756) 0x47d74f MOV %R12,(%RDX,%R11,8) |
(756) 0x47d753 LEA 0x2(%R15),%RBX |
(756) 0x47d757 MOV (%RDX,%RBX,8),%R9 |
(756) 0x47d75b TEST %R9,%R9 |
(756) 0x47d75e JS 47d769 |
(756) 0x47d760 ADD -0x8(%RAX,%R10,1),%R9 |
(756) 0x47d765 MOV %R9,(%RDX,%RBX,8) |
(756) 0x47d769 LEA 0x3(%R15),%R8 |
(756) 0x47d76d MOV (%RDX,%R8,8),%RSI |
(756) 0x47d771 TEST %RSI,%RSI |
(756) 0x47d774 JS 47d77f |
(756) 0x47d776 ADD -0x8(%RAX,%R10,1),%RSI |
(756) 0x47d77b MOV %RSI,(%RDX,%R8,8) |
(756) 0x47d77f LEA 0x4(%R15),%RDI |
(756) 0x47d783 MOV (%RDX,%RDI,8),%RCX |
(756) 0x47d787 TEST %RCX,%RCX |
(756) 0x47d78a JS 47d795 |
(756) 0x47d78c ADD -0x8(%RAX,%R10,1),%RCX |
(756) 0x47d791 MOV %RCX,(%RDX,%RDI,8) |
(756) 0x47d795 LEA 0x5(%R15),%R11 |
(756) 0x47d799 MOV (%RDX,%R11,8),%R12 |
(756) 0x47d79d TEST %R12,%R12 |
(756) 0x47d7a0 JS 47d7ab |
(756) 0x47d7a2 ADD -0x8(%RAX,%R10,1),%R12 |
(756) 0x47d7a7 MOV %R12,(%RDX,%R11,8) |
(756) 0x47d7ab LEA 0x6(%R15),%RBX |
(756) 0x47d7af MOV (%RDX,%RBX,8),%R9 |
(756) 0x47d7b3 TEST %R9,%R9 |
(756) 0x47d7b6 JS 47d7c1 |
(756) 0x47d7b8 ADD -0x8(%RAX,%R10,1),%R9 |
(756) 0x47d7bd MOV %R9,(%RDX,%RBX,8) |
(756) 0x47d7c1 ADD $0x7,%R15 |
(756) 0x47d7c5 CMP %R15,-0x40(%RBP) |
(756) 0x47d7c9 JG 47d716 |
0x47d7cf NOP |
0x47d7d0 VMOVSD %XMM3,-0xb0(%RBP) |
0x47d7d8 CALL 411290 <GOMP_barrier@plt> |
0x47d7dd VMOVSD -0xb0(%RBP),%XMM3 |
0x47d7e5 CMPQ $0,-0x100(%RBP) |
0x47d7ed JLE 4809d4 |
0x47d7f3 MOV -0x100(%RBP),%R8 |
0x47d7fa MOV $0xff,%ESI |
0x47d7ff MOV %R13,%RDI |
0x47d802 VMOVSD %XMM3,-0xb0(%RBP) |
0x47d80a LEA (,%R8,8),%RDX |
0x47d812 CALL 4110a0 <memset@plt> |
0x47d817 MOV -0x70(%RBP),%RCX |
0x47d81b VMOVSD -0xb0(%RBP),%XMM3 |
0x47d823 MOV 0x130(%RCX),%R10 |
0x47d82a CMPQ $0,(%R10) |
0x47d82e JLE 47f390 |
0x47d834 MOV -0x60(%RBP),%R9 |
0x47d838 XOR %R15D,%R15D |
0x47d83b NOPL (%RAX,%RAX,1) |
(735) 0x47d840 MOVQ $-0x1,(%R9,%R15,8) |
(735) 0x47d848 INC %R15 |
(735) 0x47d84b CMP %R15,(%R10) |
(735) 0x47d84e JG 47d840 |
0x47d850 VMOVSD %XMM3,-0xb0(%RBP) |
0x47d858 CALL 411290 <GOMP_barrier@plt> |
0x47d85d MOV -0x108(%RBP),%RBX |
0x47d864 VMOVSD -0xb0(%RBP),%XMM3 |
0x47d86c CMP %RBX,-0x40(%RBP) |
0x47d870 JLE 47e1e6 |
0x47d876 MOV -0x70(%RBP),%R11 |
0x47d87a MOV $-0x2,%RDX |
0x47d881 MOV -0x48(%RBP),%R12 |
0x47d885 MOV %R14,%R10 |
0x47d888 KXNORB %K2,%K2,%K2 |
0x47d88c MOV %RDX,-0x48(%RBP) |
0x47d890 VMOVSD -0x1d0(%RBP),%XMM15 |
0x47d898 VXORPD %XMM6,%XMM6,%XMM6 |
0x47d89c VXORPD %XMM5,%XMM5,%XMM5 |
0x47d8a0 MOV 0xc0(%R11),%RSI |
0x47d8a7 MOV 0xb0(%R11),%RAX |
0x47d8ae MOV %R13,%R14 |
0x47d8b1 MOV 0x38(%R11),%RDI |
0x47d8b5 MOV -0x58(%RBP),%R9 |
0x47d8b9 MOV %RSI,-0xf0(%RBP) |
0x47d8c0 MOV -0x108(%RBP),%R8 |
0x47d8c7 MOV %RAX,-0xb0(%RBP) |
0x47d8ce MOV %RDI,-0x118(%RBP) |
0x47d8d5 JMP 47d90d |
0x47d8d7 NOPW (%RAX,%RAX,1) |
(736) 0x47d8e0 MOV (%R12,%R8,8),%R11 |
(736) 0x47d8e4 MOV -0xf0(%RBP),%RBX |
(736) 0x47d8eb MOV -0xb0(%RBP),%RCX |
(736) 0x47d8f2 MOV %R11,(%RBX,%R13,8) |
(736) 0x47d8f6 VMOVSD %XMM15,(%RCX,%R13,8) |
(736) 0x47d8fc INC %R8 |
(736) 0x47d8ff DECQ -0x48(%RBP) |
(736) 0x47d903 CMP %R8,-0x40(%RBP) |
(736) 0x47d907 JE 47e1e0 |
(736) 0x47d90d MOV -0x38(%RBP),%RCX |
(736) 0x47d911 MOV (%R10,%R8,8),%RBX |
(736) 0x47d915 MOV (%R9,%R8,8),%R13 |
(736) 0x47d919 MOV (%RCX,%R8,8),%R15 |
(736) 0x47d91d TEST %RBX,%RBX |
(736) 0x47d920 JNS 47d8e0 |
(736) 0x47d922 CMP $-0x3,%RBX |
(736) 0x47d926 JE 47d8fc |
(736) 0x47d928 MOV -0x50(%RBP),%R11 |
(736) 0x47d92c DECQ -0x48(%RBP) |
(736) 0x47d930 MOV %R15,-0x128(%RBP) |
(736) 0x47d937 MOV (%R11,%R8,8),%RDI |
(736) 0x47d93b MOV 0x8(%R11,%R8,8),%RSI |
(736) 0x47d940 MOV %R13,-0x108(%RBP) |
(736) 0x47d947 CMP %RSI,%RDI |
(736) 0x47d94a JGE 47db64 |
(736) 0x47d950 MOV %R9,-0x130(%RBP) |
(736) 0x47d957 MOV -0x198(%RBP),%RBX |
(736) 0x47d95e MOV %R15,%RDX |
(736) 0x47d961 MOV %RSI,%RAX |
(736) 0x47d964 MOV -0x108(%RBP),%R9 |
(736) 0x47d96b MOV %R8,%RCX |
(736) 0x47d96e JMP 47d9af |
(749) 0x47d970 ADD %R14,%RSI |
(749) 0x47d973 CMP (%RSI),%R13 |
(749) 0x47d976 JLE 47d9a3 |
(749) 0x47d978 MOV %R9,(%RSI) |
(749) 0x47d97b MOV -0xb0(%RBP),%R15 |
(749) 0x47d982 MOV -0xf0(%RBP),%RSI |
(749) 0x47d989 MOV (%R12,%R8,8),%RAX |
(749) 0x47d98d MOV %RAX,(%RSI,%R9,8) |
(749) 0x47d991 VMOVSD %XMM3,(%R15,%R9,8) |
(749) 0x47d997 INC %R9 |
(749) 0x47d99a MOV -0x50(%RBP),%R11 |
(749) 0x47d99e MOV 0x8(%R11,%RCX,8),%RAX |
(749) 0x47d9a3 INC %RDI |
(749) 0x47d9a6 CMP %RAX,%RDI |
(749) 0x47d9a9 JGE 47db50 |
(749) 0x47d9af MOV (%RBX,%RDI,8),%R8 |
(749) 0x47d9b3 MOV (%R10,%R8,8),%R15 |
(749) 0x47d9b7 LEA (,%R8,8),%RSI |
(749) 0x47d9bf TEST %R15,%R15 |
(749) 0x47d9c2 JNS 47d970 |
(749) 0x47d9c4 CMP $-0x3,%R15 |
(749) 0x47d9c8 JE 47d9a3 |
(749) 0x47d9ca MOV -0x48(%RBP),%RAX |
(749) 0x47d9ce MOV -0x50(%RBP),%R15 |
(749) 0x47d9d2 ADD $0x8,%RSI |
(749) 0x47d9d6 MOV %RAX,(%R14,%R8,8) |
(749) 0x47d9da MOV (%R15,%R8,8),%RAX |
(749) 0x47d9de ADD %RSI,%R15 |
(749) 0x47d9e1 MOV (%R15),%R11 |
(749) 0x47d9e4 CMP %R11,%RAX |
(749) 0x47d9e7 JGE 47da4b |
(749) 0x47d9e9 MOV %RDI,-0x58(%RBP) |
(749) 0x47d9ed MOV %RCX,-0x108(%RBP) |
(749) 0x47d9f4 NOPL (%RAX) |
(752) 0x47d9f8 MOV (%RBX,%RAX,8),%RCX |
(752) 0x47d9fc CMPQ $0,(%R10,%RCX,8) |
(752) 0x47da01 LEA (,%RCX,8),%RDI |
(752) 0x47da09 JS 47da38 |
(752) 0x47da0b ADD %R14,%RDI |
(752) 0x47da0e CMP (%RDI),%R13 |
(752) 0x47da11 JLE 47da38 |
(752) 0x47da13 MOV %R9,(%RDI) |
(752) 0x47da16 MOV -0xb0(%RBP),%RDI |
(752) 0x47da1d MOV (%R12,%RCX,8),%R11 |
(752) 0x47da21 MOV -0xf0(%RBP),%RCX |
(752) 0x47da28 MOV %R11,(%RCX,%R9,8) |
(752) 0x47da2c VMOVSD %XMM3,(%RDI,%R9,8) |
(752) 0x47da32 INC %R9 |
(752) 0x47da35 MOV (%R15),%R11 |
(752) 0x47da38 INC %RAX |
(752) 0x47da3b CMP %R11,%RAX |
(752) 0x47da3e JL 47d9f8 |
(749) 0x47da40 MOV -0x58(%RBP),%RDI |
(749) 0x47da44 MOV -0x108(%RBP),%RCX |
(749) 0x47da4b MOV -0x118(%RBP),%R15 |
(749) 0x47da52 CMPQ $0x1,(%R15) |
(749) 0x47da56 JLE 47d99a |
(749) 0x47da5c MOV -0x68(%RBP),%R11 |
(749) 0x47da60 MOV (%R11,%R8,8),%RAX |
(749) 0x47da64 ADD %R11,%RSI |
(749) 0x47da67 CMP (%RSI),%RAX |
(749) 0x47da6a JGE 47d99a |
(749) 0x47da70 MOV -0x70(%RBP),%R11 |
(749) 0x47da74 CMPQ $0,-0x178(%RBP) |
(749) 0x47da7c MOV %R14,-0x190(%RBP) |
(749) 0x47da83 MOV 0xf0(%R11),%R8 |
(749) 0x47da8a MOV (%R8),%R15 |
(749) 0x47da8d MOV 0xd8(%R11),%R8 |
(749) 0x47da94 MOV 0xc8(%R11),%R11 |
(749) 0x47da9b MOV %R8,-0x58(%RBP) |
(749) 0x47da9f MOV %R11,-0x108(%RBP) |
(749) 0x47daa6 JE 480418 |
(749) 0x47daac MOV %RDI,-0x1c8(%RBP) |
(749) 0x47dab3 MOV -0xf8(%RBP),%R14 |
(749) 0x47daba MOV %R12,-0x1a0(%RBP) |
(749) 0x47dac1 MOV -0x128(%RBP),%R12 |
(749) 0x47dac8 MOV %RCX,-0x1d0(%RBP) |
(749) 0x47dacf MOV -0x178(%RBP),%RCX |
(749) 0x47dad6 NOPW %CS:(%RAX,%RAX,1) |
(751) 0x47dae0 MOV (%R14,%RAX,8),%RDI |
(751) 0x47dae4 MOV (%RCX,%RDI,8),%R8 |
(751) 0x47dae8 CMPQ $0,(%R15,%R8,8) |
(751) 0x47daed LEA (,%R8,8),%R11 |
(751) 0x47daf5 JS 47db1e |
(751) 0x47daf7 MOV -0x60(%RBP),%RDI |
(751) 0x47dafb ADD %RDI,%R11 |
(751) 0x47dafe CMP (%R11),%RDX |
(751) 0x47db01 JLE 47db1e |
(751) 0x47db03 MOV %R12,(%R11) |
(751) 0x47db06 MOV -0x58(%RBP),%R11 |
(751) 0x47db0a MOV %R8,(%R11,%R12,8) |
(751) 0x47db0e MOV -0x108(%RBP),%R8 |
(751) 0x47db15 VMOVSD %XMM3,(%R8,%R12,8) |
(751) 0x47db1b INC %R12 |
(751) 0x47db1e INC %RAX |
(751) 0x47db21 CMP %RAX,(%RSI) |
(751) 0x47db24 JG 47dae0 |
(749) 0x47db26 MOV -0x190(%RBP),%R14 |
(749) 0x47db2d MOV -0x1c8(%RBP),%RDI |
(749) 0x47db34 MOV %R12,-0x128(%RBP) |
(749) 0x47db3b MOV -0x1d0(%RBP),%RCX |
(749) 0x47db42 MOV -0x1a0(%RBP),%R12 |
(749) 0x47db49 JMP 47d99a |
0x47db4e XCHG %AX,%AX |
(736) 0x47db50 MOV %R9,-0x108(%RBP) |
(736) 0x47db57 MOV -0x130(%RBP),%R9 |
(736) 0x47db5e MOV %RCX,%R8 |
(736) 0x47db61 MOV %RDX,%R15 |
(736) 0x47db64 MOV -0x118(%RBP),%RCX |
(736) 0x47db6b MOV (%RCX),%RDI |
(736) 0x47db6e MOV %RDI,-0x58(%RBP) |
(736) 0x47db72 CMP $0x1,%RDI |
(736) 0x47db76 JG 47efa0 |
(736) 0x47db7c MOV -0x120(%RBP),%RCX |
(736) 0x47db83 MOV -0x188(%RBP),%RBX |
(736) 0x47db8a VPBROADCASTQ %R8,%YMM8 |
(736) 0x47db90 VPBROADCASTQ %R13,%YMM7 |
(736) 0x47db96 MOV (%RCX,%R8,8),%RSI |
(736) 0x47db9a MOV 0x8(%RCX,%R8,8),%RDI |
(736) 0x47db9f VMOVSD (%RBX,%RSI,8),%XMM4 |
(736) 0x47dba4 LEA 0x1(%RSI),%RSI |
(736) 0x47dba8 CMP %RSI,%RDI |
(736) 0x47dbab JLE 47dc73 |
(736) 0x47dbb1 MOV %R12,-0x1c8(%RBP) |
(736) 0x47dbb8 MOV -0x200(%RBP),%RDX |
(736) 0x47dbbf MOV %R10,%R12 |
(736) 0x47dbc2 MOV %R8,%R11 |
(736) 0x47dbc5 MOV %R15,-0x130(%RBP) |
(736) 0x47dbcc MOV %RDI,%R15 |
(736) 0x47dbcf MOV %R9,-0x1d0(%RBP) |
(736) 0x47dbd6 JMP 47dc02 |
0x47dbd8 NOPL (%RAX,%RAX,1) |
(742) 0x47dbe0 MOV -0xb0(%RBP),%RAX |
(742) 0x47dbe7 LEA (%RAX,%R8,8),%R9 |
(742) 0x47dbeb VMOVSD (%R9),%XMM0 |
(742) 0x47dbf0 VADDSD (%RBX,%RSI,8),%XMM0,%XMM9 |
(742) 0x47dbf5 VMOVSD %XMM9,(%R9) |
(742) 0x47dbfa INC %RSI |
(742) 0x47dbfd CMP %RSI,%R15 |
(742) 0x47dc00 JE 47dc58 |
(742) 0x47dc02 MOV (%RDX,%RSI,8),%RAX |
(742) 0x47dc06 MOV (%R14,%RAX,8),%R8 |
(742) 0x47dc0a LEA (,%RAX,8),%RDI |
(742) 0x47dc12 CMP %R8,%R13 |
(742) 0x47dc15 JLE 47dbe0 |
(742) 0x47dc17 MOV -0x48(%RBP),%R10 |
(742) 0x47dc1b CMP %R10,%R8 |
(742) 0x47dc1e JE 47e228 |
(742) 0x47dc24 CMPQ $-0x3,(%R12,%RAX,8) |
(742) 0x47dc29 JE 47dbfa |
(742) 0x47dc2b CMPQ $0x1,-0x110(%RBP) |
(742) 0x47dc33 JE 47dc46 |
(742) 0x47dc35 MOV -0x180(%RBP),%R9 |
(742) 0x47dc3c MOV (%R9,%RAX,8),%RAX |
(742) 0x47dc40 CMP %RAX,(%R9,%R11,8) |
(742) 0x47dc44 JNE 47dbfa |
(742) 0x47dc46 VADDSD (%RBX,%RSI,8),%XMM4,%XMM4 |
(742) 0x47dc4b INC %RSI |
(742) 0x47dc4e CMP %RSI,%R15 |
(742) 0x47dc51 JNE 47dc02 |
(736) 0x47dc53 NOPL (%RAX,%RAX,1) |
(736) 0x47dc58 MOV %R12,%R10 |
(736) 0x47dc5b MOV -0x1d0(%RBP),%R9 |
(736) 0x47dc62 MOV -0x1c8(%RBP),%R12 |
(736) 0x47dc69 MOV %R11,%R8 |
(736) 0x47dc6c MOV -0x130(%RBP),%R15 |
(736) 0x47dc73 CMPQ $0x1,-0x58(%RBP) |
(736) 0x47dc78 JG 47f1d8 |
(736) 0x47dc7e VCOMISD %XMM5,%XMM4 |
(736) 0x47dc82 JE 47d8fc |
(736) 0x47dc88 CMP %R13,-0x108(%RBP) |
(736) 0x47dc8f JLE 47df25 |
(736) 0x47dc95 MOV -0x108(%RBP),%RSI |
(736) 0x47dc9c VMOVSD 0x13c874(%RIP),%XMM9 |
(736) 0x47dca4 MOV %R13,%R11 |
(736) 0x47dca7 VDIVSD %XMM4,%XMM9,%XMM8 |
(736) 0x47dcab SUB %R13,%RSI |
(736) 0x47dcae LEA -0x1(%RSI),%RDX |
(736) 0x47dcb2 CMP $0x6,%RDX |
(736) 0x47dcb6 JBE 480cb7 |
(736) 0x47dcbc MOV -0xb0(%RBP),%RAX |
(736) 0x47dcc3 MOV %RSI,%RCX |
(736) 0x47dcc6 VBROADCASTSD 0x13c170(%RIP),%ZMM12 |
(736) 0x47dcd0 VBROADCASTSD %XMM8,%ZMM1 |
(736) 0x47dcd6 SHR $0x3,%RCX |
(736) 0x47dcda SAL $0x6,%RCX |
(736) 0x47dcde LEA (%RAX,%R13,8),%RDX |
(736) 0x47dce2 LEA (%RCX,%RDX,1),%RDI |
(736) 0x47dce6 SUB $0x40,%RCX |
(736) 0x47dcea SHR $0x6,%RCX |
(736) 0x47dcee INC %RCX |
(736) 0x47dcf1 AND $0x7,%ECX |
(736) 0x47dcf4 JE 47ddb9 |
(736) 0x47dcfa CMP $0x1,%RCX |
(736) 0x47dcfe JE 47dd99 |
(736) 0x47dd04 CMP $0x2,%RCX |
(736) 0x47dd08 JE 47dd82 |
(736) 0x47dd0a CMP $0x3,%RCX |
(736) 0x47dd0e JE 47dd6b |
(736) 0x47dd10 CMP $0x4,%RCX |
(736) 0x47dd14 JE 47dd54 |
(736) 0x47dd16 CMP $0x5,%RCX |
(736) 0x47dd1a JE 47dd3d |
(736) 0x47dd1c CMP $0x6,%RCX |
(736) 0x47dd20 JNE 480bb4 |
(736) 0x47dd26 VMULPD (%RDX),%ZMM1,%ZMM10 |
(736) 0x47dd2c ADD $0x40,%RDX |
(736) 0x47dd30 VXORPD %ZMM12,%ZMM10,%ZMM11 |
(736) 0x47dd36 VMOVUPD %ZMM11,-0x40(%RDX) |
(736) 0x47dd3d VMULPD (%RDX),%ZMM1,%ZMM13 |
(736) 0x47dd43 ADD $0x40,%RDX |
(736) 0x47dd47 VXORPD %ZMM12,%ZMM13,%ZMM2 |
(736) 0x47dd4d VMOVUPD %ZMM2,-0x40(%RDX) |
(736) 0x47dd54 VMULPD (%RDX),%ZMM1,%ZMM0 |
(736) 0x47dd5a ADD $0x40,%RDX |
(736) 0x47dd5e VXORPD %ZMM12,%ZMM0,%ZMM9 |
(736) 0x47dd64 VMOVUPD %ZMM9,-0x40(%RDX) |
(736) 0x47dd6b VMULPD (%RDX),%ZMM1,%ZMM7 |
(736) 0x47dd71 ADD $0x40,%RDX |
(736) 0x47dd75 VXORPD %ZMM12,%ZMM7,%ZMM14 |
(736) 0x47dd7b VMOVUPD %ZMM14,-0x40(%RDX) |
(736) 0x47dd82 VMULPD (%RDX),%ZMM1,%ZMM10 |
(736) 0x47dd88 ADD $0x40,%RDX |
(736) 0x47dd8c VXORPD %ZMM12,%ZMM10,%ZMM11 |
(736) 0x47dd92 VMOVUPD %ZMM11,-0x40(%RDX) |
(736) 0x47dd99 VMULPD (%RDX),%ZMM1,%ZMM13 |
(736) 0x47dd9f ADD $0x40,%RDX |
(736) 0x47dda3 VXORPD %ZMM12,%ZMM13,%ZMM2 |
(736) 0x47dda9 VMOVUPD %ZMM2,-0x40(%RDX) |
(736) 0x47ddb0 CMP %RDX,%RDI |
(736) 0x47ddb3 JE 47de68 |
(738) 0x47ddb9 VMULPD (%RDX),%ZMM1,%ZMM0 |
(738) 0x47ddbf ADD $0x200,%RDX |
(738) 0x47ddc6 VMULPD -0x1c0(%RDX),%ZMM1,%ZMM7 |
(738) 0x47ddcd VMULPD -0x180(%RDX),%ZMM1,%ZMM10 |
(738) 0x47ddd4 VMULPD -0x140(%RDX),%ZMM1,%ZMM13 |
(738) 0x47dddb VXORPD %ZMM12,%ZMM0,%ZMM9 |
(738) 0x47dde1 VMULPD -0x100(%RDX),%ZMM1,%ZMM0 |
(738) 0x47dde8 VXORPD %ZMM12,%ZMM7,%ZMM14 |
(738) 0x47ddee VMOVUPD %ZMM9,-0x200(%RDX) |
(738) 0x47ddf5 VMULPD -0xc0(%RDX),%ZMM1,%ZMM7 |
(738) 0x47ddfc VXORPD %ZMM12,%ZMM10,%ZMM11 |
(738) 0x47de02 VMOVUPD %ZMM14,-0x1c0(%RDX) |
(738) 0x47de09 VMULPD -0x80(%RDX),%ZMM1,%ZMM10 |
(738) 0x47de10 VXORPD %ZMM12,%ZMM13,%ZMM2 |
(738) 0x47de16 VMOVUPD %ZMM11,-0x180(%RDX) |
(738) 0x47de1d VMULPD -0x40(%RDX),%ZMM1,%ZMM13 |
(738) 0x47de24 VMOVUPD %ZMM2,-0x140(%RDX) |
(738) 0x47de2b VXORPD %ZMM12,%ZMM0,%ZMM9 |
(738) 0x47de31 VXORPD %ZMM12,%ZMM7,%ZMM14 |
(738) 0x47de37 VMOVUPD %ZMM9,-0x100(%RDX) |
(738) 0x47de3e VXORPD %ZMM12,%ZMM10,%ZMM11 |
(738) 0x47de44 VMOVUPD %ZMM14,-0xc0(%RDX) |
(738) 0x47de4b VXORPD %ZMM12,%ZMM13,%ZMM2 |
(738) 0x47de51 VMOVUPD %ZMM11,-0x80(%RDX) |
(738) 0x47de58 VMOVUPD %ZMM2,-0x40(%RDX) |
(738) 0x47de5f CMP %RDX,%RDI |
(738) 0x47de62 JNE 47ddb9 |
(736) 0x47de68 MOV %RSI,%RBX |
(736) 0x47de6b AND $-0x8,%RBX |
(736) 0x47de6f ADD %RBX,%R13 |
(736) 0x47de72 TEST $0x7,%SIL |
(736) 0x47de76 JE 47df25 |
(736) 0x47de7c SUB %RBX,%RSI |
(736) 0x47de7f LEA -0x1(%RSI),%RAX |
(736) 0x47de83 CMP $0x2,%RAX |
(736) 0x47de87 JBE 47dec0 |
(736) 0x47de89 ADD %R11,%RBX |
(736) 0x47de8c MOV -0xb0(%RBP),%R11 |
(736) 0x47de93 VBROADCASTSD %XMM8,%YMM1 |
(736) 0x47de98 MOV %RSI,%RDX |
(736) 0x47de9b VBROADCASTSD 0x13bf9c(%RIP),%YMM0 |
(736) 0x47dea4 AND $-0x4,%RDX |
(736) 0x47dea8 LEA (%R11,%RBX,8),%RBX |
(736) 0x47deac ADD %RDX,%R13 |
(736) 0x47deaf AND $0x3,%ESI |
(736) 0x47deb2 VMULPD (%RBX),%YMM1,%YMM12 |
(736) 0x47deb6 VXORPD %YMM0,%YMM12,%YMM9 |
(736) 0x47deba VMOVUPD %YMM9,(%RBX) |
(736) 0x47debe JE 47df25 |
(736) 0x47dec0 MOV -0xb0(%RBP),%RDI |
(736) 0x47dec7 LEA (,%R13,8),%RSI |
(736) 0x47decf VMOVQ 0x13bf69(%RIP),%XMM14 |
(736) 0x47ded7 LEA 0x1(%R13),%RAX |
(736) 0x47dedb MOV -0x108(%RBP),%R11 |
(736) 0x47dee2 LEA (%RDI,%RSI,1),%RCX |
(736) 0x47dee6 VMULSD (%RCX),%XMM8,%XMM7 |
(736) 0x47deea VXORPD %XMM14,%XMM7,%XMM10 |
(736) 0x47deef VMOVSD %XMM10,(%RCX) |
(736) 0x47def3 CMP %RAX,%R11 |
(736) 0x47def6 JLE 47df25 |
(736) 0x47def8 LEA 0x8(%RDI,%RSI,1),%RBX |
(736) 0x47defd LEA 0x2(%R13),%R13 |
(736) 0x47df01 VMULSD (%RBX),%XMM8,%XMM11 |
(736) 0x47df05 VXORPD %XMM14,%XMM11,%XMM13 |
(736) 0x47df0a VMOVSD %XMM13,(%RBX) |
(736) 0x47df0e CMP %R13,%R11 |
(736) 0x47df11 JLE 47df25 |
(736) 0x47df13 LEA 0x10(%RDI,%RSI,1),%RDX |
(736) 0x47df18 VMULSD (%RDX),%XMM8,%XMM8 |
(736) 0x47df1c VXORPD %XMM14,%XMM8,%XMM2 |
(736) 0x47df21 VMOVSD %XMM2,(%RDX) |
(736) 0x47df25 MOV -0x128(%RBP),%RDI |
(736) 0x47df2c CMP %R15,%RDI |
(736) 0x47df2f JLE 47d8fc |
(736) 0x47df35 SUB %R15,%RDI |
(736) 0x47df38 MOV -0x70(%RBP),%RSI |
(736) 0x47df3c VMOVSD 0x13c5d4(%RIP),%XMM1 |
(736) 0x47df44 MOV %R15,%R11 |
(736) 0x47df47 LEA -0x1(%RDI),%RAX |
(736) 0x47df4b MOV %RDI,%RCX |
(736) 0x47df4e VDIVSD %XMM4,%XMM1,%XMM12 |
(736) 0x47df52 MOV 0xc8(%RSI),%R13 |
(736) 0x47df59 CMP $0x6,%RAX |
(736) 0x47df5d JBE 480cbe |
(736) 0x47df63 MOV %RDI,%RDX |
(736) 0x47df66 LEA (%R13,%R15,8),%RSI |
(736) 0x47df6b VBROADCASTSD 0x13becb(%RIP),%ZMM0 |
(736) 0x47df75 VBROADCASTSD %XMM12,%ZMM9 |
(736) 0x47df7b SHR $0x3,%RDX |
(736) 0x47df7f SAL $0x6,%RDX |
(736) 0x47df83 LEA (%RDX,%RSI,1),%RDI |
(736) 0x47df87 SUB $0x40,%RDX |
(736) 0x47df8b SHR $0x6,%RDX |
(736) 0x47df8f INC %RDX |
(736) 0x47df92 AND $0x7,%EDX |
(736) 0x47df95 JE 47e05a |
(736) 0x47df9b CMP $0x1,%RDX |
(736) 0x47df9f JE 47e03a |
(736) 0x47dfa5 CMP $0x2,%RDX |
(736) 0x47dfa9 JE 47e023 |
(736) 0x47dfab CMP $0x3,%RDX |
(736) 0x47dfaf JE 47e00c |
(736) 0x47dfb1 CMP $0x4,%RDX |
(736) 0x47dfb5 JE 47dff5 |
(736) 0x47dfb7 CMP $0x5,%RDX |
(736) 0x47dfbb JE 47dfde |
(736) 0x47dfbd CMP $0x6,%RDX |
(736) 0x47dfc1 JNE 480bd0 |
(736) 0x47dfc7 VMULPD (%RSI),%ZMM9,%ZMM14 |
(736) 0x47dfcd ADD $0x40,%RSI |
(736) 0x47dfd1 VXORPD %ZMM0,%ZMM14,%ZMM10 |
(736) 0x47dfd7 VMOVUPD %ZMM10,-0x40(%RSI) |
(736) 0x47dfde VMULPD (%RSI),%ZMM9,%ZMM11 |
(736) 0x47dfe4 ADD $0x40,%RSI |
(736) 0x47dfe8 VXORPD %ZMM0,%ZMM11,%ZMM13 |
(736) 0x47dfee VMOVUPD %ZMM13,-0x40(%RSI) |
(736) 0x47dff5 VMULPD (%RSI),%ZMM9,%ZMM8 |
(736) 0x47dffb ADD $0x40,%RSI |
(736) 0x47dfff VXORPD %ZMM0,%ZMM8,%ZMM2 |
(736) 0x47e005 VMOVUPD %ZMM2,-0x40(%RSI) |
(736) 0x47e00c VMULPD (%RSI),%ZMM9,%ZMM1 |
(736) 0x47e012 ADD $0x40,%RSI |
(736) 0x47e016 VXORPD %ZMM0,%ZMM1,%ZMM4 |
(736) 0x47e01c VMOVUPD %ZMM4,-0x40(%RSI) |
(736) 0x47e023 VMULPD (%RSI),%ZMM9,%ZMM7 |
(736) 0x47e029 ADD $0x40,%RSI |
(736) 0x47e02d VXORPD %ZMM0,%ZMM7,%ZMM14 |
(736) 0x47e033 VMOVUPD %ZMM14,-0x40(%RSI) |
(736) 0x47e03a VMULPD (%RSI),%ZMM9,%ZMM10 |
(736) 0x47e040 ADD $0x40,%RSI |
(736) 0x47e044 VXORPD %ZMM0,%ZMM10,%ZMM11 |
(736) 0x47e04a VMOVUPD %ZMM11,-0x40(%RSI) |
(736) 0x47e051 CMP %RSI,%RDI |
(736) 0x47e054 JE 47e109 |
(737) 0x47e05a VMULPD (%RSI),%ZMM9,%ZMM13 |
(737) 0x47e060 ADD $0x200,%RSI |
(737) 0x47e067 VMULPD -0x1c0(%RSI),%ZMM9,%ZMM2 |
(737) 0x47e06e VMULPD -0x180(%RSI),%ZMM9,%ZMM4 |
(737) 0x47e075 VMULPD -0x140(%RSI),%ZMM9,%ZMM14 |
(737) 0x47e07c VMULPD -0x100(%RSI),%ZMM9,%ZMM11 |
(737) 0x47e083 VXORPD %ZMM0,%ZMM13,%ZMM8 |
(737) 0x47e089 VXORPD %ZMM0,%ZMM2,%ZMM1 |
(737) 0x47e08f VMOVUPD %ZMM8,-0x200(%RSI) |
(737) 0x47e096 VMOVUPD %ZMM1,-0x1c0(%RSI) |
(737) 0x47e09d VMULPD -0xc0(%RSI),%ZMM9,%ZMM8 |
(737) 0x47e0a4 VXORPD %ZMM0,%ZMM4,%ZMM7 |
(737) 0x47e0aa VMULPD -0x80(%RSI),%ZMM9,%ZMM1 |
(737) 0x47e0b1 VMOVUPD %ZMM7,-0x180(%RSI) |
(737) 0x47e0b8 VXORPD %ZMM0,%ZMM14,%ZMM10 |
(737) 0x47e0be VMULPD -0x40(%RSI),%ZMM9,%ZMM7 |
(737) 0x47e0c5 VXORPD %ZMM0,%ZMM11,%ZMM13 |
(737) 0x47e0cb VMOVUPD %ZMM10,-0x140(%RSI) |
(737) 0x47e0d2 VMOVUPD %ZMM13,-0x100(%RSI) |
(737) 0x47e0d9 VXORPD %ZMM0,%ZMM8,%ZMM2 |
(737) 0x47e0df VXORPD %ZMM0,%ZMM1,%ZMM4 |
(737) 0x47e0e5 VMOVUPD %ZMM2,-0xc0(%RSI) |
(737) 0x47e0ec VXORPD %ZMM0,%ZMM7,%ZMM14 |
(737) 0x47e0f2 VMOVUPD %ZMM4,-0x80(%RSI) |
(737) 0x47e0f9 VMOVUPD %ZMM14,-0x40(%RSI) |
(737) 0x47e100 CMP %RSI,%RDI |
(737) 0x47e103 JNE 47e05a |
(736) 0x47e109 MOV %RCX,%RBX |
(736) 0x47e10c AND $-0x8,%RBX |
(736) 0x47e110 ADD %RBX,%R15 |
(736) 0x47e113 TEST $0x7,%CL |
(736) 0x47e116 JE 47d8fc |
(736) 0x47e11c SUB %RBX,%RCX |
(736) 0x47e11f LEA -0x1(%RCX),%RAX |
(736) 0x47e123 CMP $0x2,%RAX |
(736) 0x47e127 JBE 47e161 |
(736) 0x47e129 ADD %R11,%RBX |
(736) 0x47e12c VBROADCASTSD %XMM12,%YMM9 |
(736) 0x47e131 VBROADCASTSD 0x13bd06(%RIP),%YMM10 |
(736) 0x47e13a LEA (%R13,%RBX,8),%R11 |
(736) 0x47e13f MOV %RCX,%RBX |
(736) 0x47e142 VMULPD (%R11),%YMM9,%YMM0 |
(736) 0x47e147 AND $-0x4,%RBX |
(736) 0x47e14b ADD %RBX,%R15 |
(736) 0x47e14e AND $0x3,%ECX |
(736) 0x47e151 VXORPD %YMM10,%YMM0,%YMM11 |
(736) 0x47e156 VMOVUPD %YMM11,(%R11) |
(736) 0x47e15b JE 47d8fc |
(736) 0x47e161 LEA (,%R15,8),%RCX |
(736) 0x47e169 VMOVQ 0x13bccf(%RIP),%XMM8 |
(736) 0x47e171 MOV -0x128(%RBP),%RDI |
(736) 0x47e178 LEA 0x1(%R15),%RDX |
(736) 0x47e17c LEA (%R13,%RCX,1),%RSI |
(736) 0x47e181 VMULSD (%RSI),%XMM12,%XMM13 |
(736) 0x47e185 VXORPD %XMM8,%XMM13,%XMM2 |
(736) 0x47e18a VMOVSD %XMM2,(%RSI) |
(736) 0x47e18e CMP %RDX,%RDI |
(736) 0x47e191 JLE 47d8fc |
(736) 0x47e197 LEA 0x8(%R13,%RCX,1),%RAX |
(736) 0x47e19c LEA 0x2(%R15),%R15 |
(736) 0x47e1a0 VMULSD (%RAX),%XMM12,%XMM1 |
(736) 0x47e1a4 VXORPD %XMM8,%XMM1,%XMM4 |
(736) 0x47e1a9 VMOVSD %XMM4,(%RAX) |
(736) 0x47e1ad CMP %R15,%RDI |
(736) 0x47e1b0 JLE 47d8fc |
(736) 0x47e1b6 LEA 0x10(%R13,%RCX,1),%R13 |
(736) 0x47e1bb INC %R8 |
(736) 0x47e1be DECQ -0x48(%RBP) |
(736) 0x47e1c2 VMULSD (%R13),%XMM12,%XMM12 |
(736) 0x47e1c8 VXORPD %XMM8,%XMM12,%XMM7 |
(736) 0x47e1cd VMOVSD %XMM7,(%R13) |
(736) 0x47e1d3 CMP %R8,-0x40(%RBP) |
(736) 0x47e1d7 JNE 47d90d |
0x47e1dd NOPL (%RAX) |
0x47e1e0 MOV %R14,%R13 |
0x47e1e3 VZEROUPPER |
0x47e1e6 CMPQ $0,-0x100(%RBP) |
0x47e1ee JNE 47f3c0 |
0x47e1f4 MOV -0x70(%RBP),%R8 |
0x47e1f8 MOV 0x130(%R8),%R14 |
0x47e1ff CMPQ $0,(%R14) |
0x47e203 JNE 47f370 |
0x47e209 ADD $0x308,%RSP |
0x47e210 POP %RBX |
0x47e211 POP %R12 |
0x47e213 POP %R9 |
0x47e215 POP %R14 |
0x47e217 POP %R15 |
0x47e219 POP %RBP |
0x47e21a LEA -0x10(%R9),%RSP |
0x47e21e POP %R13 |
0x47e220 RET |
0x47e221 NOPL (%RAX) |
(742) 0x47e228 MOV -0x120(%RBP),%RCX |
(742) 0x47e22f MOV 0x13b522(%RIP),%R10 |
(742) 0x47e236 MOV (%RCX,%RAX,8),%RCX |
(742) 0x47e23a VMOVQ %R10,%XMM9 |
(742) 0x47e23f VCOMISD (%RBX,%RCX,8),%XMM5 |
(742) 0x47e244 LEA (,%RCX,8),%R8 |
(742) 0x47e24c JA 47e256 |
(742) 0x47e24e VMOVSD 0x13c2c2(%RIP),%XMM9 |
(742) 0x47e256 MOV -0x120(%RBP),%R9 |
(742) 0x47e25d LEA 0x1(%RCX),%R10 |
(742) 0x47e261 MOV %R10,-0x1a0(%RBP) |
(742) 0x47e268 MOV 0x8(%R9,%RDI,1),%R9 |
(742) 0x47e26d MOV %R10,-0x208(%RBP) |
(742) 0x47e274 MOV %R9,-0x190(%RBP) |
(742) 0x47e27b CMP %R9,%R10 |
(742) 0x47e27e JGE 4809ee |
(742) 0x47e284 SUB %RCX,%R9 |
(742) 0x47e287 LEA -0x1(%R9),%R10 |
(742) 0x47e28b LEA -0x2(%R9),%RCX |
(742) 0x47e28f MOV %R10,-0x250(%RBP) |
(742) 0x47e296 CMP $0x6,%RCX |
(742) 0x47e29a JBE 480a11 |
(742) 0x47e2a0 LEA (%R8,%RBX,1),%RCX |
(742) 0x47e2a4 VXORPD %XMM0,%XMM0,%XMM0 |
(742) 0x47e2a8 SHR $0x3,%R10 |
(742) 0x47e2ac VPBROADCASTQ %R11,%ZMM12 |
(742) 0x47e2b2 KXNORB %K3,%K3,%K3 |
(742) 0x47e2b6 MOV %R10,%R8 |
(742) 0x47e2b9 MOV %RCX,-0x268(%RBP) |
(742) 0x47e2c0 ADD $0x8,%RCX |
(742) 0x47e2c4 VPBROADCASTQ %R13,%ZMM11 |
(742) 0x47e2ca SAL $0x6,%R8 |
(742) 0x47e2ce MOV %RCX,-0x260(%RBP) |
(742) 0x47e2d5 VBROADCASTSD %XMM9,%ZMM10 |
(742) 0x47e2db VMOVAPD %ZMM0,%ZMM13 |
(742) 0x47e2e1 LEA (%R8,%RCX,1),%R10 |
(742) 0x47e2e5 SUB $0x40,%R8 |
(742) 0x47e2e9 MOV %R10,-0x230(%RBP) |
(742) 0x47e2f0 SHR $0x6,%R8 |
(742) 0x47e2f4 MOV %RDX,%R10 |
(742) 0x47e2f7 SUB %RBX,%R10 |
(742) 0x47e2fa INC %R8 |
(742) 0x47e2fd ADD $0x8,%R10 |
(742) 0x47e301 AND $0x3,%R8D |
(742) 0x47e305 JE 480950 |
(742) 0x47e30b CMP $0x1,%R8 |
(742) 0x47e30f JE 47e3dc |
(742) 0x47e315 CMP $0x2,%R8 |
(742) 0x47e319 JE 47e37c |
(742) 0x47e31b VMOVDQU64 -0x8(%RCX,%R10,1),%ZMM14 |
(742) 0x47e326 KMOVB %K3,%K5 |
(742) 0x47e32a MOV -0x268(%RBP),%RCX |
(742) 0x47e331 VMOVAPD -0x170(%RBP),%ZMM2 |
(742) 0x47e33b VPGATHERQQ (%R14,%ZMM14,8),%ZMM1{%K5} |
(742) 0x47e342 VPCMPEQQ %ZMM12,%ZMM14,%K1 |
(742) 0x47e349 ADD $0x48,%RCX |
(742) 0x47e34d VPCMPNLTQ %ZMM11,%ZMM1,%K0 |
(742) 0x47e354 KORB %K0,%K1,%K4 |
(742) 0x47e358 VMOVUPD -0x40(%RCX),%ZMM2{%K4} |
(742) 0x47e35f VMULPD %ZMM2,%ZMM10,%ZMM14 |
(742) 0x47e365 VMOVAPD %ZMM2,-0x170(%RBP) |
(742) 0x47e36f VCMPPD $0x1,%ZMM0,%ZMM14,%K6{%K4} |
(742) 0x47e376 VMOVAPD %ZMM2,%ZMM0{%K6}{z} |
(742) 0x47e37c VMOVDQU64 -0x8(%RCX,%R10,1),%ZMM1 |
(742) 0x47e387 KMOVB %K3,%K7 |
(742) 0x47e38b VMOVAPD -0x170(%RBP),%ZMM14 |
(742) 0x47e395 ADD $0x40,%RCX |
(742) 0x47e399 VPGATHERQQ (%R14,%ZMM1,8),%ZMM2{%K7} |
(742) 0x47e3a0 VPCMPEQQ %ZMM12,%ZMM1,%K5 |
(742) 0x47e3a7 VPCMPNLTQ %ZMM11,%ZMM2,%K1 |
(742) 0x47e3ae KORB %K1,%K5,%K4 |
(742) 0x47e3b2 VMOVUPD -0x40(%RCX),%ZMM14{%K4} |
(742) 0x47e3b9 VMULPD %ZMM14,%ZMM10,%ZMM1 |
(742) 0x47e3bf VMOVAPD %ZMM14,-0x170(%RBP) |
(742) 0x47e3c9 VCMPPD $0x1,%ZMM13,%ZMM1,%K6{%K4} |
(742) 0x47e3d0 VMOVAPD %ZMM14,%ZMM2{%K6}{z} |
(742) 0x47e3d6 VADDPD %ZMM2,%ZMM0,%ZMM0 |
(742) 0x47e3dc VMOVDQU64 -0x8(%RCX,%R10,1),%ZMM14 |
(742) 0x47e3e7 KMOVB %K3,%K7 |
(742) 0x47e3eb VMOVAPD -0x170(%RBP),%ZMM2 |
(742) 0x47e3f5 ADD $0x40,%RCX |
(742) 0x47e3f9 MOV -0x230(%RBP),%R8 |
(742) 0x47e400 VPGATHERQQ (%R14,%ZMM14,8),%ZMM1{%K7} |
(742) 0x47e407 VPCMPEQQ %ZMM12,%ZMM14,%K5 |
(742) 0x47e40e VPCMPNLTQ %ZMM11,%ZMM1,%K0 |
(742) 0x47e415 KORB %K0,%K5,%K1 |
(742) 0x47e419 VMOVUPD -0x40(%RCX),%ZMM2{%K1} |
(742) 0x47e420 VMULPD %ZMM2,%ZMM10,%ZMM14 |
(742) 0x47e426 VMOVAPD %ZMM2,-0x170(%RBP) |
(742) 0x47e430 VCMPPD $0x1,%ZMM13,%ZMM14,%K4{%K1} |
(742) 0x47e437 VMOVAPD %ZMM2,%ZMM1{%K4}{z} |
(742) 0x47e43d VADDPD %ZMM1,%ZMM0,%ZMM0 |
(742) 0x47e443 CMP %R8,%RCX |
(742) 0x47e446 JE 47e596 |
(746) 0x47e44c VMOVDQU64 -0x8(%RCX,%R10,1),%ZMM14 |
(746) 0x47e457 KMOVB %K3,%K6 |
(746) 0x47e45b VMOVAPD -0x170(%RBP),%ZMM1 |
(746) 0x47e465 ADD $0x100,%RCX |
(746) 0x47e46c VPGATHERQQ (%R14,%ZMM14,8),%ZMM2{%K6} |
(746) 0x47e473 VPCMPEQQ %ZMM12,%ZMM14,%K7 |
(746) 0x47e47a KMOVB %K3,%K6 |
(746) 0x47e47e VPCMPNLTQ %ZMM11,%ZMM2,%K5 |
(746) 0x47e485 KORB %K5,%K7,%K1 |
(746) 0x47e489 VMOVUPD -0x100(%RCX),%ZMM1{%K1} |
(746) 0x47e490 VMULPD %ZMM10,%ZMM1,%ZMM14 |
(746) 0x47e496 VCMPPD $0x1,%ZMM13,%ZMM14,%K4{%K1} |
(746) 0x47e49d VMOVAPD %ZMM1,%ZMM2{%K4}{z} |
(746) 0x47e4a3 KMOVB %K3,%K4 |
(746) 0x47e4a7 VADDPD %ZMM2,%ZMM0,%ZMM0 |
(746) 0x47e4ad VMOVDQU64 -0xc8(%RCX,%R10,1),%ZMM2 |
(746) 0x47e4b8 VPGATHERQQ (%R14,%ZMM2,8),%ZMM14{%K6} |
(746) 0x47e4bf VPCMPEQQ %ZMM12,%ZMM2,%K7 |
(746) 0x47e4c6 VPCMPNLTQ %ZMM11,%ZMM14,%K0 |
(746) 0x47e4cd KORB %K0,%K7,%K5 |
(746) 0x47e4d1 VMOVUPD -0xc0(%RCX),%ZMM1{%K5} |
(746) 0x47e4d8 VMULPD %ZMM10,%ZMM1,%ZMM2 |
(746) 0x47e4de VCMPPD $0x1,%ZMM13,%ZMM2,%K1{%K5} |
(746) 0x47e4e5 VMOVDQU64 -0x88(%RCX,%R10,1),%ZMM2 |
(746) 0x47e4f0 VPCMPEQQ %ZMM12,%ZMM2,%K6 |
(746) 0x47e4f7 VMOVAPD %ZMM1,%ZMM14{%K1}{z} |
(746) 0x47e4fd VADDPD %ZMM14,%ZMM0,%ZMM0 |
(746) 0x47e503 VPGATHERQQ (%R14,%ZMM2,8),%ZMM14{%K4} |
(746) 0x47e50a KMOVB %K3,%K4 |
(746) 0x47e50e VPCMPNLTQ %ZMM11,%ZMM14,%K7 |
(746) 0x47e515 KORB %K7,%K6,%K5 |
(746) 0x47e519 VMOVUPD -0x80(%RCX),%ZMM1{%K5} |
(746) 0x47e520 VMULPD %ZMM10,%ZMM1,%ZMM2 |
(746) 0x47e526 VCMPPD $0x1,%ZMM13,%ZMM2,%K1{%K5} |
(746) 0x47e52d VMOVDQU64 -0x48(%RCX,%R10,1),%ZMM2 |
(746) 0x47e538 VPCMPEQQ %ZMM12,%ZMM2,%K6 |
(746) 0x47e53f VMOVAPD %ZMM1,%ZMM14{%K1}{z} |
(746) 0x47e545 VADDPD %ZMM14,%ZMM0,%ZMM0 |
(746) 0x47e54b VPGATHERQQ (%R14,%ZMM2,8),%ZMM14{%K4} |
(746) 0x47e552 VPCMPNLTQ %ZMM11,%ZMM14,%K0 |
(746) 0x47e559 KORB %K0,%K6,%K7 |
(746) 0x47e55d VMOVUPD -0x40(%RCX),%ZMM1{%K7} |
(746) 0x47e564 VMOVAPD %ZMM1,%ZMM2 |
(746) 0x47e56a VMOVAPD %ZMM1,-0x170(%RBP) |
(746) 0x47e574 VMULPD %ZMM1,%ZMM10,%ZMM1 |
(746) 0x47e57a VCMPPD $0x1,%ZMM13,%ZMM1,%K5{%K7} |
(746) 0x47e581 VMOVAPD %ZMM2,%ZMM14{%K5}{z} |
(746) 0x47e587 VADDPD %ZMM14,%ZMM0,%ZMM0 |
(746) 0x47e58d CMP %R8,%RCX |
(746) 0x47e590 JNE 47e44c |
(742) 0x47e596 VEXTRACTF64X4 $0x1,%ZMM0,%YMM12 |
(742) 0x47e59d MOV -0x250(%RBP),%R10 |
(742) 0x47e5a4 MOV -0x1a0(%RBP),%R8 |
(742) 0x47e5ab VADDPD %YMM0,%YMM12,%YMM11 |
(742) 0x47e5af MOV %R10,%RCX |
(742) 0x47e5b2 AND $-0x8,%RCX |
(742) 0x47e5b6 VEXTRACTF64X2 $0x1,%YMM11,%XMM10 |
(742) 0x47e5bd ADD %RCX,%R8 |
(742) 0x47e5c0 AND $0x7,%R10D |
(742) 0x47e5c4 VADDPD %XMM11,%XMM10,%XMM13 |
(742) 0x47e5c9 VADDPD %YMM12,%YMM0,%YMM11 |
(742) 0x47e5ce VUNPCKHPD %XMM13,%XMM13,%XMM2 |
(742) 0x47e5d3 VADDPD %XMM13,%XMM2,%XMM1 |
(742) 0x47e5d8 VADDSD %XMM1,%XMM3,%XMM10 |
(742) 0x47e5dc JE 47e728 |
(742) 0x47e5e2 SUB %RCX,%R9 |
(742) 0x47e5e5 LEA -0x1(%R9),%R10 |
(742) 0x47e5e9 SUB $0x2,%R9 |
(742) 0x47e5ed CMP $0x2,%R9 |
(742) 0x47e5f1 JBE 47e682 |
(742) 0x47e5f7 MOV -0x1a0(%RBP),%R9 |
(742) 0x47e5fe KMOVB %K2,%K3 |
(742) 0x47e602 VMOVAPD -0x1f0(%RBP),%YMM13 |
(742) 0x47e60a VBROADCASTSD %XMM9,%YMM14 |
(742) 0x47e60f ADD %R9,%RCX |
(742) 0x47e612 VMOVDQU (%RDX,%RCX,8),%YMM12 |
(742) 0x47e617 VPGATHERQQ (%R14,%YMM12,8),%YMM10{%K3} |
(742) 0x47e61e VPCMPEQQ %YMM12,%YMM8,%K1 |
(742) 0x47e625 VPCMPNLTQ %YMM7,%YMM10,%K4 |
(742) 0x47e62c KORB %K4,%K1,%K6 |
(742) 0x47e630 VMOVUPD (%RBX,%RCX,8),%YMM13{%K6} |
(742) 0x47e637 VMULPD %YMM13,%YMM14,%YMM2 |
(742) 0x47e63c VMOVAPD %YMM13,-0x1f0(%RBP) |
(742) 0x47e644 VCMPPD $0x1,%YMM6,%YMM2,%K7{%K6} |
(742) 0x47e64b VMOVAPD %YMM13,%YMM13{%K7}{z} |
(742) 0x47e651 VADDPD %YMM13,%YMM11,%YMM11 |
(742) 0x47e656 VEXTRACTF64X2 $0x1,%YMM11,%XMM1 |
(742) 0x47e65d VADDPD %XMM11,%XMM1,%XMM14 |
(742) 0x47e662 VUNPCKHPD %XMM14,%XMM14,%XMM0 |
(742) 0x47e667 VADDPD %XMM14,%XMM0,%XMM10 |
(742) 0x47e66c VADDSD %XMM10,%XMM3,%XMM10 |
(742) 0x47e671 TEST $0x3,%R10B |
(742) 0x47e675 JE 47e728 |
(742) 0x47e67b AND $-0x4,%R10 |
(742) 0x47e67f ADD %R10,%R8 |
(742) 0x47e682 MOV (%RDX,%R8,8),%R10 |
(742) 0x47e686 LEA (,%R8,8),%RCX |
(742) 0x47e68e CMP (%R14,%R10,8),%R13 |
(742) 0x47e692 JLE 47e699 |
(742) 0x47e694 CMP %R11,%R10 |
(742) 0x47e697 JNE 47e6b2 |
(742) 0x47e699 VMOVSD (%RBX,%RCX,1),%XMM12 |
(742) 0x47e69e VXORPD %XMM2,%XMM2,%XMM2 |
(742) 0x47e6a2 VMULSD %XMM9,%XMM12,%XMM13 |
(742) 0x47e6a7 VCOMISD %XMM13,%XMM2 |
(742) 0x47e6ac JA 4805c4 |
(742) 0x47e6b2 LEA 0x1(%R8),%R9 |
(742) 0x47e6b6 CMP %R9,-0x190(%RBP) |
(742) 0x47e6bd JLE 47e728 |
(742) 0x47e6bf MOV 0x8(%RDX,%RCX,1),%R10 |
(742) 0x47e6c4 CMP (%R14,%R10,8),%R13 |
(742) 0x47e6c8 JLE 47e6cf |
(742) 0x47e6ca CMP %R10,%R11 |
(742) 0x47e6cd JNE 47e6e9 |
(742) 0x47e6cf VMOVSD 0x8(%RBX,%RCX,1),%XMM11 |
(742) 0x47e6d5 VXORPD %XMM14,%XMM14,%XMM14 |
(742) 0x47e6da VMULSD %XMM9,%XMM11,%XMM1 |
(742) 0x47e6df VCOMISD %XMM1,%XMM14 |
(742) 0x47e6e3 JA 4805ce |
(742) 0x47e6e9 MOV -0x190(%RBP),%R9 |
(742) 0x47e6f0 ADD $0x2,%R8 |
(742) 0x47e6f4 CMP %R9,%R8 |
(742) 0x47e6f7 JGE 47e728 |
(742) 0x47e6f9 MOV 0x10(%RDX,%RCX,1),%R8 |
(742) 0x47e6fe CMP (%R14,%R8,8),%R13 |
(742) 0x47e702 JLE 47e709 |
(742) 0x47e704 CMP %R8,%R11 |
(742) 0x47e707 JNE 47e728 |
(742) 0x47e709 VMOVSD 0x10(%RBX,%RCX,1),%XMM0 |
(742) 0x47e70f VXORPD %XMM13,%XMM13,%XMM13 |
(742) 0x47e714 VMULSD %XMM0,%XMM9,%XMM12 |
(742) 0x47e718 VCOMISD %XMM12,%XMM13 |
(742) 0x47e71d JA 4805d8 |
(742) 0x47e723 NOPL (%RAX,%RAX,1) |
(742) 0x47e728 CMPQ $0x1,-0x58(%RBP) |
(742) 0x47e72d JG 47f560 |
(742) 0x47e733 VCOMISD %XMM5,%XMM10 |
(742) 0x47e737 VMOVSD (%RBX,%RSI,8),%XMM2 |
(742) 0x47e73c JNE 47feb0 |
(742) 0x47e742 VADDSD %XMM2,%XMM4,%XMM4 |
(742) 0x47e746 JMP 47dbfa |
0x47e74b NOPL (%RAX,%RAX,1) |
(762) 0x47e750 MOV -0x68(%RBP),%R15 |
(762) 0x47e754 MOV (%R15,%R9,8),%RDX |
(762) 0x47e758 ADD %R15,%RDI |
(762) 0x47e75b CMP (%RDI),%RDX |
(762) 0x47e75e JGE 47ce18 |
(762) 0x47e764 MOV -0x70(%RBP),%R9 |
(762) 0x47e768 CMPQ $0,-0x178(%RBP) |
(762) 0x47e770 MOV 0xf0(%R9),%R12 |
(762) 0x47e777 MOV (%R12),%R15 |
(762) 0x47e77b JE 4804a0 |
(762) 0x47e781 MOV %R10,-0x130(%RBP) |
(762) 0x47e788 MOV %R8,-0x2f0(%RBP) |
(762) 0x47e78f MOV %R13,-0x128(%RBP) |
(762) 0x47e796 MOV -0xf8(%RBP),%R13 |
(762) 0x47e79d MOV %RSI,-0x270(%RBP) |
(762) 0x47e7a4 MOV -0x178(%RBP),%RSI |
(762) 0x47e7ab NOPL (%RAX,%RAX,1) |
(764) 0x47e7b0 MOV (%R13,%RDX,8),%R10 |
(764) 0x47e7b5 MOV (%RSI,%R10,8),%R9 |
(764) 0x47e7b9 CMPQ $0,(%R15,%R9,8) |
(764) 0x47e7be LEA (,%R9,8),%R12 |
(764) 0x47e7c6 JS 47e7f3 |
(764) 0x47e7c8 MOV -0x60(%RBP),%R8 |
(764) 0x47e7cc ADD %R8,%R12 |
(764) 0x47e7cf MOV -0x38(%RBP),%R8 |
(764) 0x47e7d3 MOV (%R12),%R10 |
(764) 0x47e7d7 CMP %R10,(%R8,%RAX,8) |
(764) 0x47e7db JLE 47e7f3 |
(764) 0x47e7dd MOV -0xf0(%RBP),%R8 |
(764) 0x47e7e4 MOVQ $0x1,(%R8,%R9,8) |
(764) 0x47e7ec MOV %RCX,(%R12) |
(764) 0x47e7f0 INC %RCX |
(764) 0x47e7f3 INC %RDX |
(764) 0x47e7f6 CMP %RDX,(%RDI) |
(764) 0x47e7f9 JG 47e7b0 |
(762) 0x47e7fb MOV -0x128(%RBP),%R13 |
(762) 0x47e802 MOV -0x130(%RBP),%R10 |
(762) 0x47e809 MOV -0x2f0(%RBP),%R8 |
(762) 0x47e810 MOV -0x270(%RBP),%RSI |
(762) 0x47e817 JMP 47ce18 |
0x47e81c NOPL (%RAX) |
0x47e820 CMP $0x1,%R8 |
0x47e824 JLE 47ea84 |
0x47e82a MOV $0x1,%R12D |
0x47e830 MOV %R8,%R10 |
0x47e833 SUB %R12,%R10 |
0x47e836 AND $0x7,%R10D |
0x47e83a JE 480b25 |
0x47e840 CMP $0x1,%R10 |
0x47e844 JE 47e94b |
0x47e84a CMP $0x2,%R10 |
0x47e84e JE 47e926 |
0x47e854 CMP $0x3,%R10 |
0x47e858 JE 47e901 |
0x47e85e CMP $0x4,%R10 |
0x47e862 JE 47e8dc |
0x47e864 CMP $0x5,%R10 |
0x47e868 JE 47e8b7 |
0x47e86a CMP $0x6,%R10 |
0x47e86e JE 47e892 |
0x47e870 MOV (%R11),%R15 |
0x47e873 MOV -0xb0(%RBP),%RDX |
0x47e87a MOV $0x2,%R12D |
0x47e880 ADD %R15,0x8(%R11) |
0x47e884 MOV (%RDX),%RAX |
0x47e887 ADD %RAX,0x8(%RDX) |
0x47e88b MOV (%RCX),%RSI |
0x47e88e ADD %RSI,0x8(%RCX) |
0x47e892 MOV -0x8(%R11,%R12,8),%RDI |
0x47e897 MOV -0xb0(%RBP),%RBX |
0x47e89e ADD %RDI,(%R11,%R12,8) |
0x47e8a2 MOV -0x8(%RBX,%R12,8),%R9 |
0x47e8a7 ADD %R9,(%RBX,%R12,8) |
0x47e8ab MOV -0x8(%RCX,%R12,8),%R10 |
0x47e8b0 ADD %R10,(%RCX,%R12,8) |
0x47e8b4 INC %R12 |
0x47e8b7 MOV -0x8(%R11,%R12,8),%R15 |
0x47e8bc MOV -0xb0(%RBP),%RAX |
0x47e8c3 ADD %R15,(%R11,%R12,8) |
0x47e8c7 MOV -0x8(%RAX,%R12,8),%RDX |
0x47e8cc ADD %RDX,(%RAX,%R12,8) |
0x47e8d0 MOV -0x8(%RCX,%R12,8),%RSI |
0x47e8d5 ADD %RSI,(%RCX,%R12,8) |
0x47e8d9 INC %R12 |
0x47e8dc MOV -0x8(%R11,%R12,8),%RDI |
0x47e8e1 MOV -0xb0(%RBP),%RBX |
0x47e8e8 ADD %RDI,(%R11,%R12,8) |
0x47e8ec MOV -0x8(%RBX,%R12,8),%R9 |
0x47e8f1 ADD %R9,(%RBX,%R12,8) |
0x47e8f5 MOV -0x8(%RCX,%R12,8),%R10 |
0x47e8fa ADD %R10,(%RCX,%R12,8) |
0x47e8fe INC %R12 |
0x47e901 MOV -0x8(%R11,%R12,8),%R15 |
0x47e906 MOV -0xb0(%RBP),%RAX |
0x47e90d ADD %R15,(%R11,%R12,8) |
0x47e911 MOV -0x8(%RAX,%R12,8),%RDX |
0x47e916 ADD %RDX,(%RAX,%R12,8) |
0x47e91a MOV -0x8(%RCX,%R12,8),%RSI |
0x47e91f ADD %RSI,(%RCX,%R12,8) |
0x47e923 INC %R12 |
0x47e926 MOV -0x8(%R11,%R12,8),%RDI |
0x47e92b MOV -0xb0(%RBP),%RBX |
0x47e932 ADD %RDI,(%R11,%R12,8) |
0x47e936 MOV -0x8(%RBX,%R12,8),%R9 |
0x47e93b ADD %R9,(%RBX,%R12,8) |
0x47e93f MOV -0x8(%RCX,%R12,8),%R10 |
0x47e944 ADD %R10,(%RCX,%R12,8) |
0x47e948 INC %R12 |
0x47e94b MOV -0x8(%R11,%R12,8),%R15 |
0x47e950 MOV -0xb0(%RBP),%RAX |
0x47e957 ADD %R15,(%R11,%R12,8) |
0x47e95b MOV %RAX,%RBX |
0x47e95e MOV -0x8(%RAX,%R12,8),%RDX |
0x47e963 ADD %RDX,(%RAX,%R12,8) |
0x47e967 MOV -0x8(%RCX,%R12,8),%RSI |
0x47e96c ADD %RSI,(%RCX,%R12,8) |
0x47e970 INC %R12 |
0x47e973 CMP %R12,%R8 |
0x47e976 JE 47ea84 |
(755) 0x47e97c MOV -0x8(%R11,%R12,8),%RDI |
(755) 0x47e981 LEA 0x1(%R12),%R15 |
(755) 0x47e986 ADD %RDI,(%R11,%R12,8) |
(755) 0x47e98a LEA 0x2(%R12),%RDI |
(755) 0x47e98f MOV -0x8(%RBX,%R12,8),%R9 |
(755) 0x47e994 ADD %R9,(%RBX,%R12,8) |
(755) 0x47e998 MOV -0x8(%RCX,%R12,8),%R10 |
(755) 0x47e99d ADD %R10,(%RCX,%R12,8) |
(755) 0x47e9a1 MOV -0x8(%R11,%R15,8),%RAX |
(755) 0x47e9a6 ADD %RAX,(%R11,%R15,8) |
(755) 0x47e9aa LEA 0x3(%R12),%RAX |
(755) 0x47e9af MOV -0x8(%RBX,%R15,8),%RDX |
(755) 0x47e9b4 ADD %RDX,(%RBX,%R15,8) |
(755) 0x47e9b8 MOV -0x8(%RCX,%R15,8),%RSI |
(755) 0x47e9bd ADD %RSI,(%RCX,%R15,8) |
(755) 0x47e9c1 MOV -0x8(%R11,%RDI,8),%R9 |
(755) 0x47e9c6 ADD %R9,(%R11,%RDI,8) |
(755) 0x47e9ca MOV -0x8(%RBX,%RDI,8),%R10 |
(755) 0x47e9cf ADD %R10,(%RBX,%RDI,8) |
(755) 0x47e9d3 LEA 0x4(%R12),%R10 |
(755) 0x47e9d8 MOV -0x8(%RCX,%RDI,8),%R15 |
(755) 0x47e9dd ADD %R15,(%RCX,%RDI,8) |
(755) 0x47e9e1 MOV -0x8(%R11,%RAX,8),%RDX |
(755) 0x47e9e6 ADD %RDX,(%R11,%RAX,8) |
(755) 0x47e9ea LEA 0x5(%R12),%RDX |
(755) 0x47e9ef MOV -0x8(%RBX,%RAX,8),%RSI |
(755) 0x47e9f4 ADD %RSI,(%RBX,%RAX,8) |
(755) 0x47e9f8 MOV -0x8(%RCX,%RAX,8),%RDI |
(755) 0x47e9fd ADD %RDI,(%RCX,%RAX,8) |
(755) 0x47ea01 MOV -0x8(%R11,%R10,8),%R9 |
(755) 0x47ea06 ADD %R9,(%R11,%R10,8) |
(755) 0x47ea0a MOV -0x8(%RBX,%R10,8),%R15 |
(755) 0x47ea0f ADD %R15,(%RBX,%R10,8) |
(755) 0x47ea13 LEA 0x6(%R12),%R15 |
(755) 0x47ea18 MOV -0x8(%RCX,%R10,8),%RAX |
(755) 0x47ea1d ADD %RAX,(%RCX,%R10,8) |
(755) 0x47ea21 MOV -0x8(%R11,%RDX,8),%RSI |
(755) 0x47ea26 ADD %RSI,(%R11,%RDX,8) |
(755) 0x47ea2a LEA 0x7(%R12),%RSI |
(755) 0x47ea2f ADD $0x8,%R12 |
(755) 0x47ea33 MOV -0x8(%RBX,%RDX,8),%RDI |
(755) 0x47ea38 ADD %RDI,(%RBX,%RDX,8) |
(755) 0x47ea3c MOV -0x8(%RCX,%RDX,8),%R10 |
(755) 0x47ea41 ADD %R10,(%RCX,%RDX,8) |
(755) 0x47ea45 MOV -0x8(%R11,%R15,8),%R9 |
(755) 0x47ea4a ADD %R9,(%R11,%R15,8) |
(755) 0x47ea4e MOV -0x8(%RBX,%R15,8),%RAX |
(755) 0x47ea53 ADD %RAX,(%RBX,%R15,8) |
(755) 0x47ea57 MOV -0x8(%RCX,%R15,8),%RDX |
(755) 0x47ea5c ADD %RDX,(%RCX,%R15,8) |
(755) 0x47ea60 MOV -0x8(%R11,%RSI,8),%RDI |
(755) 0x47ea65 ADD %RDI,(%R11,%RSI,8) |
(755) 0x47ea69 MOV -0x8(%RBX,%RSI,8),%R10 |
(755) 0x47ea6e ADD %R10,(%RBX,%RSI,8) |
(755) 0x47ea72 MOV -0x8(%RCX,%RSI,8),%R15 |
(755) 0x47ea77 ADD %R15,(%RCX,%RSI,8) |
(755) 0x47ea7b CMP %R12,%R8 |
(755) 0x47ea7e JNE 47e97c |
0x47ea84 VMOVSD %XMM1,-0xb0(%RBP) |
0x47ea8c CALL 411290 <GOMP_barrier@plt> |
0x47ea91 CALL 411290 <GOMP_barrier@plt> |
0x47ea96 CMPQ $0x4,-0x250(%RBP) |
0x47ea9e VMOVSD -0xb0(%RBP),%XMM3 |
0x47eaa6 JE 4805e1 |
0x47eaac MOV -0x100(%RBP),%R11 |
0x47eab3 MOV -0x58(%RBP),%RCX |
0x47eab7 MOV -0x38(%RBP),%RAX |
0x47eabb MOV -0x70(%RBP),%R9 |
0x47eabf MOV (%RCX,%R11,8),%RBX |
0x47eac3 MOV (%RAX,%R11,8),%RDI |
0x47eac7 MOV %RBX,0xe0(%R9) |
0x47eace MOV %RDI,0xe8(%R9) |
0x47ead5 TEST %RBX,%RBX |
0x47ead8 JNE 480520 |
0x47eade TEST %RDI,%RDI |
0x47eae1 JNE 480570 |
0x47eae7 MOV -0x70(%RBP),%RDX |
0x47eaeb MOV 0x38(%RDX),%RSI |
0x47eaef CMPQ $0x1,(%RSI) |
0x47eaf3 JLE 47d7e5 |
0x47eaf9 MOV -0x70(%RBP),%R10 |
0x47eafd CMPQ $0,-0x100(%RBP) |
0x47eb05 MOV 0x180(%R10),%R8 |
0x47eb0c MOV 0x130(%R10),%R9 |
0x47eb13 MOV (%R8),%RSI |
0x47eb16 JLE 4809aa |
0x47eb1c MOV -0x100(%RBP),%R15 |
0x47eb23 LEA -0x1(%R15),%RBX |
0x47eb27 CMP $0x6,%RBX |
0x47eb2b JBE 480d2a |
0x47eb31 SHR $0x3,%R15 |
0x47eb35 MOV -0x48(%RBP),%R11 |
0x47eb39 VPBROADCASTQ -0x190(%RBP),%ZMM12 |
0x47eb40 MOV %R15,%RDX |
0x47eb43 SAL $0x6,%RDX |
0x47eb47 MOV %R11,%R10 |
0x47eb4a LEA (%RDX,%R11,1),%RDI |
0x47eb4e SUB $0x40,%RDX |
0x47eb52 SHR $0x6,%RDX |
0x47eb56 INC %RDX |
0x47eb59 AND $0x7,%EDX |
0x47eb5c JE 47ebf5 |
0x47eb62 CMP $0x1,%RDX |
0x47eb66 JE 47ebdf |
0x47eb68 CMP $0x2,%RDX |
0x47eb6c JE 47ebce |
0x47eb6e CMP $0x3,%RDX |
0x47eb72 JE 47ebbd |
0x47eb74 CMP $0x4,%RDX |
0x47eb78 JE 47ebac |
0x47eb7a CMP $0x5,%RDX |
0x47eb7e JE 47eb9b |
0x47eb80 CMP $0x6,%RDX |
0x47eb84 JNE 480c3f |
0x47eb8a VPADDQ (%R10),%ZMM12,%ZMM14 |
0x47eb90 ADD $0x40,%R10 |
0x47eb94 VMOVDQU64 %ZMM14,-0x40(%R10) |
0x47eb9b VPADDQ (%R10),%ZMM12,%ZMM15 |
0x47eba1 ADD $0x40,%R10 |
0x47eba5 VMOVDQU64 %ZMM15,-0x40(%R10) |
0x47ebac VPADDQ (%R10),%ZMM12,%ZMM6 |
0x47ebb2 ADD $0x40,%R10 |
0x47ebb6 VMOVDQU64 %ZMM6,-0x40(%R10) |
0x47ebbd VPADDQ (%R10),%ZMM12,%ZMM0 |
0x47ebc3 ADD $0x40,%R10 |
0x47ebc7 VMOVDQU64 %ZMM0,-0x40(%R10) |
0x47ebce VPADDQ (%R10),%ZMM12,%ZMM1 |
0x47ebd4 ADD $0x40,%R10 |
0x47ebd8 VMOVDQU64 %ZMM1,-0x40(%R10) |
0x47ebdf VPADDQ (%R10),%ZMM12,%ZMM2 |
0x47ebe5 ADD $0x40,%R10 |
0x47ebe9 VMOVDQU64 %ZMM2,-0x40(%R10) |
0x47ebf0 CMP %RDI,%R10 |
0x47ebf3 JE 47ec70 |
(754) 0x47ebf5 VPADDQ (%R10),%ZMM12,%ZMM7 |
(754) 0x47ebfb VPADDQ 0x40(%R10),%ZMM12,%ZMM8 |
(754) 0x47ec02 ADD $0x200,%R10 |
(754) 0x47ec09 VPADDQ -0x180(%R10),%ZMM12,%ZMM9 |
(754) 0x47ec10 VPADDQ -0x140(%R10),%ZMM12,%ZMM4 |
(754) 0x47ec17 VPADDQ -0x100(%R10),%ZMM12,%ZMM5 |
(754) 0x47ec1e VPADDQ -0xc0(%R10),%ZMM12,%ZMM10 |
(754) 0x47ec25 VMOVDQU64 %ZMM7,-0x200(%R10) |
(754) 0x47ec2c VPADDQ -0x80(%R10),%ZMM12,%ZMM11 |
(754) 0x47ec33 VPADDQ -0x40(%R10),%ZMM12,%ZMM13 |
(754) 0x47ec3a VMOVDQU64 %ZMM8,-0x1c0(%R10) |
(754) 0x47ec41 VMOVDQU64 %ZMM9,-0x180(%R10) |
(754) 0x47ec48 VMOVDQU64 %ZMM4,-0x140(%R10) |
(754) 0x47ec4f VMOVDQU64 %ZMM5,-0x100(%R10) |
(754) 0x47ec56 VMOVDQU64 %ZMM10,-0xc0(%R10) |
(754) 0x47ec5d VMOVDQU64 %ZMM11,-0x80(%R10) |
(754) 0x47ec64 VMOVDQU64 %ZMM13,-0x40(%R10) |
(754) 0x47ec6b CMP %RDI,%R10 |
(754) 0x47ec6e JNE 47ebf5 |
0x47ec70 MOV -0x100(%RBP),%R8 |
0x47ec77 MOV %R8,%RAX |
0x47ec7a AND $-0x8,%RAX |
0x47ec7e MOV %RAX,%R12 |
0x47ec81 CMP %RAX,%R8 |
0x47ec84 JE 480cce |
0x47ec8a MOV -0x100(%RBP),%R15 |
0x47ec91 SUB %R12,%R15 |
0x47ec94 LEA -0x1(%R15),%RCX |
0x47ec98 CMP $0x2,%RCX |
0x47ec9c JBE 47eccb |
0x47ec9e MOV -0x48(%RBP),%R11 |
0x47eca2 VPBROADCASTQ -0x190(%RBP),%YMM14 |
0x47ecab MOV %R15,%RDX |
0x47ecae AND $-0x4,%RDX |
0x47ecb2 LEA (%R11,%R12,8),%R12 |
0x47ecb6 ADD %RDX,%RAX |
0x47ecb9 AND $0x3,%R15D |
0x47ecbd VPADDQ (%R12),%YMM14,%YMM15 |
0x47ecc3 VMOVDQU %YMM15,(%R12) |
0x47ecc9 JE 47ed05 |
0x47eccb MOV -0x48(%RBP),%R8 |
0x47eccf MOV -0x190(%RBP),%R15 |
0x47ecd6 LEA (,%RAX,8),%RDI |
0x47ecde LEA 0x1(%RAX),%RCX |
0x47ece2 MOV -0x100(%RBP),%R10 |
0x47ece9 ADD %R15,(%R8,%RDI,1) |
0x47eced CMP %RCX,%R10 |
0x47ecf0 JLE 47ed05 |
0x47ecf2 ADD $0x2,%RAX |
0x47ecf6 ADD %R15,0x8(%R8,%RDI,1) |
0x47ecfb CMP %RAX,%R10 |
0x47ecfe JLE 47ed05 |
0x47ed00 ADD %R15,0x10(%R8,%RDI,1) |
0x47ed05 MOV (%R9),%RCX |
0x47ed08 MOV -0x260(%RBP),%R8 |
0x47ed0f VMOVSD %XMM3,-0xb0(%RBP) |
0x47ed17 MOV -0x48(%RBP),%RDX |
0x47ed1b MOV -0x268(%RBP),%RDI |
0x47ed22 VZEROUPPER |
0x47ed25 CALL 54fcb0 <hypre_alt_insert_new_nodes> |
0x47ed2a CMP $0x6,%RBX |
0x47ed2e VMOVSD -0xb0(%RBP),%XMM3 |
0x47ed36 JBE 480d23 |
0x47ed3c VPBROADCASTQ -0x190(%RBP),%ZMM12 |
0x47ed43 MOV -0x100(%RBP),%RBX |
0x47ed4a MOV -0x48(%RBP),%R9 |
0x47ed4e SHR $0x3,%RBX |
0x47ed52 MOV %R9,%RAX |
0x47ed55 SAL $0x6,%RBX |
0x47ed59 LEA (%RBX,%R9,1),%R11 |
0x47ed5d SUB $0x40,%RBX |
0x47ed61 SHR $0x6,%RBX |
0x47ed65 INC %RBX |
0x47ed68 AND $0x7,%EBX |
0x47ed6b JE 47ee30 |
0x47ed71 CMP $0x1,%RBX |
0x47ed75 JE 47ee10 |
0x47ed7b CMP $0x2,%RBX |
0x47ed7f JE 47edf9 |
0x47ed81 CMP $0x3,%RBX |
0x47ed85 JE 47ede2 |
0x47ed87 CMP $0x4,%RBX |
0x47ed8b JE 47edcb |
0x47ed8d CMP $0x5,%RBX |
0x47ed91 JE 47edb4 |
0x47ed93 CMP $0x6,%RBX |
0x47ed97 JNE 480c1a |
0x47ed9d VMOVDQU64 (%RAX),%ZMM1 |
0x47eda3 ADD $0x40,%RAX |
0x47eda7 VPSUBQ %ZMM12,%ZMM1,%ZMM2 |
0x47edad VMOVDQU64 %ZMM2,-0x40(%RAX) |
0x47edb4 VMOVDQU64 (%RAX),%ZMM7 |
0x47edba ADD $0x40,%RAX |
0x47edbe VPSUBQ %ZMM12,%ZMM7,%ZMM8 |
0x47edc4 VMOVDQU64 %ZMM8,-0x40(%RAX) |
0x47edcb VMOVDQU64 (%RAX),%ZMM9 |
0x47edd1 ADD $0x40,%RAX |
0x47edd5 VPSUBQ %ZMM12,%ZMM9,%ZMM4 |
0x47eddb VMOVDQU64 %ZMM4,-0x40(%RAX) |
0x47ede2 VMOVDQU64 (%RAX),%ZMM5 |
0x47ede8 ADD $0x40,%RAX |
0x47edec VPSUBQ %ZMM12,%ZMM5,%ZMM10 |
0x47edf2 VMOVDQU64 %ZMM10,-0x40(%RAX) |
0x47edf9 VMOVDQU64 (%RAX),%ZMM11 |
0x47edff ADD $0x40,%RAX |
0x47ee03 VPSUBQ %ZMM12,%ZMM11,%ZMM13 |
0x47ee09 VMOVDQU64 %ZMM13,-0x40(%RAX) |
0x47ee10 VMOVDQU64 (%RAX),%ZMM14 |
0x47ee16 ADD $0x40,%RAX |
0x47ee1a VPSUBQ %ZMM12,%ZMM14,%ZMM15 |
0x47ee20 VMOVDQU64 %ZMM15,-0x40(%RAX) |
0x47ee27 CMP %R11,%RAX |
0x47ee2a JE 47eede |
(753) 0x47ee30 VMOVDQU64 (%RAX),%ZMM6 |
(753) 0x47ee36 VMOVDQU64 0x40(%RAX),%ZMM1 |
(753) 0x47ee3d ADD $0x200,%RAX |
(753) 0x47ee43 VMOVDQU64 -0x180(%RAX),%ZMM7 |
(753) 0x47ee4a VMOVDQU64 -0x140(%RAX),%ZMM9 |
(753) 0x47ee51 VPSUBQ %ZMM12,%ZMM6,%ZMM0 |
(753) 0x47ee57 VMOVDQU64 -0x100(%RAX),%ZMM5 |
(753) 0x47ee5e VMOVDQU64 -0xc0(%RAX),%ZMM11 |
(753) 0x47ee65 VPSUBQ %ZMM12,%ZMM1,%ZMM2 |
(753) 0x47ee6b VMOVDQU64 -0x80(%RAX),%ZMM14 |
(753) 0x47ee72 VMOVDQU64 -0x40(%RAX),%ZMM6 |
(753) 0x47ee79 VMOVDQU64 %ZMM0,-0x200(%RAX) |
(753) 0x47ee80 VPSUBQ %ZMM12,%ZMM7,%ZMM8 |
(753) 0x47ee86 VPSUBQ %ZMM12,%ZMM9,%ZMM4 |
(753) 0x47ee8c VPSUBQ %ZMM12,%ZMM5,%ZMM10 |
(753) 0x47ee92 VMOVDQU64 %ZMM2,-0x1c0(%RAX) |
(753) 0x47ee99 VPSUBQ %ZMM12,%ZMM11,%ZMM13 |
(753) 0x47ee9f VPSUBQ %ZMM12,%ZMM14,%ZMM15 |
(753) 0x47eea5 VMOVDQU64 %ZMM8,-0x180(%RAX) |
(753) 0x47eeac VPSUBQ %ZMM12,%ZMM6,%ZMM0 |
(753) 0x47eeb2 VMOVDQU64 %ZMM4,-0x140(%RAX) |
(753) 0x47eeb9 VMOVDQU64 %ZMM10,-0x100(%RAX) |
(753) 0x47eec0 VMOVDQU64 %ZMM13,-0xc0(%RAX) |
(753) 0x47eec7 VMOVDQU64 %ZMM15,-0x80(%RAX) |
(753) 0x47eece VMOVDQU64 %ZMM0,-0x40(%RAX) |
(753) 0x47eed5 CMP %R11,%RAX |
(753) 0x47eed8 JNE 47ee30 |
0x47eede MOV -0x100(%RBP),%RDX |
0x47eee5 MOV %RDX,%RDI |
0x47eee8 AND $-0x8,%RDI |
0x47eeec MOV %RDI,-0x118(%RBP) |
0x47eef3 MOV %RDI,%RSI |
0x47eef6 CMP %RDI,%RDX |
0x47eef9 JE 48089a |
0x47eeff MOV -0x100(%RBP),%R8 |
0x47ef06 SUB %RSI,%R8 |
0x47ef09 LEA -0x1(%R8),%RCX |
0x47ef0d CMP $0x2,%RCX |
0x47ef11 JBE 47ef4d |
0x47ef13 MOV -0x48(%RBP),%R10 |
0x47ef17 VPBROADCASTQ -0x190(%RBP),%YMM12 |
0x47ef20 MOV %R8,%R15 |
0x47ef23 AND $-0x4,%R15 |
0x47ef27 LEA (%R10,%RSI,8),%R12 |
0x47ef2b ADD %R15,-0x118(%RBP) |
0x47ef32 VMOVDQU (%R12),%YMM1 |
0x47ef38 VPSUBQ %YMM12,%YMM1,%YMM2 |
0x47ef3d VMOVDQU %YMM2,(%R12) |
0x47ef43 TEST $0x3,%R8B |
0x47ef47 JE 48089a |
0x47ef4d MOV -0x118(%RBP),%R9 |
0x47ef54 MOV -0x48(%RBP),%R11 |
0x47ef58 MOV -0x190(%RBP),%RSI |
0x47ef5f MOV -0x100(%RBP),%RDI |
0x47ef66 LEA (,%R9,8),%RBX |
0x47ef6e LEA 0x1(%R9),%RAX |
0x47ef72 SUB %RSI,(%R11,%RBX,1) |
0x47ef76 CMP %RAX,%RDI |
0x47ef79 JLE 48089a |
0x47ef7f ADD $0x2,%R9 |
0x47ef83 SUB %RSI,0x8(%R11,%RBX,1) |
0x47ef88 CMP %R9,%RDI |
0x47ef8b JLE 48089a |
0x47ef91 SUB %RSI,0x10(%R11,%RBX,1) |
0x47ef96 VZEROUPPER |
0x47ef99 JMP 47d7f3 |
0x47ef9e XCHG %AX,%AX |
(736) 0x47efa0 MOV -0x68(%RBP),%R11 |
(736) 0x47efa4 MOV (%R11,%R8,8),%RSI |
(736) 0x47efa8 CMP 0x8(%R11,%R8,8),%RSI |
(736) 0x47efad JGE 47db7c |
(736) 0x47efb3 MOV -0x70(%RBP),%RAX |
(736) 0x47efb7 MOV -0x128(%RBP),%RCX |
(736) 0x47efbe MOV %R14,-0x58(%RBP) |
(736) 0x47efc2 MOV %R12,-0x1a0(%RBP) |
(736) 0x47efc9 MOV -0x1c0(%RBP),%R14 |
(736) 0x47efd0 MOV 0xd8(%RAX),%RBX |
(736) 0x47efd7 MOV 0xf0(%RAX),%RDX |
(736) 0x47efde MOV %R9,-0x208(%RBP) |
(736) 0x47efe5 MOV 0xc8(%RAX),%RDI |
(736) 0x47efec MOV -0x60(%RBP),%R12 |
(736) 0x47eff0 MOV %R13,-0x130(%RBP) |
(736) 0x47eff7 MOV (%RDX),%R11 |
(736) 0x47effa MOV -0x210(%RBP),%R13 |
(736) 0x47f001 MOV %RBX,-0x190(%RBP) |
(736) 0x47f008 MOV -0x108(%RBP),%R9 |
(736) 0x47f00f MOV -0x178(%RBP),%RBX |
(736) 0x47f016 MOV %R10,-0x230(%RBP) |
(736) 0x47f01d MOV %RDI,-0x128(%RBP) |
(736) 0x47f024 JMP 47f068 |
0x47f026 NOPW %CS:(%RAX,%RAX,1) |
(747) 0x47f030 ADD %R12,%RDI |
(747) 0x47f033 CMP (%RDI),%R15 |
(747) 0x47f036 JLE 47f056 |
(747) 0x47f038 MOV -0x190(%RBP),%RDX |
(747) 0x47f03f MOV -0x128(%RBP),%R10 |
(747) 0x47f046 MOV %RCX,(%RDI) |
(747) 0x47f049 MOV %RAX,(%RDX,%RCX,8) |
(747) 0x47f04d VMOVSD %XMM3,(%R10,%RCX,8) |
(747) 0x47f053 INC %RCX |
(747) 0x47f056 MOV -0x68(%RBP),%RDI |
(747) 0x47f05a INC %RSI |
(747) 0x47f05d CMP %RSI,0x8(%RDI,%R8,8) |
(747) 0x47f062 JLE 47f190 |
(747) 0x47f068 MOV -0xf8(%RBP),%R10 |
(747) 0x47f06f MOV (%R10,%RSI,8),%RAX |
(747) 0x47f073 TEST %RBX,%RBX |
(747) 0x47f076 JE 47f07c |
(747) 0x47f078 MOV (%RBX,%RAX,8),%RAX |
(747) 0x47f07c MOV (%R11,%RAX,8),%RDX |
(747) 0x47f080 LEA (,%RAX,8),%RDI |
(747) 0x47f088 TEST %RDX,%RDX |
(747) 0x47f08b JNS 47f030 |
(747) 0x47f08d CMP $-0x3,%RDX |
(747) 0x47f091 JE 47f056 |
(747) 0x47f093 MOV -0x48(%RBP),%R10 |
(747) 0x47f097 MOV -0x1f8(%RBP),%RAX |
(747) 0x47f09e MOV %R10,(%R12,%RDI,1) |
(747) 0x47f0a2 LEA 0x8(%RAX,%RDI,1),%R10 |
(747) 0x47f0a7 MOV (%RAX,%RDI,1),%RDX |
(747) 0x47f0ab MOV (%R10),%RDI |
(747) 0x47f0ae CMP %RDI,%RDX |
(747) 0x47f0b1 JGE 47f056 |
(747) 0x47f0b3 MOV %RSI,-0x1c8(%RBP) |
(747) 0x47f0ba MOV -0x1a8(%RBP),%RSI |
(747) 0x47f0c1 MOV %RBX,-0x108(%RBP) |
(747) 0x47f0c8 MOV %R8,-0x1d0(%RBP) |
(747) 0x47f0cf JMP 47f128 |
0x47f0d1 NOPL (%RAX) |
(748) 0x47f0d8 CMP %RAX,%R14 |
(748) 0x47f0db JG 47f132 |
(748) 0x47f0dd MOV -0x58(%RBP),%R8 |
(748) 0x47f0e1 SUB %R14,%RAX |
(748) 0x47f0e4 LEA (%R8,%RAX,8),%RBX |
(748) 0x47f0e8 MOV -0x130(%RBP),%R8 |
(748) 0x47f0ef CMP (%RBX),%R8 |
(748) 0x47f0f2 JLE 47f120 |
(748) 0x47f0f4 MOV -0x1a0(%RBP),%RDI |
(748) 0x47f0fb MOV -0xb0(%RBP),%R8 |
(748) 0x47f102 MOV %R9,(%RBX) |
(748) 0x47f105 MOV -0xf0(%RBP),%RBX |
(748) 0x47f10c MOV (%RDI,%RAX,8),%RAX |
(748) 0x47f110 MOV %RAX,(%RBX,%R9,8) |
(748) 0x47f114 VMOVSD %XMM3,(%R8,%R9,8) |
(748) 0x47f11a INC %R9 |
(748) 0x47f11d MOV (%R10),%RDI |
(748) 0x47f120 INC %RDX |
(748) 0x47f123 CMP %RDI,%RDX |
(748) 0x47f126 JGE 47f166 |
(748) 0x47f128 MOV (%R13,%RDX,8),%RAX |
(748) 0x47f12d CMP %RAX,%RSI |
(748) 0x47f130 JG 47f0d8 |
(748) 0x47f132 NOT %RAX |
(748) 0x47f135 LEA (%R12,%RAX,8),%RBX |
(748) 0x47f139 CMP (%RBX),%R15 |
(748) 0x47f13c JLE 47f120 |
(748) 0x47f13e MOV -0x190(%RBP),%R8 |
(748) 0x47f145 MOV %RCX,(%RBX) |
(748) 0x47f148 INC %RDX |
(748) 0x47f14b MOV %RAX,(%R8,%RCX,8) |
(748) 0x47f14f MOV -0x128(%RBP),%RAX |
(748) 0x47f156 VMOVSD %XMM3,(%RAX,%RCX,8) |
(748) 0x47f15b INC %RCX |
(748) 0x47f15e MOV (%R10),%RDI |
(748) 0x47f161 CMP %RDI,%RDX |
(748) 0x47f164 JL 47f128 |
(747) 0x47f166 MOV -0x1c8(%RBP),%RSI |
(747) 0x47f16d MOV -0x1d0(%RBP),%R8 |
(747) 0x47f174 MOV -0x68(%RBP),%RDI |
(747) 0x47f178 MOV -0x108(%RBP),%RBX |
(747) 0x47f17f INC %RSI |
(747) 0x47f182 CMP %RSI,0x8(%RDI,%R8,8) |
(747) 0x47f187 JG 47f068 |
(736) 0x47f18d NOPL (%RAX) |
(736) 0x47f190 MOV -0x118(%RBP),%RAX |
(736) 0x47f197 MOV -0x58(%RBP),%R14 |
(736) 0x47f19b MOV %R9,-0x108(%RBP) |
(736) 0x47f1a2 MOV -0x1a0(%RBP),%R12 |
(736) 0x47f1a9 MOV -0x230(%RBP),%R10 |
(736) 0x47f1b0 MOV %RCX,-0x128(%RBP) |
(736) 0x47f1b7 MOV (%RAX),%RBX |
(736) 0x47f1ba MOV -0x130(%RBP),%R13 |
(736) 0x47f1c1 MOV -0x208(%RBP),%R9 |
(736) 0x47f1c8 MOV %RBX,-0x58(%RBP) |
(736) 0x47f1cc JMP 47db7c |
0x47f1d1 NOPL (%RAX) |
(736) 0x47f1d8 MOV -0x238(%RBP),%RBX |
(736) 0x47f1df MOV (%RBX,%R8,8),%RCX |
(736) 0x47f1e3 MOV 0x8(%RBX,%R8,8),%R11 |
(736) 0x47f1e8 CMP %R11,%RCX |
(736) 0x47f1eb JGE 47dc7e |
(736) 0x47f1f1 MOV -0x70(%RBP),%RDI |
(736) 0x47f1f5 SAL $0x3,%RCX |
(736) 0x47f1f9 MOV %R12,-0x1c8(%RBP) |
(736) 0x47f200 MOV %R10,-0x1d0(%RBP) |
(736) 0x47f207 MOV 0x100(%RDI),%RAX |
(736) 0x47f20e MOV 0xf0(%RDI),%RDX |
(736) 0x47f215 MOV (%RAX),%RBX |
(736) 0x47f218 MOV (%RDX),%RSI |
(736) 0x47f21b MOV %R9,%RAX |
(736) 0x47f21e MOV %RBX,-0x1a0(%RBP) |
(736) 0x47f225 MOV 0xc8(%RDI),%RBX |
(736) 0x47f22c MOV -0x1b0(%RBP),%RDI |
(736) 0x47f233 MOV %RSI,-0x130(%RBP) |
(736) 0x47f23a MOV -0x1b8(%RBP),%RSI |
(736) 0x47f241 LEA (%RDI,%RCX,1),%RDX |
(736) 0x47f245 LEA (%RDI,%R11,8),%R11 |
(736) 0x47f249 MOV %RDX,-0x58(%RBP) |
(736) 0x47f24d ADD %RSI,%RCX |
(736) 0x47f250 MOV -0x60(%RBP),%RDX |
(736) 0x47f254 JMP 47f284 |
0x47f256 NOPW %CS:(%RAX,%RAX,1) |
(739) 0x47f260 LEA (%RBX,%RDI,8),%R9 |
(739) 0x47f264 VMOVSD (%R9),%XMM2 |
(739) 0x47f269 VADDSD (%RCX),%XMM2,%XMM0 |
(739) 0x47f26d VMOVSD %XMM0,(%R9) |
(739) 0x47f272 ADDQ $0x8,-0x58(%RBP) |
(739) 0x47f277 ADD $0x8,%RCX |
(739) 0x47f27b MOV -0x58(%RBP),%R10 |
(739) 0x47f27f CMP %R11,%R10 |
(739) 0x47f282 JE 47f2e0 |
(739) 0x47f284 MOV -0x58(%RBP),%R12 |
(739) 0x47f288 MOV (%R12),%R9 |
(739) 0x47f28c MOV (%RDX,%R9,8),%RDI |
(739) 0x47f290 LEA (,%R9,8),%R12 |
(739) 0x47f298 CMP %RDI,%R15 |
(739) 0x47f29b JLE 47f260 |
(739) 0x47f29d MOV -0x48(%RBP),%R10 |
(739) 0x47f2a1 CMP %R10,%RDI |
(739) 0x47f2a4 JE 47f438 |
(739) 0x47f2aa MOV -0x130(%RBP),%RSI |
(739) 0x47f2b1 CMPQ $-0x3,(%RSI,%R9,8) |
(739) 0x47f2b6 JE 47f272 |
(739) 0x47f2b8 CMPQ $0x1,-0x110(%RBP) |
(739) 0x47f2c0 JE 47f2da |
(739) 0x47f2c2 MOV -0x1a0(%RBP),%RDI |
(739) 0x47f2c9 MOV -0x180(%RBP),%R12 |
(739) 0x47f2d0 MOV (%RDI,%R9,8),%R9 |
(739) 0x47f2d4 CMP %R9,(%R12,%R8,8) |
(739) 0x47f2d8 JNE 47f272 |
(739) 0x47f2da VADDSD (%RCX),%XMM4,%XMM4 |
(739) 0x47f2de JMP 47f272 |
(736) 0x47f2e0 MOV -0x1c8(%RBP),%R12 |
(736) 0x47f2e7 MOV -0x1d0(%RBP),%R10 |
(736) 0x47f2ee MOV %RAX,%R9 |
(736) 0x47f2f1 JMP 47dc7e |
0x47f2f6 NOPW %CS:(%RAX,%RAX,1) |
0x47f300 MOV %RSI,%R12 |
0x47f303 MOV $0x8,%ESI |
0x47f308 MOV %R8,-0x118(%RBP) |
0x47f30f MOV %R12,%RDI |
0x47f312 MOV %RCX,-0x108(%RBP) |
0x47f319 VMOVSD %XMM3,-0x40(%RBP) |
0x47f31e CALL 5b0aa0 <hypre_CAlloc> |
0x47f323 TEST %R12,%R12 |
0x47f326 VMOVSD -0x40(%RBP),%XMM3 |
0x47f32b MOV -0x108(%RBP),%RCX |
0x47f332 MOV -0x118(%RBP),%R8 |
0x47f339 MOV %RAX,%R13 |
0x47f33c JLE 47cc31 |
0x47f342 LEA (,%R12,8),%RDX |
0x47f34a MOV $0xff,%ESI |
0x47f34f MOV %RAX,%RDI |
0x47f352 CALL 4110a0 <memset@plt> |
0x47f357 VMOVSD -0x40(%RBP),%XMM3 |
0x47f35c MOV -0x108(%RBP),%RCX |
0x47f363 MOV -0x118(%RBP),%R8 |
0x47f36a JMP 47cc31 |
0x47f36f NOP |
0x47f370 MOV -0x60(%RBP),%RDI |
0x47f374 ADD $0x308,%RSP |
0x47f37b POP %RBX |
0x47f37c POP %R12 |
0x47f37e POP %R10 |
0x47f380 POP %R14 |
0x47f382 POP %R15 |
0x47f384 POP %RBP |
0x47f385 LEA -0x10(%R10),%RSP |
0x47f389 POP %R13 |
0x47f38b JMP 5b0b60 |
0x47f390 VMOVSD %XMM3,-0xb0(%RBP) |
0x47f398 CALL 411290 <GOMP_barrier@plt> |
0x47f39d MOV -0x108(%RBP),%R12 |
0x47f3a4 VMOVSD -0xb0(%RBP),%XMM3 |
0x47f3ac CMP %R12,-0x40(%RBP) |
0x47f3b0 JG 47d876 |
0x47f3b6 NOPW %CS:(%RAX,%RAX,1) |
0x47f3c0 MOV %R13,%RDI |
0x47f3c3 CALL 5b0b60 <hypre_Free> |
0x47f3c8 JMP 47e1f4 |
0x47f3cd NOPL (%RAX) |
0x47f3d0 MOV $0x8,%ESI |
0x47f3d5 MOV %R8,-0x118(%RBP) |
0x47f3dc MOV %RCX,-0x108(%RBP) |
0x47f3e3 VMOVSD %XMM3,-0x40(%RBP) |
0x47f3e8 CALL 5b0aa0 <hypre_CAlloc> |
0x47f3ed MOV -0x70(%RBP),%R15 |
0x47f3f1 VMOVSD -0x40(%RBP),%XMM3 |
0x47f3f6 MOV -0x108(%RBP),%RCX |
0x47f3fd MOV -0x118(%RBP),%R8 |
0x47f404 MOV %RAX,-0x60(%RBP) |
0x47f408 MOV %RAX,%R11 |
0x47f40b MOV 0x130(%R15),%RDI |
0x47f412 CMPQ $0,(%RDI) |
0x47f416 JLE 47cc48 |
0x47f41c XOR %EDX,%EDX |
0x47f41e XCHG %AX,%AX |
(766) 0x47f420 MOVQ $-0x1,(%R11,%RDX,8) |
(766) 0x47f428 INC %RDX |
(766) 0x47f42b CMP %RDX,(%RDI) |
(766) 0x47f42e JG 47f420 |
0x47f430 JMP 47cc48 |
0x47f435 NOPL (%RAX) |
(739) 0x47f438 MOV -0x258(%RBP),%RDI |
(739) 0x47f43f VMOVSD %XMM3,%XMM3,%XMM8 |
(739) 0x47f443 MOV (%RDI,%R9,8),%RSI |
(739) 0x47f447 MOV 0x8(%RDI,%R12,1),%R12 |
(739) 0x47f44c MOV %RSI,-0x208(%RBP) |
(739) 0x47f453 MOV %RSI,%R10 |
(739) 0x47f456 MOV %R12,-0x190(%RBP) |
(739) 0x47f45d CMP %RSI,%R12 |
(739) 0x47f460 JLE 480c8e |
(739) 0x47f466 SUB %RSI,%R12 |
(739) 0x47f469 AND $0x3,%R12D |
(739) 0x47f46d JE 47faad |
(739) 0x47f473 CMP $0x1,%R12 |
(739) 0x47f477 JE 47f51d |
(739) 0x47f47d CMP $0x2,%R12 |
(739) 0x47f481 JE 47f4d7 |
(739) 0x47f483 MOV -0x240(%RBP),%RSI |
(739) 0x47f48a MOV (%RSI,%R10,8),%R9 |
(739) 0x47f48e CMP %R9,-0x1a8(%RBP) |
(739) 0x47f495 JLE 480c54 |
(739) 0x47f49b MOV -0x1c0(%RBP),%RDI |
(739) 0x47f4a2 CMP %R9,%RDI |
(739) 0x47f4a5 JG 480c54 |
(739) 0x47f4ab SUB %RDI,%R9 |
(739) 0x47f4ae CMP (%R14,%R9,8),%R13 |
(739) 0x47f4b2 JLE 47f4b9 |
(739) 0x47f4b4 CMP %R9,%R8 |
(739) 0x47f4b7 JNE 47f4cd |
(739) 0x47f4b9 MOV -0x248(%RBP),%R12 |
(739) 0x47f4c0 MOV -0x208(%RBP),%R10 |
(739) 0x47f4c7 VADDSD (%R12,%R10,8),%XMM3,%XMM8 |
(739) 0x47f4cd MOV -0x208(%RBP),%RSI |
(739) 0x47f4d4 INC %RSI |
(739) 0x47f4d7 MOV -0x240(%RBP),%R9 |
(739) 0x47f4de MOV (%R9,%RSI,8),%RDI |
(739) 0x47f4e2 CMP %RDI,-0x1a8(%RBP) |
(739) 0x47f4e9 JLE 480a75 |
(739) 0x47f4ef MOV -0x1c0(%RBP),%R12 |
(739) 0x47f4f6 CMP %RDI,%R12 |
(739) 0x47f4f9 JG 480a75 |
(739) 0x47f4ff SUB %R12,%RDI |
(739) 0x47f502 CMP (%R14,%RDI,8),%R13 |
(739) 0x47f506 JLE 47f50d |
(739) 0x47f508 CMP %RDI,%R8 |
(739) 0x47f50b JNE 47f51a |
(739) 0x47f50d MOV -0x248(%RBP),%R10 |
(739) 0x47f514 VADDSD (%R10,%RSI,8),%XMM8,%XMM8 |
(739) 0x47f51a INC %RSI |
(739) 0x47f51d MOV -0x240(%RBP),%R9 |
(739) 0x47f524 MOV (%R9,%RSI,8),%RDI |
(739) 0x47f528 CMP %RDI,-0x1a8(%RBP) |
(739) 0x47f52f JLE 47fa87 |
(739) 0x47f535 MOV -0x1c0(%RBP),%R12 |
(739) 0x47f53c CMP %RDI,%R12 |
(739) 0x47f53f JG 47fa87 |
(739) 0x47f545 SUB %R12,%RDI |
(739) 0x47f548 CMP (%R14,%RDI,8),%R13 |
(739) 0x47f54c JLE 47fa90 |
(739) 0x47f552 CMP %RDI,%R8 |
(739) 0x47f555 JE 47fa90 |
(739) 0x47f55b JMP 47fa9d |
(742) 0x47f560 MOV -0x238(%RBP),%RCX |
(742) 0x47f567 MOV 0x8(%RCX,%RDI,1),%R10 |
(742) 0x47f56c MOV (%RCX,%RAX,8),%R8 |
(742) 0x47f570 MOV %R10,-0x268(%RBP) |
(742) 0x47f577 CMP %R10,%R8 |
(742) 0x47f57a JGE 47e733 |
(742) 0x47f580 SUB %R8,%R10 |
(742) 0x47f583 MOV %R8,-0x260(%RBP) |
(742) 0x47f58a LEA -0x1(%R10),%R9 |
(742) 0x47f58e MOV %R10,-0x230(%RBP) |
(742) 0x47f595 CMP $0x6,%R9 |
(742) 0x47f599 JBE 480d14 |
(742) 0x47f59f MOV -0x1b8(%RBP),%R9 |
(742) 0x47f5a6 SHR $0x3,%R10 |
(742) 0x47f5aa VXORPD %XMM1,%XMM1,%XMM1 |
(742) 0x47f5ae VPBROADCASTQ -0x130(%RBP),%ZMM12 |
(742) 0x47f5b5 KXNORB %K0,%K0,%K0 |
(742) 0x47f5b9 SAL $0x6,%R10 |
(742) 0x47f5bd VBROADCASTSD %XMM9,%ZMM11 |
(742) 0x47f5c3 VMOVAPD %ZMM1,%ZMM13 |
(742) 0x47f5c9 LEA (%R9,%R8,8),%RCX |
(742) 0x47f5cd MOV %R10,-0x2f0(%RBP) |
(742) 0x47f5d4 MOV -0x1b0(%RBP),%R9 |
(742) 0x47f5db ADD %RCX,%R10 |
(742) 0x47f5de MOV %RCX,-0x270(%RBP) |
(742) 0x47f5e5 MOV %R10,-0x250(%RBP) |
(742) 0x47f5ec MOV -0x1b8(%RBP),%R10 |
(742) 0x47f5f3 SUB %R10,%R9 |
(742) 0x47f5f6 MOV %R9,%R10 |
(742) 0x47f5f9 MOV -0x2f0(%RBP),%R9 |
(742) 0x47f600 SUB $0x40,%R9 |
(742) 0x47f604 SHR $0x6,%R9 |
(742) 0x47f608 INC %R9 |
(742) 0x47f60b AND $0x3,%R9D |
(742) 0x47f60f JE 47f745 |
(742) 0x47f615 CMP $0x1,%R9 |
(742) 0x47f619 JE 47f6e0 |
(742) 0x47f61f CMP $0x2,%R9 |
(742) 0x47f623 JE 47f68b |
(742) 0x47f625 MOV -0x270(%RBP),%R9 |
(742) 0x47f62c KMOVB %K0,%K5 |
(742) 0x47f630 VMOVAPD -0x2b0(%RBP),%ZMM2 |
(742) 0x47f63a ADD $0x40,%RCX |
(742) 0x47f63e VMOVDQU64 (%R9,%R10,1),%ZMM14 |
(742) 0x47f645 MOV -0x60(%RBP),%R9 |
(742) 0x47f649 VMOVDQA64 %ZMM14,-0x2f0(%RBP) |
(742) 0x47f653 VPGATHERQQ (%R9,%ZMM14,8),%ZMM0{%K5} |
(742) 0x47f65a MOV -0x270(%RBP),%R9 |
(742) 0x47f661 VPCMPNLTQ %ZMM12,%ZMM0,%K3 |
(742) 0x47f668 VMOVUPD (%R9),%ZMM2{%K3} |
(742) 0x47f66e VMULPD %ZMM2,%ZMM11,%ZMM14 |
(742) 0x47f674 VMOVAPD %ZMM2,-0x2b0(%RBP) |
(742) 0x47f67e VCMPPD $0x1,%ZMM1,%ZMM14,%K1{%K3} |
(742) 0x47f685 VMOVAPD %ZMM2,%ZMM1{%K1}{z} |
(742) 0x47f68b VMOVDQU64 (%RCX,%R10,1),%ZMM2 |
(742) 0x47f692 MOV -0x60(%RBP),%R9 |
(742) 0x47f696 KMOVB %K0,%K4 |
(742) 0x47f69a ADD $0x40,%RCX |
(742) 0x47f69e VMOVAPD -0x2b0(%RBP),%ZMM14 |
(742) 0x47f6a8 VPGATHERQQ (%R9,%ZMM2,8),%ZMM0{%K4} |
(742) 0x47f6af VPCMPNLTQ %ZMM12,%ZMM0,%K6 |
(742) 0x47f6b6 VMOVUPD -0x40(%RCX),%ZMM14{%K6} |
(742) 0x47f6bd VMULPD %ZMM14,%ZMM11,%ZMM2 |
(742) 0x47f6c3 VMOVAPD %ZMM14,-0x2b0(%RBP) |
(742) 0x47f6cd VCMPPD $0x1,%ZMM13,%ZMM2,%K7{%K6} |
(742) 0x47f6d4 VMOVAPD %ZMM14,%ZMM0{%K7}{z} |
(742) 0x47f6da VADDPD %ZMM0,%ZMM1,%ZMM1 |
(742) 0x47f6e0 VMOVDQU64 (%RCX,%R10,1),%ZMM14 |
(742) 0x47f6e7 MOV -0x60(%RBP),%R9 |
(742) 0x47f6eb KMOVB %K0,%K5 |
(742) 0x47f6ef ADD $0x40,%RCX |
(742) 0x47f6f3 VPGATHERQQ (%R9,%ZMM14,8),%ZMM2{%K5} |
(742) 0x47f6fa VMOVAPD -0x2b0(%RBP),%ZMM14 |
(742) 0x47f704 MOV -0x250(%RBP),%R9 |
(742) 0x47f70b VPCMPNLTQ %ZMM12,%ZMM2,%K3 |
(742) 0x47f712 VMOVUPD -0x40(%RCX),%ZMM14{%K3} |
(742) 0x47f719 VMULPD %ZMM14,%ZMM11,%ZMM0 |
(742) 0x47f71f VMOVAPD %ZMM14,-0x2b0(%RBP) |
(742) 0x47f729 VCMPPD $0x1,%ZMM13,%ZMM0,%K1{%K3} |
(742) 0x47f730 VMOVAPD %ZMM14,%ZMM2{%K1}{z} |
(742) 0x47f736 VADDPD %ZMM2,%ZMM1,%ZMM1 |
(742) 0x47f73c CMP %R9,%RCX |
(742) 0x47f73f JE 47f86f |
(742) 0x47f745 MOV %RAX,-0x2f0(%RBP) |
(742) 0x47f74c MOV -0x60(%RBP),%R9 |
(745) 0x47f750 VMOVDQU64 (%RCX,%R10,1),%ZMM14 |
(745) 0x47f757 KMOVB %K0,%K4 |
(745) 0x47f75b KMOVB %K0,%K5 |
(745) 0x47f75f MOV -0x250(%RBP),%RAX |
(745) 0x47f766 ADD $0x100,%RCX |
(745) 0x47f76d VPGATHERQQ (%R9,%ZMM14,8),%ZMM0{%K4} |
(745) 0x47f774 KMOVB %K0,%K4 |
(745) 0x47f778 VPCMPNLTQ %ZMM12,%ZMM0,%K6 |
(745) 0x47f77f VMOVAPD -0x2b0(%RBP),%ZMM0 |
(745) 0x47f789 VMOVUPD -0x100(%RCX),%ZMM0{%K6} |
(745) 0x47f790 VMULPD %ZMM11,%ZMM0,%ZMM2 |
(745) 0x47f796 VCMPPD $0x1,%ZMM13,%ZMM2,%K7{%K6} |
(745) 0x47f79d VMOVAPD %ZMM0,%ZMM14{%K7}{z} |
(745) 0x47f7a3 VADDPD %ZMM14,%ZMM1,%ZMM1 |
(745) 0x47f7a9 VMOVDQU64 -0xc0(%RCX,%R10,1),%ZMM14 |
(745) 0x47f7b1 VPGATHERQQ (%R9,%ZMM14,8),%ZMM2{%K5} |
(745) 0x47f7b8 KMOVB %K0,%K5 |
(745) 0x47f7bc VPCMPNLTQ %ZMM12,%ZMM2,%K3 |
(745) 0x47f7c3 VMOVUPD -0xc0(%RCX),%ZMM0{%K3} |
(745) 0x47f7ca VMULPD %ZMM11,%ZMM0,%ZMM14 |
(745) 0x47f7d0 VCMPPD $0x1,%ZMM13,%ZMM14,%K1{%K3} |
(745) 0x47f7d7 VMOVDQU64 -0x80(%RCX,%R10,1),%ZMM14 |
(745) 0x47f7df VMOVAPD %ZMM0,%ZMM2{%K1}{z} |
(745) 0x47f7e5 VADDPD %ZMM2,%ZMM1,%ZMM1 |
(745) 0x47f7eb VPGATHERQQ (%R9,%ZMM14,8),%ZMM2{%K4} |
(745) 0x47f7f2 VPCMPNLTQ %ZMM12,%ZMM2,%K6 |
(745) 0x47f7f9 VMOVUPD -0x80(%RCX),%ZMM0{%K6} |
(745) 0x47f800 VMULPD %ZMM11,%ZMM0,%ZMM14 |
(745) 0x47f806 VCMPPD $0x1,%ZMM13,%ZMM14,%K7{%K6} |
(745) 0x47f80d VMOVDQU64 -0x40(%RCX,%R10,1),%ZMM14 |
(745) 0x47f815 VMOVAPD %ZMM0,%ZMM2{%K7}{z} |
(745) 0x47f81b VADDPD %ZMM2,%ZMM1,%ZMM1 |
(745) 0x47f821 VPGATHERQQ (%R9,%ZMM14,8),%ZMM2{%K5} |
(745) 0x47f828 VPCMPNLTQ %ZMM12,%ZMM2,%K3 |
(745) 0x47f82f VMOVUPD -0x40(%RCX),%ZMM0{%K3} |
(745) 0x47f836 VMOVAPD %ZMM0,%ZMM14 |
(745) 0x47f83c VMOVAPD %ZMM0,-0x2b0(%RBP) |
(745) 0x47f846 VMULPD %ZMM0,%ZMM11,%ZMM0 |
(745) 0x47f84c VCMPPD $0x1,%ZMM13,%ZMM0,%K1{%K3} |
(745) 0x47f853 VMOVAPD %ZMM14,%ZMM2{%K1}{z} |
(745) 0x47f859 VADDPD %ZMM2,%ZMM1,%ZMM1 |
(745) 0x47f85f CMP %RAX,%RCX |
(745) 0x47f862 JNE 47f750 |
(742) 0x47f868 MOV -0x2f0(%RBP),%RAX |
(742) 0x47f86f VEXTRACTF64X4 $0x1,%ZMM1,%YMM12 |
(742) 0x47f876 MOV -0x230(%RBP),%R10 |
(742) 0x47f87d VADDPD %YMM1,%YMM12,%YMM11 |
(742) 0x47f881 VADDPD %YMM12,%YMM1,%YMM1 |
(742) 0x47f886 MOV %R10,%RCX |
(742) 0x47f889 AND $-0x8,%RCX |
(742) 0x47f88d VEXTRACTF64X2 $0x1,%YMM11,%XMM13 |
(742) 0x47f894 ADD %RCX,%R8 |
(742) 0x47f897 AND $0x7,%R10D |
(742) 0x47f89b VADDPD %XMM11,%XMM13,%XMM14 |
(742) 0x47f8a0 VUNPCKHPD %XMM14,%XMM14,%XMM0 |
(742) 0x47f8a5 VADDPD %XMM14,%XMM0,%XMM2 |
(742) 0x47f8aa VADDSD %XMM2,%XMM10,%XMM2 |
(742) 0x47f8ae JE 480cc5 |
(742) 0x47f8b4 MOV -0x230(%RBP),%R9 |
(742) 0x47f8bb SUB %RCX,%R9 |
(742) 0x47f8be LEA -0x1(%R9),%R10 |
(742) 0x47f8c2 CMP $0x2,%R10 |
(742) 0x47f8c6 JBE 480d34 |
(742) 0x47f8cc MOV -0x260(%RBP),%R10 |
(742) 0x47f8d3 VPBROADCASTQ -0x130(%RBP),%YMM11 |
(742) 0x47f8dc KXNORB %K4,%K4,%K4 |
(742) 0x47f8e0 VBROADCASTSD %XMM9,%YMM12 |
(742) 0x47f8e5 VXORPD %XMM2,%XMM2,%XMM2 |
(742) 0x47f8e9 ADD %R10,%RCX |
(742) 0x47f8ec MOV -0x1b0(%RBP),%R10 |
(742) 0x47f8f3 VMOVDQU (%R10,%RCX,8),%YMM13 |
(742) 0x47f8f9 MOV -0x60(%RBP),%R10 |
(742) 0x47f8fd VMOVDQA %YMM13,-0x230(%RBP) |
(742) 0x47f905 VPGATHERQQ (%R10,%YMM13,8),%YMM14{%K4} |
(742) 0x47f90c VMOVAPD -0x310(%RBP),%YMM13 |
(742) 0x47f914 MOV -0x1b8(%RBP),%R10 |
(742) 0x47f91b VPCMPNLTQ %YMM11,%YMM14,%K6 |
(742) 0x47f922 VMOVUPD (%R10,%RCX,8),%YMM13{%K6} |
(742) 0x47f929 MOV %R9,%RCX |
(742) 0x47f92c AND $-0x4,%RCX |
(742) 0x47f930 VMULPD %YMM13,%YMM12,%YMM0 |
(742) 0x47f935 VMOVAPD %YMM13,-0x310(%RBP) |
(742) 0x47f93d ADD %RCX,%R8 |
(742) 0x47f940 AND $0x3,%R9D |
(742) 0x47f944 VCMPPD $0x1,%YMM2,%YMM0,%K7{%K6} |
(742) 0x47f94b VBLENDMPD %YMM13,%YMM2,%YMM12{%K7} |
(742) 0x47f951 VADDPD %YMM12,%YMM1,%YMM1 |
(742) 0x47f956 VEXTRACTF64X2 $0x1,%YMM1,%XMM14 |
(742) 0x47f95d VADDPD %XMM1,%XMM14,%XMM11 |
(742) 0x47f961 VUNPCKHPD %XMM11,%XMM11,%XMM13 |
(742) 0x47f966 VADDPD %XMM11,%XMM13,%XMM0 |
(742) 0x47f96b VADDSD %XMM0,%XMM10,%XMM10 |
(742) 0x47f96f JE 47e733 |
(742) 0x47f975 MOV -0x1b0(%RBP),%R10 |
(742) 0x47f97c LEA (,%R8,8),%R9 |
(742) 0x47f984 MOV -0x130(%RBP),%RCX |
(742) 0x47f98b MOV %R9,-0x230(%RBP) |
(742) 0x47f992 MOV (%R10,%R8,8),%R9 |
(742) 0x47f996 MOV -0x60(%RBP),%R10 |
(742) 0x47f99a CMP %RCX,(%R10,%R9,8) |
(742) 0x47f99e JL 47f9c1 |
(742) 0x47f9a0 MOV -0x1b8(%RBP),%R9 |
(742) 0x47f9a7 VXORPD %XMM2,%XMM2,%XMM2 |
(742) 0x47f9ab VMOVSD (%R9,%R8,8),%XMM12 |
(742) 0x47f9b1 VMULSD %XMM9,%XMM12,%XMM1 |
(742) 0x47f9b6 VCOMISD %XMM1,%XMM2 |
(742) 0x47f9ba JBE 47f9c1 |
(742) 0x47f9bc VADDSD %XMM12,%XMM10,%XMM10 |
(742) 0x47f9c1 LEA 0x1(%R8),%R10 |
(742) 0x47f9c5 CMP %R10,-0x268(%RBP) |
(742) 0x47f9cc JLE 47e733 |
(742) 0x47f9d2 MOV -0x1b0(%RBP),%RCX |
(742) 0x47f9d9 MOV -0x230(%RBP),%R9 |
(742) 0x47f9e0 MOV -0x130(%RBP),%R10 |
(742) 0x47f9e7 MOV 0x8(%RCX,%R9,1),%R9 |
(742) 0x47f9ec MOV -0x60(%RBP),%RCX |
(742) 0x47f9f0 CMP %R10,(%RCX,%R9,8) |
(742) 0x47f9f4 JL 47fa21 |
(742) 0x47f9f6 MOV -0x1b8(%RBP),%R9 |
(742) 0x47f9fd MOV -0x230(%RBP),%RCX |
(742) 0x47fa04 VXORPD %XMM13,%XMM13,%XMM13 |
(742) 0x47fa09 VMOVSD 0x8(%R9,%RCX,1),%XMM14 |
(742) 0x47fa10 VMULSD %XMM9,%XMM14,%XMM11 |
(742) 0x47fa15 VCOMISD %XMM11,%XMM13 |
(742) 0x47fa1a JBE 47fa21 |
(742) 0x47fa1c VADDSD %XMM14,%XMM10,%XMM10 |
(742) 0x47fa21 MOV -0x268(%RBP),%R10 |
(742) 0x47fa28 ADD $0x2,%R8 |
(742) 0x47fa2c CMP %R10,%R8 |
(742) 0x47fa2f JGE 47e733 |
(742) 0x47fa35 MOV -0x1b0(%RBP),%R8 |
(742) 0x47fa3c MOV -0x230(%RBP),%R9 |
(742) 0x47fa43 MOV -0x60(%RBP),%RCX |
(742) 0x47fa47 MOV -0x130(%RBP),%R10 |
(742) 0x47fa4e MOV 0x10(%R8,%R9,1),%R8 |
(742) 0x47fa53 CMP (%RCX,%R8,8),%R10 |
(742) 0x47fa57 JG 47e733 |
(742) 0x47fa5d MOV -0x1b8(%RBP),%R8 |
(742) 0x47fa64 VXORPD %XMM1,%XMM1,%XMM1 |
(742) 0x47fa68 VMOVSD 0x10(%R8,%R9,1),%XMM0 |
(742) 0x47fa6f VMULSD %XMM0,%XMM9,%XMM12 |
(742) 0x47fa73 VCOMISD %XMM12,%XMM1 |
(742) 0x47fa78 JBE 47e733 |
(742) 0x47fa7e VADDSD %XMM0,%XMM10,%XMM10 |
(742) 0x47fa82 JMP 47e733 |
(739) 0x47fa87 NOT %RDI |
(739) 0x47fa8a CMP (%RDX,%RDI,8),%R15 |
(739) 0x47fa8e JG 47fa9d |
(739) 0x47fa90 MOV -0x248(%RBP),%R10 |
(739) 0x47fa97 VADDSD (%R10,%RSI,8),%XMM8,%XMM8 |
(739) 0x47fa9d INC %RSI |
(739) 0x47faa0 CMP %RSI,-0x190(%RBP) |
(739) 0x47faa7 JE 47fba8 |
(739) 0x47faad MOV -0x240(%RBP),%R9 |
(739) 0x47fab4 MOV -0x1a8(%RBP),%RDI |
(739) 0x47fabb MOV %RAX,-0x230(%RBP) |
(739) 0x47fac2 MOV %RCX,-0x250(%RBP) |
(739) 0x47fac9 MOV -0x1c0(%RBP),%R10 |
(739) 0x47fad0 MOV -0x248(%RBP),%RCX |
(740) 0x47fad7 MOV (%R9,%RSI,8),%RAX |
(740) 0x47fadb CMP %RAX,%RDI |
(740) 0x47fade JLE 47fe98 |
(740) 0x47fae4 CMP %RAX,%R10 |
(740) 0x47fae7 JG 47fe98 |
(740) 0x47faed SUB %R10,%RAX |
(740) 0x47faf0 CMP (%R14,%RAX,8),%R13 |
(740) 0x47faf4 JLE 47fafb |
(740) 0x47faf6 CMP %RAX,%R8 |
(740) 0x47faf9 JNE 47fb00 |
(740) 0x47fafb VADDSD (%RCX,%RSI,8),%XMM8,%XMM8 |
(740) 0x47fb00 LEA 0x1(%RSI),%RAX |
(740) 0x47fb04 MOV (%R9,%RAX,8),%RSI |
(740) 0x47fb08 CMP %RSI,%RDI |
(740) 0x47fb0b JLE 47fe80 |
(740) 0x47fb11 CMP %RSI,%R10 |
(740) 0x47fb14 JG 47fe80 |
(740) 0x47fb1a SUB %R10,%RSI |
(740) 0x47fb1d CMP (%R14,%RSI,8),%R13 |
(740) 0x47fb21 JLE 47fb28 |
(740) 0x47fb23 CMP %RSI,%R8 |
(740) 0x47fb26 JNE 47fb2d |
(740) 0x47fb28 VADDSD (%RCX,%RAX,8),%XMM8,%XMM8 |
(740) 0x47fb2d LEA 0x1(%RAX),%R12 |
(740) 0x47fb31 MOV (%R9,%R12,8),%RSI |
(740) 0x47fb35 CMP %RSI,%RDI |
(740) 0x47fb38 JLE 47fe68 |
(740) 0x47fb3e CMP %RSI,%R10 |
(740) 0x47fb41 JG 47fe68 |
(740) 0x47fb47 SUB %R10,%RSI |
(740) 0x47fb4a CMP (%R14,%RSI,8),%R13 |
(740) 0x47fb4e JLE 47fb55 |
(740) 0x47fb50 CMP %RSI,%R8 |
(740) 0x47fb53 JNE 47fb5b |
(740) 0x47fb55 VADDSD (%RCX,%R12,8),%XMM8,%XMM8 |
(740) 0x47fb5b LEA 0x2(%RAX),%R12 |
(740) 0x47fb5f MOV (%R9,%R12,8),%RSI |
(740) 0x47fb63 CMP %RSI,%RDI |
(740) 0x47fb66 JLE 47fe50 |
(740) 0x47fb6c CMP %RSI,%R10 |
(740) 0x47fb6f JG 47fe50 |
(740) 0x47fb75 SUB %R10,%RSI |
(740) 0x47fb78 CMP (%R14,%RSI,8),%R13 |
(740) 0x47fb7c JLE 47fb83 |
(740) 0x47fb7e CMP %RSI,%R8 |
(740) 0x47fb81 JNE 47fb89 |
(740) 0x47fb83 VADDSD (%RCX,%R12,8),%XMM8,%XMM8 |
(740) 0x47fb89 LEA 0x3(%RAX),%RSI |
(740) 0x47fb8d CMP %RSI,-0x190(%RBP) |
(740) 0x47fb94 JNE 47fad7 |
(739) 0x47fb9a MOV -0x230(%RBP),%RAX |
(739) 0x47fba1 MOV -0x250(%RBP),%RCX |
(739) 0x47fba8 VXORPD %XMM1,%XMM1,%XMM1 |
(739) 0x47fbac VCOMISD %XMM1,%XMM8 |
(739) 0x47fbb0 JE 47f2da |
(739) 0x47fbb6 MOV -0x208(%RBP),%R9 |
(739) 0x47fbbd MOV -0x240(%RBP),%RDI |
(739) 0x47fbc4 MOV -0x190(%RBP),%RSI |
(739) 0x47fbcb VMOVSD (%RCX),%XMM12 |
(739) 0x47fbcf SAL $0x3,%R9 |
(739) 0x47fbd3 MOV -0x248(%RBP),%R10 |
(739) 0x47fbda LEA (%RDI,%R9,1),%R12 |
(739) 0x47fbde LEA (%RDI,%RSI,8),%RDI |
(739) 0x47fbe2 VDIVSD %XMM8,%XMM12,%XMM2 |
(739) 0x47fbe7 MOV %RDI,-0x190(%RBP) |
(739) 0x47fbee SUB %R12,%RDI |
(739) 0x47fbf1 ADD %R10,%R9 |
(739) 0x47fbf4 SUB $0x8,%RDI |
(739) 0x47fbf8 SHR $0x3,%RDI |
(739) 0x47fbfc INC %RDI |
(739) 0x47fbff AND $0x3,%EDI |
(739) 0x47fc02 JE 47fd39 |
(739) 0x47fc08 CMP $0x1,%RDI |
(739) 0x47fc0c JE 47fcce |
(739) 0x47fc12 CMP $0x2,%RDI |
(739) 0x47fc16 JE 47fc73 |
(739) 0x47fc18 MOV (%R12),%RSI |
(739) 0x47fc1c CMP %RSI,-0x1a8(%RBP) |
(739) 0x47fc23 JLE 480da0 |
(739) 0x47fc29 MOV -0x1c0(%RBP),%R10 |
(739) 0x47fc30 CMP %RSI,%R10 |
(739) 0x47fc33 JG 480da0 |
(739) 0x47fc39 SUB %R10,%RSI |
(739) 0x47fc3c MOV %RSI,%RDI |
(739) 0x47fc3f MOV (%R14,%RSI,8),%RSI |
(739) 0x47fc43 CMP %RSI,%R13 |
(739) 0x47fc46 JG 47fc61 |
(739) 0x47fc48 MOV -0xb0(%RBP),%R10 |
(739) 0x47fc4f VMOVSD (%R9),%XMM14 |
(739) 0x47fc54 LEA (%R10,%RSI,8),%RSI |
(739) 0x47fc58 VFMADD213SD (%RSI),%XMM2,%XMM14 |
(739) 0x47fc5d VMOVSD %XMM14,(%RSI) |
(739) 0x47fc61 CMP %RDI,%R8 |
(739) 0x47fc64 JNE 47fc6b |
(739) 0x47fc66 VFMADD231SD (%R9),%XMM2,%XMM4 |
(739) 0x47fc6b ADD $0x8,%R12 |
(739) 0x47fc6f ADD $0x8,%R9 |
(739) 0x47fc73 MOV (%R12),%RSI |
(739) 0x47fc77 CMP %RSI,-0x1a8(%RBP) |
(739) 0x47fc7e JLE 480d3d |
(739) 0x47fc84 MOV -0x1c0(%RBP),%R10 |
(739) 0x47fc8b CMP %RSI,%R10 |
(739) 0x47fc8e JG 480d3d |
(739) 0x47fc94 SUB %R10,%RSI |
(739) 0x47fc97 MOV %RSI,%RDI |
(739) 0x47fc9a MOV (%R14,%RSI,8),%RSI |
(739) 0x47fc9e CMP %RSI,%R13 |
(739) 0x47fca1 JG 47fcbc |
(739) 0x47fca3 MOV -0xb0(%RBP),%R10 |
(739) 0x47fcaa VMOVSD (%R9),%XMM11 |
(739) 0x47fcaf LEA (%R10,%RSI,8),%RSI |
(739) 0x47fcb3 VFMADD213SD (%RSI),%XMM2,%XMM11 |
(739) 0x47fcb8 VMOVSD %XMM11,(%RSI) |
(739) 0x47fcbc CMP %RDI,%R8 |
(739) 0x47fcbf JNE 47fcc6 |
(739) 0x47fcc1 VFMADD231SD (%R9),%XMM2,%XMM4 |
(739) 0x47fcc6 ADD $0x8,%R12 |
(739) 0x47fcca ADD $0x8,%R9 |
(739) 0x47fcce MOV (%R12),%RSI |
(739) 0x47fcd2 CMP %RSI,-0x1a8(%RBP) |
(739) 0x47fcd9 JLE 480c66 |
(739) 0x47fcdf MOV -0x1c0(%RBP),%R10 |
(739) 0x47fce6 CMP %RSI,%R10 |
(739) 0x47fce9 JG 480c66 |
(739) 0x47fcef SUB %R10,%RSI |
(739) 0x47fcf2 MOV %RSI,%RDI |
(739) 0x47fcf5 MOV (%R14,%RSI,8),%RSI |
(739) 0x47fcf9 CMP %RSI,%R13 |
(739) 0x47fcfc JG 47fd17 |
(739) 0x47fcfe MOV -0xb0(%RBP),%R10 |
(739) 0x47fd05 VMOVSD (%R9),%XMM0 |
(739) 0x47fd0a LEA (%R10,%RSI,8),%RSI |
(739) 0x47fd0e VFMADD213SD (%RSI),%XMM2,%XMM0 |
(739) 0x47fd13 VMOVSD %XMM0,(%RSI) |
(739) 0x47fd17 CMP %RDI,%R8 |
(739) 0x47fd1a JNE 47fd21 |
(739) 0x47fd1c VFMADD231SD (%R9),%XMM2,%XMM4 |
(739) 0x47fd21 MOV -0x190(%RBP),%RSI |
(739) 0x47fd28 ADD $0x8,%R12 |
(739) 0x47fd2c ADD $0x8,%R9 |
(739) 0x47fd30 CMP %RSI,%R12 |
(739) 0x47fd33 JE 47f272 |
(739) 0x47fd39 MOV %RCX,-0x230(%RBP) |
(739) 0x47fd40 MOV -0x1c0(%RBP),%R10 |
(739) 0x47fd47 MOV %RAX,-0x208(%RBP) |
(739) 0x47fd4e MOV -0x1a8(%RBP),%RAX |
(741) 0x47fd55 MOV (%R12),%RSI |
(741) 0x47fd59 CMP %RSI,%RAX |
(741) 0x47fd5c JLE 480afe |
(741) 0x47fd62 CMP %RSI,%R10 |
(741) 0x47fd65 JG 480afe |
(741) 0x47fd6b SUB %R10,%RSI |
(741) 0x47fd6e MOV (%R14,%RSI,8),%RDI |
(741) 0x47fd72 CMP %RDI,%R13 |
(741) 0x47fd75 JLE 480b96 |
(741) 0x47fd7b CMP %RSI,%R8 |
(741) 0x47fd7e JNE 47fd85 |
(741) 0x47fd80 VFMADD231SD (%R9),%XMM2,%XMM4 |
(741) 0x47fd85 MOV 0x8(%R12),%RSI |
(741) 0x47fd8a LEA 0x8(%R12),%RDI |
(741) 0x47fd8f ADD $0x8,%R9 |
(741) 0x47fd93 CMP %RSI,%RAX |
(741) 0x47fd96 JLE 480ad7 |
(741) 0x47fd9c CMP %RSI,%R10 |
(741) 0x47fd9f JG 480ad7 |
(741) 0x47fda5 SUB %R10,%RSI |
(741) 0x47fda8 MOV (%R14,%RSI,8),%R12 |
(741) 0x47fdac CMP %R12,%R13 |
(741) 0x47fdaf JLE 480b75 |
(741) 0x47fdb5 CMP %RSI,%R8 |
(741) 0x47fdb8 JNE 47fdbf |
(741) 0x47fdba VFMADD231SD (%R9),%XMM2,%XMM4 |
(741) 0x47fdbf MOV 0x8(%RDI),%RSI |
(741) 0x47fdc3 CMP %RSI,%RAX |
(741) 0x47fdc6 JLE 480aaf |
(741) 0x47fdcc CMP %RSI,%R10 |
(741) 0x47fdcf JG 480aaf |
(741) 0x47fdd5 SUB %R10,%RSI |
(741) 0x47fdd8 MOV (%R14,%RSI,8),%R12 |
(741) 0x47fddc CMP %R12,%R13 |
(741) 0x47fddf JLE 480b53 |
(741) 0x47fde5 CMP %RSI,%R8 |
(741) 0x47fde8 JNE 47fdf0 |
(741) 0x47fdea VFMADD231SD 0x8(%R9),%XMM2,%XMM4 |
(741) 0x47fdf0 MOV 0x10(%RDI),%RSI |
(741) 0x47fdf4 CMP %RSI,%RAX |
(741) 0x47fdf7 JLE 480a87 |
(741) 0x47fdfd CMP %RSI,%R10 |
(741) 0x47fe00 JG 480a87 |
(741) 0x47fe06 SUB %R10,%RSI |
(741) 0x47fe09 MOV (%R14,%RSI,8),%R12 |
(741) 0x47fe0d CMP %R12,%R13 |
(741) 0x47fe10 JLE 480b31 |
(741) 0x47fe16 CMP %RSI,%R8 |
(741) 0x47fe19 JNE 47fe21 |
(741) 0x47fe1b VFMADD231SD 0x10(%R9),%XMM2,%XMM4 |
(741) 0x47fe21 LEA 0x18(%RDI),%R12 |
(741) 0x47fe25 MOV -0x190(%RBP),%RDI |
(741) 0x47fe2c ADD $0x18,%R9 |
(741) 0x47fe30 CMP %RDI,%R12 |
(741) 0x47fe33 JNE 47fd55 |
(739) 0x47fe39 MOV -0x208(%RBP),%RAX |
(739) 0x47fe40 MOV -0x230(%RBP),%RCX |
(739) 0x47fe47 JMP 47f272 |
0x47fe4c NOPL (%RAX) |
(740) 0x47fe50 NOT %RSI |
(740) 0x47fe53 CMP (%RDX,%RSI,8),%R15 |
(740) 0x47fe57 JG 47fb89 |
(740) 0x47fe5d JMP 47fb83 |
0x47fe62 NOPW (%RAX,%RAX,1) |
(740) 0x47fe68 NOT %RSI |
(740) 0x47fe6b CMP (%RDX,%RSI,8),%R15 |
(740) 0x47fe6f JG 47fb5b |
(740) 0x47fe75 JMP 47fb55 |
0x47fe7a NOPW (%RAX,%RAX,1) |
(740) 0x47fe80 NOT %RSI |
(740) 0x47fe83 CMP (%RDX,%RSI,8),%R15 |
(740) 0x47fe87 JG 47fb2d |
(740) 0x47fe8d JMP 47fb28 |
0x47fe92 NOPW (%RAX,%RAX,1) |
(740) 0x47fe98 NOT %RAX |
(740) 0x47fe9b CMP (%RDX,%RAX,8),%R15 |
(740) 0x47fe9f JG 47fb00 |
(740) 0x47fea5 JMP 47fafb |
0x47feaa NOPW (%RAX,%RAX,1) |
(742) 0x47feb0 MOV -0x1a0(%RBP),%R9 |
(742) 0x47feb7 MOV -0x190(%RBP),%RCX |
(742) 0x47febe VDIVSD %XMM10,%XMM2,%XMM0 |
(742) 0x47fec3 CMP %RCX,%R9 |
(742) 0x47fec6 JGE 47fffa |
(742) 0x47fecc SUB %R9,%RCX |
(742) 0x47fecf VXORPD %XMM1,%XMM1,%XMM1 |
(742) 0x47fed3 AND $0x3,%ECX |
(742) 0x47fed6 JE 4807cf |
(742) 0x47fedc CMP $0x1,%RCX |
(742) 0x47fee0 JE 47ff6e |
(742) 0x47fee6 CMP $0x2,%RCX |
(742) 0x47feea JE 47ff3a |
(742) 0x47feec MOV (%RDX,%R9,8),%RCX |
(742) 0x47fef0 MOV (%R14,%RCX,8),%R8 |
(742) 0x47fef4 CMP %R8,%R13 |
(742) 0x47fef7 JG 47ff20 |
(742) 0x47fef9 VMOVSD (%RBX,%R9,8),%XMM14 |
(742) 0x47feff VMULSD %XMM9,%XMM14,%XMM10 |
(742) 0x47ff04 VCOMISD %XMM10,%XMM1 |
(742) 0x47ff09 JBE 47ff29 |
(742) 0x47ff0b MOV -0xb0(%RBP),%R10 |
(742) 0x47ff12 LEA (%R10,%R8,8),%R9 |
(742) 0x47ff16 VFMADD213SD (%R9),%XMM0,%XMM14 |
(742) 0x47ff1b VMOVSD %XMM14,(%R9) |
(742) 0x47ff20 CMP %RCX,%R11 |
(742) 0x47ff23 JE 480d72 |
(742) 0x47ff29 MOV -0x1a0(%RBP),%R8 |
(742) 0x47ff30 INC %R8 |
(742) 0x47ff33 MOV %R8,-0x208(%RBP) |
(742) 0x47ff3a MOV -0x208(%RBP),%R10 |
(742) 0x47ff41 MOV (%RDX,%R10,8),%R9 |
(742) 0x47ff45 MOV (%R14,%R9,8),%RCX |
(742) 0x47ff49 CMP %RCX,%R13 |
(742) 0x47ff4c JG 480a3d |
(742) 0x47ff52 VMOVSD (%RBX,%R10,8),%XMM12 |
(742) 0x47ff58 VMULSD %XMM9,%XMM12,%XMM2 |
(742) 0x47ff5d VCOMISD %XMM2,%XMM1 |
(742) 0x47ff61 JA 480a28 |
(742) 0x47ff67 INCQ -0x208(%RBP) |
(742) 0x47ff6e MOV -0x208(%RBP),%R10 |
(742) 0x47ff75 MOV (%RDX,%R10,8),%RCX |
(742) 0x47ff79 MOV (%R14,%RCX,8),%R8 |
(742) 0x47ff7d CMP %R8,%R13 |
(742) 0x47ff80 JG 480971 |
(742) 0x47ff86 VMOVSD (%RBX,%R10,8),%XMM11 |
(742) 0x47ff8c VMULSD %XMM9,%XMM11,%XMM13 |
(742) 0x47ff91 VCOMISD %XMM13,%XMM1 |
(742) 0x47ff96 JA 48095c |
(742) 0x47ff9c INCQ -0x208(%RBP) |
(742) 0x47ffa3 MOV -0x208(%RBP),%RCX |
(742) 0x47ffaa CMP %RCX,-0x190(%RBP) |
(742) 0x47ffb1 JE 47fffa |
(742) 0x47ffb3 MOV %RAX,-0x1a0(%RBP) |
(742) 0x47ffba MOV (%RDX,%RCX,8),%RAX |
(742) 0x47ffbe MOV (%R14,%RAX,8),%R8 |
(742) 0x47ffc2 CMP %R8,%R13 |
(742) 0x47ffc5 JLE 4807e8 |
(744) 0x47ffcb CMP %RAX,%R11 |
(744) 0x47ffce JNE 4807fd |
(744) 0x47ffd4 VMOVSD (%RBX,%RCX,8),%XMM11 |
(744) 0x47ffd9 VMULSD %XMM9,%XMM11,%XMM13 |
(744) 0x47ffde VCOMISD %XMM13,%XMM1 |
(744) 0x47ffe3 JBE 4807fd |
(744) 0x47ffe9 VFMADD231SD %XMM11,%XMM0,%XMM4 |
(744) 0x47ffee JMP 4807fd |
(742) 0x47fff3 MOV -0x1a0(%RBP),%RAX |
(742) 0x47fffa CMPQ $0x1,-0x58(%RBP) |
(742) 0x47ffff JLE 47dbfa |
(742) 0x480005 MOV -0x238(%RBP),%RCX |
(742) 0x48000c MOV (%RCX,%RAX,8),%RAX |
(742) 0x480010 MOV 0x8(%RCX,%RDI,1),%R9 |
(742) 0x480015 CMP %R9,%RAX |
(742) 0x480018 JGE 47dbfa |
(742) 0x48001e MOV -0x70(%RBP),%RDI |
(742) 0x480022 MOV %R9,%R10 |
(742) 0x480025 VXORPD %XMM1,%XMM1,%XMM1 |
(742) 0x480029 SUB %RAX,%R10 |
(742) 0x48002c MOV 0xc8(%RDI),%R8 |
(742) 0x480033 AND $0x7,%R10D |
(742) 0x480037 JE 48023d |
(742) 0x48003d CMP $0x1,%R10 |
(742) 0x480041 JE 480211 |
(742) 0x480047 CMP $0x2,%R10 |
(742) 0x48004b JE 4801cc |
(742) 0x480051 CMP $0x3,%R10 |
(742) 0x480055 JE 480187 |
(742) 0x48005b CMP $0x4,%R10 |
(742) 0x48005f JE 480143 |
(742) 0x480065 CMP $0x5,%R10 |
(742) 0x480069 JE 4800fe |
(742) 0x48006f CMP $0x6,%R10 |
(742) 0x480073 JE 4800b9 |
(742) 0x480075 MOV -0x1b0(%RBP),%RCX |
(742) 0x48007c MOV -0x60(%RBP),%RDI |
(742) 0x480080 MOV (%RCX,%RAX,8),%R10 |
(742) 0x480084 MOV (%RDI,%R10,8),%RCX |
(742) 0x480088 CMP %RCX,-0x130(%RBP) |
(742) 0x48008f JG 4800b6 |
(742) 0x480091 MOV -0x1b8(%RBP),%R10 |
(742) 0x480098 VMOVSD (%R10,%RAX,8),%XMM12 |
(742) 0x48009e VMULSD %XMM9,%XMM12,%XMM2 |
(742) 0x4800a3 VCOMISD %XMM2,%XMM1 |
(742) 0x4800a7 JBE 4800b6 |
(742) 0x4800a9 LEA (%R8,%RCX,8),%RDI |
(742) 0x4800ad VFMADD213SD (%RDI),%XMM0,%XMM12 |
(742) 0x4800b2 VMOVSD %XMM12,(%RDI) |
(742) 0x4800b6 INC %RAX |
(742) 0x4800b9 MOV -0x1b0(%RBP),%RCX |
(742) 0x4800c0 MOV -0x60(%RBP),%RDI |
(742) 0x4800c4 MOV (%RCX,%RAX,8),%R10 |
(742) 0x4800c8 MOV (%RDI,%R10,8),%RCX |
(742) 0x4800cc CMP %RCX,-0x130(%RBP) |
(742) 0x4800d3 JG 4800fb |
(742) 0x4800d5 MOV -0x1b8(%RBP),%R10 |
(742) 0x4800dc VMOVSD (%R10,%RAX,8),%XMM14 |
(742) 0x4800e2 VMULSD %XMM9,%XMM14,%XMM10 |
(742) 0x4800e7 VCOMISD %XMM10,%XMM1 |
(742) 0x4800ec JBE 4800fb |
(742) 0x4800ee LEA (%R8,%RCX,8),%RDI |
(742) 0x4800f2 VFMADD213SD (%RDI),%XMM0,%XMM14 |
(742) 0x4800f7 VMOVSD %XMM14,(%RDI) |
(742) 0x4800fb INC %RAX |
(742) 0x4800fe MOV -0x1b0(%RBP),%RCX |
(742) 0x480105 MOV -0x60(%RBP),%RDI |
(742) 0x480109 MOV (%RCX,%RAX,8),%R10 |
(742) 0x48010d MOV (%RDI,%R10,8),%RCX |
(742) 0x480111 CMP %RCX,-0x130(%RBP) |
(742) 0x480118 JG 480140 |
(742) 0x48011a MOV -0x1b8(%RBP),%R10 |
(742) 0x480121 VMOVSD (%R10,%RAX,8),%XMM11 |
(742) 0x480127 VMULSD %XMM9,%XMM11,%XMM13 |
(742) 0x48012c VCOMISD %XMM13,%XMM1 |
(742) 0x480131 JBE 480140 |
(742) 0x480133 LEA (%R8,%RCX,8),%RDI |
(742) 0x480137 VFMADD213SD (%RDI),%XMM0,%XMM11 |
(742) 0x48013c VMOVSD %XMM11,(%RDI) |
(742) 0x480140 INC %RAX |
(742) 0x480143 MOV -0x1b0(%RBP),%RCX |
(742) 0x48014a MOV -0x60(%RBP),%RDI |
(742) 0x48014e MOV (%RCX,%RAX,8),%R10 |
(742) 0x480152 MOV (%RDI,%R10,8),%RCX |
(742) 0x480156 CMP %RCX,-0x130(%RBP) |
(742) 0x48015d JG 480184 |
(742) 0x48015f MOV -0x1b8(%RBP),%R10 |
(742) 0x480166 VMOVSD (%R10,%RAX,8),%XMM12 |
(742) 0x48016c VMULSD %XMM9,%XMM12,%XMM2 |
(742) 0x480171 VCOMISD %XMM2,%XMM1 |
(742) 0x480175 JBE 480184 |
(742) 0x480177 LEA (%R8,%RCX,8),%RDI |
(742) 0x48017b VFMADD213SD (%RDI),%XMM0,%XMM12 |
(742) 0x480180 VMOVSD %XMM12,(%RDI) |
(742) 0x480184 INC %RAX |
(742) 0x480187 MOV -0x1b0(%RBP),%RCX |
(742) 0x48018e MOV -0x60(%RBP),%RDI |
(742) 0x480192 MOV (%RCX,%RAX,8),%R10 |
(742) 0x480196 MOV (%RDI,%R10,8),%RCX |
(742) 0x48019a CMP %RCX,-0x130(%RBP) |
(742) 0x4801a1 JG 4801c9 |
(742) 0x4801a3 MOV -0x1b8(%RBP),%R10 |
(742) 0x4801aa VMOVSD (%R10,%RAX,8),%XMM14 |
(742) 0x4801b0 VMULSD %XMM9,%XMM14,%XMM10 |
(742) 0x4801b5 VCOMISD %XMM10,%XMM1 |
(742) 0x4801ba JBE 4801c9 |
(742) 0x4801bc LEA (%R8,%RCX,8),%RDI |
(742) 0x4801c0 VFMADD213SD (%RDI),%XMM0,%XMM14 |
(742) 0x4801c5 VMOVSD %XMM14,(%RDI) |
(742) 0x4801c9 INC %RAX |
(742) 0x4801cc MOV -0x1b0(%RBP),%RCX |
(742) 0x4801d3 MOV -0x60(%RBP),%RDI |
(742) 0x4801d7 MOV (%RCX,%RAX,8),%R10 |
(742) 0x4801db MOV (%RDI,%R10,8),%RCX |
(742) 0x4801df CMP %RCX,-0x130(%RBP) |
(742) 0x4801e6 JG 48020e |
(742) 0x4801e8 MOV -0x1b8(%RBP),%R10 |
(742) 0x4801ef VMOVSD (%R10,%RAX,8),%XMM11 |
(742) 0x4801f5 VMULSD %XMM9,%XMM11,%XMM13 |
(742) 0x4801fa VCOMISD %XMM13,%XMM1 |
(742) 0x4801ff JBE 48020e |
(742) 0x480201 LEA (%R8,%RCX,8),%RDI |
(742) 0x480205 VFMADD213SD (%RDI),%XMM0,%XMM11 |
(742) 0x48020a VMOVSD %XMM11,(%RDI) |
(742) 0x48020e INC %RAX |
(742) 0x480211 MOV -0x1b0(%RBP),%RCX |
(742) 0x480218 MOV -0x60(%RBP),%RDI |
(742) 0x48021c MOV (%RCX,%RAX,8),%R10 |
(742) 0x480220 MOV (%RDI,%R10,8),%RCX |
(742) 0x480224 CMP %RCX,-0x130(%RBP) |
(742) 0x48022b JLE 480bec |
(742) 0x480231 INC %RAX |
(742) 0x480234 CMP %RAX,%R9 |
(742) 0x480237 JE 47dbfa |
(742) 0x48023d MOV -0x1b0(%RBP),%RCX |
(742) 0x480244 MOV -0x130(%RBP),%RDI |
(742) 0x48024b MOV %R14,-0x190(%RBP) |
(742) 0x480252 MOV %RDX,-0x1a0(%RBP) |
(742) 0x480259 MOV -0x60(%RBP),%RDX |
(742) 0x48025d MOV %RSI,-0x208(%RBP) |
(742) 0x480264 MOV -0x1b8(%RBP),%RSI |
(743) 0x48026b MOV (%RCX,%RAX,8),%R14 |
(743) 0x48026f MOV (%RDX,%R14,8),%R10 |
(743) 0x480273 CMP %R10,%RDI |
(743) 0x480276 JG 480297 |
(743) 0x480278 VMOVSD (%RSI,%RAX,8),%XMM14 |
(743) 0x48027d VMULSD %XMM9,%XMM14,%XMM10 |
(743) 0x480282 VCOMISD %XMM10,%XMM1 |
(743) 0x480287 JBE 480297 |
(743) 0x480289 LEA (%R8,%R10,8),%R14 |
(743) 0x48028d VFMADD213SD (%R14),%XMM0,%XMM14 |
(743) 0x480292 VMOVSD %XMM14,(%R14) |
(743) 0x480297 INC %RAX |
(743) 0x48029a MOV (%RCX,%RAX,8),%R10 |
(743) 0x48029e MOV (%RDX,%R10,8),%R14 |
(743) 0x4802a2 CMP %R14,%RDI |
(743) 0x4802a5 JG 4802c6 |
(743) 0x4802a7 VMOVSD (%RSI,%RAX,8),%XMM11 |
(743) 0x4802ac VMULSD %XMM9,%XMM11,%XMM13 |
(743) 0x4802b1 VCOMISD %XMM13,%XMM1 |
(743) 0x4802b6 JBE 4802c6 |
(743) 0x4802b8 LEA (%R8,%R14,8),%R10 |
(743) 0x4802bc VFMADD213SD (%R10),%XMM0,%XMM11 |
(743) 0x4802c1 VMOVSD %XMM11,(%R10) |
(743) 0x4802c6 LEA 0x1(%RAX),%R10 |
(743) 0x4802ca MOV (%RCX,%R10,8),%R14 |
(743) 0x4802ce MOV (%RDX,%R14,8),%R14 |
(743) 0x4802d2 CMP %R14,%RDI |
(743) 0x4802d5 JG 4802f6 |
(743) 0x4802d7 VMOVSD (%RSI,%R10,8),%XMM12 |
(743) 0x4802dd VMULSD %XMM9,%XMM12,%XMM2 |
(743) 0x4802e2 VCOMISD %XMM2,%XMM1 |
(743) 0x4802e6 JBE 4802f6 |
(743) 0x4802e8 LEA (%R8,%R14,8),%R10 |
(743) 0x4802ec VFMADD213SD (%R10),%XMM0,%XMM12 |
(743) 0x4802f1 VMOVSD %XMM12,(%R10) |
(743) 0x4802f6 LEA 0x2(%RAX),%R10 |
(743) 0x4802fa MOV (%RCX,%R10,8),%R14 |
(743) 0x4802fe MOV (%RDX,%R14,8),%R14 |
(743) 0x480302 CMP %R14,%RDI |
(743) 0x480305 JG 480327 |
(743) 0x480307 VMOVSD (%RSI,%R10,8),%XMM14 |
(743) 0x48030d VMULSD %XMM9,%XMM14,%XMM10 |
(743) 0x480312 VCOMISD %XMM10,%XMM1 |
(743) 0x480317 JBE 480327 |
(743) 0x480319 LEA (%R8,%R14,8),%R10 |
(743) 0x48031d VFMADD213SD (%R10),%XMM0,%XMM14 |
(743) 0x480322 VMOVSD %XMM14,(%R10) |
(743) 0x480327 LEA 0x3(%RAX),%R10 |
(743) 0x48032b MOV (%RCX,%R10,8),%R14 |
(743) 0x48032f MOV (%RDX,%R14,8),%R14 |
(743) 0x480333 CMP %R14,%RDI |
(743) 0x480336 JG 480358 |
(743) 0x480338 VMOVSD (%RSI,%R10,8),%XMM11 |
(743) 0x48033e VMULSD %XMM9,%XMM11,%XMM13 |
(743) 0x480343 VCOMISD %XMM13,%XMM1 |
(743) 0x480348 JBE 480358 |
(743) 0x48034a LEA (%R8,%R14,8),%R10 |
(743) 0x48034e VFMADD213SD (%R10),%XMM0,%XMM11 |
(743) 0x480353 VMOVSD %XMM11,(%R10) |
(743) 0x480358 LEA 0x4(%RAX),%R10 |
(743) 0x48035c MOV (%RCX,%R10,8),%R14 |
(743) 0x480360 MOV (%RDX,%R14,8),%R14 |
(743) 0x480364 CMP %R14,%RDI |
(743) 0x480367 JG 480388 |
(743) 0x480369 VMOVSD (%RSI,%R10,8),%XMM12 |
(743) 0x48036f VMULSD %XMM9,%XMM12,%XMM2 |
(743) 0x480374 VCOMISD %XMM2,%XMM1 |
(743) 0x480378 JBE 480388 |
(743) 0x48037a LEA (%R8,%R14,8),%R10 |
(743) 0x48037e VFMADD213SD (%R10),%XMM0,%XMM12 |
(743) 0x480383 VMOVSD %XMM12,(%R10) |
(743) 0x480388 LEA 0x5(%RAX),%R10 |
(743) 0x48038c MOV (%RCX,%R10,8),%R14 |
(743) 0x480390 MOV (%RDX,%R14,8),%R14 |
(743) 0x480394 CMP %R14,%RDI |
(743) 0x480397 JG 4803b9 |
(743) 0x480399 VMOVSD (%RSI,%R10,8),%XMM14 |
(743) 0x48039f VMULSD %XMM9,%XMM14,%XMM10 |
(743) 0x4803a4 VCOMISD %XMM10,%XMM1 |
(743) 0x4803a9 JBE 4803b9 |
(743) 0x4803ab LEA (%R8,%R14,8),%R10 |
(743) 0x4803af VFMADD213SD (%R10),%XMM0,%XMM14 |
(743) 0x4803b4 VMOVSD %XMM14,(%R10) |
(743) 0x4803b9 LEA 0x6(%RAX),%R10 |
(743) 0x4803bd MOV (%RCX,%R10,8),%R14 |
(743) 0x4803c1 MOV (%RDX,%R14,8),%R14 |
(743) 0x4803c5 CMP %R14,%RDI |
(743) 0x4803c8 JG 4803ea |
(743) 0x4803ca VMOVSD (%RSI,%R10,8),%XMM11 |
(743) 0x4803d0 VMULSD %XMM9,%XMM11,%XMM13 |
(743) 0x4803d5 VCOMISD %XMM13,%XMM1 |
(743) 0x4803da JBE 4803ea |
(743) 0x4803dc LEA (%R8,%R14,8),%R10 |
(743) 0x4803e0 VFMADD213SD (%R10),%XMM0,%XMM11 |
(743) 0x4803e5 VMOVSD %XMM11,(%R10) |
(743) 0x4803ea ADD $0x7,%RAX |
(743) 0x4803ee CMP %RAX,%R9 |
(743) 0x4803f1 JNE 48026b |
(742) 0x4803f7 MOV -0x190(%RBP),%R14 |
(742) 0x4803fe MOV -0x1a0(%RBP),%RDX |
(742) 0x480405 MOV -0x208(%RBP),%RSI |
(742) 0x48040c JMP 47dbfa |
0x480411 NOPL (%RAX) |
(749) 0x480418 MOV %RDI,-0x1a0(%RBP) |
(749) 0x48041f MOV -0x128(%RBP),%R14 |
(749) 0x480426 MOV %RCX,-0x1c8(%RBP) |
(749) 0x48042d MOV -0xf8(%RBP),%RCX |
(749) 0x480434 NOPL (%RAX) |
(750) 0x480438 MOV (%RCX,%RAX,8),%R8 |
(750) 0x48043c CMPQ $0,(%R15,%R8,8) |
(750) 0x480441 LEA (,%R8,8),%R11 |
(750) 0x480449 JS 480472 |
(750) 0x48044b MOV -0x60(%RBP),%RDI |
(750) 0x48044f ADD %RDI,%R11 |
(750) 0x480452 CMP (%R11),%RDX |
(750) 0x480455 JLE 480472 |
(750) 0x480457 MOV %R14,(%R11) |
(750) 0x48045a MOV -0x58(%RBP),%R11 |
(750) 0x48045e MOV %R8,(%R11,%R14,8) |
(750) 0x480462 MOV -0x108(%RBP),%R8 |
(750) 0x480469 VMOVSD %XMM3,(%R8,%R14,8) |
(750) 0x48046f INC %R14 |
(750) 0x480472 INC %RAX |
(750) 0x480475 CMP %RAX,(%RSI) |
(750) 0x480478 JG 480438 |
(749) 0x48047a MOV -0x1a0(%RBP),%RDI |
(749) 0x480481 MOV -0x1c8(%RBP),%RCX |
(749) 0x480488 MOV %R14,-0x128(%RBP) |
(749) 0x48048f MOV -0x190(%RBP),%R14 |
(749) 0x480496 JMP 47d99a |
0x48049b NOPL (%RAX,%RAX,1) |
(762) 0x4804a0 MOV %R10,-0x128(%RBP) |
(762) 0x4804a7 MOV %R8,-0x130(%RBP) |
(762) 0x4804ae MOV %RSI,-0x2f0(%RBP) |
(762) 0x4804b5 MOV -0xf8(%RBP),%RSI |
(762) 0x4804bc NOPL (%RAX) |
(763) 0x4804c0 MOV (%RSI,%RDX,8),%R9 |
(763) 0x4804c4 CMPQ $0,(%R15,%R9,8) |
(763) 0x4804c9 LEA (,%R9,8),%R12 |
(763) 0x4804d1 JS 4804fe |
(763) 0x4804d3 MOV -0x60(%RBP),%R8 |
(763) 0x4804d7 ADD %R8,%R12 |
(763) 0x4804da MOV -0x38(%RBP),%R8 |
(763) 0x4804de MOV (%R12),%R10 |
(763) 0x4804e2 CMP %R10,(%R8,%RAX,8) |
(763) 0x4804e6 JLE 4804fe |
(763) 0x4804e8 MOV -0xf0(%RBP),%R8 |
(763) 0x4804ef MOVQ $0x1,(%R8,%R9,8) |
(763) 0x4804f7 MOV %RCX,(%R12) |
(763) 0x4804fb INC %RCX |
(763) 0x4804fe INC %RDX |
(763) 0x480501 CMP %RDX,(%RDI) |
(763) 0x480504 JG 4804c0 |
(762) 0x480506 MOV -0x128(%RBP),%R10 |
(762) 0x48050d MOV -0x130(%RBP),%R8 |
(762) 0x480514 MOV -0x2f0(%RBP),%RSI |
(762) 0x48051b JMP 47ce18 |
0x480520 MOV $0x8,%ESI |
0x480525 MOV %RBX,%RDI |
0x480528 VMOVSD %XMM3,-0xb0(%RBP) |
0x480530 CALL 5b0aa0 <hypre_CAlloc> |
0x480535 MOV -0x70(%RBP),%R15 |
0x480539 MOV $0x8,%ESI |
0x48053e MOV %RAX,0xc0(%R15) |
0x480545 MOV 0xe0(%R15),%RDI |
0x48054c CALL 5b0aa0 <hypre_CAlloc> |
0x480551 MOV 0xe8(%R15),%RDI |
0x480558 VMOVSD -0xb0(%RBP),%XMM3 |
0x480560 MOV %RAX,0xb0(%R15) |
0x480567 TEST %RDI,%RDI |
0x48056a JE 47eae7 |
0x480570 MOV $0x8,%ESI |
0x480575 VMOVSD %XMM3,-0xb0(%RBP) |
0x48057d CALL 5b0aa0 <hypre_CAlloc> |
0x480582 MOV -0x70(%RBP),%R12 |
0x480586 MOV $0x8,%ESI |
0x48058b MOV %RAX,0xd8(%R12) |
0x480593 MOV 0xe8(%R12),%RDI |
0x48059b CALL 5b0aa0 <hypre_CAlloc> |
0x4805a0 MOV 0x38(%R12),%RDI |
0x4805a5 VMOVSD -0xb0(%RBP),%XMM3 |
0x4805ad MOV %RAX,0xc8(%R12) |
0x4805b5 CMPQ $0x1,(%RDI) |
0x4805b9 JG 47eaf9 |
0x4805bf JMP 47d7e5 |
(742) 0x4805c4 VADDSD %XMM12,%XMM10,%XMM10 |
(742) 0x4805c9 JMP 47e6b2 |
(742) 0x4805ce VADDSD %XMM11,%XMM10,%XMM10 |
(742) 0x4805d3 JMP 47e6e9 |
(742) 0x4805d8 VADDSD %XMM0,%XMM10,%XMM10 |
(742) 0x4805dc JMP 47e728 |
0x4805e1 VMOVSD %XMM3,-0xb0(%RBP) |
0x4805e9 CALL 5b3c40 <time_getWallclockSeconds> |
0x4805ee MOV -0x70(%RBP),%R12 |
0x4805f2 MOV $0x5ba480,%EDI |
0x4805f7 MOV $0x1,%EAX |
0x4805fc VSUBSD 0x178(%R12),%XMM0,%XMM0 |
0x480606 MOV 0x30(%R12),%R8 |
0x48060b MOV (%R8),%RSI |
0x48060e VMOVSD %XMM0,0x178(%R12) |
0x480618 CALL 5b0cd0 <hypre_printf> |
0x48061d XOR %EDI,%EDI |
0x48061f CALL 4115b0 <fflush@plt> |
0x480624 CALL 5b3c40 <time_getWallclockSeconds> |
0x480629 VMOVSD -0xb0(%RBP),%XMM3 |
0x480631 VMOVSD %XMM0,0x178(%R12) |
0x48063b JMP 47eaac |
0x480640 MOV -0x40(%RBP),%RSI |
0x480644 LEA 0x1(%RSI),%RDI |
0x480648 SUB %RAX,%RSI |
0x48064b INC %RSI |
0x48064e AND $0x7,%ESI |
0x480651 JE 480d65 |
0x480657 CMP $0x1,%RSI |
0x48065b JE 480719 |
0x480661 CMP $0x2,%RSI |
0x480665 JE 480700 |
0x48066b CMP $0x3,%RSI |
0x48066f JE 4806e7 |
0x480671 CMP $0x4,%RSI |
0x480675 JE 4806ce |
0x480677 CMP $0x5,%RSI |
0x48067b JE 4806b5 |
0x48067d CMP $0x6,%RSI |
0x480681 JE 48069c |
0x480683 MOV (%R11),%R12 |
0x480686 MOV -0x58(%RBP),%RCX |
0x48068a MOV -0x38(%RBP),%RBX |
0x48068e ADD %R12,(%RCX,%RAX,8) |
0x480692 MOV (%RDX),%R9 |
0x480695 ADD %R9,(%RBX,%RAX,8) |
0x480699 INC %RAX |
0x48069c MOV (%R11),%R8 |
0x48069f MOV -0x58(%RBP),%R15 |
0x4806a3 MOV -0x38(%RBP),%R12 |
0x4806a7 ADD %R8,(%R15,%RAX,8) |
0x4806ab MOV (%RDX),%RSI |
0x4806ae ADD %RSI,(%R12,%RAX,8) |
0x4806b2 INC %RAX |
0x4806b5 MOV (%R11),%RCX |
0x4806b8 MOV -0x58(%RBP),%R9 |
0x4806bc MOV -0x38(%RBP),%RBX |
0x4806c0 ADD %RCX,(%R9,%RAX,8) |
0x4806c4 MOV (%RDX),%R8 |
0x4806c7 ADD %R8,(%RBX,%RAX,8) |
0x4806cb INC %RAX |
0x4806ce MOV (%R11),%R15 |
0x4806d1 MOV -0x58(%RBP),%RSI |
0x4806d5 MOV -0x38(%RBP),%RCX |
0x4806d9 ADD %R15,(%RSI,%RAX,8) |
0x4806dd MOV (%RDX),%R12 |
0x4806e0 ADD %R12,(%RCX,%RAX,8) |
0x4806e4 INC %RAX |
0x4806e7 MOV (%R11),%R9 |
0x4806ea MOV -0x58(%RBP),%R8 |
0x4806ee MOV -0x38(%RBP),%RBX |
0x4806f2 ADD %R9,(%R8,%RAX,8) |
0x4806f6 MOV (%RDX),%R15 |
0x4806f9 ADD %R15,(%RBX,%RAX,8) |
0x4806fd INC %RAX |
0x480700 MOV (%R11),%RSI |
0x480703 MOV -0x58(%RBP),%R12 |
0x480707 MOV -0x38(%RBP),%R9 |
0x48070b ADD %RSI,(%R12,%RAX,8) |
0x48070f MOV (%RDX),%RCX |
0x480712 ADD %RCX,(%R9,%RAX,8) |
0x480716 INC %RAX |
0x480719 MOV (%R11),%R8 |
0x48071c MOV -0x58(%RBP),%R15 |
0x480720 MOV -0x38(%RBP),%RBX |
0x480724 ADD %R8,(%R15,%RAX,8) |
0x480728 MOV (%RDX),%RSI |
0x48072b ADD %RSI,(%RBX,%RAX,8) |
0x48072f INC %RAX |
0x480732 CMP %RDI,%RAX |
0x480735 JE 47d595 |
0x48073b MOV -0x58(%RBP),%R12 |
(757) 0x48073f MOV (%R11),%RCX |
(757) 0x480742 ADD %RCX,(%R12,%RAX,8) |
(757) 0x480746 MOV (%RDX),%R9 |
(757) 0x480749 ADD %R9,(%RBX,%RAX,8) |
(757) 0x48074d MOV (%R11),%R8 |
(757) 0x480750 ADD %R8,0x8(%R12,%RAX,8) |
(757) 0x480755 MOV (%RDX),%R15 |
(757) 0x480758 ADD %R15,0x8(%RBX,%RAX,8) |
(757) 0x48075d MOV (%R11),%RSI |
(757) 0x480760 ADD %RSI,0x10(%R12,%RAX,8) |
(757) 0x480765 MOV (%RDX),%RCX |
(757) 0x480768 ADD %RCX,0x10(%RBX,%RAX,8) |
(757) 0x48076d MOV (%R11),%R9 |
(757) 0x480770 ADD %R9,0x18(%R12,%RAX,8) |
(757) 0x480775 MOV (%RDX),%R8 |
(757) 0x480778 ADD %R8,0x18(%RBX,%RAX,8) |
(757) 0x48077d MOV (%R11),%R15 |
(757) 0x480780 ADD %R15,0x20(%R12,%RAX,8) |
(757) 0x480785 MOV (%RDX),%RSI |
(757) 0x480788 ADD %RSI,0x20(%RBX,%RAX,8) |
(757) 0x48078d MOV (%R11),%RCX |
(757) 0x480790 ADD %RCX,0x28(%R12,%RAX,8) |
(757) 0x480795 MOV (%RDX),%R9 |
(757) 0x480798 ADD %R9,0x28(%RBX,%RAX,8) |
(757) 0x48079d MOV (%R11),%R8 |
(757) 0x4807a0 ADD %R8,0x30(%R12,%RAX,8) |
(757) 0x4807a5 MOV (%RDX),%R15 |
(757) 0x4807a8 ADD %R15,0x30(%RBX,%RAX,8) |
(757) 0x4807ad MOV (%R11),%RSI |
(757) 0x4807b0 ADD %RSI,0x38(%R12,%RAX,8) |
(757) 0x4807b5 MOV (%RDX),%RCX |
(757) 0x4807b8 ADD %RCX,0x38(%RBX,%RAX,8) |
(757) 0x4807bd ADD $0x8,%RAX |
(757) 0x4807c1 CMP %RDI,%RAX |
(757) 0x4807c4 JNE 48073f |
0x4807ca JMP 47d595 |
(742) 0x4807cf MOV %RAX,-0x1a0(%RBP) |
(742) 0x4807d6 MOV -0x208(%RBP),%RCX |
(742) 0x4807dd JMP 480884 |
0x4807e2 NOPW (%RAX,%RAX,1) |
(744) 0x4807e8 VMOVSD (%RBX,%RCX,8),%XMM14 |
(744) 0x4807ed VMULSD %XMM9,%XMM14,%XMM10 |
(744) 0x4807f2 VCOMISD %XMM10,%XMM1 |
(744) 0x4807f7 JA 4809f7 |
(744) 0x4807fd INC %RCX |
(744) 0x480800 MOV (%RDX,%RCX,8),%RAX |
(744) 0x480804 MOV (%R14,%RAX,8),%R8 |
(744) 0x480808 CMP %R8,%R13 |
(744) 0x48080b JG 480927 |
(744) 0x480811 VMOVSD (%RBX,%RCX,8),%XMM12 |
(744) 0x480816 VMULSD %XMM9,%XMM12,%XMM2 |
(744) 0x48081b VCOMISD %XMM2,%XMM1 |
(744) 0x48081f JA 480912 |
(744) 0x480825 LEA 0x1(%RCX),%R8 |
(744) 0x480829 MOV (%RDX,%R8,8),%R9 |
(744) 0x48082d MOV (%R14,%R9,8),%R10 |
(744) 0x480831 CMP %R10,%R13 |
(744) 0x480834 JG 4808ea |
(744) 0x48083a VMOVSD (%RBX,%R8,8),%XMM11 |
(744) 0x480840 VMULSD %XMM9,%XMM11,%XMM13 |
(744) 0x480845 VCOMISD %XMM13,%XMM1 |
(744) 0x48084a JA 4808d5 |
(744) 0x480850 LEA 0x2(%RCX),%R8 |
(744) 0x480854 MOV (%RDX,%R8,8),%R9 |
(744) 0x480858 MOV (%R14,%R9,8),%R10 |
(744) 0x48085c CMP %R10,%R13 |
(744) 0x48085f JG 4808b7 |
(744) 0x480861 VMOVSD (%RBX,%R8,8),%XMM14 |
(744) 0x480867 VMULSD %XMM9,%XMM14,%XMM10 |
(744) 0x48086c VCOMISD %XMM10,%XMM1 |
(744) 0x480871 JA 4808a2 |
(744) 0x480873 ADD $0x3,%RCX |
(744) 0x480877 CMP %RCX,-0x190(%RBP) |
(744) 0x48087e JE 47fff3 |
(744) 0x480884 MOV (%RDX,%RCX,8),%RAX |
(744) 0x480888 MOV (%R14,%RAX,8),%R8 |
(744) 0x48088c CMP %R8,%R13 |
(744) 0x48088f JLE 4807e8 |
(744) 0x480895 JMP 47ffcb |
0x48089a VZEROUPPER |
0x48089d JMP 47d7f3 |
(744) 0x4808a2 MOV -0xb0(%RBP),%RAX |
(744) 0x4808a9 LEA (%RAX,%R10,8),%R10 |
(744) 0x4808ad VFMADD213SD (%R10),%XMM0,%XMM14 |
(744) 0x4808b2 VMOVSD %XMM14,(%R10) |
(744) 0x4808b7 CMP %R9,%R11 |
(744) 0x4808ba JNE 480873 |
(744) 0x4808bc VMOVSD (%RBX,%R8,8),%XMM11 |
(744) 0x4808c2 VMULSD %XMM9,%XMM11,%XMM13 |
(744) 0x4808c7 VCOMISD %XMM13,%XMM1 |
(744) 0x4808cc JBE 480873 |
(744) 0x4808ce VFMADD231SD %XMM11,%XMM0,%XMM4 |
(744) 0x4808d3 JMP 480873 |
(744) 0x4808d5 MOV -0xb0(%RBP),%RAX |
(744) 0x4808dc LEA (%RAX,%R10,8),%R10 |
(744) 0x4808e0 VFMADD213SD (%R10),%XMM0,%XMM11 |
(744) 0x4808e5 VMOVSD %XMM11,(%R10) |
(744) 0x4808ea CMP %R9,%R11 |
(744) 0x4808ed JNE 480850 |
(744) 0x4808f3 VMOVSD (%RBX,%R8,8),%XMM12 |
(744) 0x4808f9 VMULSD %XMM9,%XMM12,%XMM2 |
(744) 0x4808fe VCOMISD %XMM2,%XMM1 |
(744) 0x480902 JBE 480850 |
(744) 0x480908 VFMADD231SD %XMM12,%XMM0,%XMM4 |
(744) 0x48090d JMP 480850 |
(744) 0x480912 MOV -0xb0(%RBP),%R9 |
(744) 0x480919 LEA (%R9,%R8,8),%R10 |
(744) 0x48091d VFMADD213SD (%R10),%XMM0,%XMM12 |
(744) 0x480922 VMOVSD %XMM12,(%R10) |
(744) 0x480927 CMP %RAX,%R11 |
(744) 0x48092a JNE 480825 |
(744) 0x480930 VMOVSD (%RBX,%RCX,8),%XMM14 |
(744) 0x480935 VMULSD %XMM9,%XMM14,%XMM10 |
(744) 0x48093a VCOMISD %XMM10,%XMM1 |
(744) 0x48093f JBE 480825 |
(744) 0x480945 VFMADD231SD %XMM14,%XMM0,%XMM4 |
(744) 0x48094a JMP 480825 |
0x48094f NOP |
(742) 0x480950 MOV -0x230(%RBP),%R8 |
(742) 0x480957 JMP 47e44c |
(742) 0x48095c MOV -0xb0(%RBP),%R9 |
(742) 0x480963 LEA (%R9,%R8,8),%R10 |
(742) 0x480967 VFMADD213SD (%R10),%XMM0,%XMM11 |
(742) 0x48096c VMOVSD %XMM11,(%R10) |
(742) 0x480971 CMP %RCX,%R11 |
(742) 0x480974 JNE 47ff9c |
(742) 0x48097a MOV -0x208(%RBP),%RCX |
(742) 0x480981 VMOVSD (%RBX,%RCX,8),%XMM12 |
(742) 0x480986 VMULSD %XMM9,%XMM12,%XMM2 |
(742) 0x48098b VCOMISD %XMM2,%XMM1 |
(742) 0x48098f JBE 47ff9c |
(742) 0x480995 VFMADD231SD %XMM12,%XMM0,%XMM4 |
(742) 0x48099a JMP 47ff9c |
0x48099f MOV %RBX,%RAX |
0x4809a2 XOR %R15D,%R15D |
0x4809a5 JMP 47d020 |
0x4809aa MOV (%R9),%RCX |
0x4809ad MOV -0x260(%RBP),%R8 |
0x4809b4 VMOVSD %XMM3,-0xb0(%RBP) |
0x4809bc MOV -0x48(%RBP),%RDX |
0x4809c0 MOV -0x268(%RBP),%RDI |
0x4809c7 CALL 54fcb0 <hypre_alt_insert_new_nodes> |
0x4809cc VMOVSD -0xb0(%RBP),%XMM3 |
0x4809d4 MOV -0x70(%RBP),%RCX |
0x4809d8 MOV 0x130(%RCX),%R10 |
0x4809df CMPQ $0,(%R10) |
0x4809e3 JG 47d834 |
0x4809e9 JMP 47d850 |
(742) 0x4809ee VMOVSD %XMM3,%XMM3,%XMM10 |
(742) 0x4809f2 JMP 47e728 |
(744) 0x4809f7 MOV -0xb0(%RBP),%R9 |
(744) 0x4809fe LEA (%R9,%R8,8),%R10 |
(744) 0x480a02 VFMADD213SD (%R10),%XMM0,%XMM14 |
(744) 0x480a07 VMOVSD %XMM14,(%R10) |
(744) 0x480a0c JMP 47ffcb |
(742) 0x480a11 MOV -0x1a0(%RBP),%R8 |
(742) 0x480a18 VMOVSD %XMM3,%XMM3,%XMM10 |
(742) 0x480a1c VXORPD %XMM11,%XMM11,%XMM11 |
(742) 0x480a21 XOR %ECX,%ECX |
(742) 0x480a23 JMP 47e5e2 |
(742) 0x480a28 MOV -0xb0(%RBP),%R8 |
(742) 0x480a2f LEA (%R8,%RCX,8),%R10 |
(742) 0x480a33 VFMADD213SD (%R10),%XMM0,%XMM12 |
(742) 0x480a38 VMOVSD %XMM12,(%R10) |
(742) 0x480a3d CMP %R9,%R11 |
(742) 0x480a40 JNE 47ff67 |
(742) 0x480a46 MOV -0x208(%RBP),%R9 |
(742) 0x480a4d VMOVSD (%RBX,%R9,8),%XMM14 |
(742) 0x480a53 VMULSD %XMM9,%XMM14,%XMM10 |
(742) 0x480a58 VCOMISD %XMM10,%XMM1 |
(742) 0x480a5d JBE 47ff67 |
(742) 0x480a63 VFMADD231SD %XMM14,%XMM0,%XMM4 |
(742) 0x480a68 JMP 47ff67 |
0x480a6d VZEROUPPER |
0x480a70 JMP 47d595 |
(739) 0x480a75 NOT %RDI |
(739) 0x480a78 CMP (%RDX,%RDI,8),%R15 |
(739) 0x480a7c JG 47f51a |
(739) 0x480a82 JMP 47f50d |
(741) 0x480a87 NOT %RSI |
(741) 0x480a8a MOV (%RDX,%RSI,8),%RSI |
(741) 0x480a8e CMP %RSI,%R15 |
(741) 0x480a91 JG 47fe21 |
(741) 0x480a97 VMOVSD 0x10(%R9),%XMM13 |
(741) 0x480a9d LEA (%RBX,%RSI,8),%RCX |
(741) 0x480aa1 VFMADD213SD (%RCX),%XMM2,%XMM13 |
(741) 0x480aa6 VMOVSD %XMM13,(%RCX) |
(741) 0x480aaa JMP 47fe21 |
(741) 0x480aaf NOT %RSI |
(741) 0x480ab2 MOV (%RDX,%RSI,8),%RSI |
(741) 0x480ab6 CMP %RSI,%R15 |
(741) 0x480ab9 JG 47fdf0 |
(741) 0x480abf VMOVSD 0x8(%R9),%XMM10 |
(741) 0x480ac5 LEA (%RBX,%RSI,8),%RCX |
(741) 0x480ac9 VFMADD213SD (%RCX),%XMM2,%XMM10 |
(741) 0x480ace VMOVSD %XMM10,(%RCX) |
(741) 0x480ad2 JMP 47fdf0 |
(741) 0x480ad7 NOT %RSI |
(741) 0x480ada MOV (%RDX,%RSI,8),%RSI |
(741) 0x480ade CMP %RSI,%R15 |
(741) 0x480ae1 JG 47fdbf |
(741) 0x480ae7 VMOVSD (%R9),%XMM12 |
(741) 0x480aec LEA (%RBX,%RSI,8),%RCX |
(741) 0x480af0 VFMADD213SD (%RCX),%XMM2,%XMM12 |
(741) 0x480af5 VMOVSD %XMM12,(%RCX) |
(741) 0x480af9 JMP 47fdbf |
(741) 0x480afe NOT %RSI |
(741) 0x480b01 MOV (%RDX,%RSI,8),%RSI |
(741) 0x480b05 CMP %RSI,%R15 |
(741) 0x480b08 JG 47fd85 |
(741) 0x480b0e VMOVSD (%R9),%XMM8 |
(741) 0x480b13 LEA (%RBX,%RSI,8),%RCX |
(741) 0x480b17 VFMADD213SD (%RCX),%XMM2,%XMM8 |
(741) 0x480b1c VMOVSD %XMM8,(%RCX) |
(741) 0x480b20 JMP 47fd85 |
0x480b25 MOV -0xb0(%RBP),%RBX |
0x480b2c JMP 47e97c |
(741) 0x480b31 MOV -0xb0(%RBP),%RCX |
(741) 0x480b38 VMOVSD 0x10(%R9),%XMM11 |
(741) 0x480b3e LEA (%RCX,%R12,8),%R12 |
(741) 0x480b42 VFMADD213SD (%R12),%XMM2,%XMM11 |
(741) 0x480b48 VMOVSD %XMM11,(%R12) |
(741) 0x480b4e JMP 47fe16 |
(741) 0x480b53 MOV -0xb0(%RBP),%RCX |
(741) 0x480b5a VMOVSD 0x8(%R9),%XMM14 |
(741) 0x480b60 LEA (%RCX,%R12,8),%R12 |
(741) 0x480b64 VFMADD213SD (%R12),%XMM2,%XMM14 |
(741) 0x480b6a VMOVSD %XMM14,(%R12) |
(741) 0x480b70 JMP 47fde5 |
(741) 0x480b75 MOV -0xb0(%RBP),%RCX |
(741) 0x480b7c VMOVSD (%R9),%XMM1 |
(741) 0x480b81 LEA (%RCX,%R12,8),%R12 |
(741) 0x480b85 VFMADD213SD (%R12),%XMM2,%XMM1 |
(741) 0x480b8b VMOVSD %XMM1,(%R12) |
(741) 0x480b91 JMP 47fdb5 |
(741) 0x480b96 MOV -0xb0(%RBP),%RCX |
(741) 0x480b9d VMOVSD (%R9),%XMM7 |
(741) 0x480ba2 LEA (%RCX,%RDI,8),%RDI |
(741) 0x480ba6 VFMADD213SD (%RDI),%XMM2,%XMM7 |
(741) 0x480bab VMOVSD %XMM7,(%RDI) |
(741) 0x480baf JMP 47fd7b |
(736) 0x480bb4 VMULPD (%RDX),%ZMM1,%ZMM7 |
(736) 0x480bba ADD $0x40,%RDX |
(736) 0x480bbe VXORPD %ZMM12,%ZMM7,%ZMM14 |
(736) 0x480bc4 VMOVUPD %ZMM14,-0x40(%RDX) |
(736) 0x480bcb JMP 47dd26 |
(736) 0x480bd0 VMULPD (%RSI),%ZMM9,%ZMM4 |
(736) 0x480bd6 ADD $0x40,%RSI |
(736) 0x480bda VXORPD %ZMM0,%ZMM4,%ZMM7 |
(736) 0x480be0 VMOVUPD %ZMM7,-0x40(%RSI) |
(736) 0x480be7 JMP 47dfc7 |
(742) 0x480bec MOV -0x1b8(%RBP),%R10 |
(742) 0x480bf3 VMOVSD (%R10,%RAX,8),%XMM12 |
(742) 0x480bf9 VMULSD %XMM9,%XMM12,%XMM2 |
(742) 0x480bfe VCOMISD %XMM2,%XMM1 |
(742) 0x480c02 JBE 480231 |
(742) 0x480c08 LEA (%R8,%RCX,8),%RDI |
(742) 0x480c0c VFMADD213SD (%RDI),%XMM0,%XMM12 |
(742) 0x480c11 VMOVSD %XMM12,(%RDI) |
(742) 0x480c15 JMP 480231 |
0x480c1a VMOVDQU64 (%R9),%ZMM6 |
0x480c20 ADD $0x40,%RAX |
0x480c24 VPSUBQ %ZMM12,%ZMM6,%ZMM0 |
0x480c2a VMOVDQA64 %ZMM6,-0xb0(%RBP) |
0x480c34 VMOVDQU64 %ZMM0,(%R9) |
0x480c3a JMP 47ed9d |
0x480c3f VPADDQ (%R11),%ZMM12,%ZMM13 |
0x480c45 ADD $0x40,%R10 |
0x480c49 VMOVDQU64 %ZMM13,(%R11) |
0x480c4f JMP 47eb8a |
(739) 0x480c54 NOT %R9 |
(739) 0x480c57 CMP (%RDX,%R9,8),%R15 |
(739) 0x480c5b JG 47f4cd |
(739) 0x480c61 JMP 47f4b9 |
(739) 0x480c66 NOT %RSI |
(739) 0x480c69 MOV (%RDX,%RSI,8),%RSI |
(739) 0x480c6d CMP %RSI,%R15 |
(739) 0x480c70 JG 47fd21 |
(739) 0x480c76 VMOVSD (%R9),%XMM9 |
(739) 0x480c7b LEA (%RBX,%RSI,8),%R10 |
(739) 0x480c7f VFMADD213SD (%R10),%XMM2,%XMM9 |
(739) 0x480c84 VMOVSD %XMM9,(%R10) |
(739) 0x480c89 JMP 47fd21 |
(739) 0x480c8e VXORPD %XMM7,%XMM7,%XMM7 |
(739) 0x480c92 VCOMISD %XMM7,%XMM3 |
(739) 0x480c96 JE 47f2da |
(739) 0x480c9c JMP 47f272 |
0x480ca1 MOV -0x108(%RBP),%R12 |
0x480ca8 CMP %R12,-0x40(%RBP) |
0x480cac JG 47d595 |
0x480cb2 JMP 47d7d0 |
(736) 0x480cb7 XOR %EBX,%EBX |
(736) 0x480cb9 JMP 47de7c |
(736) 0x480cbe XOR %EBX,%EBX |
(736) 0x480cc0 JMP 47e11c |
(742) 0x480cc5 VMOVSD %XMM2,%XMM2,%XMM10 |
(742) 0x480cc9 JMP 47e733 |
0x480cce MOV (%R9),%RCX |
0x480cd1 MOV -0x260(%RBP),%R8 |
0x480cd8 VMOVDQA64 %ZMM12,-0xf0(%RBP) |
0x480ce2 MOV -0x48(%RBP),%RDX |
0x480ce6 MOV -0x268(%RBP),%RDI |
0x480ced VMOVSD %XMM3,-0xb0(%RBP) |
0x480cf5 VZEROUPPER |
0x480cf8 CALL 54fcb0 <hypre_alt_insert_new_nodes> |
0x480cfd VMOVSD -0xb0(%RBP),%XMM3 |
0x480d05 VMOVDQA64 -0xf0(%RBP),%ZMM12 |
0x480d0f JMP 47ed43 |
(742) 0x480d14 VMOVSD %XMM10,%XMM10,%XMM2 |
(742) 0x480d18 VXORPD %XMM1,%XMM1,%XMM1 |
(742) 0x480d1c XOR %ECX,%ECX |
(742) 0x480d1e JMP 47f8b4 |
0x480d23 XOR %ESI,%ESI |
0x480d25 JMP 47eeff |
0x480d2a XOR %EAX,%EAX |
0x480d2c XOR %R12D,%R12D |
0x480d2f JMP 47ec8a |
(742) 0x480d34 VMOVSD %XMM2,%XMM2,%XMM10 |
(742) 0x480d38 JMP 47f975 |
(739) 0x480d3d NOT %RSI |
(739) 0x480d40 MOV (%RDX,%RSI,8),%RSI |
(739) 0x480d44 CMP %RSI,%R15 |
(739) 0x480d47 JG 47fcc6 |
(739) 0x480d4d VMOVSD (%R9),%XMM13 |
(739) 0x480d52 LEA (%RBX,%RSI,8),%R10 |
(739) 0x480d56 VFMADD213SD (%R10),%XMM2,%XMM13 |
(739) 0x480d5b VMOVSD %XMM13,(%R10) |
(739) 0x480d60 JMP 47fcc6 |
0x480d65 MOV -0x38(%RBP),%RBX |
0x480d69 MOV -0x58(%RBP),%R12 |
0x480d6d JMP 48073f |
(742) 0x480d72 MOV -0x1a0(%RBP),%RCX |
(742) 0x480d79 VMOVSD (%RBX,%RCX,8),%XMM11 |
(742) 0x480d7e VMULSD %XMM9,%XMM11,%XMM13 |
(742) 0x480d83 VCOMISD %XMM13,%XMM1 |
(742) 0x480d88 JBE 47ff29 |
(742) 0x480d8e VFMADD231SD %XMM11,%XMM0,%XMM4 |
(742) 0x480d93 JMP 47ff29 |
0x480d98 XOR %R9D,%R9D |
0x480d9b JMP 47d4da |
(739) 0x480da0 NOT %RSI |
(739) 0x480da3 MOV (%RDX,%RSI,8),%RSI |
(739) 0x480da7 CMP %RSI,%R15 |
(739) 0x480daa JG 47fc6b |
(739) 0x480db0 VMOVSD (%R9),%XMM10 |
(739) 0x480db5 LEA (%RBX,%RSI,8),%R10 |
(739) 0x480db9 VFMADD213SD (%R10),%XMM2,%XMM10 |
(739) 0x480dbe VMOVSD %XMM10,(%R10) |
(739) 0x480dc3 JMP 47fc6b |
0x480dc8 NOPL (%RAX,%RAX,1) |
Path / |
Source file and lines | par_lr_interp.c:1196-1757 |
Module | exec |
nb instructions | 1058 |
nb uops | 1144 |
loop length | 5148 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 6 |
used ymm registers | 9 |
used zmm registers | 15 |
nb stack references | 43 |
micro-operation queue | 194.00 cycles |
front end | 194.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 76.20 | 76.20 | 137.67 | 137.67 | 107.50 | 76.20 | 76.20 | 107.50 | 107.50 | 107.50 | 76.20 | 137.67 |
cycles | 76.20 | 76.20 | 137.67 | 137.67 | 107.50 | 76.20 | 76.20 | 107.50 | 107.50 | 107.50 | 76.20 | 137.67 |
Cycles executing div or sqrt instructions | 10.00 |
FE+BE cycles | 211.03-211.02 |
Stall cycles | 0.00 |
Front-end | 194.00 |
Dispatch | 137.67 |
DIV/SQRT | 10.00 |
Overall L1 | 194.00 |
all | 25% |
load | 31% |
store | 20% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 5% |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 23% |
load | 26% |
store | 18% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 96% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 7% |
all | 31% |
load | 38% |
store | 29% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 93% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 13% |
all | 13% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 29% |
load | 34% |
store | 27% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 91% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 12% |
other | 13% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x10(%RSP),%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
PUSHQ -0x8(%R13) | 2 | 0 | 0 | 0.33 | 0.33 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0.33 | 5-12 | 0.62 |
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x308,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDI,-0x70(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x158(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x140(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x138(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x128(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x120(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x118(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RBX,-0xb0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x110(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x170(%RDI),%XMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,-0x210(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x108(%RDI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x168(%RDI),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,-0x1f8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x160(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x150(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,-0x260(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x148(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11,-0x240(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,-0x258(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM6,-0x1d0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,-0x248(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xf8(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa8(%RAX),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RDI),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa0(%RAX),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R15,-0xf0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x98(%RAX),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x90(%RAX),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x80(%RAX),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RAX),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x88(%RAX),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x68(%RAX),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,-0xf8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x70(%RAX),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x60(%RAX),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,-0x68(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,-0x198(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x58(%RAX),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x50(%RAX),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x48(%RAX),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14,-0x1a8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,-0x1c0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,-0x1b0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,-0x238(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,-0x1b8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,-0x190(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,-0x100(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,-0x200(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,-0x120(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x40(%RAX),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RAX),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RAX),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RAX),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RAX),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R12,-0x188(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x8(%RAX),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14,-0x268(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,-0x178(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RAX),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,-0x250(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,-0x180(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,-0x110(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RSI,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 47f300 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x28a0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x70(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x130(%RSI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R10),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RDI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 47f3d0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2970> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R8,-0x1a0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,-0x130(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM3,-0x128(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b3bd0 <hypre_GetThreadNum> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RAX,-0x118(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b3bc0 <hypre_NumActiveThreads> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %R12,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVSD -0x128(%RBP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x1a0(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x100(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA -0x1(%RSI),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CQTO | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %RSI | 5 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 10 |
IMUL %RAX,%R9 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %R9,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %RCX,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R9,-0x108(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x130(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMOVE -0x100(%RBP),%RAX | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.50 |
CMP %R9,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RAX,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JLE 48099f <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3f3f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x70(%RBP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x108(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,-0x1c8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R8,-0x208(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x38(%R10),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,-0x230(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x58(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 47cd1b <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2bb> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RCX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x208(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x230(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x1c8(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,-0xf0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,-0x1c8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,-0x1a0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,-0x128(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM0,-0x130(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 411290 <GOMP_barrier@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x40(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x1c8(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x118(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x58(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x38(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xb0(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (,%R11,8),%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RBX,(%R9,%R11,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (,%R8,8),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RDX,(%RDI,%R11,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,(%RSI,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x128(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,-0x1c8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%R15,%R10,1),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RBX,(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0xf0(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x208(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RBX,%R10,1),%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RDX,(%RBX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 411290 <GOMP_barrier@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x118(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xf0(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x128(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x130(%RBP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %R15,%R15 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV -0x1a0(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JE 47e820 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1dc0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RCX,-0x118(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,-0xf0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 411290 <GOMP_barrier@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
TEST %R15,%R15 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
VMOVSD -0xf0(%RBP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x118(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x128(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x1c8(%RBP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JLE 47d7d0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xd70> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x108(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RAX,-0x40(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JL 480ca1 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x4241> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x40(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x108(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA -0x8(%R10),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%RDI,%RDX,1),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD %R9,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %RSI,%R15 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%R15),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R15,-0x118(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,-0x130(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP $0x2,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JBE 480640 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3be0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x38(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (,%RAX,8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0x58(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x8(%R12),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,-0x128(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%R8,%RSI,1),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R8,%RDI,1),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%RCX,%RDI,1),%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%RCX,%RSI,1),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x40,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RBX,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SETAE %R8B | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP %R15,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,-0xf0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SETAE %DIL | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
OR %EDI,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
CMP %R12,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SETAE %DIL | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP %RBX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x58(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SETAE %BL | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
OR %EBX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD %RSI,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x38(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
AND %R8D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
CMP %RCX,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x208(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SETAE %R8B | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD %RBX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0xf0(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %RSI,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SETAE %SIL | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
OR %ESI,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
AND %EDI,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
CMP %RCX,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SETAE %SIL | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP %R15,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SETAE %R15B | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
OR %R15D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
TEST %SIL,%R8B | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 480640 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3be0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP %RCX,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SETAE %R8B | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP %R12,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SETAE %R12B | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
OR %R8B,%R12B | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 480640 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3be0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMPQ $0x6,-0x130(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JBE 480d98 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x4338> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x118(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VPBROADCASTQ (%R11),%ZMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
XOR %ESI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPBROADCASTQ (%RDX),%ZMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
SHR $0x3,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
SAL $0x6,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA -0x40(%R8),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SHR $0x6,%RDI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
INC %RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $0x7,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 47d39f <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x93f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x1,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47d36f <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x90f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x2,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47d348 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x8e8> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x3,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47d321 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x8c1> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x4,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47d2fa <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x89a> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x5,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47d2d3 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x873> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x6,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47d2ac <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x84c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VPADDQ (%RBX),%ZMM4,%ZMM2 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
MOV $0x40,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVDQU64 %ZMM2,(%RBX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ (%R9),%ZMM5,%ZMM7 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM7,(%R9) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
MOV -0xf0(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VPADDQ (%RBX,%RSI,1),%ZMM4,%ZMM8 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM8,(%RBX,%RSI,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ (%R9,%RSI,1),%ZMM5,%ZMM9 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM9,(%R9,%RSI,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
ADD $0x40,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0xf0(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VPADDQ (%R15,%RSI,1),%ZMM4,%ZMM10 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM10,(%R15,%RSI,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ (%R9,%RSI,1),%ZMM5,%ZMM11 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM11,(%R9,%RSI,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
ADD $0x40,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0xf0(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VPADDQ (%RCX,%RSI,1),%ZMM4,%ZMM12 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM12,(%RCX,%RSI,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ (%R9,%RSI,1),%ZMM5,%ZMM13 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM13,(%R9,%RSI,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
ADD $0x40,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0xf0(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VPADDQ (%R12,%RSI,1),%ZMM4,%ZMM14 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM14,(%R12,%RSI,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ (%R9,%RSI,1),%ZMM5,%ZMM15 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM15,(%R9,%RSI,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
ADD $0x40,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0xf0(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VPADDQ (%RDI,%RSI,1),%ZMM4,%ZMM6 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM6,(%RDI,%RSI,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ (%R9,%RSI,1),%ZMM5,%ZMM0 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM0,(%R9,%RSI,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
ADD $0x40,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0xf0(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VPADDQ (%RBX,%RSI,1),%ZMM4,%ZMM1 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM1,(%RBX,%RSI,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ (%R9,%RSI,1),%ZMM5,%ZMM2 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM2,(%R9,%RSI,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
ADD $0x40,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %R8,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47d4ab <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xa4b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x118(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x8,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD %R9,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
TEST $0x7,%R8B | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 480a6d <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x400d> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
SUB %R9,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%R8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R8,-0x118(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP $0x2,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JBE 47d536 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xad6> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x128(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x58(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VPBROADCASTQ (%R11),%YMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
MOV (%RDX),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R15,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x38(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SAL $0x3,%R9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
VPBROADCASTQ %RBX,%YMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%RCX,%R9,1),%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD %RDI,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VPADDQ (%R12),%YMM4,%YMM5 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VMOVDQU %YMM5,(%R12) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VPADDQ (%R9),%YMM10,%YMM11 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VMOVDQU %YMM11,(%R9) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
MOV -0x118(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD %R8,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
AND $0x3,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 480a6d <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x400d> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV (%R11),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x58(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (,%RAX,8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0x38(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x40(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R15,(%R12,%RSI,1) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV (%RDX),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RDI,(%RCX,%RSI,1) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
CMP %RAX,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 480a6d <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x400d> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV (%R11),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x8(%RSI),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x2,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD %R8,(%R12,%R9,1) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV (%RDX),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R15,(%RCX,%R9,1) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
CMP %RAX,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 480a6d <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x400d> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV (%R11),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x10,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD %RAX,(%R12,%RSI,1) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV (%RDX),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RDX,(%RCX,%RSI,1) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
MOV -0x108(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x48(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x40(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV (%R11,%RAX,8),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
NOT %RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RDI,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
AND $0x7,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
TEST %R12,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JS 47d5d4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xb74> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0xb0(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x48(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x108(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD -0x8(%RBX,%R10,1),%R12 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %R12,(%R9,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x108(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %R15,-0x40(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JLE 47d7d0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xd70> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 47d70b <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xcab> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x1,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47d6e1 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xc81> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x2,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47d6c1 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xc61> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x3,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47d6a1 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xc41> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x4,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47d681 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xc21> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x5,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47d661 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xc01> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x6,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47d641 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xbe1> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x48(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RSI,%R15,8),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RAX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JS 47d63e <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xbde> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0xb0(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD -0x8(%RCX,%R10,1),%RAX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RAX,(%RSI,%R15,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x48(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI,%R15,8),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JS 47d65e <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xbfe> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0xb0(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD -0x8(%R11,%R10,1),%RDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RDX,(%RDI,%R15,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x48(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R12,%R15,8),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RBX,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JS 47d67e <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xc1e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0xb0(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD -0x8(%R9,%R10,1),%RBX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RBX,(%R12,%R15,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x48(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R8,%R15,8),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RSI,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JS 47d69e <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xc3e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0xb0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD -0x8(%RAX,%R10,1),%RSI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RSI,(%R8,%R15,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x48(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI,%R15,8),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JS 47d6be <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xc5e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0xb0(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD -0x8(%RCX,%R10,1),%RDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RDX,(%RDI,%R15,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x48(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R11,%R15,8),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %R12,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JS 47d6de <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xc7e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0xb0(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD -0x8(%RBX,%R10,1),%R12 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %R12,(%R11,%R15,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x48(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R9,%R15,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %R8,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JS 47d6fe <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xc9e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0xb0(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD -0x8(%RSI,%R10,1),%R8 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %R8,(%R9,%R15,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %R15,-0x40(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JLE 47d7d0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xd70> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0xb0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x48(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD %XMM3,-0xb0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 411290 <GOMP_barrier@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD -0xb0(%RBP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMPQ $0,-0x100(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JLE 4809d4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3f74> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x100(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R13,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVSD %XMM3,-0xb0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (,%R8,8),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 4110a0 <memset@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x70(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0xb0(%RBP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x130(%RCX),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMPQ $0,(%R10) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JLE 47f390 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2930> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x60(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD %XMM3,-0xb0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 411290 <GOMP_barrier@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x108(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0xb0(%RBP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %RBX,-0x40(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JLE 47e1e6 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1786> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x70(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $-0x2,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x48(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
KXNORB %K2,%K2,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
MOV %RDX,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD -0x1d0(%RBP),%XMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM6,%XMM6,%XMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VXORPD %XMM5,%XMM5,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0xc0(%R11),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%R11),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R13,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x38(%R11),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x58(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,-0xf0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x108(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xb0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,-0x118(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 47d90d <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xead> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R14,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CMPQ $0,-0x100(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JNE 47f3c0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2960> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x70(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x130(%R8),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMPQ $0,(%R14) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JNE 47f370 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2910> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD $0x308,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
LEA -0x10(%R9),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP $0x1,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 47ea84 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2024> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x1,%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %R12,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
AND $0x7,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 480b25 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x40c5> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x1,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47e94b <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1eeb> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x2,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47e926 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1ec6> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x3,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47e901 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1ea1> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x4,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47e8dc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1e7c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x5,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47e8b7 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1e57> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x6,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47e892 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1e32> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV (%R11),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xb0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x2,%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R15,0x8(%R11) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV (%RDX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RAX,0x8(%RDX) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV (%RCX),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RSI,0x8(%RCX) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV -0x8(%R11,%R12,8),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xb0(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RDI,(%R11,%R12,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV -0x8(%RBX,%R12,8),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R9,(%RBX,%R12,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV -0x8(%RCX,%R12,8),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R10,(%RCX,%R12,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
INC %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x8(%R11,%R12,8),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xb0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R15,(%R11,%R12,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV -0x8(%RAX,%R12,8),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RDX,(%RAX,%R12,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV -0x8(%RCX,%R12,8),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RSI,(%RCX,%R12,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
INC %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x8(%R11,%R12,8),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xb0(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RDI,(%R11,%R12,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV -0x8(%RBX,%R12,8),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R9,(%RBX,%R12,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV -0x8(%RCX,%R12,8),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R10,(%RCX,%R12,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
INC %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x8(%R11,%R12,8),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xb0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R15,(%R11,%R12,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV -0x8(%RAX,%R12,8),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RDX,(%RAX,%R12,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV -0x8(%RCX,%R12,8),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RSI,(%RCX,%R12,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
INC %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x8(%R11,%R12,8),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xb0(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RDI,(%R11,%R12,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV -0x8(%RBX,%R12,8),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R9,(%RBX,%R12,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV -0x8(%RCX,%R12,8),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R10,(%RCX,%R12,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
INC %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x8(%R11,%R12,8),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xb0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R15,(%R11,%R12,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x8(%RAX,%R12,8),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RDX,(%RAX,%R12,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV -0x8(%RCX,%R12,8),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RSI,(%RCX,%R12,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
INC %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %R12,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47ea84 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2024> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSD %XMM1,-0xb0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 411290 <GOMP_barrier@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
CALL 411290 <GOMP_barrier@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
CMPQ $0x4,-0x250(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
VMOVSD -0xb0(%RBP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JE 4805e1 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3b81> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x100(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x58(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x38(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x70(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RCX,%R11,8),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX,%R11,8),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RBX,0xe0(%R9) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0xe8(%R9) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RBX,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 480520 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3ac0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
TEST %RDI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 480570 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3b10> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x70(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RDX),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMPQ $0x1,(%RSI) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JLE 47d7e5 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xd85> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x70(%RBP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMPQ $0,-0x100(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x180(%R10),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x130(%R10),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R8),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JLE 4809aa <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3f4a> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x100(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA -0x1(%R15),%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP $0x6,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JBE 480d2a <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x42ca> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
SHR $0x3,%R15 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV -0x48(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VPBROADCASTQ -0x190(%RBP),%ZMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
MOV %R15,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x6,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %R11,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (%RDX,%R11,1),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB $0x40,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SHR $0x6,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
INC %RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $0x7,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 47ebf5 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2195> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x1,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47ebdf <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x217f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x2,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47ebce <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x216e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x3,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47ebbd <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x215d> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x4,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47ebac <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x214c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x5,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47eb9b <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x213b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x6,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 480c3f <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x41df> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VPADDQ (%R10),%ZMM12,%ZMM14 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
ADD $0x40,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVDQU64 %ZMM14,-0x40(%R10) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ (%R10),%ZMM12,%ZMM15 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
ADD $0x40,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVDQU64 %ZMM15,-0x40(%R10) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ (%R10),%ZMM12,%ZMM6 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
ADD $0x40,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVDQU64 %ZMM6,-0x40(%R10) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ (%R10),%ZMM12,%ZMM0 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
ADD $0x40,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVDQU64 %ZMM0,-0x40(%R10) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ (%R10),%ZMM12,%ZMM1 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
ADD $0x40,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVDQU64 %ZMM1,-0x40(%R10) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ (%R10),%ZMM12,%ZMM2 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
ADD $0x40,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVDQU64 %ZMM2,-0x40(%R10) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
CMP %RDI,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47ec70 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2210> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x100(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x8,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %RAX,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RAX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 480cce <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x426e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x100(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %R12,%R15 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%R15),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP $0x2,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JBE 47eccb <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x226b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x48(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VPBROADCASTQ -0x190(%RBP),%YMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
MOV %R15,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R11,%R12,8),%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD %RDX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
AND $0x3,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
VPADDQ (%R12),%YMM14,%YMM15 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VMOVDQU %YMM15,(%R12) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
JE 47ed05 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x22a5> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x48(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x190(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (,%RAX,8),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x1(%RAX),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0x100(%RBP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R15,(%R8,%RDI,1) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
CMP %RCX,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 47ed05 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x22a5> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD $0x2,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD %R15,0x8(%R8,%RDI,1) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
CMP %RAX,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 47ed05 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x22a5> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %R15,0x10(%R8,%RDI,1) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV (%R9),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x260(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM3,-0xb0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x48(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x268(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 54fcb0 <hypre_alt_insert_new_nodes> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
CMP $0x6,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVSD -0xb0(%RBP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JBE 480d23 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x42c3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VPBROADCASTQ -0x190(%RBP),%ZMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
MOV -0x100(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x48(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SHR $0x3,%RBX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %R9,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x6,%RBX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%RBX,%R9,1),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB $0x40,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SHR $0x6,%RBX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
INC %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $0x7,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 47ee30 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x23d0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x1,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47ee10 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x23b0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x2,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47edf9 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2399> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x3,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47ede2 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2382> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x4,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47edcb <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x236b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x5,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47edb4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2354> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x6,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 480c1a <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x41ba> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVDQU64 (%RAX),%ZMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
ADD $0x40,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VPSUBQ %ZMM12,%ZMM1,%ZMM2 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
VMOVDQU64 %ZMM2,-0x40(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVDQU64 (%RAX),%ZMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
ADD $0x40,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VPSUBQ %ZMM12,%ZMM7,%ZMM8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
VMOVDQU64 %ZMM8,-0x40(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVDQU64 (%RAX),%ZMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
ADD $0x40,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VPSUBQ %ZMM12,%ZMM9,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
VMOVDQU64 %ZMM4,-0x40(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVDQU64 (%RAX),%ZMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
ADD $0x40,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VPSUBQ %ZMM12,%ZMM5,%ZMM10 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
VMOVDQU64 %ZMM10,-0x40(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVDQU64 (%RAX),%ZMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
ADD $0x40,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VPSUBQ %ZMM12,%ZMM11,%ZMM13 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
VMOVDQU64 %ZMM13,-0x40(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVDQU64 (%RAX),%ZMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
ADD $0x40,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VPSUBQ %ZMM12,%ZMM14,%ZMM15 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
VMOVDQU64 %ZMM15,-0x40(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
CMP %R11,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47eede <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x247e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x100(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x8,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %RDI,-0x118(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RDI,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 48089a <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3e3a> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x100(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %RSI,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%R8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP $0x2,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JBE 47ef4d <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x24ed> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x48(%RBP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VPBROADCASTQ -0x190(%RBP),%YMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
MOV %R8,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%R15 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R10,%RSI,8),%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD %R15,-0x118(%RBP) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
VMOVDQU (%R12),%YMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VPSUBQ %YMM12,%YMM1,%YMM2 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VMOVDQU %YMM2,(%R12) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
TEST $0x3,%R8B | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 48089a <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3e3a> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x118(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x48(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x190(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x100(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (,%R9,8),%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x1(%R9),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %RSI,(%R11,%RBX,1) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
CMP %RAX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 48089a <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3e3a> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD $0x2,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RSI,0x8(%R11,%RBX,1) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
CMP %R9,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 48089a <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3e3a> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
SUB %RSI,0x10(%R11,%RBX,1) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 47d7f3 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xd93> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RSI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8,-0x118(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RCX,-0x108(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM3,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b0aa0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
TEST %R12,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
VMOVSD -0x40(%RBP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x108(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x118(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JLE 47cc31 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1d1> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (,%R12,8),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RAX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4110a0 <memset@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD -0x40(%RBP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x108(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x118(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 47cc31 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1d1> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0x60(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x308,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
LEA -0x10(%R10),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
JMP 5b0b60 <hypre_Free> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
VMOVSD %XMM3,-0xb0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 411290 <GOMP_barrier@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x108(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0xb0(%RBP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %R12,-0x40(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JG 47d876 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xe16> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R13,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 5b0b60 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
JMP 47e1f4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1794> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8,-0x118(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,-0x108(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM3,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b0aa0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x70(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x40(%RBP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x108(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x118(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x60(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x130(%R15),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMPQ $0,(%RDI) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JLE 47cc48 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1e8> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 47cc48 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1e8> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVSD %XMM3,-0xb0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b0aa0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x70(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RAX,0xc0(%R15) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe0(%R15),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CALL 5b0aa0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xe8(%R15),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0xb0(%RBP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0xb0(%R15) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RDI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 47eae7 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2087> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVSD %XMM3,-0xb0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b0aa0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x70(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RAX,0xd8(%R12) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe8(%R12),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CALL 5b0aa0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x38(%R12),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0xb0(%RBP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0xc8(%R12) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMPQ $0x1,(%RDI) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JG 47eaf9 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2099> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 47d7e5 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xd85> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
VMOVSD %XMM3,-0xb0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b3c40 <time_getWallclockSeconds> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x70(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x5ba480,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x1,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VSUBSD 0x178(%R12),%XMM0,%XMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
MOV 0x30(%R12),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R8),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,0x178(%R12) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b0cd0 <hypre_printf> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDI,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 4115b0 <fflush@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
CALL 5b3c40 <time_getWallclockSeconds> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD -0xb0(%RBP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,0x178(%R12) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 47eaac <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x204c> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV -0x40(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x1(%RSI),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %RAX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
INC %RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $0x7,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 480d65 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x4305> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x1,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 480719 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3cb9> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x2,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 480700 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3ca0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x3,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 4806e7 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3c87> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x4,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 4806ce <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3c6e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x5,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 4806b5 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3c55> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x6,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 48069c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3c3c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV (%R11),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x58(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x38(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R12,(%RCX,%RAX,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV (%RDX),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R9,(%RBX,%RAX,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV (%R11),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x58(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x38(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R8,(%R15,%RAX,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV (%RDX),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RSI,(%R12,%RAX,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV (%R11),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x58(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x38(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RCX,(%R9,%RAX,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV (%RDX),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R8,(%RBX,%RAX,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV (%R11),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x58(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x38(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R15,(%RSI,%RAX,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV (%RDX),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R12,(%RCX,%RAX,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV (%R11),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x58(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x38(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R9,(%R8,%RAX,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV (%RDX),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R15,(%RBX,%RAX,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV (%R11),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x58(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x38(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RSI,(%R12,%RAX,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV (%RDX),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RCX,(%R9,%RAX,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV (%R11),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x58(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x38(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R8,(%R15,%RAX,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV (%RDX),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RSI,(%RBX,%RAX,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RDI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47d595 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xb35> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x58(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 47d595 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xb35> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 47d7f3 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xd93> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RBX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 47d020 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x5c0> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV (%R9),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x260(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM3,-0xb0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x48(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x268(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CALL 54fcb0 <hypre_alt_insert_new_nodes> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD -0xb0(%RBP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x70(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x130(%RCX),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMPQ $0,(%R10) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JG 47d834 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xdd4> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 47d850 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xdf0> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 47d595 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xb35> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV -0xb0(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 47e97c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1f1c> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
VMOVDQU64 (%R9),%ZMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
ADD $0x40,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VPSUBQ %ZMM12,%ZMM6,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
VMOVDQA64 %ZMM6,-0xb0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVDQU64 %ZMM0,(%R9) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
JMP 47ed9d <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x233d> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
VPADDQ (%R11),%ZMM12,%ZMM13 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
ADD $0x40,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVDQU64 %ZMM13,(%R11) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
JMP 47eb8a <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x212a> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV -0x108(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %R12,-0x40(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JG 47d595 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xb35> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 47d7d0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xd70> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV (%R9),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x260(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVDQA64 %ZMM12,-0xf0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
MOV -0x48(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x268(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM3,-0xb0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 54fcb0 <hypre_alt_insert_new_nodes> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD -0xb0(%RBP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVDQA64 -0xf0(%RBP),%ZMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
JMP 47ed43 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x22e3> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
XOR %ESI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 47eeff <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x249f> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %R12D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 47ec8a <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x222a> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV -0x38(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x58(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 48073f <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3cdf> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
XOR %R9D,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 47d4da <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xa7a> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | par_lr_interp.c:1196-1757 |
Module | exec |
nb instructions | 1058 |
nb uops | 1144 |
loop length | 5148 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 6 |
used ymm registers | 9 |
used zmm registers | 15 |
nb stack references | 43 |
micro-operation queue | 194.00 cycles |
front end | 194.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 76.20 | 76.20 | 137.67 | 137.67 | 107.50 | 76.20 | 76.20 | 107.50 | 107.50 | 107.50 | 76.20 | 137.67 |
cycles | 76.20 | 76.20 | 137.67 | 137.67 | 107.50 | 76.20 | 76.20 | 107.50 | 107.50 | 107.50 | 76.20 | 137.67 |
Cycles executing div or sqrt instructions | 10.00 |
FE+BE cycles | 211.03-211.02 |
Stall cycles | 0.00 |
Front-end | 194.00 |
Dispatch | 137.67 |
DIV/SQRT | 10.00 |
Overall L1 | 194.00 |
all | 25% |
load | 31% |
store | 20% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 5% |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 23% |
load | 26% |
store | 18% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 96% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 7% |
all | 31% |
load | 38% |
store | 29% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 93% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 13% |
all | 13% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 29% |
load | 34% |
store | 27% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 91% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 12% |
other | 13% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x10(%RSP),%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
PUSHQ -0x8(%R13) | 2 | 0 | 0 | 0.33 | 0.33 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0.33 | 5-12 | 0.62 |
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x308,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDI,-0x70(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x158(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x140(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x138(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x128(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x120(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x118(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RBX,-0xb0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x110(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x170(%RDI),%XMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,-0x210(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x108(%RDI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x168(%RDI),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,-0x1f8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x160(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x150(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,-0x260(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x148(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11,-0x240(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,-0x258(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM6,-0x1d0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,-0x248(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xf8(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa8(%RAX),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RDI),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa0(%RAX),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R15,-0xf0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x98(%RAX),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x90(%RAX),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x80(%RAX),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RAX),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x88(%RAX),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x68(%RAX),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,-0xf8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x70(%RAX),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x60(%RAX),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,-0x68(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,-0x198(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x58(%RAX),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x50(%RAX),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x48(%RAX),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14,-0x1a8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,-0x1c0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,-0x1b0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,-0x238(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,-0x1b8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,-0x190(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,-0x100(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,-0x200(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,-0x120(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x40(%RAX),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RAX),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RAX),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RAX),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RAX),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R12,-0x188(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x8(%RAX),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14,-0x268(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,-0x178(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RAX),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,-0x250(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,-0x180(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,-0x110(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RSI,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 47f300 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x28a0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x70(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x130(%RSI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R10),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RDI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 47f3d0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2970> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R8,-0x1a0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,-0x130(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM3,-0x128(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b3bd0 <hypre_GetThreadNum> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RAX,-0x118(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b3bc0 <hypre_NumActiveThreads> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %R12,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVSD -0x128(%RBP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x1a0(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x100(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA -0x1(%RSI),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CQTO | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %RSI | 5 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 10 |
IMUL %RAX,%R9 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %R9,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %RCX,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R9,-0x108(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x130(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMOVE -0x100(%RBP),%RAX | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.50 |
CMP %R9,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RAX,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JLE 48099f <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3f3f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x70(%RBP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x108(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,-0x1c8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R8,-0x208(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x38(%R10),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,-0x230(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x58(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 47cd1b <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2bb> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RCX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x208(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x230(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x1c8(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,-0xf0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,-0x1c8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,-0x1a0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,-0x128(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM0,-0x130(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 411290 <GOMP_barrier@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x40(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x1c8(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x118(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x58(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x38(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xb0(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (,%R11,8),%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RBX,(%R9,%R11,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (,%R8,8),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RDX,(%RDI,%R11,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,(%RSI,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x128(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,-0x1c8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%R15,%R10,1),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RBX,(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0xf0(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x208(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RBX,%R10,1),%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RDX,(%RBX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 411290 <GOMP_barrier@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x118(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xf0(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x128(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x130(%RBP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %R15,%R15 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV -0x1a0(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JE 47e820 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1dc0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RCX,-0x118(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,-0xf0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 411290 <GOMP_barrier@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
TEST %R15,%R15 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
VMOVSD -0xf0(%RBP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x118(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x128(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x1c8(%RBP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JLE 47d7d0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xd70> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x108(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RAX,-0x40(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JL 480ca1 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x4241> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x40(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x108(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA -0x8(%R10),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%RDI,%RDX,1),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD %R9,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %RSI,%R15 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%R15),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R15,-0x118(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,-0x130(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP $0x2,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JBE 480640 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3be0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x38(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (,%RAX,8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0x58(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x8(%R12),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,-0x128(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%R8,%RSI,1),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R8,%RDI,1),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%RCX,%RDI,1),%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%RCX,%RSI,1),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x40,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RBX,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SETAE %R8B | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP %R15,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,-0xf0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SETAE %DIL | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
OR %EDI,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
CMP %R12,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SETAE %DIL | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP %RBX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x58(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SETAE %BL | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
OR %EBX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD %RSI,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x38(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
AND %R8D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
CMP %RCX,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x208(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SETAE %R8B | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD %RBX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0xf0(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %RSI,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SETAE %SIL | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
OR %ESI,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
AND %EDI,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
CMP %RCX,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SETAE %SIL | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP %R15,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SETAE %R15B | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
OR %R15D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
TEST %SIL,%R8B | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 480640 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3be0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP %RCX,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SETAE %R8B | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP %R12,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SETAE %R12B | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
OR %R8B,%R12B | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 480640 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3be0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMPQ $0x6,-0x130(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JBE 480d98 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x4338> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x118(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VPBROADCASTQ (%R11),%ZMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
XOR %ESI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPBROADCASTQ (%RDX),%ZMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
SHR $0x3,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
SAL $0x6,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA -0x40(%R8),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SHR $0x6,%RDI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
INC %RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $0x7,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 47d39f <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x93f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x1,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47d36f <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x90f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x2,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47d348 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x8e8> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x3,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47d321 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x8c1> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x4,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47d2fa <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x89a> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x5,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47d2d3 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x873> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x6,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47d2ac <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x84c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VPADDQ (%RBX),%ZMM4,%ZMM2 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
MOV $0x40,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVDQU64 %ZMM2,(%RBX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ (%R9),%ZMM5,%ZMM7 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM7,(%R9) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
MOV -0xf0(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VPADDQ (%RBX,%RSI,1),%ZMM4,%ZMM8 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM8,(%RBX,%RSI,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ (%R9,%RSI,1),%ZMM5,%ZMM9 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM9,(%R9,%RSI,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
ADD $0x40,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0xf0(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VPADDQ (%R15,%RSI,1),%ZMM4,%ZMM10 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM10,(%R15,%RSI,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ (%R9,%RSI,1),%ZMM5,%ZMM11 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM11,(%R9,%RSI,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
ADD $0x40,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0xf0(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VPADDQ (%RCX,%RSI,1),%ZMM4,%ZMM12 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM12,(%RCX,%RSI,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ (%R9,%RSI,1),%ZMM5,%ZMM13 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM13,(%R9,%RSI,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
ADD $0x40,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0xf0(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VPADDQ (%R12,%RSI,1),%ZMM4,%ZMM14 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM14,(%R12,%RSI,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ (%R9,%RSI,1),%ZMM5,%ZMM15 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM15,(%R9,%RSI,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
ADD $0x40,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0xf0(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VPADDQ (%RDI,%RSI,1),%ZMM4,%ZMM6 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM6,(%RDI,%RSI,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ (%R9,%RSI,1),%ZMM5,%ZMM0 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM0,(%R9,%RSI,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
ADD $0x40,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0xf0(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VPADDQ (%RBX,%RSI,1),%ZMM4,%ZMM1 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM1,(%RBX,%RSI,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ (%R9,%RSI,1),%ZMM5,%ZMM2 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VMOVDQU64 %ZMM2,(%R9,%RSI,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
ADD $0x40,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %R8,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47d4ab <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xa4b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x118(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x8,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD %R9,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
TEST $0x7,%R8B | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 480a6d <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x400d> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
SUB %R9,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%R8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R8,-0x118(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP $0x2,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JBE 47d536 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xad6> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x128(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x58(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VPBROADCASTQ (%R11),%YMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
MOV (%RDX),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R15,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x38(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SAL $0x3,%R9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
VPBROADCASTQ %RBX,%YMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%RCX,%R9,1),%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD %RDI,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VPADDQ (%R12),%YMM4,%YMM5 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VMOVDQU %YMM5,(%R12) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VPADDQ (%R9),%YMM10,%YMM11 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VMOVDQU %YMM11,(%R9) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
MOV -0x118(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD %R8,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
AND $0x3,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 480a6d <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x400d> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV (%R11),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x58(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (,%RAX,8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0x38(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x40(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R15,(%R12,%RSI,1) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV (%RDX),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RDI,(%RCX,%RSI,1) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
CMP %RAX,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 480a6d <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x400d> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV (%R11),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x8(%RSI),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x2,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD %R8,(%R12,%R9,1) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV (%RDX),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R15,(%RCX,%R9,1) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
CMP %RAX,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 480a6d <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x400d> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV (%R11),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x10,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD %RAX,(%R12,%RSI,1) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV (%RDX),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RDX,(%RCX,%RSI,1) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
MOV -0x108(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x48(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x40(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV (%R11,%RAX,8),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
NOT %RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RDI,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
AND $0x7,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
TEST %R12,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JS 47d5d4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xb74> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0xb0(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x48(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x108(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD -0x8(%RBX,%R10,1),%R12 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %R12,(%R9,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x108(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %R15,-0x40(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JLE 47d7d0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xd70> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 47d70b <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xcab> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x1,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47d6e1 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xc81> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x2,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47d6c1 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xc61> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x3,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47d6a1 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xc41> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x4,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47d681 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xc21> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x5,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47d661 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xc01> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x6,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47d641 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xbe1> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x48(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RSI,%R15,8),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RAX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JS 47d63e <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xbde> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0xb0(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD -0x8(%RCX,%R10,1),%RAX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RAX,(%RSI,%R15,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x48(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI,%R15,8),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JS 47d65e <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xbfe> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0xb0(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD -0x8(%R11,%R10,1),%RDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RDX,(%RDI,%R15,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x48(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R12,%R15,8),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RBX,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JS 47d67e <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xc1e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0xb0(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD -0x8(%R9,%R10,1),%RBX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RBX,(%R12,%R15,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x48(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R8,%R15,8),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RSI,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JS 47d69e <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xc3e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0xb0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD -0x8(%RAX,%R10,1),%RSI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RSI,(%R8,%R15,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x48(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI,%R15,8),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JS 47d6be <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xc5e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0xb0(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD -0x8(%RCX,%R10,1),%RDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RDX,(%RDI,%R15,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x48(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R11,%R15,8),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %R12,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JS 47d6de <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xc7e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0xb0(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD -0x8(%RBX,%R10,1),%R12 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %R12,(%R11,%R15,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x48(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R9,%R15,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %R8,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JS 47d6fe <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xc9e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0xb0(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD -0x8(%RSI,%R10,1),%R8 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %R8,(%R9,%R15,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %R15,-0x40(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JLE 47d7d0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xd70> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0xb0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x48(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD %XMM3,-0xb0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 411290 <GOMP_barrier@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD -0xb0(%RBP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMPQ $0,-0x100(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JLE 4809d4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3f74> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x100(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R13,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVSD %XMM3,-0xb0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (,%R8,8),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 4110a0 <memset@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x70(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0xb0(%RBP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x130(%RCX),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMPQ $0,(%R10) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JLE 47f390 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2930> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x60(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD %XMM3,-0xb0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 411290 <GOMP_barrier@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x108(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0xb0(%RBP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %RBX,-0x40(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JLE 47e1e6 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1786> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x70(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $-0x2,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x48(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
KXNORB %K2,%K2,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
MOV %RDX,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD -0x1d0(%RBP),%XMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM6,%XMM6,%XMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VXORPD %XMM5,%XMM5,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0xc0(%R11),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%R11),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R13,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x38(%R11),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x58(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,-0xf0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x108(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xb0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,-0x118(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 47d90d <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xead> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R14,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CMPQ $0,-0x100(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JNE 47f3c0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2960> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x70(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x130(%R8),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMPQ $0,(%R14) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JNE 47f370 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2910> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD $0x308,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
LEA -0x10(%R9),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP $0x1,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 47ea84 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2024> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x1,%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %R12,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
AND $0x7,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 480b25 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x40c5> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x1,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47e94b <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1eeb> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x2,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47e926 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1ec6> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x3,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47e901 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1ea1> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x4,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47e8dc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1e7c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x5,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47e8b7 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1e57> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x6,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47e892 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1e32> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV (%R11),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xb0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x2,%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R15,0x8(%R11) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV (%RDX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RAX,0x8(%RDX) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV (%RCX),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RSI,0x8(%RCX) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV -0x8(%R11,%R12,8),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xb0(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RDI,(%R11,%R12,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV -0x8(%RBX,%R12,8),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R9,(%RBX,%R12,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV -0x8(%RCX,%R12,8),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R10,(%RCX,%R12,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
INC %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x8(%R11,%R12,8),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xb0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R15,(%R11,%R12,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV -0x8(%RAX,%R12,8),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RDX,(%RAX,%R12,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV -0x8(%RCX,%R12,8),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RSI,(%RCX,%R12,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
INC %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x8(%R11,%R12,8),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xb0(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RDI,(%R11,%R12,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV -0x8(%RBX,%R12,8),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R9,(%RBX,%R12,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV -0x8(%RCX,%R12,8),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R10,(%RCX,%R12,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
INC %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x8(%R11,%R12,8),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xb0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R15,(%R11,%R12,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV -0x8(%RAX,%R12,8),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RDX,(%RAX,%R12,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV -0x8(%RCX,%R12,8),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RSI,(%RCX,%R12,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
INC %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x8(%R11,%R12,8),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xb0(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RDI,(%R11,%R12,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV -0x8(%RBX,%R12,8),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R9,(%RBX,%R12,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV -0x8(%RCX,%R12,8),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R10,(%RCX,%R12,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
INC %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x8(%R11,%R12,8),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xb0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R15,(%R11,%R12,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x8(%RAX,%R12,8),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RDX,(%RAX,%R12,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV -0x8(%RCX,%R12,8),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RSI,(%RCX,%R12,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
INC %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %R12,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47ea84 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2024> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSD %XMM1,-0xb0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 411290 <GOMP_barrier@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
CALL 411290 <GOMP_barrier@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
CMPQ $0x4,-0x250(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
VMOVSD -0xb0(%RBP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JE 4805e1 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3b81> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x100(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x58(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x38(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x70(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RCX,%R11,8),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX,%R11,8),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RBX,0xe0(%R9) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0xe8(%R9) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RBX,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 480520 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3ac0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
TEST %RDI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 480570 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3b10> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x70(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RDX),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMPQ $0x1,(%RSI) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JLE 47d7e5 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xd85> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x70(%RBP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMPQ $0,-0x100(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x180(%R10),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x130(%R10),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R8),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JLE 4809aa <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3f4a> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x100(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA -0x1(%R15),%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP $0x6,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JBE 480d2a <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x42ca> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
SHR $0x3,%R15 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV -0x48(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VPBROADCASTQ -0x190(%RBP),%ZMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
MOV %R15,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x6,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %R11,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (%RDX,%R11,1),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB $0x40,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SHR $0x6,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
INC %RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $0x7,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 47ebf5 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2195> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x1,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47ebdf <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x217f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x2,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47ebce <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x216e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x3,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47ebbd <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x215d> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x4,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47ebac <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x214c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x5,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47eb9b <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x213b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x6,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 480c3f <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x41df> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VPADDQ (%R10),%ZMM12,%ZMM14 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
ADD $0x40,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVDQU64 %ZMM14,-0x40(%R10) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ (%R10),%ZMM12,%ZMM15 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
ADD $0x40,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVDQU64 %ZMM15,-0x40(%R10) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ (%R10),%ZMM12,%ZMM6 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
ADD $0x40,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVDQU64 %ZMM6,-0x40(%R10) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ (%R10),%ZMM12,%ZMM0 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
ADD $0x40,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVDQU64 %ZMM0,-0x40(%R10) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ (%R10),%ZMM12,%ZMM1 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
ADD $0x40,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVDQU64 %ZMM1,-0x40(%R10) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VPADDQ (%R10),%ZMM12,%ZMM2 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
ADD $0x40,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVDQU64 %ZMM2,-0x40(%R10) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
CMP %RDI,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47ec70 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2210> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x100(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x8,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %RAX,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RAX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 480cce <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x426e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x100(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %R12,%R15 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%R15),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP $0x2,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JBE 47eccb <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x226b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x48(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VPBROADCASTQ -0x190(%RBP),%YMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
MOV %R15,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R11,%R12,8),%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD %RDX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
AND $0x3,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
VPADDQ (%R12),%YMM14,%YMM15 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VMOVDQU %YMM15,(%R12) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
JE 47ed05 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x22a5> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x48(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x190(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (,%RAX,8),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x1(%RAX),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0x100(%RBP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R15,(%R8,%RDI,1) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
CMP %RCX,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 47ed05 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x22a5> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD $0x2,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD %R15,0x8(%R8,%RDI,1) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
CMP %RAX,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 47ed05 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x22a5> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %R15,0x10(%R8,%RDI,1) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV (%R9),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x260(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM3,-0xb0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x48(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x268(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 54fcb0 <hypre_alt_insert_new_nodes> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
CMP $0x6,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVSD -0xb0(%RBP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JBE 480d23 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x42c3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VPBROADCASTQ -0x190(%RBP),%ZMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
MOV -0x100(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x48(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SHR $0x3,%RBX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %R9,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x6,%RBX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%RBX,%R9,1),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB $0x40,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SHR $0x6,%RBX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
INC %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $0x7,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 47ee30 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x23d0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x1,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47ee10 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x23b0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x2,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47edf9 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2399> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x3,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47ede2 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2382> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x4,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47edcb <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x236b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x5,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47edb4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2354> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x6,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 480c1a <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x41ba> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVDQU64 (%RAX),%ZMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
ADD $0x40,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VPSUBQ %ZMM12,%ZMM1,%ZMM2 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
VMOVDQU64 %ZMM2,-0x40(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVDQU64 (%RAX),%ZMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
ADD $0x40,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VPSUBQ %ZMM12,%ZMM7,%ZMM8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
VMOVDQU64 %ZMM8,-0x40(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVDQU64 (%RAX),%ZMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
ADD $0x40,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VPSUBQ %ZMM12,%ZMM9,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
VMOVDQU64 %ZMM4,-0x40(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVDQU64 (%RAX),%ZMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
ADD $0x40,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VPSUBQ %ZMM12,%ZMM5,%ZMM10 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
VMOVDQU64 %ZMM10,-0x40(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVDQU64 (%RAX),%ZMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
ADD $0x40,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VPSUBQ %ZMM12,%ZMM11,%ZMM13 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
VMOVDQU64 %ZMM13,-0x40(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVDQU64 (%RAX),%ZMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
ADD $0x40,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VPSUBQ %ZMM12,%ZMM14,%ZMM15 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
VMOVDQU64 %ZMM15,-0x40(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
CMP %R11,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47eede <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x247e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x100(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x8,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %RDI,-0x118(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RDI,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 48089a <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3e3a> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x100(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %RSI,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%R8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP $0x2,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JBE 47ef4d <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x24ed> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x48(%RBP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VPBROADCASTQ -0x190(%RBP),%YMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
MOV %R8,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%R15 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R10,%RSI,8),%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD %R15,-0x118(%RBP) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
VMOVDQU (%R12),%YMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VPSUBQ %YMM12,%YMM1,%YMM2 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VMOVDQU %YMM2,(%R12) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
TEST $0x3,%R8B | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 48089a <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3e3a> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x118(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x48(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x190(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x100(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (,%R9,8),%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x1(%R9),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %RSI,(%R11,%RBX,1) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
CMP %RAX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 48089a <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3e3a> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD $0x2,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RSI,0x8(%R11,%RBX,1) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
CMP %R9,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 48089a <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3e3a> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
SUB %RSI,0x10(%R11,%RBX,1) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 47d7f3 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xd93> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RSI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8,-0x118(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RCX,-0x108(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM3,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b0aa0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
TEST %R12,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
VMOVSD -0x40(%RBP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x108(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x118(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JLE 47cc31 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1d1> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (,%R12,8),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RAX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4110a0 <memset@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD -0x40(%RBP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x108(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x118(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 47cc31 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1d1> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0x60(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x308,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
LEA -0x10(%R10),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
JMP 5b0b60 <hypre_Free> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
VMOVSD %XMM3,-0xb0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 411290 <GOMP_barrier@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x108(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0xb0(%RBP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %R12,-0x40(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JG 47d876 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xe16> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R13,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 5b0b60 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
JMP 47e1f4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1794> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8,-0x118(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,-0x108(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM3,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b0aa0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x70(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x40(%RBP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x108(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x118(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x60(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x130(%R15),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMPQ $0,(%RDI) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JLE 47cc48 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1e8> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 47cc48 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1e8> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVSD %XMM3,-0xb0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b0aa0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x70(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RAX,0xc0(%R15) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe0(%R15),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CALL 5b0aa0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xe8(%R15),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0xb0(%RBP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0xb0(%R15) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RDI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 47eae7 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2087> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVSD %XMM3,-0xb0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b0aa0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x70(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RAX,0xd8(%R12) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe8(%R12),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CALL 5b0aa0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x38(%R12),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0xb0(%RBP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0xc8(%R12) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMPQ $0x1,(%RDI) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JG 47eaf9 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2099> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 47d7e5 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xd85> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
VMOVSD %XMM3,-0xb0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b3c40 <time_getWallclockSeconds> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x70(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x5ba480,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x1,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VSUBSD 0x178(%R12),%XMM0,%XMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
MOV 0x30(%R12),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R8),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,0x178(%R12) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b0cd0 <hypre_printf> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDI,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 4115b0 <fflush@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
CALL 5b3c40 <time_getWallclockSeconds> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD -0xb0(%RBP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,0x178(%R12) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 47eaac <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x204c> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV -0x40(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x1(%RSI),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %RAX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
INC %RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $0x7,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 480d65 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x4305> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x1,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 480719 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3cb9> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x2,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 480700 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3ca0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x3,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 4806e7 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3c87> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x4,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 4806ce <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3c6e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x5,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 4806b5 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3c55> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x6,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 48069c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3c3c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV (%R11),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x58(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x38(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R12,(%RCX,%RAX,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV (%RDX),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R9,(%RBX,%RAX,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV (%R11),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x58(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x38(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R8,(%R15,%RAX,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV (%RDX),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RSI,(%R12,%RAX,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV (%R11),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x58(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x38(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RCX,(%R9,%RAX,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV (%RDX),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R8,(%RBX,%RAX,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV (%R11),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x58(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x38(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R15,(%RSI,%RAX,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV (%RDX),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R12,(%RCX,%RAX,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV (%R11),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x58(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x38(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R9,(%R8,%RAX,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV (%RDX),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R15,(%RBX,%RAX,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV (%R11),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x58(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x38(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RSI,(%R12,%RAX,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV (%RDX),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RCX,(%R9,%RAX,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV (%R11),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x58(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x38(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R8,(%R15,%RAX,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV (%RDX),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RSI,(%RBX,%RAX,8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RDI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 47d595 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xb35> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x58(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 47d595 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xb35> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 47d7f3 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xd93> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RBX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 47d020 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x5c0> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV (%R9),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x260(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM3,-0xb0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x48(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x268(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CALL 54fcb0 <hypre_alt_insert_new_nodes> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD -0xb0(%RBP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x70(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x130(%RCX),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMPQ $0,(%R10) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JG 47d834 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xdd4> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 47d850 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xdf0> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 47d595 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xb35> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV -0xb0(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 47e97c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1f1c> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
VMOVDQU64 (%R9),%ZMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
ADD $0x40,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VPSUBQ %ZMM12,%ZMM6,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
VMOVDQA64 %ZMM6,-0xb0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVDQU64 %ZMM0,(%R9) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
JMP 47ed9d <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x233d> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
VPADDQ (%R11),%ZMM12,%ZMM13 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
ADD $0x40,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVDQU64 %ZMM13,(%R11) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
JMP 47eb8a <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x212a> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV -0x108(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %R12,-0x40(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JG 47d595 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xb35> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 47d7d0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xd70> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV (%R9),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x260(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVDQA64 %ZMM12,-0xf0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
MOV -0x48(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x268(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM3,-0xb0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 54fcb0 <hypre_alt_insert_new_nodes> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD -0xb0(%RBP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVDQA64 -0xf0(%RBP),%ZMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
JMP 47ed43 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x22e3> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
XOR %ESI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 47eeff <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x249f> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %R12D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 47ec8a <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x222a> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV -0x38(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x58(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 48073f <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3cdf> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
XOR %R9D,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 47d4da <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xa7a> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼hypre_BoomerAMGBuildExtPIInterp._omp_fn.0– | 0.25 | 0.05 |
○Loop 735 - par_lr_interp.c:1458-1459 - exec | 0 | 0 |
○Loop 766 - par_lr_interp.c:1230-1231 - exec | 0 | 0 |
○Loop 755 - par_lr_interp.c:1378-1382 - exec | 0 | 0 |
▼Loop 736 - par_lr_interp.c:1393-1748 - exec– | 0 | 0 |
▼Loop 742 - par_lr_interp.c:1393-1675 - exec– | 0.08 | 0.01 |
○Loop 744 - par_lr_interp.c:1644-1651 - exec | 0.04 | 0.01 |
○Loop 746 - par_lr_interp.c:1624-1627 - exec | 0.03 | 0 |
○Loop 743 - par_lr_interp.c:1655-1660 - exec | 0 | 0 |
○Loop 745 - par_lr_interp.c:1632-1636 - exec | 0 | 0 |
▼Loop 749 - par_lr_interp.c:1494-1655 - exec– | 0.01 | 0.01 |
○Loop 752 - par_lr_interp.c:1516-1526 - exec | 0.04 | 0.01 |
○Loop 750 - par_lr_interp.c:1532-1545 - exec | 0 | 0 |
○Loop 751 - par_lr_interp.c:1532-1545 - exec | 0 | 0 |
○Loop 737 - par_lr_interp.c:1744-1745 - exec | 0 | 0 |
▼Loop 747 - par_lr_interp.c:1555-1596 - exec– | 0 | 0 |
○Loop 748 - par_lr_interp.c:1573-1596 - exec | 0 | 0 |
○Loop 738 - par_lr_interp.c:1742-1743 - exec | 0 | 0 |
▼Loop 739 - par_lr_interp.c:1680-1735 - exec– | 0 | 0 |
○Loop 741 - par_lr_interp.c:1707-1723 - exec | 0 | 0 |
○Loop 740 - par_lr_interp.c:1688-1700 - exec | 0 | 0 |
▼Loop 759 - par_lr_interp.c:1244-1532 - exec– | 0 | 0.01 |
▼Loop 762 - par_lr_interp.c:1264-1532 - exec– | 0.01 | 0.01 |
○Loop 765 - par_lr_interp.c:1277-1285 - exec | 0.03 | 0.01 |
○Loop 763 - par_lr_interp.c:1291-1303 - exec | 0 | 0 |
○Loop 764 - par_lr_interp.c:1291-1303 - exec | 0 | 0 |
▼Loop 760 - par_lr_interp.c:1313-1350 - exec– | 0 | 0 |
○Loop 761 - par_lr_interp.c:1331-1350 - exec | 0 | 0 |
○Loop 758 - par_lr_interp.c:1393-1396 - exec | 0 | 0 |
○Loop 757 - par_lr_interp.c:1393-1396 - exec | 0 | 0 |
○Loop 754 - par_lr_interp.c:1444-1445 - exec | 0 | 0 |
○Loop 753 - par_lr_interp.c:1451-1452 - exec | 0 | 0 |
○Loop 756 - par_lr_interp.c:1400-1403 - exec | 0 | 0 |