Loop Id: 1833 | Module: exec | Source: par_strength.c:492-513 | Coverage: 0.1% |
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Loop Id: 1833 | Module: exec | Source: par_strength.c:492-513 | Coverage: 0.1% |
---|
0x50d270 MOV 0xd8(%RSP),%RCX |
0x50d278 ADD %RCX,(%R8) |
0x50d27b MOV (%R9),%RDX |
0x50d27e ADD %R11,%RDX |
0x50d281 MOV %RDX,(%R9) |
0x50d284 MOV -0x8(%RDI),%RAX |
0x50d288 MOV (%RDI),%R15 |
0x50d28b MOV (%R8),%RCX |
0x50d28e CMP %R15,%RAX |
0x50d291 JGE 50d2ba |
0x50d293 NOPL (%RAX,%RAX,1) |
(1835) 0x50d298 MOV (%RBX,%RAX,8),%RDX |
(1835) 0x50d29c TEST %RDX,%RDX |
(1835) 0x50d29f JS 50d9a0 |
(1835) 0x50d2a5 MOV %RDX,(%R14,%RCX,8) |
(1835) 0x50d2a9 INC %RAX |
(1835) 0x50d2ac INC %RCX |
(1835) 0x50d2af MOV (%RDI),%R15 |
(1835) 0x50d2b2 CMP %R15,%RAX |
(1835) 0x50d2b5 JL 50d298 |
0x50d2b7 MOV (%R9),%RDX |
0x50d2ba MOV -0x8(%RSI),%RAX |
0x50d2be MOV (%RSI),%R15 |
0x50d2c1 CMP %RAX,%R15 |
0x50d2c4 JLE 50d2f0 |
0x50d2c6 NOPW %CS:(%RAX,%RAX,1) |
(1834) 0x50d2d0 MOV (%R12,%RAX,8),%RCX |
(1834) 0x50d2d4 TEST %RCX,%RCX |
(1834) 0x50d2d7 JS 50d9b8 |
(1834) 0x50d2dd MOV %RCX,(%R13,%RDX,8) |
(1834) 0x50d2e2 INC %RAX |
(1834) 0x50d2e5 INC %RDX |
(1834) 0x50d2e8 MOV (%RSI),%R15 |
(1834) 0x50d2eb CMP %RAX,%R15 |
(1834) 0x50d2ee JG 50d2d0 |
0x50d2f0 ADD $0x8,%R8 |
0x50d2f4 ADD $0x8,%R9 |
0x50d2f8 ADD $0x8,%RDI |
0x50d2fc ADD $0x8,%RSI |
0x50d300 CMP %R10,%R8 |
0x50d303 JNE 50d270 |
(1835) 0x50d9a0 INC %RAX |
(1835) 0x50d9a3 CMP %R15,%RAX |
(1835) 0x50d9a6 JL 50d298 |
0x50d9ac JMP 50d2b7 |
(1834) 0x50d9b8 INC %RAX |
(1834) 0x50d9bb CMP %R15,%RAX |
(1834) 0x50d9be JL 50d2d0 |
0x50d9c4 JMP 50d2f0 |
/home/eoseret/qaas_runs_CPU_9468/171-147-2675/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 492 - 513 |
-------------------------------------------------------------------------------- |
492: for (i = start; i < stop; i++) |
493: { |
494: S_diag_i[i] += jS_diag; |
495: S_offd_i[i] += jS_offd; |
496: |
497: jS = S_diag_i[i]; |
498: for (jA = A_diag_i[i]; jA < A_diag_i[i+1]; jA++) |
499: { |
500: if (S_temp_diag_j[jA] > -1) |
501: { |
502: S_diag_j[jS] = S_temp_diag_j[jA]; |
503: jS++; |
504: } |
505: } |
506: |
507: jS = S_offd_i[i]; |
508: for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++) |
509: { |
510: if (S_temp_offd_j[jA] > -1) |
511: { |
512: S_offd_j[jS] = S_temp_offd_j[jA]; |
513: jS++; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 8.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.44 |
Bottlenecks | micro-operation queue, |
Function | hypre_BoomerAMGCreateS._omp_fn.1 |
Source | par_strength.c:492-498,par_strength.c:507-508 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 4.33 |
CQA cycles if no scalar integer | 4.33 |
CQA cycles if FP arith vectorized | 4.33 |
CQA cycles if fully vectorized | 0.54 |
Front-end cycles | 4.33 |
DIV/SQRT cycles | 1.70 |
P0 cycles | 1.60 |
P1 cycles | 3.00 |
P2 cycles | 3.00 |
P3 cycles | 1.00 |
P4 cycles | 1.60 |
P5 cycles | 1.50 |
P6 cycles | 1.00 |
P7 cycles | 1.00 |
P8 cycles | 1.00 |
P9 cycles | 1.60 |
P10 cycles | 3.00 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 4.61 |
Stall cycles (UFS) | 0.00 |
Nb insns | 25.00 |
Nb uops | 26.00 |
Nb loads | 9.00 |
Nb stores | 2.00 |
Nb stack references | 1.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 20.31 |
Bytes prefetched | 0.00 |
Bytes loaded | 72.00 |
Bytes stored | 16.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 8.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.44 |
Bottlenecks | micro-operation queue, |
Function | hypre_BoomerAMGCreateS._omp_fn.1 |
Source | par_strength.c:492-498,par_strength.c:507-508 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 4.33 |
CQA cycles if no scalar integer | 4.33 |
CQA cycles if FP arith vectorized | 4.33 |
CQA cycles if fully vectorized | 0.54 |
Front-end cycles | 4.33 |
DIV/SQRT cycles | 1.70 |
P0 cycles | 1.60 |
P1 cycles | 3.00 |
P2 cycles | 3.00 |
P3 cycles | 1.00 |
P4 cycles | 1.60 |
P5 cycles | 1.50 |
P6 cycles | 1.00 |
P7 cycles | 1.00 |
P8 cycles | 1.00 |
P9 cycles | 1.60 |
P10 cycles | 3.00 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 4.61 |
Stall cycles (UFS) | 0.00 |
Nb insns | 25.00 |
Nb uops | 26.00 |
Nb loads | 9.00 |
Nb stores | 2.00 |
Nb stack references | 1.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 20.31 |
Bytes prefetched | 0.00 |
Bytes loaded | 72.00 |
Bytes stored | 16.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Path / |
Function | hypre_BoomerAMGCreateS._omp_fn.1 |
Source file and lines | par_strength.c:492-513 |
Module | exec |
nb instructions | 25 |
nb uops | 26 |
loop length | 100 |
used x86 registers | 11 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 1 |
micro-operation queue | 4.33 cycles |
front end | 4.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.70 | 1.60 | 3.00 | 3.00 | 1.00 | 1.60 | 1.50 | 1.00 | 1.00 | 1.00 | 1.60 | 3.00 |
cycles | 1.70 | 1.60 | 3.00 | 3.00 | 1.00 | 1.60 | 1.50 | 1.00 | 1.00 | 1.00 | 1.60 | 3.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 4.61 |
Stall cycles | 0.00 |
Front-end | 4.33 |
Dispatch | 3.00 |
Overall L1 | 4.33 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV 0xd8(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RCX,(%R8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV (%R9),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R11,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDX,(%R9) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x8(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R8),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %R15,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 50d2ba <hypre_BoomerAMGCreateS._omp_fn.1+0x97a> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV (%R9),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x8(%RSI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RSI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %RAX,%R15 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 50d2f0 <hypre_BoomerAMGCreateS._omp_fn.1+0x9b0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x8,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0x8,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0x8,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0x8,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %R10,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 50d270 <hypre_BoomerAMGCreateS._omp_fn.1+0x930> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 50d2b7 <hypre_BoomerAMGCreateS._omp_fn.1+0x977> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
JMP 50d2f0 <hypre_BoomerAMGCreateS._omp_fn.1+0x9b0> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
Function | hypre_BoomerAMGCreateS._omp_fn.1 |
Source file and lines | par_strength.c:492-513 |
Module | exec |
nb instructions | 25 |
nb uops | 26 |
loop length | 100 |
used x86 registers | 11 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 1 |
micro-operation queue | 4.33 cycles |
front end | 4.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.70 | 1.60 | 3.00 | 3.00 | 1.00 | 1.60 | 1.50 | 1.00 | 1.00 | 1.00 | 1.60 | 3.00 |
cycles | 1.70 | 1.60 | 3.00 | 3.00 | 1.00 | 1.60 | 1.50 | 1.00 | 1.00 | 1.00 | 1.60 | 3.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 4.61 |
Stall cycles | 0.00 |
Front-end | 4.33 |
Dispatch | 3.00 |
Overall L1 | 4.33 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV 0xd8(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RCX,(%R8) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV (%R9),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R11,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDX,(%R9) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x8(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R8),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %R15,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 50d2ba <hypre_BoomerAMGCreateS._omp_fn.1+0x97a> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV (%R9),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x8(%RSI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RSI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %RAX,%R15 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 50d2f0 <hypre_BoomerAMGCreateS._omp_fn.1+0x9b0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x8,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0x8,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0x8,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0x8,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %R10,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 50d270 <hypre_BoomerAMGCreateS._omp_fn.1+0x930> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 50d2b7 <hypre_BoomerAMGCreateS._omp_fn.1+0x977> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
JMP 50d2f0 <hypre_BoomerAMGCreateS._omp_fn.1+0x9b0> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |