Function: hypre_BoomerAMGBuildMultipass.extracted.27 | Module: exec | Source: par_multi_interp.c:1575-1663 [...] | Coverage: 0.42% |
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Function: hypre_BoomerAMGBuildMultipass.extracted.27 | Module: exec | Source: par_multi_interp.c:1575-1663 [...] | Coverage: 0.42% |
---|
/home/eoseret/qaas_runs_CPU_9468/171-147-2675/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1575 - 1663 |
-------------------------------------------------------------------------------- |
1575: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa) |
[...] |
1585: if (n_fine) |
1586: { tmp_marker = hypre_CTAlloc(HYPRE_Int,n_fine); } |
1587: tmp_marker_offd = NULL; |
1588: if (num_cols_offd) |
1589: { tmp_marker_offd = hypre_CTAlloc(HYPRE_Int,num_cols_offd); } |
1590: for (i=0; i < n_fine; i++) |
1591: { tmp_marker[i] = -1; } |
1592: for (i=0; i < num_cols_offd; i++) |
1593: { tmp_marker_offd[i] = -1; } |
1594: |
1595: /* Compute this thread's range of pass_length */ |
1596: my_thread_num = hypre_GetThreadNum(); |
1597: num_threads = hypre_NumActiveThreads(); |
1598: thread_start = pass_pointer[1] + (pass_length/num_threads)*my_thread_num; |
1599: if (my_thread_num == num_threads-1) |
[...] |
1605: for (i=thread_start; i < thread_stop; i++) |
1606: { |
1607: i1 = pass_array[i]; |
1608: sum_C = 0; |
1609: sum_N = 0; |
1610: j_start = P_diag_start[i1]; |
1611: j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1]; |
1612: for (j=j_start; j < j_end; j++) |
1613: { |
1614: k1 = P_diag_pass[1][j]; |
1615: tmp_marker[C_array[k1]] = i1; |
1616: } |
1617: cnt = P_diag_i[i1]; |
1618: for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++) |
1619: { |
1620: j1 = A_diag_j[j]; |
1621: if (CF_marker[j1] != -3 && |
1622: (num_functions == 1 || dof_func[i1] == dof_func[j1])) |
1623: sum_N += A_diag_data[j]; |
1624: if (j1 != -1 && tmp_marker[j1] == i1) |
1625: { |
1626: P_diag_data[cnt] = A_diag_data[j]; |
1627: P_diag_j[cnt++] = fine_to_coarse[j1]; |
1628: sum_C += A_diag_data[j]; |
1629: } |
1630: } |
1631: j_start = P_offd_start[i1]; |
1632: j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1]; |
1633: for (j=j_start; j < j_end; j++) |
1634: { |
1635: k1 = P_offd_pass[1][j]; |
1636: tmp_marker_offd[C_array_offd[k1]] = i1; |
1637: } |
1638: cnt_offd = P_offd_i[i1]; |
1639: for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++) |
1640: { |
1641: if (col_offd_S_to_A) |
1642: j1 = map_A_to_S[A_offd_j[j]]; |
1643: else |
1644: j1 = A_offd_j[j]; |
1645: if (CF_marker_offd[j1] != -3 && |
1646: (num_functions == 1 || dof_func[i1] == dof_func_offd[j1])) |
1647: sum_N += A_offd_data[j]; |
1648: if (j1 != -1 && tmp_marker_offd[j1] == i1) |
1649: { |
1650: P_offd_data[cnt_offd] = A_offd_data[j]; |
1651: P_offd_j[cnt_offd++] = map_S_to_new[j1]; |
1652: sum_C += A_offd_data[j]; |
1653: } |
1654: } |
1655: diagonal = A_diag_data[A_diag_i[i1]]; |
1656: if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal); |
1657: for (j=P_diag_i[i1]; j < cnt; j++) |
1658: P_diag_data[j] *= alfa; |
1659: for (j=P_offd_i[i1]; j < cnt_offd; j++) |
1660: P_offd_data[j] *= alfa; |
1661: } |
1662: hypre_TFree(tmp_marker); |
1663: hypre_TFree(tmp_marker_offd); |
0x443140 PUSH %RBP |
0x443141 MOV %RSP,%RBP |
0x443144 PUSH %R15 |
0x443146 PUSH %R14 |
0x443148 PUSH %R13 |
0x44314a PUSH %R12 |
0x44314c PUSH %RBX |
0x44314d SUB $0xe8,%RSP |
0x443154 MOV %R9,-0xd0(%RBP) |
0x44315b MOV %R8,-0x90(%RBP) |
0x443162 MOV %RCX,-0xa0(%RBP) |
0x443169 MOV %RDX,-0x40(%RBP) |
0x44316d MOV 0xe8(%RBP),%RAX |
0x443174 MOV %RAX,-0x50(%RBP) |
0x443178 MOV 0xe0(%RBP),%RAX |
0x44317f MOV %RAX,-0x108(%RBP) |
0x443186 MOV 0xd8(%RBP),%RDI |
0x44318d MOV 0xd0(%RBP),%RAX |
0x443194 MOV %RAX,-0x110(%RBP) |
0x44319b MOV 0xc8(%RBP),%RAX |
0x4431a2 MOV %RAX,-0x100(%RBP) |
0x4431a9 MOV 0xc0(%RBP),%RAX |
0x4431b0 MOV %RAX,-0xc8(%RBP) |
0x4431b7 MOV 0xb8(%RBP),%RAX |
0x4431be MOV %RAX,-0xc0(%RBP) |
0x4431c5 MOV 0xb0(%RBP),%RAX |
0x4431cc MOV %RAX,-0xe8(%RBP) |
0x4431d3 MOV 0xa8(%RBP),%RAX |
0x4431da MOV %RAX,-0xe0(%RBP) |
0x4431e1 MOV 0xa0(%RBP),%RAX |
0x4431e8 MOV %RAX,-0x38(%RBP) |
0x4431ec MOV 0x98(%RBP),%RAX |
0x4431f3 MOV %RAX,-0xd8(%RBP) |
0x4431fa MOV 0x90(%RBP),%RBX |
0x443201 MOV 0x88(%RBP),%R15 |
0x443208 MOV 0x80(%RBP),%RAX |
0x44320f MOV %RAX,-0xf0(%RBP) |
0x443216 MOV 0x78(%RBP),%R12 |
0x44321a MOV 0x70(%RBP),%RAX |
0x44321e MOV %RAX,-0xf8(%RBP) |
0x443225 MOV 0x68(%RBP),%RAX |
0x443229 MOV %RAX,-0x60(%RBP) |
0x44322d MOV 0x60(%RBP),%RAX |
0x443231 MOV %RAX,-0x48(%RBP) |
0x443235 MOV 0x58(%RBP),%RAX |
0x443239 MOV %RAX,-0xb8(%RBP) |
0x443240 MOV 0x50(%RBP),%RAX |
0x443244 MOV %RAX,-0x58(%RBP) |
0x443248 MOV 0x48(%RBP),%RAX |
0x44324c MOV %RAX,-0x88(%RBP) |
0x443253 MOV 0x40(%RBP),%RCX |
0x443257 MOV 0x38(%RBP),%RAX |
0x44325b MOV %RAX,-0xb0(%RBP) |
0x443262 MOV 0x30(%RBP),%RAX |
0x443266 MOV %RAX,-0x80(%RBP) |
0x44326a MOV 0x28(%RBP),%RAX |
0x44326e MOV %RAX,-0x98(%RBP) |
0x443275 MOV 0x20(%RBP),%RAX |
0x443279 MOV %RAX,-0x78(%RBP) |
0x44327d MOV 0x18(%RBP),%RAX |
0x443281 MOV %RAX,-0x68(%RBP) |
0x443285 MOV 0x10(%RBP),%RAX |
0x443289 MOV %RAX,-0x70(%RBP) |
0x44328d TEST %RDI,%RDI |
0x443290 MOV %RCX,-0x30(%RBP) |
0x443294 MOV %RDI,-0xa8(%RBP) |
0x44329b JE 443335 |
0x4432a1 MOV $0x8,%ESI |
0x4432a6 CALL 4e72c0 <hypre_CAlloc> |
0x4432ab MOV -0x30(%RBP),%RCX |
0x4432af MOV %RAX,%R13 |
0x4432b2 TEST %RCX,%RCX |
0x4432b5 JE 443341 |
0x4432bb MOV $0x8,%ESI |
0x4432c0 MOV %RCX,%RDI |
0x4432c3 CALL 4e72c0 <hypre_CAlloc> |
0x4432c8 MOV %RAX,%R14 |
0x4432cb MOV -0xa8(%RBP),%RDX |
0x4432d2 TEST %RDX,%RDX |
0x4432d5 JLE 4432e8 |
0x4432d7 SAL $0x3,%RDX |
0x4432db MOV %R13,%RDI |
0x4432de MOV $0xff,%ESI |
0x4432e3 CALL 4f03c0 <_intel_fast_memset> |
0x4432e8 MOV -0x30(%RBP),%RDX |
0x4432ec TEST %RDX,%RDX |
0x4432ef JLE 443302 |
0x4432f1 SAL $0x3,%RDX |
0x4432f5 MOV %R14,%RDI |
0x4432f8 MOV $0xff,%ESI |
0x4432fd CALL 4f03c0 <_intel_fast_memset> |
0x443302 CALL 4e8ff0 <hypre_GetThreadNum> |
0x443307 MOV %RAX,-0x30(%RBP) |
0x44330b CALL 4e8fe0 <hypre_NumActiveThreads> |
0x443310 MOV %RAX,%RCX |
0x443313 MOV -0x38(%RBP),%RAX |
0x443317 MOV 0x8(%RAX),%RDI |
0x44331b MOV -0x50(%RBP),%R8 |
0x44331f MOV %R8,%RAX |
0x443322 OR %RCX,%RAX |
0x443325 SHR $0x20,%RAX |
0x443329 JE 443352 |
0x44332b MOV %R8,%RAX |
0x44332e CQTO |
0x443330 IDIV %RCX |
0x443333 JMP 443359 |
0x443335 XOR %R13D,%R13D |
0x443338 TEST %RCX,%RCX |
0x44333b JNE 4432bb |
0x443341 XOR %R14D,%R14D |
0x443344 MOV -0xa8(%RBP),%RDX |
0x44334b TEST %RDX,%RDX |
0x44334e JG 4432d7 |
0x443350 JMP 4432e8 |
0x443352 MOV %R8D,%EAX |
0x443355 XOR %EDX,%EDX |
0x443357 DIV %ECX |
0x443359 MOV -0x40(%RBP),%R10 |
0x44335d MOV %RAX,%RDX |
0x443360 MOV -0x30(%RBP),%R9 |
0x443364 IMUL %R9,%RDX |
0x443368 DEC %RCX |
0x44336b LEA 0x1(%R9),%RSI |
0x44336f IMUL %RAX,%RSI |
0x443373 CMP %RCX,%R9 |
0x443376 CMOVE %R8,%RSI |
0x44337a MOV %RSI,-0x38(%RBP) |
0x44337e CMP %RSI,%RDX |
0x443381 JGE 4438a7 |
0x443387 MOV -0x38(%RBP),%RAX |
0x44338b ADD %RDI,%RAX |
0x44338e MOV %RAX,-0x38(%RBP) |
0x443392 ADD %RDI,%RDX |
0x443395 VXORPD %XMM0,%XMM0,%XMM0 |
0x443399 VMOVDDUP 0xbc8bf(%RIP),%XMM1 |
0x4433a1 JMP 4433c1 |
0x4433a3 NOPW %CS:(%RAX,%RAX,1) |
(955) 0x4433b0 MOV -0x50(%RBP),%RDX |
(955) 0x4433b4 INC %RDX |
(955) 0x4433b7 CMP -0x38(%RBP),%RDX |
(955) 0x4433bb JGE 4438a7 |
(955) 0x4433c1 MOV -0xd8(%RBP),%RAX |
(955) 0x4433c8 MOV %RDX,-0x50(%RBP) |
(955) 0x4433cc MOV (%RAX,%RDX,8),%RAX |
(955) 0x4433d0 MOV -0xe0(%RBP),%RCX |
(955) 0x4433d7 MOV (%RCX,%RAX,8),%RDI |
(955) 0x4433db MOV -0x58(%RBP),%RCX |
(955) 0x4433df MOV (%RCX,%RAX,8),%RSI |
(955) 0x4433e3 MOV 0x8(%RCX,%RAX,8),%RCX |
(955) 0x4433e8 LEA (%RCX,%RDI,1),%RDX |
(955) 0x4433ec SUB %RSI,%RDX |
(955) 0x4433ef CMP %RDX,%RDI |
(955) 0x4433f2 JGE 4434c5 |
(955) 0x4433f8 MOV -0xc0(%RBP),%RDX |
(955) 0x4433ff MOV 0x8(%RDX),%R8 |
(955) 0x443403 SUB %RSI,%RCX |
(955) 0x443406 CMP $0x8,%RCX |
(955) 0x44340a JB 443490 |
(955) 0x443410 MOV %RCX,%R9 |
(955) 0x443413 SHR $0x3,%R9 |
(955) 0x443417 LEA 0x38(%R8,%RDI,8),%R10 |
(955) 0x44341c NOPL (%RAX) |
(965) 0x443420 MOV -0x38(%R10),%RDX |
(965) 0x443424 MOV (%R15,%RDX,8),%RDX |
(965) 0x443428 MOV %RAX,(%R13,%RDX,8) |
(965) 0x44342d MOV -0x30(%R10),%RDX |
(965) 0x443431 MOV (%R15,%RDX,8),%RDX |
(965) 0x443435 MOV %RAX,(%R13,%RDX,8) |
(965) 0x44343a MOV -0x28(%R10),%RDX |
(965) 0x44343e MOV (%R15,%RDX,8),%RDX |
(965) 0x443442 MOV %RAX,(%R13,%RDX,8) |
(965) 0x443447 MOV -0x20(%R10),%RDX |
(965) 0x44344b MOV (%R15,%RDX,8),%RDX |
(965) 0x44344f MOV %RAX,(%R13,%RDX,8) |
(965) 0x443454 MOV -0x18(%R10),%RDX |
(965) 0x443458 MOV (%R15,%RDX,8),%RDX |
(965) 0x44345c MOV %RAX,(%R13,%RDX,8) |
(965) 0x443461 MOV -0x10(%R10),%RDX |
(965) 0x443465 MOV (%R15,%RDX,8),%RDX |
(965) 0x443469 MOV %RAX,(%R13,%RDX,8) |
(965) 0x44346e MOV -0x8(%R10),%RDX |
(965) 0x443472 MOV (%R15,%RDX,8),%RDX |
(965) 0x443476 MOV %RAX,(%R13,%RDX,8) |
(965) 0x44347b MOV (%R10),%RDX |
(965) 0x44347e MOV (%R15,%RDX,8),%RDX |
(965) 0x443482 MOV %RAX,(%R13,%RDX,8) |
(965) 0x443487 ADD $0x40,%R10 |
(965) 0x44348b DEC %R9 |
(965) 0x44348e JNE 443420 |
(955) 0x443490 MOV %RCX,%R9 |
(955) 0x443493 AND $-0x8,%R9 |
(955) 0x443497 CMP %RCX,%R9 |
(955) 0x44349a MOV -0x40(%RBP),%R10 |
(955) 0x44349e JAE 4434c5 |
(955) 0x4434a0 LEA (%R8,%RDI,8),%RDI |
(955) 0x4434a4 NOPW %CS:(%RAX,%RAX,1) |
(964) 0x4434b0 MOV (%RDI,%R9,8),%RDX |
(964) 0x4434b4 MOV (%R15,%RDX,8),%RDX |
(964) 0x4434b8 MOV %RAX,(%R13,%RDX,8) |
(964) 0x4434bd INC %R9 |
(964) 0x4434c0 CMP %R9,%RCX |
(964) 0x4434c3 JNE 4434b0 |
(955) 0x4434c5 MOV -0x58(%RBP),%RCX |
(955) 0x4434c9 MOV (%RCX,%RAX,8),%RDX |
(955) 0x4434cd MOV -0x68(%RBP),%RCX |
(955) 0x4434d1 MOV (%RCX,%RAX,8),%RDI |
(955) 0x4434d5 MOV 0x8(%RCX,%RAX,8),%R8 |
(955) 0x4434da INC %RDI |
(955) 0x4434dd VXORPD %XMM4,%XMM4,%XMM4 |
(955) 0x4434e1 CMP %R8,%RDI |
(955) 0x4434e4 MOV %RDX,-0x30(%RBP) |
(955) 0x4434e8 VXORPD %XMM3,%XMM3,%XMM3 |
(955) 0x4434ec JGE 4435a0 |
(955) 0x4434f2 MOV -0xb8(%RBP),%RCX |
(955) 0x4434f9 MOV -0x78(%RBP),%RSI |
(955) 0x4434fd JMP 44350c |
0x4434ff NOP |
(963) 0x443500 INC %RDI |
(963) 0x443503 CMP %R8,%RDI |
(963) 0x443506 JGE 4435a0 |
(963) 0x44350c MOV (%RSI,%RDI,8),%R9 |
(963) 0x443510 CMPQ $-0x3,(%R10,%R9,8) |
(963) 0x443515 JE 44353f |
(963) 0x443517 CMPQ $0x1,-0xa0(%RBP) |
(963) 0x44351f JE 443536 |
(963) 0x443521 MOV -0x90(%RBP),%RSI |
(963) 0x443528 MOV (%RSI,%RAX,8),%RDX |
(963) 0x44352c CMP (%RSI,%R9,8),%RDX |
(963) 0x443530 MOV -0x78(%RBP),%RSI |
(963) 0x443534 JNE 44353f |
(963) 0x443536 MOV -0x70(%RBP),%RDX |
(963) 0x44353a VADDSD (%RDX,%RDI,8),%XMM3,%XMM3 |
(963) 0x44353f CMP $-0x1,%R9 |
(963) 0x443543 JE 443500 |
(963) 0x443545 CMP %RAX,(%R13,%R9,8) |
(963) 0x44354a JNE 443500 |
(963) 0x44354c MOV -0x70(%RBP),%R8 |
(963) 0x443550 VMOVSD (%R8,%RDI,8),%XMM5 |
(963) 0x443556 MOV -0x88(%RBP),%RDX |
(963) 0x44355d MOV -0x30(%RBP),%R11 |
(963) 0x443561 VMOVSD %XMM5,(%RDX,%R11,8) |
(963) 0x443567 MOV -0x108(%RBP),%RDX |
(963) 0x44356e MOV (%RDX,%R9,8),%RDX |
(963) 0x443572 MOV %RDX,(%RCX,%R11,8) |
(963) 0x443576 INC %R11 |
(963) 0x443579 MOV %R11,-0x30(%RBP) |
(963) 0x44357d VADDSD (%R8,%RDI,8),%XMM4,%XMM4 |
(963) 0x443583 MOV -0x68(%RBP),%RDX |
(963) 0x443587 MOV 0x8(%RDX,%RAX,8),%R8 |
(963) 0x44358c JMP 443500 |
0x443591 NOPW %CS:(%RAX,%RAX,1) |
(955) 0x4435a0 MOV -0xe8(%RBP),%RDX |
(955) 0x4435a7 MOV (%RDX,%RAX,8),%R8 |
(955) 0x4435ab MOV -0x60(%RBP),%RCX |
(955) 0x4435af MOV (%RCX,%RAX,8),%RSI |
(955) 0x4435b3 MOV 0x8(%RCX,%RAX,8),%RDI |
(955) 0x4435b8 LEA (%RDI,%R8,1),%RDX |
(955) 0x4435bc SUB %RSI,%RDX |
(955) 0x4435bf CMP %RDX,%R8 |
(955) 0x4435c2 JGE 443684 |
(955) 0x4435c8 MOV -0xc8(%RBP),%RDX |
(955) 0x4435cf MOV 0x8(%RDX),%R9 |
(955) 0x4435d3 SUB %RSI,%RDI |
(955) 0x4435d6 CMP $0x8,%RDI |
(955) 0x4435da JB 443658 |
(955) 0x4435e0 MOV %RDI,%R10 |
(955) 0x4435e3 SHR $0x3,%R10 |
(955) 0x4435e7 LEA 0x38(%R9,%R8,8),%R11 |
(955) 0x4435ec NOPL (%RAX) |
(962) 0x4435f0 MOV -0x38(%R11),%RDX |
(962) 0x4435f4 MOV (%RBX,%RDX,8),%RDX |
(962) 0x4435f8 MOV %RAX,(%R14,%RDX,8) |
(962) 0x4435fc MOV -0x30(%R11),%RDX |
(962) 0x443600 MOV (%RBX,%RDX,8),%RDX |
(962) 0x443604 MOV %RAX,(%R14,%RDX,8) |
(962) 0x443608 MOV -0x28(%R11),%RDX |
(962) 0x44360c MOV (%RBX,%RDX,8),%RDX |
(962) 0x443610 MOV %RAX,(%R14,%RDX,8) |
(962) 0x443614 MOV -0x20(%R11),%RDX |
(962) 0x443618 MOV (%RBX,%RDX,8),%RDX |
(962) 0x44361c MOV %RAX,(%R14,%RDX,8) |
(962) 0x443620 MOV -0x18(%R11),%RDX |
(962) 0x443624 MOV (%RBX,%RDX,8),%RDX |
(962) 0x443628 MOV %RAX,(%R14,%RDX,8) |
(962) 0x44362c MOV -0x10(%R11),%RDX |
(962) 0x443630 MOV (%RBX,%RDX,8),%RDX |
(962) 0x443634 MOV %RAX,(%R14,%RDX,8) |
(962) 0x443638 MOV -0x8(%R11),%RDX |
(962) 0x44363c MOV (%RBX,%RDX,8),%RDX |
(962) 0x443640 MOV %RAX,(%R14,%RDX,8) |
(962) 0x443644 MOV (%R11),%RDX |
(962) 0x443647 MOV (%RBX,%RDX,8),%RDX |
(962) 0x44364b MOV %RAX,(%R14,%RDX,8) |
(962) 0x44364f ADD $0x40,%R11 |
(962) 0x443653 DEC %R10 |
(962) 0x443656 JNE 4435f0 |
(955) 0x443658 MOV %RDI,%R10 |
(955) 0x44365b AND $-0x8,%R10 |
(955) 0x44365f CMP %RDI,%R10 |
(955) 0x443662 JAE 443684 |
(955) 0x443664 LEA (%R9,%R8,8),%R8 |
(955) 0x443668 NOPL (%RAX,%RAX,1) |
(961) 0x443670 MOV (%R8,%R10,8),%RDX |
(961) 0x443674 MOV (%RBX,%RDX,8),%RDX |
(961) 0x443678 MOV %RAX,(%R14,%RDX,8) |
(961) 0x44367c INC %R10 |
(961) 0x44367f CMP %R10,%RDI |
(961) 0x443682 JNE 443670 |
(955) 0x443684 MOV -0x60(%RBP),%RCX |
(955) 0x443688 MOV (%RCX,%RAX,8),%RDI |
(955) 0x44368c MOV -0x80(%RBP),%RCX |
(955) 0x443690 MOV (%RCX,%RAX,8),%R8 |
(955) 0x443694 MOV 0x8(%RCX,%RAX,8),%R10 |
(955) 0x443699 CMP %R10,%R8 |
(955) 0x44369c JGE 443780 |
(955) 0x4436a2 MOV -0xb0(%RBP),%RCX |
(955) 0x4436a9 LEA (%RCX,%R8,8),%R9 |
(955) 0x4436ad MOV -0xd0(%RBP),%RSI |
(955) 0x4436b4 JMP 4436d0 |
0x4436b6 NOPW %CS:(%RAX,%RAX,1) |
(960) 0x4436c0 INC %R8 |
(960) 0x4436c3 ADD $0x8,%R9 |
(960) 0x4436c7 CMP %R10,%R8 |
(960) 0x4436ca JGE 443780 |
(960) 0x4436d0 MOV %R9,%RDX |
(960) 0x4436d3 TEST %RSI,%RSI |
(960) 0x4436d6 JE 4436e6 |
(960) 0x4436d8 MOV (%R9),%RDX |
(960) 0x4436db MOV -0x110(%RBP),%R11 |
(960) 0x4436e2 LEA (%R11,%RDX,8),%RDX |
(960) 0x4436e6 MOV (%RDX),%R11 |
(960) 0x4436e9 CMPQ $-0x3,(%R12,%R11,8) |
(960) 0x4436ee JE 443725 |
(960) 0x4436f0 CMPQ $0x1,-0xa0(%RBP) |
(960) 0x4436f8 JE 443718 |
(960) 0x4436fa MOV -0x90(%RBP),%RDX |
(960) 0x443701 MOV (%RDX,%RAX,8),%RDX |
(960) 0x443705 MOV %R12,%RCX |
(960) 0x443708 MOV -0xf0(%RBP),%R12 |
(960) 0x44370f CMP (%R12,%R11,8),%RDX |
(960) 0x443713 MOV %RCX,%R12 |
(960) 0x443716 JNE 443725 |
(960) 0x443718 MOV -0x98(%RBP),%RCX |
(960) 0x44371f VADDSD (%RCX,%R8,8),%XMM3,%XMM3 |
(960) 0x443725 CMP $-0x1,%R11 |
(960) 0x443729 JE 4436c0 |
(960) 0x44372b CMP %RAX,(%R14,%R11,8) |
(960) 0x44372f JNE 4436c0 |
(960) 0x443731 MOV -0x98(%RBP),%R10 |
(960) 0x443738 VMOVSD (%R10,%R8,8),%XMM5 |
(960) 0x44373e MOV -0x48(%RBP),%RCX |
(960) 0x443742 VMOVSD %XMM5,(%RCX,%RDI,8) |
(960) 0x443747 MOV -0x100(%RBP),%RDX |
(960) 0x44374e MOV (%RDX,%R11,8),%RDX |
(960) 0x443752 MOV -0xf8(%RBP),%RCX |
(960) 0x443759 MOV %RDX,(%RCX,%RDI,8) |
(960) 0x44375d INC %RDI |
(960) 0x443760 VADDSD (%R10,%R8,8),%XMM4,%XMM4 |
(960) 0x443766 MOV -0x80(%RBP),%RCX |
(960) 0x44376a MOV 0x8(%RCX,%RAX,8),%R10 |
(960) 0x44376f JMP 4436c0 |
0x443774 NOPW %CS:(%RAX,%RAX,1) |
(955) 0x443780 MOV -0x68(%RBP),%RCX |
(955) 0x443784 MOV (%RCX,%RAX,8),%RDX |
(955) 0x443788 MOV -0x70(%RBP),%RCX |
(955) 0x44378c VMULSD (%RCX,%RDX,8),%XMM4,%XMM4 |
(955) 0x443791 VUCOMISD %XMM0,%XMM4 |
(955) 0x443795 JE 44379f |
(955) 0x443797 VXORPD %XMM1,%XMM3,%XMM2 |
(955) 0x44379b VDIVSD %XMM4,%XMM2,%XMM2 |
(955) 0x44379f MOV -0x58(%RBP),%RCX |
(955) 0x4437a3 MOV (%RCX,%RAX,8),%R9 |
(955) 0x4437a7 MOV -0x30(%RBP),%RSI |
(955) 0x4437ab MOV %RSI,%R10 |
(955) 0x4437ae SUB %R9,%R10 |
(955) 0x4437b1 MOV -0x48(%RBP),%RDX |
(955) 0x4437b5 MOV -0x88(%RBP),%RCX |
(955) 0x4437bc JLE 443824 |
(955) 0x4437be MOV %R10,%R8 |
(955) 0x4437c1 AND $-0x4,%R8 |
(955) 0x4437c5 JE 443802 |
(955) 0x4437c7 LEA -0x1(%R8),%R11 |
(955) 0x4437cb VBROADCASTSD %XMM2,%YMM3 |
(955) 0x4437d0 LEA (%RCX,%R9,8),%RSI |
(955) 0x4437d4 XOR %EDX,%EDX |
(955) 0x4437d6 NOPW %CS:(%RAX,%RAX,1) |
(959) 0x4437e0 VMULPD (%RSI,%RDX,8),%YMM3,%YMM4 |
(959) 0x4437e5 VMOVUPD %YMM4,(%RSI,%RDX,8) |
(959) 0x4437ea ADD $0x4,%RDX |
(959) 0x4437ee CMP %R11,%RDX |
(959) 0x4437f1 JBE 4437e0 |
(955) 0x4437f3 CMP %R8,%R10 |
(955) 0x4437f6 MOV -0x48(%RBP),%RDX |
(955) 0x4437fa MOV -0x30(%RBP),%RSI |
(955) 0x4437fe JNE 443805 |
(955) 0x443800 JMP 443824 |
(955) 0x443802 XOR %R8D,%R8D |
(955) 0x443805 ADD %R9,%R8 |
(955) 0x443808 NOPL (%RAX,%RAX,1) |
(958) 0x443810 VMULSD (%RCX,%R8,8),%XMM2,%XMM3 |
(958) 0x443816 VMOVSD %XMM3,(%RCX,%R8,8) |
(958) 0x44381c INC %R8 |
(958) 0x44381f CMP %R8,%RSI |
(958) 0x443822 JNE 443810 |
(955) 0x443824 MOV -0x60(%RBP),%RCX |
(955) 0x443828 MOV (%RCX,%RAX,8),%RCX |
(955) 0x44382c MOV %RDI,%R8 |
(955) 0x44382f SUB %RCX,%R8 |
(955) 0x443832 MOV -0x40(%RBP),%R10 |
(955) 0x443836 JLE 4433b0 |
(955) 0x44383c MOV %R8,%RAX |
(955) 0x44383f AND $-0x4,%RAX |
(955) 0x443843 JE 443882 |
(955) 0x443845 LEA -0x1(%RAX),%R9 |
(955) 0x443849 VBROADCASTSD %XMM2,%YMM3 |
(955) 0x44384e LEA (%RDX,%RCX,8),%RSI |
(955) 0x443852 XOR %EDX,%EDX |
(955) 0x443854 NOPW %CS:(%RAX,%RAX,1) |
(957) 0x443860 VMULPD (%RSI,%RDX,8),%YMM3,%YMM4 |
(957) 0x443865 VMOVUPD %YMM4,(%RSI,%RDX,8) |
(957) 0x44386a ADD $0x4,%RDX |
(957) 0x44386e CMP %R9,%RDX |
(957) 0x443871 JBE 443860 |
(955) 0x443873 CMP %RAX,%R8 |
(955) 0x443876 MOV -0x48(%RBP),%RDX |
(955) 0x44387a JE 4433b0 |
(955) 0x443880 JMP 443884 |
(955) 0x443882 XOR %EAX,%EAX |
(955) 0x443884 ADD %RCX,%RAX |
(955) 0x443887 NOPW (%RAX,%RAX,1) |
(956) 0x443890 VMULSD (%RDX,%RAX,8),%XMM2,%XMM3 |
(956) 0x443895 VMOVSD %XMM3,(%RDX,%RAX,8) |
(956) 0x44389a INC %RAX |
(956) 0x44389d CMP %RAX,%RDI |
(956) 0x4438a0 JNE 443890 |
(955) 0x4438a2 JMP 4433b0 |
0x4438a7 MOV %R13,%RDI |
0x4438aa VZEROUPPER |
0x4438ad CALL 4e7390 <hypre_Free> |
0x4438b2 MOV %R14,%RDI |
0x4438b5 ADD $0xe8,%RSP |
0x4438bc POP %RBX |
0x4438bd POP %R12 |
0x4438bf POP %R13 |
0x4438c1 POP %R14 |
0x4438c3 POP %R15 |
0x4438c5 POP %RBP |
0x4438c6 JMP 4e7390 |
0x4438cb NOPL (%RAX,%RAX,1) |
Path / |
Source file and lines | par_multi_interp.c:1575-1663 |
Module | exec |
nb instructions | 154 |
nb uops | 169 |
loop length | 703 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 57 |
micro-operation queue | 28.17 cycles |
front end | 28.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 7.50 | 8.00 | 15.00 | 15.00 | 22.50 | 7.60 | 7.50 | 22.50 | 22.50 | 22.50 | 7.40 | 15.00 |
cycles | 7.50 | 11.40 | 15.00 | 15.00 | 22.50 | 7.60 | 7.50 | 22.50 | 22.50 | 22.50 | 7.40 | 15.00 |
Cycles executing div or sqrt instructions | 16.00 |
FE+BE cycles | 26.56-26.61 |
Stall cycles | 0.00 |
Front-end | 28.17 |
Dispatch | 22.50 |
DIV/SQRT | 16.00 |
Overall L1 | 28.17 |
all | 1% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 3% |
all | 50% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 2% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 6% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 11% |
all | 18% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 9% |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0xe8,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R9,-0xd0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,-0x90(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,-0xa0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x108(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xd8(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x110(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xc8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x100(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xc0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xc8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xb8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xc0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xb0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xe8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xe0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x98(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xd8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x90(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x88(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x80(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xf0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x78(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x70(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xf8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x68(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x60(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x60(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x58(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xb8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x50(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x48(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x88(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x40(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xb0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x30(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x80(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x28(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x98(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x20(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x78(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x68(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x70(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RDI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV %RCX,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,-0xa8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JE 443335 <hypre_BoomerAMGBuildMultipass.extracted.27+0x1f5> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 4e72c0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x30(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 443341 <hypre_BoomerAMGBuildMultipass.extracted.27+0x201> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4e72c0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0xa8(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 4432e8 <hypre_BoomerAMGBuildMultipass.extracted.27+0x1a8> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
SAL $0x3,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %R13,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 4f03c0 <_intel_fast_memset> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x30(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 443302 <hypre_BoomerAMGBuildMultipass.extracted.27+0x1c2> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
SAL $0x3,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %R14,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 4f03c0 <_intel_fast_memset> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
CALL 4e8ff0 <hypre_GetThreadNum> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4e8fe0 <hypre_NumActiveThreads> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x38(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RAX),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x50(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
OR %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SHR $0x20,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
JE 443352 <hypre_BoomerAMGBuildMultipass.extracted.27+0x212> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R8,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CQTO | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %RCX | 5 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 10 |
JMP 443359 <hypre_BoomerAMGBuildMultipass.extracted.27+0x219> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
XOR %R13D,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 4432bb <hypre_BoomerAMGBuildMultipass.extracted.27+0x17b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %R14D,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0xa8(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JG 4432d7 <hypre_BoomerAMGBuildMultipass.extracted.27+0x197> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 4432e8 <hypre_BoomerAMGBuildMultipass.extracted.27+0x1a8> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV %R8D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
DIV %ECX | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV -0x40(%RBP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x30(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R9,%RDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DEC %RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x1(%R9),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
IMUL %RAX,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
CMP %RCX,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVE %R8,%RSI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RSI,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %RSI,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4438a7 <hypre_BoomerAMGBuildMultipass.extracted.27+0x767> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x38(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RDI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RAX,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %RDI,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVDDUP 0xbc8bf(%RIP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 4433c1 <hypre_BoomerAMGBuildMultipass.extracted.27+0x281> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R13,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 4e7390 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %R14,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0xe8,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
JMP 4e7390 <hypre_Free> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | par_multi_interp.c:1575-1663 |
Module | exec |
nb instructions | 154 |
nb uops | 169 |
loop length | 703 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 57 |
micro-operation queue | 28.17 cycles |
front end | 28.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 7.50 | 8.00 | 15.00 | 15.00 | 22.50 | 7.60 | 7.50 | 22.50 | 22.50 | 22.50 | 7.40 | 15.00 |
cycles | 7.50 | 11.40 | 15.00 | 15.00 | 22.50 | 7.60 | 7.50 | 22.50 | 22.50 | 22.50 | 7.40 | 15.00 |
Cycles executing div or sqrt instructions | 16.00 |
FE+BE cycles | 26.56-26.61 |
Stall cycles | 0.00 |
Front-end | 28.17 |
Dispatch | 22.50 |
DIV/SQRT | 16.00 |
Overall L1 | 28.17 |
all | 1% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 3% |
all | 50% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 2% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 6% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 11% |
all | 18% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 9% |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0xe8,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R9,-0xd0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,-0x90(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,-0xa0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x108(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xd8(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x110(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xc8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x100(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xc0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xc8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xb8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xc0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xb0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xe8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xe0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x98(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xd8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x90(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x88(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x80(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xf0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x78(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x70(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xf8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x68(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x60(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x60(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x58(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xb8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x50(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x48(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x88(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x40(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xb0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x30(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x80(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x28(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x98(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x20(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x78(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x68(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x70(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RDI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV %RCX,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,-0xa8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JE 443335 <hypre_BoomerAMGBuildMultipass.extracted.27+0x1f5> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 4e72c0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x30(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 443341 <hypre_BoomerAMGBuildMultipass.extracted.27+0x201> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4e72c0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0xa8(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 4432e8 <hypre_BoomerAMGBuildMultipass.extracted.27+0x1a8> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
SAL $0x3,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %R13,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 4f03c0 <_intel_fast_memset> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x30(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 443302 <hypre_BoomerAMGBuildMultipass.extracted.27+0x1c2> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
SAL $0x3,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %R14,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 4f03c0 <_intel_fast_memset> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
CALL 4e8ff0 <hypre_GetThreadNum> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4e8fe0 <hypre_NumActiveThreads> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x38(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RAX),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x50(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
OR %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SHR $0x20,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
JE 443352 <hypre_BoomerAMGBuildMultipass.extracted.27+0x212> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R8,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CQTO | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %RCX | 5 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 10 |
JMP 443359 <hypre_BoomerAMGBuildMultipass.extracted.27+0x219> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
XOR %R13D,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 4432bb <hypre_BoomerAMGBuildMultipass.extracted.27+0x17b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %R14D,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0xa8(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JG 4432d7 <hypre_BoomerAMGBuildMultipass.extracted.27+0x197> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 4432e8 <hypre_BoomerAMGBuildMultipass.extracted.27+0x1a8> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV %R8D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
DIV %ECX | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV -0x40(%RBP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x30(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R9,%RDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DEC %RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x1(%R9),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
IMUL %RAX,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
CMP %RCX,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVE %R8,%RSI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RSI,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %RSI,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4438a7 <hypre_BoomerAMGBuildMultipass.extracted.27+0x767> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x38(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RDI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RAX,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %RDI,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVDDUP 0xbc8bf(%RIP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 4433c1 <hypre_BoomerAMGBuildMultipass.extracted.27+0x281> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R13,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 4e7390 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %R14,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0xe8,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
JMP 4e7390 <hypre_Free> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼hypre_BoomerAMGBuildMultipass.extracted.27– | 0.42 | 0.08 |
▼Loop 955 - par_multi_interp.c:1585-1660 - exec– | 0.05 | 0.01 |
○Loop 963 - par_multi_interp.c:1618-1628 - exec | 0.36 | 0.06 |
○Loop 964 - par_multi_interp.c:1612-1615 - exec | 0.01 | 0 |
○Loop 957 - par_multi_interp.c:1659-1660 - exec | 0 | 0 |
○Loop 958 - par_multi_interp.c:1657-1658 - exec | 0 | 0 |
○Loop 960 - par_multi_interp.c:1622-1652 - exec | 0 | 0 |
○Loop 962 - par_multi_interp.c:1633-1636 - exec | 0 | 0 |
○Loop 961 - par_multi_interp.c:1633-1636 - exec | 0 | 0 |
○Loop 965 - par_multi_interp.c:1612-1615 - exec | 0 | 0 |
○Loop 959 - par_multi_interp.c:1657-1658 - exec | 0 | 0 |
○Loop 956 - par_multi_interp.c:1659-1660 - exec | 0 | 0 |