Function: hypre_ParCSRRelaxThreads.extracted.57 | Module: exec | Source: ams.c:3662-3682 | Coverage: 36.98% |
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Function: hypre_ParCSRRelaxThreads.extracted.57 | Module: exec | Source: ams.c:3662-3682 | Coverage: 36.98% |
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/home/eoseret/qaas_runs_CPU_9468/171-147-2675/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3662 - 3682 |
-------------------------------------------------------------------------------- |
3662: #pragma omp parallel for private(i,ii,jj,res) HYPRE_SMP_SCHEDULE |
3663: #endif |
3664: for (i = 0; i < n; i++) |
3665: { |
3666: /*----------------------------------------------------------- |
3667: * If diagonal is nonzero, relax point i; otherwise, skip it. |
3668: *-----------------------------------------------------------*/ |
3669: if (A_diag_data[A_diag_i[i]] != zero) |
3670: { |
3671: res = f_data[i]; |
3672: for (jj = A_diag_i[i]; jj < A_diag_i[i+1]; jj++) |
3673: { |
3674: ii = A_diag_j[jj]; |
3675: res -= A_diag_data[jj] * Vtemp_data[ii]; |
3676: } |
3677: for (jj = A_offd_i[i]; jj < A_offd_i[i+1]; jj++) |
3678: { |
3679: ii = A_offd_j[jj]; |
3680: res -= A_offd_data[jj] * Vext_data[ii]; |
3681: } |
3682: u_data[i] += (relax_weight*res)/l1_norms[i]; |
0x4aaba0 PUSH %RBP |
0x4aaba1 MOV %RSP,%RBP |
0x4aaba4 PUSH %R15 |
0x4aaba6 PUSH %R14 |
0x4aaba8 PUSH %R13 |
0x4aabaa PUSH %R12 |
0x4aabac PUSH %RBX |
0x4aabad SUB $0x68,%RSP |
0x4aabb1 MOV 0x48(%RBP),%RBX |
0x4aabb5 MOV 0x40(%RBP),%R13 |
0x4aabb9 MOV 0x38(%RBP),%RAX |
0x4aabbd MOV %RAX,-0x80(%RBP) |
0x4aabc1 MOV 0x30(%RBP),%RAX |
0x4aabc5 MOV %RAX,-0x78(%RBP) |
0x4aabc9 MOV 0x28(%RBP),%RAX |
0x4aabcd MOV %RAX,-0x38(%RBP) |
0x4aabd1 MOV 0x20(%RBP),%R14 |
0x4aabd5 MOV 0x18(%RBP),%RAX |
0x4aabd9 MOV %RAX,-0x70(%RBP) |
0x4aabdd MOV 0x10(%RBP),%R12 |
0x4aabe1 MOVL $0,-0x48(%RBP) |
0x4aabe8 MOV %R9,-0x30(%RBP) |
0x4aabec MOV %R8,%R15 |
0x4aabef MOV %RCX,-0x40(%RBP) |
0x4aabf3 MOV %RDX,-0x68(%RBP) |
0x4aabf7 MOV (%RDI),%ESI |
0x4aabf9 MOVQ $0,-0x58(%RBP) |
0x4aac01 MOVQ $0x1,-0x90(%RBP) |
0x4aac0c SUB $0x8,%RSP |
0x4aac10 LEA -0x90(%RBP),%RAX |
0x4aac17 LEA -0x48(%RBP),%RCX |
0x4aac1b LEA -0x58(%RBP),%R8 |
0x4aac1f LEA 0x60(%RBP),%R9 |
0x4aac23 MOV $0x536b10,%EDI |
0x4aac28 MOV %ESI,-0x44(%RBP) |
0x4aac2b MOV $0x22,%EDX |
0x4aac30 PUSH $0x1 |
0x4aac32 PUSH $0x1 |
0x4aac34 PUSH %RAX |
0x4aac35 CALL 410420 <__kmpc_for_static_init_8@plt> |
0x4aac3a MOV -0x30(%RBP),%RCX |
0x4aac3e ADD $0x20,%RSP |
0x4aac42 MOV -0x58(%RBP),%R11 |
0x4aac46 MOV 0x60(%RBP),%RAX |
0x4aac4a SUB %R11,%RAX |
0x4aac4d MOV %RAX,-0x88(%RBP) |
0x4aac54 JAE 4aac74 |
0x4aac56 MOV $0x536b30,%EDI |
0x4aac5b MOV -0x44(%RBP),%ESI |
0x4aac5e ADD $0x68,%RSP |
0x4aac62 POP %RBX |
0x4aac63 POP %R12 |
0x4aac65 POP %R13 |
0x4aac67 POP %R14 |
0x4aac69 POP %R15 |
0x4aac6b POP %RBP |
0x4aac6c VZEROUPPER |
0x4aac6f JMP 410170 |
0x4aac74 VMOVSD -0x40(%RBP),%XMM0 |
0x4aac79 XOR %EDX,%EDX |
0x4aac7b VXORPD %XMM1,%XMM1,%XMM1 |
0x4aac7f MOV %R11,-0x50(%RBP) |
0x4aac83 JMP 4aacbf |
0x4aac85 NOPW %CS:(%RAX,%RAX,1) |
(3223) 0x4aac90 VMULSD %XMM0,%XMM2,%XMM2 |
(3223) 0x4aac94 MOV -0x68(%RBP),%RAX |
(3223) 0x4aac98 VDIVSD (%RAX,%RSI,8),%XMM2,%XMM2 |
(3223) 0x4aac9d MOV -0x78(%RBP),%RAX |
(3223) 0x4aaca1 VADDSD (%RAX,%RSI,8),%XMM2,%XMM2 |
(3223) 0x4aaca6 VMOVSD %XMM2,(%RAX,%RSI,8) |
(3223) 0x4aacab MOV -0x40(%RBP),%RDX |
(3223) 0x4aacaf LEA 0x1(%RDX),%RAX |
(3223) 0x4aacb3 CMP -0x88(%RBP),%RDX |
(3223) 0x4aacba MOV %RAX,%RDX |
(3223) 0x4aacbd JE 4aac56 |
(3223) 0x4aacbf LEA (%R11,%RDX,1),%RSI |
(3223) 0x4aacc3 MOV (%RCX,%RSI,8),%R9 |
(3223) 0x4aacc7 VUCOMISD (%R15,%R9,8),%XMM1 |
(3223) 0x4aaccd JE 4aacaf |
(3223) 0x4aaccf MOV -0x80(%RBP),%RAX |
(3223) 0x4aacd3 VMOVSD (%RAX,%RSI,8),%XMM2 |
(3223) 0x4aacd8 MOV 0x8(%RCX,%RSI,8),%RDI |
(3223) 0x4aacdd MOV %RDI,%R10 |
(3223) 0x4aace0 SUB %R9,%R10 |
(3223) 0x4aace3 MOV %RDX,-0x40(%RBP) |
(3223) 0x4aace7 JLE 4aad60 |
(3223) 0x4aace9 MOV %R10,%R8 |
(3223) 0x4aacec AND $-0x4,%R8 |
(3223) 0x4aacf0 JE 4aad66 |
(3223) 0x4aacf2 LEA -0x1(%R8),%R11 |
(3223) 0x4aacf6 LEA (%R15,%R9,8),%RAX |
(3223) 0x4aacfa LEA (%R12,%R9,8),%RCX |
(3223) 0x4aacfe VXORPD %XMM3,%XMM3,%XMM3 |
(3223) 0x4aad02 XOR %EDX,%EDX |
(3223) 0x4aad04 NOPW %CS:(%RAX,%RAX,1) |
(3227) 0x4aad10 VMOVUPD (%RCX,%RDX,8),%YMM4 |
(3227) 0x4aad15 VXORPD %XMM5,%XMM5,%XMM5 |
(3227) 0x4aad19 KXNORW %K0,%K0,%K1 |
(3227) 0x4aad1d VGATHERQPD (%R13,%YMM4,8),%YMM5{%K1} |
(3227) 0x4aad25 VFNMADD231PD (%RAX,%RDX,8),%YMM5,%YMM3 |
(3227) 0x4aad2b ADD $0x4,%RDX |
(3227) 0x4aad2f CMP %R11,%RDX |
(3227) 0x4aad32 JBE 4aad10 |
(3223) 0x4aad34 VEXTRACTF128 $0x1,%YMM3,%XMM4 |
(3223) 0x4aad3a VADDPD %XMM4,%XMM3,%XMM3 |
(3223) 0x4aad3e VSHUFPD $0x1,%XMM3,%XMM3,%XMM4 |
(3223) 0x4aad43 VADDSD %XMM4,%XMM3,%XMM3 |
(3223) 0x4aad47 VADDSD %XMM3,%XMM2,%XMM2 |
(3223) 0x4aad4b CMP %R8,%R10 |
(3223) 0x4aad4e MOV -0x38(%RBP),%RDX |
(3223) 0x4aad52 MOV -0x30(%RBP),%RCX |
(3223) 0x4aad56 MOV -0x50(%RBP),%R11 |
(3223) 0x4aad5a JNE 4aad6d |
(3223) 0x4aad5c JMP 4aad89 |
0x4aad5e XCHG %AX,%AX |
(3223) 0x4aad60 MOV -0x38(%RBP),%RDX |
(3223) 0x4aad64 JMP 4aad89 |
(3223) 0x4aad66 XOR %R8D,%R8D |
(3223) 0x4aad69 MOV -0x38(%RBP),%RDX |
(3223) 0x4aad6d ADD %R9,%R8 |
(3226) 0x4aad70 MOV (%R12,%R8,8),%RAX |
(3226) 0x4aad74 VMOVSD (%R13,%RAX,8),%XMM3 |
(3226) 0x4aad7b VFNMADD231SD (%R15,%R8,8),%XMM3,%XMM2 |
(3226) 0x4aad81 INC %R8 |
(3226) 0x4aad84 CMP %R8,%RDI |
(3226) 0x4aad87 JNE 4aad70 |
(3223) 0x4aad89 MOV -0x70(%RBP),%RAX |
(3223) 0x4aad8d MOV (%RAX,%RSI,8),%R9 |
(3223) 0x4aad91 MOV 0x8(%RAX,%RSI,8),%RDI |
(3223) 0x4aad96 MOV %RDI,%R10 |
(3223) 0x4aad99 SUB %R9,%R10 |
(3223) 0x4aad9c JLE 4aac90 |
(3223) 0x4aada2 MOV %R10,%R8 |
(3223) 0x4aada5 AND $-0x4,%R8 |
(3223) 0x4aada9 JE 4aae22 |
(3223) 0x4aadab LEA -0x1(%R8),%R11 |
(3223) 0x4aadaf LEA (%R14,%R9,8),%RAX |
(3223) 0x4aadb3 MOV %R9,-0x60(%RBP) |
(3223) 0x4aadb7 LEA (%RDX,%R9,8),%RCX |
(3223) 0x4aadbb VXORPD %XMM3,%XMM3,%XMM3 |
(3223) 0x4aadbf XOR %R9D,%R9D |
(3223) 0x4aadc2 NOPW %CS:(%RAX,%RAX,1) |
(3225) 0x4aadd0 VMOVUPD (%RCX,%R9,8),%YMM4 |
(3225) 0x4aadd6 VXORPD %XMM5,%XMM5,%XMM5 |
(3225) 0x4aadda KXNORW %K0,%K0,%K1 |
(3225) 0x4aadde VGATHERQPD (%RBX,%YMM4,8),%YMM5{%K1} |
(3225) 0x4aade5 VFNMADD231PD (%RAX,%R9,8),%YMM5,%YMM3 |
(3225) 0x4aadeb ADD $0x4,%R9 |
(3225) 0x4aadef CMP %R11,%R9 |
(3225) 0x4aadf2 JBE 4aadd0 |
(3223) 0x4aadf4 VEXTRACTF128 $0x1,%YMM3,%XMM4 |
(3223) 0x4aadfa VADDPD %XMM4,%XMM3,%XMM3 |
(3223) 0x4aadfe VSHUFPD $0x1,%XMM3,%XMM3,%XMM4 |
(3223) 0x4aae03 VADDSD %XMM4,%XMM3,%XMM3 |
(3223) 0x4aae07 VADDSD %XMM3,%XMM2,%XMM2 |
(3223) 0x4aae0b CMP %R8,%R10 |
(3223) 0x4aae0e MOV -0x30(%RBP),%RCX |
(3223) 0x4aae12 MOV -0x50(%RBP),%R11 |
(3223) 0x4aae16 MOV -0x60(%RBP),%R9 |
(3223) 0x4aae1a JE 4aac90 |
(3223) 0x4aae20 JMP 4aae25 |
(3223) 0x4aae22 XOR %R8D,%R8D |
(3223) 0x4aae25 ADD %R9,%R8 |
(3223) 0x4aae28 NOPL (%RAX,%RAX,1) |
(3224) 0x4aae30 MOV (%RDX,%R8,8),%RAX |
(3224) 0x4aae34 VMOVSD (%RBX,%RAX,8),%XMM3 |
(3224) 0x4aae39 VFNMADD231SD (%R14,%R8,8),%XMM3,%XMM2 |
(3224) 0x4aae3f INC %R8 |
(3224) 0x4aae42 CMP %R8,%RDI |
(3224) 0x4aae45 JNE 4aae30 |
(3223) 0x4aae47 JMP 4aac90 |
0x4aae4c NOPL (%RAX) |
Path / |
Source file and lines | ams.c:3662-3682 |
Module | exec |
nb instructions | 66 |
nb uops | 68 |
loop length | 246 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 22 |
micro-operation queue | 11.33 cycles |
front end | 11.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.10 | 1.00 | 6.67 | 6.67 | 11.50 | 1.00 | 0.90 | 11.50 | 11.50 | 11.50 | 1.00 | 6.67 |
cycles | 1.10 | 1.00 | 6.67 | 6.67 | 11.50 | 1.00 | 0.90 | 11.50 | 11.50 | 11.50 | 1.00 | 6.67 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 11.59 |
Stall cycles | 0.08-0.08 |
RS full (events) | 0.27-0.26 |
Front-end | 11.33 |
Dispatch | 11.50 |
Overall L1 | 11.50 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 25% |
all | 50% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 7% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 40% |
all | 11% |
load | 10% |
store | 10% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 18% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 11% |
load | 11% |
store | 10% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 15% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x68,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x48(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x40(%RBP),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x80(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x30(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x78(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x28(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x20(%RBP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x70(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVL $0,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RCX,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,-0x68(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVQ $0,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVQ $0x1,-0x90(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x90(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x48(%RBP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x58(%RBP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x60(%RBP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x536b10,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,-0x44(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x22,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 410420 <__kmpc_for_static_init_8@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x30(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x20,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x58(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x60(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %R11,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RAX,-0x88(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JAE 4aac74 <hypre_ParCSRRelaxThreads.extracted.57+0xd4> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x536b30,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x44(%RBP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x68,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 410170 <__kmpc_for_static_fini@plt> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
VMOVSD -0x40(%RBP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VXORPD %XMM1,%XMM1,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R11,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 4aacbf <hypre_ParCSRRelaxThreads.extracted.57+0x11f> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | ams.c:3662-3682 |
Module | exec |
nb instructions | 66 |
nb uops | 68 |
loop length | 246 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 22 |
micro-operation queue | 11.33 cycles |
front end | 11.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.10 | 1.00 | 6.67 | 6.67 | 11.50 | 1.00 | 0.90 | 11.50 | 11.50 | 11.50 | 1.00 | 6.67 |
cycles | 1.10 | 1.00 | 6.67 | 6.67 | 11.50 | 1.00 | 0.90 | 11.50 | 11.50 | 11.50 | 1.00 | 6.67 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 11.59 |
Stall cycles | 0.08-0.08 |
RS full (events) | 0.27-0.26 |
Front-end | 11.33 |
Dispatch | 11.50 |
Overall L1 | 11.50 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 25% |
all | 50% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 7% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 40% |
all | 11% |
load | 10% |
store | 10% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 18% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 11% |
load | 11% |
store | 10% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 15% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x68,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x48(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x40(%RBP),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x80(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x30(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x78(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x28(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x20(%RBP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x70(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVL $0,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RCX,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,-0x68(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVQ $0,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVQ $0x1,-0x90(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x90(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x48(%RBP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x58(%RBP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x60(%RBP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x536b10,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,-0x44(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x22,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 410420 <__kmpc_for_static_init_8@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x30(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x20,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x58(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x60(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %R11,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RAX,-0x88(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JAE 4aac74 <hypre_ParCSRRelaxThreads.extracted.57+0xd4> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x536b30,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x44(%RBP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x68,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 410170 <__kmpc_for_static_fini@plt> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
VMOVSD -0x40(%RBP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VXORPD %XMM1,%XMM1,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R11,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 4aacbf <hypre_ParCSRRelaxThreads.extracted.57+0x11f> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼hypre_ParCSRRelaxThreads.extracted.57– | 36.98 | 7.37 |
▼Loop 3223 - ams.c:3662-3682 - exec– | 4.22 | 0.75 |
○Loop 3227 - ams.c:3672-3675 - exec | 29.73 | 5.28 |
○Loop 3226 - ams.c:3672-3675 - exec | 3 | 0.53 |
○Loop 3225 - ams.c:3677-3680 - exec | 0.03 | 0.01 |
○Loop 3224 - ams.c:3677-3680 - exec | 0 | 0 |