OV - exec - Loop 823

	Loop Id: 823	Module: exec	Source: par_lr_interp.c:1609-1675 [...]	Coverage: 0.17%

0x4398ec LDUR	X14, [X29, #488]

0x4398f0 LDR	D4, [X8, X13,LSL #3]

0x4398f4 LDR	D3, [X14, X3,LSL #3]

0x4398f8 FADD	D3, D4, D3

0x4398fc STR	D3, [X8, X13,LSL #3]

0x439900 ADD	X3, X3, #1

0x439904 CMP	X3, X4

0x439908 B.EQ	439cec

0x43990c LDR	X20, [X15, X3,LSL #3]

0x439910 LDR	X13, [X22, X20,LSL #3]

0x439914 CMP	X13, X5

0x439918 B.GE	4398ec

0x43991c CMP	X13, X7

0x439920 B.NE	4399a0

0x439924 LDUR	X13, [X29, #496]

0x439928 LDUR	X15, [X29, #424]

0x43992c ADD	X21, X20, #1

0x439930 LDR	D4, [X13]

0x439934 LDR	X14, [X15, X20,LSL #3]

0x439938 LDUR	X13, [X29, #488]

0x43993c LDR	X16, [X15, X21,LSL #3]

0x439940 LDR	D3, [X13, X14,LSL #3]

0x439944 ADD	X2, X14, #1

0x439948 FCMP	D3, #0

0x43994c FCSEL	D3, D1, D0, #11

0x439950 CMP	X2, X16

0x439954 B.GE	4399e8

0x439958 SUB	W13, W14, W16

0x43995c TBNZ	W13, #0, 4399d8

0x439960 LDUR	X13, [X29, #440]

0x439964 LDR	X13, [X13, X2,LSL #3]

0x439968 LDR	X15, [X22, X13,LSL #3]

0x43996c CMP	X13, X27

0x439970 CCMP	X15, X5, #0, #1

0x439974 B.LT	439990

0x439978 LDUR	X13, [X29, #488]

0x43997c LDR	D5, [X13, X2,LSL #3]

0x439980 FMUL	D6, D5, D3

0x439984 FCMP	D6, #0

0x439988 B.GE	439990

0x43998c FADD	D4, D5, D4

0x439990 ADD	X18, X14, #2

0x439994 B	4399dc

0x4399a0 LDR	X13, [X10, X20,LSL #3]

0x4399a4 CMN	X13, #3

0x4399a8 B.EQ	439900

0x4399ac CMP	X25, #1

0x4399b0 B.EQ	4399c8

0x4399b4 LDR	X14, [SP, #216]

0x4399b8 LDR	X13, [X14, X27,LSL #3]

0x4399bc LDR	X14, [X14, X20,LSL #3]

0x4399c0 CMP	X13, X14

0x4399c4 B.NE	439900

0x4399c8 LDUR	X13, [X29, #488]

0x4399cc LDR	D3, [X13, X3,LSL #3]

0x4399d0 FADD	D2, D3, D2

0x4399d4 B	439900

0x4399d8 ORR	X18, XZR, X2

0x4399dc SUB	X13, X16, #2

0x4399e0 CMP	X13, X14

0x4399e4 B.NE	439a18

0x4399e8 CMP	X19, #2

0x4399ec B.LT	439ac8

0x4399f0 LDR	X15, [X26, X20,LSL #3]

0x4399f4 LDR	X13, [X26, X21,LSL #3]

0x4399f8 CMP	X13, X15

0x4399fc B.LE	439ac8

0x439a00 LDUR	X17, [X29, #360]

0x439a04 LDR	X18, [X17]

0x439a08 SUB	W17, W13, W15

0x439a0c TBNZ	W17, #0, 439a90

0x439a10 ORR	X0, XZR, X15

0x439a14 B	439abc

0x439a18 LDP	X17, X15, [X29, #880]

0x439a1c SUB	X13, X16, X18

0x439a20 ADD	X15, X15, X18,LSL #3

0x439a24 ADD	X18, X17, X18,LSL #3

0x439a28 B	439a3c

  (827) 0x439a2c ADD	X18, X18, #16

  (827) 0x439a30 SUBS	X13, X13, #2

  (827) 0x439a34 ADD	X15, X15, #16

  (827) 0x439a38 B.EQ	4399e8

  (827) 0x439a3c LDUR	X17, [X18, #504]

  (827) 0x439a40 LDR	X0, [X22, X17,LSL #3]

  (827) 0x439a44 CMP	X17, X27

  (827) 0x439a48 CCMP	X0, X5, #0, #1

  (827) 0x439a4c B.LT	439a64

  (827) 0x439a50 LDUR	D5, [X15, #504]

  (827) 0x439a54 FMUL	D6, D5, D3

  (827) 0x439a58 FCMP	D6, #0

  (827) 0x439a5c B.GE	439a64

  (827) 0x439a60 FADD	D4, D5, D4

  (827) 0x439a64 LDR	X17, [X18]

  (827) 0x439a68 LDR	X0, [X22, X17,LSL #3]

  (827) 0x439a6c CMP	X17, X27

  (827) 0x439a70 CCMP	X0, X5, #0, #1

  (827) 0x439a74 B.LT	439a2c

  (827) 0x439a78 LDR	D5, [X15]

  (827) 0x439a7c FMUL	D6, D5, D3

  (827) 0x439a80 FCMP	D6, #0

  (827) 0x439a84 B.GE	439a2c

  (827) 0x439a88 FADD	D4, D5, D4

  (827) 0x439a8c B	439a2c

0x439a90 LDR	X17, [SP, #208]

0x439a94 LDR	X17, [X17, X15,LSL #3]

0x439a98 LDR	X17, [X23, X17,LSL #3]

0x439a9c CMP	X17, X9

0x439aa0 B.LT	439ab8

0x439aa4 LDR	D5, [X18, X15,LSL #3]

0x439aa8 FMUL	D6, D5, D3

0x439aac FCMP	D6, #0

0x439ab0 B.GE	439ab8

0x439ab4 FADD	D4, D5, D4

0x439ab8 ADD	X0, X15, #1

0x439abc ADD	X15, X15, #1

0x439ac0 CMP	X13, X15

0x439ac4 B.NE	439ba0

0x439ac8 LDUR	X13, [X29, #488]

0x439acc FCMP	D4, #0

0x439ad0 LDR	D5, [X13, X3,LSL #3]

0x439ad4 B.EQ	439b94

0x439ad8 FDIV	D4, D5, D4

0x439adc CMP	X2, X16

0x439ae0 B.GE	439b5c

0x439ae4 LDUR	X13, [X29, #432]

0x439ae8 ORN	X15, XZR, X14

0x439aec ADD	X15, X15, X16

0x439af0 LDP	X16, X17, [X29, #880]

0x439af4 LDR	X13, [X13]

0x439af8 ADD	X16, X16, X14,LSL #3

0x439afc ADD	X14, X17, X14,LSL #3

0x439b00 B	439b10

  (825) 0x439b04 SUBS	X15, X15, #1

  (825) 0x439b08 ADD	X14, X14, #8

  (825) 0x439b0c B.EQ	439b5c

  (825) 0x439b10 LDR	X18, [X16], #8

  (825) 0x439b14 LDR	X0, [X22, X18,LSL #3]

  (825) 0x439b18 CMP	X0, X5

  (825) 0x439b1c B.LT	439b3c

  (825) 0x439b20 LDR	D5, [X14]

  (825) 0x439b24 FMUL	D6, D5, D3

  (825) 0x439b28 FCMP	D6, #0

  (825) 0x439b2c B.GE	439b3c

  (825) 0x439b30 LDR	D6, [X13, X0,LSL #3]

  (825) 0x439b34 FMADD	D5, D5, D4, D6

  (825) 0x439b38 STR	D5, [X13, X0,LSL #3]

  (825) 0x439b3c CMP	X18, X27

  (825) 0x439b40 B.NE	439b04

  (825) 0x439b44 LDR	D5, [X14]

  (825) 0x439b48 FMUL	D6, D5, D3

  (825) 0x439b4c FCMP	D6, #0

  (825) 0x439b50 B.GE	439b04

  (825) 0x439b54 FMADD	D2, D5, D4, D2

  (825) 0x439b58 B	439b04

0x439b5c CMP	X19, #2

0x439b60 B.LT	439c5c

0x439b64 LDR	X15, [X26, X20,LSL #3]

0x439b68 LDR	X13, [X26, X21,LSL #3]

0x439b6c CMP	X13, X15

0x439b70 B.LE	439c5c

0x439b74 LDUR	X14, [X29, #360]

0x439b78 SUB	W17, W13, W15

0x439b7c LDR	X16, [X14]

0x439b80 LDUR	X14, [X29, #400]

0x439b84 LDR	X14, [X14]

0x439b88 TBNZ	W17, #0, 439c1c

0x439b8c ORR	X18, XZR, X15

0x439b90 B	439c50

0x439b94 LDUR	X15, [X29, #440]

0x439b98 FADD	D2, D5, D2

0x439b9c B	439900

0x439ba0 LDR	X15, [SP, #200]

0x439ba4 ADD	X17, X18, X0,LSL #3

0x439ba8 SUB	X13, X13, X0

0x439bac ADD	X18, X17, #8

0x439bb0 ADD	X15, X15, X0,LSL #3

0x439bb4 B	439bd0

  (826) 0x439bc0 SUBS	X13, X13, #2

  (826) 0x439bc4 ADD	X15, X15, #16

  (826) 0x439bc8 ADD	X18, X18, #16

  (826) 0x439bcc B.EQ	439ac8

  (826) 0x439bd0 LDUR	X17, [X15, #504]

  (826) 0x439bd4 LDR	X17, [X23, X17,LSL #3]

  (826) 0x439bd8 CMP	X17, X9

  (826) 0x439bdc B.LT	439bf4

  (826) 0x439be0 LDUR	D5, [X18, #504]

  (826) 0x439be4 FMUL	D6, D5, D3

  (826) 0x439be8 FCMP	D6, #0

  (826) 0x439bec B.GE	439bf4

  (826) 0x439bf0 FADD	D4, D5, D4

  (826) 0x439bf4 LDR	X17, [X15]

  (826) 0x439bf8 LDR	X17, [X23, X17,LSL #3]

  (826) 0x439bfc CMP	X17, X9

  (826) 0x439c00 B.LT	439bc0

  (826) 0x439c04 LDR	D5, [X18]

  (826) 0x439c08 FMUL	D6, D5, D3

  (826) 0x439c0c FCMP	D6, #0

  (826) 0x439c10 B.GE	439bc0

  (826) 0x439c14 FADD	D4, D5, D4

  (826) 0x439c18 B	439bc0

0x439c1c LDR	X17, [SP, #208]

0x439c20 LDR	X17, [X17, X15,LSL #3]

0x439c24 LDR	X18, [X23, X17,LSL #3]

0x439c28 CMP	X18, X9

0x439c2c B.LT	439c4c

0x439c30 LDR	D5, [X16, X15,LSL #3]

0x439c34 FMUL	D6, D5, D3

0x439c38 FCMP	D6, #0

0x439c3c B.GE	439c4c

0x439c40 LDR	D6, [X14, X18,LSL #3]

0x439c44 FMADD	D5, D5, D4, D6

0x439c48 STR	D5, [X14, X18,LSL #3]

0x439c4c ADD	X18, X15, #1

0x439c50 ADD	X15, X15, #1

0x439c54 CMP	X13, X15

0x439c58 B.NE	439c64

0x439c5c LDUR	X15, [X29, #440]

0x439c60 B	439900

0x439c64 LDR	X15, [SP, #200]

0x439c68 ADD	X16, X16, X18,LSL #3

0x439c6c SUB	X13, X13, X18

0x439c70 ADD	X16, X16, #8

0x439c74 ADD	X15, X15, X18,LSL #3

0x439c78 B	439c90

  (824) 0x439c80 SUBS	X13, X13, #2

  (824) 0x439c84 ADD	X15, X15, #16

  (824) 0x439c88 ADD	X16, X16, #16

  (824) 0x439c8c B.EQ	439c5c

  (824) 0x439c90 LDUR	X17, [X15, #504]

  (824) 0x439c94 LDR	X18, [X23, X17,LSL #3]

  (824) 0x439c98 CMP	X18, X9

  (824) 0x439c9c B.LT	439cbc

  (824) 0x439ca0 LDUR	D5, [X16, #504]

  (824) 0x439ca4 FMUL	D6, D5, D3

  (824) 0x439ca8 FCMP	D6, #0

  (824) 0x439cac B.GE	439cbc

  (824) 0x439cb0 LDR	D6, [X14, X18,LSL #3]

  (824) 0x439cb4 FMADD	D5, D5, D4, D6

  (824) 0x439cb8 STR	D5, [X14, X18,LSL #3]

  (824) 0x439cbc LDR	X17, [X15]

  (824) 0x439cc0 LDR	X18, [X23, X17,LSL #3]

  (824) 0x439cc4 CMP	X18, X9

  (824) 0x439cc8 B.LT	439c80

  (824) 0x439ccc LDR	D5, [X16]

  (824) 0x439cd0 FMUL	D6, D5, D3

  (824) 0x439cd4 FCMP	D6, #0

  (824) 0x439cd8 B.GE	439c80

  (824) 0x439cdc LDR	D6, [X14, X18,LSL #3]

  (824) 0x439ce0 FMADD	D5, D5, D4, D6

  (824) 0x439ce4 STR	D5, [X14, X18,LSL #3]

  (824) 0x439ce8 B	439c80

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c: 1609 - 1675

--------------------------------------------------------------------------------

1609:            for (jj = A_diag_i[i]+1; jj < A_diag_i[i+1]; jj++)

1610:            { /* i1 is a c-point and strongly influences i, accumulate

1611:               * a_(i,i1) into interpolation weight */

1612:              i1 = A_diag_j[jj];

1613:              if (P_marker[i1] >= jj_begin_row)

1614:              {

1615:                P_diag_data[P_marker[i1]] += A_diag_data[jj];

1616:              }

1617:              else if(P_marker[i1] == strong_f_marker)

1618:              {

1619:                sum = zero;

1620:                sgn = 1;

1621:                if(A_diag_data[A_diag_i[i1]] < 0) sgn = -1;

1622:                /* Loop over row of A for point i1 and calculate the sum

1623:                 * of the connections to c-points that strongly influence i. */

1624:                for(jj1 = A_diag_i[i1]+1; jj1 < A_diag_i[i1+1]; jj1++)

1625:                {

1626:                  i2 = A_diag_j[jj1];

1627:                  if((P_marker[i2] >= jj_begin_row || i2 == i) && (sgn*A_diag_data[jj1]) < 0)

1628:                    sum += A_diag_data[jj1];

1629:                }

1630:                if(num_procs > 1)

1631:                {

1632:                  for(jj1 = A_offd_i[i1]; jj1< A_offd_i[i1+1]; jj1++)

1633:                  {

1634:                    i2 = A_offd_j[jj1];

1635:                    if(P_marker_offd[i2] >= jj_begin_row_offd &&

1636:                       (sgn*A_offd_data[jj1]) < 0)

1637:                       sum += A_offd_data[jj1];

1638:                  }

1639:                }

1640:                if(sum != 0)

1641:                {

1642:                  distribute = A_diag_data[jj]/sum;

1643:                  /* Loop over row of A for point i1 and do the distribution */

1644:                  for(jj1 = A_diag_i[i1]+1; jj1 < A_diag_i[i1+1]; jj1++)

1645:                  {

1646:                    i2 = A_diag_j[jj1];

1647:                    if(P_marker[i2] >= jj_begin_row && (sgn*A_diag_data[jj1]) < 0)

1648:                       P_diag_data[P_marker[i2]] +=

1649:                       distribute*A_diag_data[jj1];

1650:                        if(i2 == i && (sgn*A_diag_data[jj1]) < 0)

1651:                          diagonal += distribute*A_diag_data[jj1];

1652:                  }

1653:                  if(num_procs > 1)

1654:                  {

1655:                    for(jj1 = A_offd_i[i1]; jj1 < A_offd_i[i1+1]; jj1++)

1656:                    {

1657:                      i2 = A_offd_j[jj1];

1658:                      if(P_marker_offd[i2] >= jj_begin_row_offd &&

1659:                                 (sgn*A_offd_data[jj1]) < 0)

1660:                        P_offd_data[P_marker_offd[i2]] +=

[...]

1667:                  diagonal += A_diag_data[jj];

1668:                }

1669:              }

1670:              /* neighbor i1 weakly influences i, accumulate a_(i,i1) into

1671:               * diagonal */

1672:              else if (CF_marker[i1] != -3)

1673:              {

1674:                if(num_functions == 1 || dof_func[i] == dof_func[i1])

1675:                  diagonal += A_diag_data[jj];

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.51
CQA speedup if FP arith vectorized	1.60
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildExtPIInterp.omp_outlined
Source	par_lr_interp.c:1609-1609,par_lr_interp.c:1612-1621,par_lr_interp.c:1624-1637,par_lr_interp.c:1640-1644,par_lr_interp.c:1653-1660,par_lr_interp.c:1667-1667,par_lr_interp.c:1672-1675
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	19.25
CQA cycles if no scalar integer	7.67
CQA cycles if FP arith vectorized	12.06
CQA cycles if fully vectorized	9.63
Front-end cycles	19.25
P0 cycles	17.50
P1 cycles	17.50
P2 cycles	8.25
P3 cycles	8.25
P4 cycles	8.17
P5 cycles	8.17
P6 cycles	8.08
P7 cycles	8.08
P8 cycles	5.00
P9 cycles	4.50
P10 cycles	4.25
P11 cycles	4.25
P12 cycles	18.00
P13 cycles	18.00
P14 cycles	18.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	1.75 - 3.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	154.00
Nb uops	154.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.57
Nb FLOP add-sub	5.00
Nb FLOP mul	3.00
Nb FLOP fma	1.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.27
Bytes prefetched	0.00
Bytes loaded	432.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	2.51
CQA speedup if FP arith vectorized	1.60
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildExtPIInterp.omp_outlined
Source	par_lr_interp.c:1609-1609,par_lr_interp.c:1612-1621,par_lr_interp.c:1624-1637,par_lr_interp.c:1640-1644,par_lr_interp.c:1653-1660,par_lr_interp.c:1667-1667,par_lr_interp.c:1672-1675
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	19.25
CQA cycles if no scalar integer	7.67
CQA cycles if FP arith vectorized	12.06
CQA cycles if fully vectorized	9.63
Front-end cycles	19.25
P0 cycles	17.50
P1 cycles	17.50
P2 cycles	8.25
P3 cycles	8.25
P4 cycles	8.17
P5 cycles	8.17
P6 cycles	8.08
P7 cycles	8.08
P8 cycles	5.00
P9 cycles	4.50
P10 cycles	4.25
P11 cycles	4.25
P12 cycles	18.00
P13 cycles	18.00
P14 cycles	18.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	1.75 - 3.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	154.00
Nb uops	154.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.57
Nb FLOP add-sub	5.00
Nb FLOP mul	3.00
Nb FLOP fma	1.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.27
Bytes prefetched	0.00
Bytes loaded	432.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildExtPIInterp.omp_outlined
Source file and lines	par_lr_interp.c:1609-1675
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1609-1660,1667-1675.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1609,1612-1621,1624-1637,1640-1644,1653-1660,1667,1672-1675.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 19.25 to 7.67 cycles (2.51x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 19.25 to 9.62 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 11 FP arithmetical operations:

6: addition or subtraction (1 inside FMA instructions)
4: multiply (1 inside FMA instructions)
1: divide

The binary loop is loading 432 bytes. The binary loop is storing 16 bytes.

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	154
loop length	616
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

19.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	17.50	17.50	8.25	8.25	8.17	8.17	8.08	8.08	5.00	4.50	4.25	4.25	18.00	18.00	18.00	0.00	0.00
cycles	17.50	17.50	8.25	8.25	8.17	8.17	8.08	8.08	5.00	4.50	4.25	4.25	18.00	18.00	18.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

1.75-3.50

Cycles summary

Front-end	19.25
Overall L1	19.25

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 19.25 cycles. At this rate:

23% of peak load performance is reached (22.44 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.83 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 43990c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDUR X14, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D4, [X8, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D3, [X14, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FADD D3, D4, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
STR D3, [X8, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X3, X3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP X3, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 439cec <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x12ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X20, [X15, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X13, [X22, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X13, X5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4398ec <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0xeec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, X7	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 4399a0 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0xfa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X13, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDUR X15, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X21, X20, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D4, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR X14, [X15, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDUR X13, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X16, [X15, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D3, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X2, X14, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FCMP D3, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D3, D1, D0, #11	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.25	scal (50.0%)
CMP X2, X16	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4399e8 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0xfe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W13, W14, W16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
TBNZ W13, #0, 4399d8 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0xfd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X13, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X13, [X13, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X15, [X22, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X13, X27	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X15, X5, #0, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	1	scal (50.0%)
B.LT 439990 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0xf90>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X13, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D5, [X13, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL D6, D5, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FCMP D6, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
B.GE 439990 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0xf90>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FADD D4, D5, D4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
ADD X18, X14, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
B 4399dc <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0xfdc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X10, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMN X13, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 439900 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0xf00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4399c8 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0xfc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X13, [X14, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X14, [X14, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X13, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 439900 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0xf00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X13, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D3, [X13, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FADD D2, D3, D2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
B 439900 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0xf00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X18, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SUB X13, X16, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP X13, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 439a18 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1018>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X19, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 439ac8 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x10c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [X26, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X13, [X26, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X13, X15	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 439ac8 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x10c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X17, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X18, [X17]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
SUB W17, W13, W15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
TBNZ W17, #0, 439a90 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1090>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 439abc <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x10bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X17, X15, [X29, #880]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	N/A
SUB X13, X16, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X15, X15, X18,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X18, X17, X18,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
B 439a3c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x103c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X17, [X17, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X17, [X23, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X17, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 439ab8 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x10b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D5, [X18, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL D6, D5, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FCMP D6, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
B.GE 439ab8 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x10b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FADD D4, D5, D4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
ADD X0, X15, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X15, X15, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP X13, X15	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 439ba0 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x11a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X13, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
FCMP D4, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
LDR D5, [X13, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
B.EQ 439b94 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1194>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV D4, D5, D4	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
CMP X2, X16	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 439b5c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x115c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X13, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ORN X15, XZR, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X15, X15, X16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDP X16, X17, [X29, #880]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	N/A
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X16, X16, X14,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X14, X17, X14,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
B 439b10 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X19, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 439c5c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x125c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [X26, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X13, [X26, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X13, X15	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 439c5c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x125c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X14, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
SUB W17, W13, W15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X16, [X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDUR X14, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
TBNZ W17, #0, 439c1c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x121c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X18, XZR, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
B 439c50 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1250>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X15, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
FADD D2, D5, D2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
B 439900 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0xf00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X17, X18, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SUB X13, X13, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X18, X17, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X15, X15, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
B 439bd0 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x11d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X17, [X17, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X18, [X23, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X18, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 439c4c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x124c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D5, [X16, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL D6, D5, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FCMP D6, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
B.GE 439c4c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x124c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D6, [X14, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D5, D5, D4, D6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D5, [X14, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X18, X15, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X15, X15, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP X13, X15	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 439c64 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1264>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X15, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
B 439900 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0xf00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X16, X16, X18,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SUB X13, X13, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X16, X16, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X15, X15, X18,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
B 439c90 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1290>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_BoomerAMGBuildExtPIInterp.omp_outlined
Source file and lines	par_lr_interp.c:1609-1675
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 19.25 to 7.67 cycles (2.51x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 11 FP arithmetical operations:

6: addition or subtraction (1 inside FMA instructions)
4: multiply (1 inside FMA instructions)
1: divide

The binary loop is loading 432 bytes. The binary loop is storing 16 bytes.

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	154
loop length	616
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

19.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	17.50	17.50	8.25	8.25	8.17	8.17	8.08	8.08	5.00	4.50	4.25	4.25	18.00	18.00	18.00	0.00	0.00
cycles	17.50	17.50	8.25	8.25	8.17	8.17	8.08	8.08	5.00	4.50	4.25	4.25	18.00	18.00	18.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

1.75-3.50

Cycles summary

Front-end	19.25
Overall L1	19.25

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 19.25 cycles. At this rate:

23% of peak load performance is reached (22.44 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.83 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 43990c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDUR X14, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D4, [X8, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D3, [X14, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FADD D3, D4, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
STR D3, [X8, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X3, X3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP X3, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 439cec <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x12ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X20, [X15, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X13, [X22, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X13, X5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4398ec <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0xeec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, X7	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 4399a0 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0xfa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X13, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDUR X15, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X21, X20, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D4, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR X14, [X15, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDUR X13, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X16, [X15, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D3, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X2, X14, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FCMP D3, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D3, D1, D0, #11	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.25	scal (50.0%)
CMP X2, X16	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4399e8 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0xfe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W13, W14, W16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
TBNZ W13, #0, 4399d8 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0xfd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X13, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X13, [X13, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X15, [X22, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X13, X27	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X15, X5, #0, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	1	scal (50.0%)
B.LT 439990 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0xf90>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X13, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D5, [X13, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL D6, D5, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FCMP D6, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
B.GE 439990 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0xf90>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FADD D4, D5, D4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
ADD X18, X14, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
B 4399dc <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0xfdc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X10, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMN X13, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 439900 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0xf00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4399c8 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0xfc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X13, [X14, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X14, [X14, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X13, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 439900 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0xf00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X13, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D3, [X13, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FADD D2, D3, D2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
B 439900 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0xf00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X18, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SUB X13, X16, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP X13, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 439a18 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1018>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X19, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 439ac8 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x10c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [X26, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X13, [X26, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X13, X15	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 439ac8 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x10c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X17, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X18, [X17]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
SUB W17, W13, W15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
TBNZ W17, #0, 439a90 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1090>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 439abc <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x10bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X17, X15, [X29, #880]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	N/A
SUB X13, X16, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X15, X15, X18,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X18, X17, X18,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
B 439a3c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x103c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X17, [X17, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X17, [X23, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X17, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 439ab8 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x10b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D5, [X18, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL D6, D5, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FCMP D6, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
B.GE 439ab8 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x10b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FADD D4, D5, D4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
ADD X0, X15, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X15, X15, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP X13, X15	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 439ba0 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x11a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X13, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
FCMP D4, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
LDR D5, [X13, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
B.EQ 439b94 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1194>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV D4, D5, D4	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
CMP X2, X16	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 439b5c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x115c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X13, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ORN X15, XZR, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X15, X15, X16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDP X16, X17, [X29, #880]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	N/A
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X16, X16, X14,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X14, X17, X14,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
B 439b10 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X19, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 439c5c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x125c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [X26, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X13, [X26, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X13, X15	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 439c5c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x125c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X14, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
SUB W17, W13, W15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X16, [X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDUR X14, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
TBNZ W17, #0, 439c1c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x121c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X18, XZR, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
B 439c50 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1250>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X15, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
FADD D2, D5, D2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
B 439900 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0xf00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X17, X18, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SUB X13, X13, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X18, X17, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X15, X15, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
B 439bd0 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x11d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X17, [X17, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X18, [X23, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X18, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 439c4c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x124c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D5, [X16, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL D6, D5, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FCMP D6, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
B.GE 439c4c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x124c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D6, [X14, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D5, D5, D4, D6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D5, [X14, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X18, X15, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X15, X15, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP X13, X15	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 439c64 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1264>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X15, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
B 439900 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0xf00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X16, X16, X18,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SUB X13, X13, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X16, X16, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X15, X15, X18,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
B 439c90 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1290>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

▶Scalability Runs Description

Run 1x1	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_NUM_THREADS: 1OMP_PLACES: threads
Run 1x2	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 2OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x4	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 4OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x8	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 8OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x16	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 16OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x24	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 24OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x32	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 32OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x40	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 40OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x48	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 48OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x56	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 56OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x64	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 64OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x72	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 72OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x80	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 80OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x88	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 88OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x96	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 96OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads

(1x1) Efficiency	(1x1) Potential Speed-Up (%)	(1x2) Efficiency	(1x2) Potential Speed-Up (%)	(1x4) Efficiency	(1x4) Potential Speed-Up (%)	(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x16) Efficiency	(1x16) Potential Speed-Up (%)	(1x24) Efficiency	(1x24) Potential Speed-Up (%)	(1x32) Efficiency	(1x32) Potential Speed-Up (%)	(1x40) Efficiency	(1x40) Potential Speed-Up (%)	(1x48) Efficiency	(1x48) Potential Speed-Up (%)	(1x56) Efficiency	(1x56) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)	(1x72) Efficiency	(1x72) Potential Speed-Up (%)	(1x80) Efficiency	(1x80) Potential Speed-Up (%)	(1x88) Efficiency	(1x88) Potential Speed-Up (%)	(1x96) Efficiency	(1x96) Potential Speed-Up (%)
1	0	1.83	0	3.07	0	5.72	0	9.67	0	12.48	0	17.32	0	20.4	0	22.62	0	32.44	0	32.74	0	34.36	0	47.57	0	39.18	0	51.37	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x1	1	1	1	1	0.46499988436699	0.17479299008846
1x2	2	1.83	1.83	2	0.25500002503395	0.18003278970718
1x4	4	3.07	3.07	4	0.17999997735023	0.20040813088417
1x8	8	5.72	5.72	8	0.1000000089407	0.18434873223305
1x16	16	9.67	9.67	16	0.064999990165234	0.16697509586811
1x24	24	12.48	12.48	24	0.059999991208315	0.15046048164368
1x32	32	17.32	17.32	32	0.03999999910593	0.11829150468111
1x40	40	20.4	20.4	40	0.03999999910593	0.094464056193829
1x48	47	22.62	22.62	48	0.03999999538064	0.092759072780609
1x56	55	32.44	32.44	56	0.025000000372529	0.071147277951241
1x64	62	32.74	32.74	64	0.030000001192093	0.072930112481117
1x72	67	34.36	34.36	72	0.025000000372529	0.069572739303112
1x80	72	47.57	47.57	80	0.019999999552965	0.054604969918728
1x88	72	39.18	39.18	88	0.029999999329448	0.060498509556055
1x96	76	51.37	51.37	96	0.019999999552965	0.046339392662048

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency