OV - exec - Loop 679

0x433320 LDUR	X10, [X29, #472]

0x433324 ADD	X18, X18, #1

0x433328 CMP	X18, X10

0x43332c B.GE	433550

0x433330 LDUR	X10, [X29, #440]

0x433334 LDR	X1, [X10, X18,LSL #3]

0x433338 STR	X8, [X11, X1,LSL #3]

0x43333c STR	X9, [X12, X1,LSL #3]

0x433340 ADD	X2, X1, #1

0x433344 LDR	X3, [X13, X1,LSL #3]

0x433348 LDR	X10, [X13, X2,LSL #3]

0x43334c CMP	X3, X10

0x433350 B.GE	433460

0x433354 LDUR	X10, [X29, #480]

0x433358 LDR	X4, [X10]

0x43335c LDR	X10, [X19]

0x433360 SUB	X5, X10, #8

0x433364 LDUR	X10, [X29, #488]

0x433368 LDR	X6, [X10]

0x43336c LDUR	X10, [X29, #496]

0x433370 LDR	X10, [X10]

0x433374 SUB	X7, X10, #8

0x433378 B	433390

  (683) 0x433380 LDR	X10, [X13, X2,LSL #3]

  (683) 0x433384 ADD	X3, X3, #1

  (683) 0x433388 CMP	X3, X10

  (683) 0x43338c B.GE	433460

  (683) 0x433390 LDR	X10, [X14, X3,LSL #3]

  (683) 0x433394 LDR	X25, [X21]

  (683) 0x433398 LDR	X20, [X15, X10,LSL #3]

  (683) 0x43339c SUB	X25, X25, #1

  (683) 0x4333a0 CMP	X20, X25

  (683) 0x4333a4 B.NE	433380

  (683) 0x4333a8 ADD	X26, X10, #1

  (683) 0x4333ac LDR	X20, [X4, X26,LSL #3]

  (683) 0x4333b0 CMP	X20, #1

  (683) 0x4333b4 B.LT	433400

  (683) 0x4333b8 LDR	X25, [X11, X10,LSL #3]

  (683) 0x4333bc ADD	X30, X20, X25

  (683) 0x4333c0 B	4333d0

    (685) 0x4333c4 ADD	X25, X25, #1

    (685) 0x4333c8 CMP	X25, X30

    (685) 0x4333cc B.GE	433400

    (685) 0x4333d0 LDR	X20, [X21]

    (685) 0x4333d4 LDR	X20, [X5, X20,LSL #3]

    (685) 0x4333d8 LDR	X28, [X20, X25,LSL #3]

    (685) 0x4333dc LDR	X20, [X22, X28,LSL #3]

    (685) 0x4333e0 CMP	X20, X1

    (685) 0x4333e4 B.EQ	4333c4

    (685) 0x4333e8 LDR	X20, [X4, X2,LSL #3]

    (685) 0x4333ec ADD	X8, X8, #1

    (685) 0x4333f0 ADD	X20, X20, #1

    (685) 0x4333f4 STR	X20, [X4, X2,LSL #3]

    (685) 0x4333f8 STR	X1, [X22, X28,LSL #3]

    (685) 0x4333fc B	4333c4

  (683) 0x433400 LDR	X20, [X6, X26,LSL #3]

  (683) 0x433404 CMP	X20, #1

  (683) 0x433408 B.LT	433380

  (683) 0x43340c LDR	X10, [X12, X10,LSL #3]

  (683) 0x433410 ADD	X25, X20, X10

  (683) 0x433414 B	43342c

    (684) 0x433420 ADD	X10, X10, #1

    (684) 0x433424 CMP	X10, X25

    (684) 0x433428 B.GE	433380

    (684) 0x43342c LDR	X20, [X21]

    (684) 0x433430 LDR	X20, [X7, X20,LSL #3]

    (684) 0x433434 LDR	X26, [X20, X10,LSL #3]

    (684) 0x433438 LDR	X20, [X23, X26,LSL #3]

    (684) 0x43343c CMP	X20, X1

    (684) 0x433440 B.EQ	433420

    (684) 0x433444 LDR	X20, [X6, X2,LSL #3]

    (684) 0x433448 ADD	X9, X9, #1

    (684) 0x43344c ADD	X20, X20, #1

    (684) 0x433450 STR	X20, [X6, X2,LSL #3]

    (684) 0x433454 STR	X1, [X23, X26,LSL #3]

    (684) 0x433458 B	433420

0x433460 LDR	X3, [X16, X1,LSL #3]

0x433464 LDR	X10, [X16, X2,LSL #3]

0x433468 CMP	X3, X10

0x43346c B.GE	433320

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 939 - 976

--------------------------------------------------------------------------------

939:           for (i=thread_start; i < thread_stop; i++)

940:           {

941:              i1 = pass_array[i];

942:              P_diag_start[i1] = cnt_nz;

943:              P_offd_start[i1] = cnt_nz_offd;

944:              for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

945:              {

946:                 j1 = S_diag_j[j];

947:                 if (assigned[j1] == pass-1)

948:                 {

949:                    j_start = P_diag_start[j1];

950:                    j_end = j_start+P_diag_i[j1+1];

951:                    for (k=j_start; k < j_end; k++)

952:                    {

953:                       k1 = P_diag_pass[pass-1][k];

954:                       if (P_marker[k1] != i1)

955:                       {

956:                          cnt_nz++;

957:                          P_diag_i[i1+1]++;

958:                          P_marker[k1] = i1;

959:                       }

960:                    }

961:                    j_start = P_offd_start[j1];

962:                    j_end = j_start+P_offd_i[j1+1];

963:                    for (k=j_start; k < j_end; k++)

964:                    {

965:                       k1 = P_offd_pass[pass-1][k];

966:                       if (P_marker_offd[k1] != i1)

967:                       {

968:                          cnt_nz_offd++;

969:                          P_offd_i[i1+1]++;

970:                          P_marker_offd[k1] = i1;

[...]

976:              for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.58
Bottlenecks	P12, P13, P14,
Function	hypre_BoomerAMGBuildMultipass.omp_outlined.10
Source	par_multi_interp.c:939-944,par_multi_interp.c:976-976
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.33
CQA cycles if no scalar integer	5.33
CQA cycles if FP arith vectorized	5.33
CQA cycles if fully vectorized	2.67
Front-end cycles	3.38
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	1.25
P3 cycles	1.25
P4 cycles	1.17
P5 cycles	1.17
P6 cycles	1.08
P7 cycles	1.08
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	5.33
P13 cycles	5.33
P14 cycles	5.33
P15 cycles	1.00
P16 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	27.00
Nb uops	27.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	112.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.58
Bottlenecks	P12, P13, P14,
Function	hypre_BoomerAMGBuildMultipass.omp_outlined.10
Source	par_multi_interp.c:939-944,par_multi_interp.c:976-976
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.33
CQA cycles if no scalar integer	5.33
CQA cycles if FP arith vectorized	5.33
CQA cycles if fully vectorized	2.67
Front-end cycles	3.38
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	1.25
P3 cycles	1.25
P4 cycles	1.17
P5 cycles	1.17
P6 cycles	1.08
P7 cycles	1.08
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	5.33
P13 cycles	5.33
P14 cycles	5.33
P15 cycles	1.00
P16 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	27.00
Nb uops	27.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	112.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass.omp_outlined.10
Source file and lines	par_multi_interp.c:939-976
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:939-970,976.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:939-944,976.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 5.33 to 2.67 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 112 bytes. The binary loop is storing 16 bytes.

General properties

nb instructions	27
loop length	108
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.00	2.00	1.25	1.25	1.17	1.17	1.08	1.08	0.00	0.00	0.00	0.00	5.33	5.33	5.33	1.00	1.00
cycles	2.00	2.00	1.25	1.25	1.17	1.17	1.08	1.08	0.00	0.00	0.00	0.00	5.33	5.33	5.33	1.00	1.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.38
Overall L1	5.33

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.33 cycles. At this rate:

21% of peak load performance is reached (21.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 433320

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDUR X10, [X29, #472]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X18, X18, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CMP X18, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 433550 <hypre_BoomerAMGBuildMultipass.omp_outlined.10+0x4a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X10, [X29, #440]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X10, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [X11, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X9, [X12, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X2, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X3, [X13, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X13, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X3, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 433460 <hypre_BoomerAMGBuildMultipass.omp_outlined.10+0x3b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X10, [X29, #480]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X10]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X10, [X19]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X5, X10, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
LDUR X10, [X29, #488]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X10]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X10, [X29, #496]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X7, X10, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
B 433390 <hypre_BoomerAMGBuildMultipass.omp_outlined.10+0x2e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [X16, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X16, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X3, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.GE 433320 <hypre_BoomerAMGBuildMultipass.omp_outlined.10+0x270>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_BoomerAMGBuildMultipass.omp_outlined.10
Source file and lines	par_multi_interp.c:939-976
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:939-970,976.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:939-944,976.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 5.33 to 2.67 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 112 bytes. The binary loop is storing 16 bytes.

General properties

nb instructions	27
loop length	108
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.00	2.00	1.25	1.25	1.17	1.17	1.08	1.08	0.00	0.00	0.00	0.00	5.33	5.33	5.33	1.00	1.00
cycles	2.00	2.00	1.25	1.25	1.17	1.17	1.08	1.08	0.00	0.00	0.00	0.00	5.33	5.33	5.33	1.00	1.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.38
Overall L1	5.33

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.33 cycles. At this rate:

21% of peak load performance is reached (21.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 433320

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDUR X10, [X29, #472]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X18, X18, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CMP X18, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 433550 <hypre_BoomerAMGBuildMultipass.omp_outlined.10+0x4a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X10, [X29, #440]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X10, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [X11, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X9, [X12, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X2, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X3, [X13, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X13, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X3, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 433460 <hypre_BoomerAMGBuildMultipass.omp_outlined.10+0x3b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X10, [X29, #480]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X10]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X10, [X19]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X5, X10, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
LDUR X10, [X29, #488]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X10]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X10, [X29, #496]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X7, X10, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
B 433390 <hypre_BoomerAMGBuildMultipass.omp_outlined.10+0x2e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [X16, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X16, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X3, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.GE 433320 <hypre_BoomerAMGBuildMultipass.omp_outlined.10+0x270>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

▶Scalability Runs Description

Run 1x1	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_NUM_THREADS: 1OMP_PLACES: threads
Run 1x2	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 2OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x4	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 4OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x8	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 8OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x16	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 16OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x24	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 24OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x32	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 32OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x40	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 40OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x48	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 48OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x56	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 56OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x64	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 64OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x72	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 72OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x80	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 80OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x88	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 88OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x96	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 96OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads

(1x1) Efficiency	(1x1) Potential Speed-Up (%)	(1x2) Efficiency	(1x2) Potential Speed-Up (%)	(1x4) Efficiency	(1x4) Potential Speed-Up (%)	(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x16) Efficiency	(1x16) Potential Speed-Up (%)	(1x24) Efficiency	(1x24) Potential Speed-Up (%)	(1x32) Efficiency	(1x32) Potential Speed-Up (%)	(1x40) Efficiency	(1x40) Potential Speed-Up (%)	(1x48) Efficiency	(1x48) Potential Speed-Up (%)	(1x56) Efficiency	(1x56) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)	(1x72) Efficiency	(1x72) Potential Speed-Up (%)	(1x80) Efficiency	(1x80) Potential Speed-Up (%)	(1x88) Efficiency	(1x88) Potential Speed-Up (%)	(1x96) Efficiency	(1x96) Potential Speed-Up (%)
1	0	1.94	0	3.14	0	6.22	0	12.06	0	15.78	0	24.58	0	27.58	0	29.23	0	28.28	0	30.98	0	32.92	0	34.51	0	32.76	0	36.45	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x1	1	1	1	1	0.43999993801117	0.16539552807808
1x2	2	1.94	1.94	2	0.2250000089407	0.16042523086071
1x4	4	3.14	3.14	4	0.15499998629093	0.18512277305126
1x8	8	6.22	6.22	8	0.094999998807907	0.16036838293076
1x16	16	12.06	12.06	16	0.054999995976686	0.12671159207821
1x24	24	15.78	15.78	24	0.054999995976686	0.11260879039764
1x32	31	24.58	24.58	32	0.029999999329448	0.078860998153687
1x40	37	27.58	27.58	40	0.030000001192093	0.066124834120274
1x48	44	29.23	29.23	48	0.029999995604157	0.067912898957729
1x56	51	28.28	28.28	56	0.03999999910593	0.077245607972145
1x64	61	30.98	30.98	64	0.034999992698431	0.072930112481117
1x72	66	32.92	32.92	72	0.035000003874302	0.068719089031219
1x80	72	34.51	34.51	80	0.034999996423721	0.071223869919777
1x88	78	32.76	32.76	88	0.030000001192093	0.068468376994133
1x96	80	36.45	36.45	96	0.029999995604157	0.061785858124495

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency