OV - exec - Loop 3354

0x496f20 ORR	X21, XZR, X9

0x496f24 ORR	X26, XZR, X8

0x496f28 LDUR	X8, [X29, #456]

0x496f2c LDR	X8, [X8]

0x496f30 LDP	X9, X8, [X8, #56]

0x496f34 STR	X21, [X9, X6,LSL #3]

0x496f38 STR	X26, [X8, X6,LSL #3]

0x496f3c LDUR	X21, [X29, #392]

0x496f40 LDP	X26, X4, [SP, #120]

0x496f44 ADD	X30, X30, #1

0x496f48 CMP	X30, X7

0x496f4c B.GE	497620

0x496f50 LDR	X8, [X23]

0x496f54 LDUR	X9, [X29, #464]

0x496f58 LDR	X25, [X8, X30,LSL #3]

0x496f5c LDR	X8, [X21]

0x496f60 LDR	X9, [X9]

0x496f64 LDR	X20, [X8, X30,LSL #3]

0x496f68 LDR	X8, [X28]

0x496f6c ADD	X8, X8, X9,LSL #3

0x496f70 LDR	X9, [X8]

0x496f74 SUBS	X6, X25, X9

0x496f78 B.LT	49700c

0x496f7c LDR	X8, [X8, #8]

0x496f80 CMP	X25, X8

0x496f84 B.GE	49700c

0x496f88 LDR	X8, [SP, #112]

0x496f8c STUR	X6, [X29, #496]

0x496f90 LDR	X8, [X8]

0x496f94 CBZ	X8, 497134

0x49700c LDUR	X8, [X29, #456]

0x497010 LDR	X12, [X26]

0x497014 ADD	X24, X20, X24

0x497018 LDR	X8, [X8]

0x49701c CMP	X8, #0

0x497020 CCMP	X12, #1, #8, #1

0x497024 B.LT	496f44

0x497028 LDUR	X10, [X29, #440]

0x49702c ORR	X8, XZR, XZR

0x497030 ORR	X9, XZR, XZR

0x497034 LDR	X10, [X10]

0x497038 B	497054

  (3355) 0x497040 LDR	X12, [X26]

  (3355) 0x497044 ADD	X8, X11, X8

  (3355) 0x497048 ADD	X9, X9, #2

  (3355) 0x49704c CMP	X9, X12

  (3355) 0x497050 B.GE	496f44

  (3355) 0x497054 ADD	X13, X10, X9,LSL #3

  (3355) 0x497058 LDP	X13, X11, [X13]

  (3355) 0x49705c CMP	X13, X25

  (3355) 0x497060 CCMP	X20, #1, #8, #0

  (3355) 0x497064 B.LT	497044

  (3355) 0x497068 LDR	X13, [X4]

  (3355) 0x49706c LDR	X14, [X5]

  (3355) 0x497070 AND	X15, X11, #8063

  (3355) 0x497074 ORR	X12, XZR, XZR

  (3355) 0x497078 ADD	X16, X13, X8,LSL #3

  (3355) 0x49707c ADD	X16, X16, #8

  (3355) 0x497080 B	497090

    (3356) 0x497084 ADD	X12, X12, #1

    (3356) 0x497088 CMP	X12, X20

    (3356) 0x49708c B.EQ	497040

    (3356) 0x497090 CMP	X11, #1

    (3356) 0x497094 B.LT	497084

    (3356) 0x497098 LDR	X17, [X19]

    (3356) 0x49709c ORR	X18, XZR, X8

    (3356) 0x4970a0 B.NE	4970cc

    (3356) 0x4970a4 TBZ	W11, #0, 497084

    (3356) 0x4970a8 LDR	X0, [X13, X18,LSL #3]

    (3356) 0x4970ac LDR	X1, [X14, X12,LSL #3]

    (3356) 0x4970b0 CMP	X0, X1

    (3356) 0x4970b4 B.NE	497084

    (3356) 0x4970b8 STR	X27, [X13, X18,LSL #3]

    (3356) 0x4970bc LDR	X18, [X17, X22,LSL #3]

    (3356) 0x4970c0 ADD	X18, X18, #1

    (3356) 0x4970c4 STR	X18, [X17, X22,LSL #3]

    (3356) 0x4970c8 B	497084

    (3356) 0x4970cc ORR	X0, XZR, X15

    (3356) 0x4970d0 ORR	X1, XZR, X16

    (3356) 0x4970d4 ORR	X18, XZR, X8

    (3356) 0x4970d8 B	4970f0

      (3357) 0x4970e0 ADD	X18, X18, #2

      (3357) 0x4970e4 ADD	X1, X1, #16

      (3357) 0x4970e8 SUBS	X0, X0, #2

      (3357) 0x4970ec B.EQ	4970a4

      (3357) 0x4970f0 LDUR	X2, [X1, #504]

      (3357) 0x4970f4 LDR	X3, [X14, X12,LSL #3]

      (3357) 0x4970f8 CMP	X2, X3

      (3357) 0x4970fc B.NE	497110

      (3357) 0x497100 STUR	X27, [X1, #504]

      (3357) 0x497104 LDR	X2, [X17, X22,LSL #3]

      (3357) 0x497108 ADD	X2, X2, #1

      (3357) 0x49710c STR	X2, [X17, X22,LSL #3]

      (3357) 0x497110 LDR	X2, [X1]

      (3357) 0x497114 LDR	X3, [X14, X12,LSL #3]

      (3357) 0x497118 CMP	X2, X3

      (3357) 0x49711c B.NE	4970e0

      (3357) 0x497120 STR	X27, [X1]

      (3357) 0x497124 LDR	X2, [X17, X22,LSL #3]

      (3357) 0x497128 ADD	X2, X2, #1

      (3357) 0x49712c STR	X2, [X17, X22,LSL #3]

      (3357) 0x497130 B	4970e0

0x497134 LDUR	X8, [X29, #456]

0x497138 UBFM	X12, X6, #61, #60

0x49713c LDR	X8, [X8]

0x497140 LDP	X10, X9, [X8, #56]

0x497144 LDR	X8, [X9, X12]

0x497148 LDR	X9, [X10, X12]

0x49714c CMP	X20, #1

0x497150 B.LT	496f20

0x497154 LDP	X11, X13, [SP, #24]

0x497158 LDP	X16, X18, [SP, #56]

0x49715c LDR	X17, [SP, #80]

0x497160 ADD	X14, X12, #8

0x497164 ORR	X10, XZR, XZR

0x497168 ORR	X26, XZR, X8

0x49716c ORR	X21, XZR, X9

0x497170 LDP	X0, X1, [SP, #40]

0x497174 LDR	X15, [X5]

0x497178 LDR	X11, [X11]

0x49717c LDR	X13, [X13]

0x497180 LDR	X16, [X16]

0x497184 LDR	X17, [X17]

0x497188 LDR	X18, [X18]

0x49718c LDR	X0, [X0]

0x497190 LDR	X1, [X1]

0x497194 LDR	X12, [X11, X14]

0x497198 LDR	X14, [X13, X14]

0x49719c B	4971bc

  (3358) 0x4971a0 LDR	D0, [X17, X24,LSL #3]

  (3358) 0x4971a4 STR	D0, [X4]

  (3358) 0x4971a8 LDP	X5, X6, [X29, #1000]

  (3358) 0x4971ac ADD	X24, X24, #1

  (3358) 0x4971b0 ADD	X10, X10, #1

  (3358) 0x4971b4 CMP	X10, X20

  (3358) 0x4971b8 B.EQ	496f28

  (3358) 0x4971bc LDP	X3, X4, [X29, #984]

  (3358) 0x4971c0 LDR	X2, [X15, X24,LSL #3]

  (3358) 0x4971c4 LDR	X3, [X3]

  (3358) 0x4971c8 LDR	X4, [X4]

  (3358) 0x4971cc CMP	X2, X3

  (3358) 0x4971d0 CCMP	X2, X4, #0, #10

  (3358) 0x4971d4 B.LE	497220

  (3358) 0x4971d8 LDR	X5, [X13, X6,LSL #3]

  (3358) 0x4971dc SUBS	X3, X8, X5

  (3358) 0x4971e0 B.LE	497204

  (3358) 0x4971e4 ADD	X4, X1, X5,LSL #3

  (3358) 0x4971e8 ADD	X5, X0, X5,LSL #3

    (3360) 0x4971ec LDR	X6, [X5], #8

    (3360) 0x4971f0 CMP	X6, X2

    (3360) 0x4971f4 B.EQ	4971a0

    (3360) 0x4971f8 ADD	X4, X4, #8

    (3360) 0x4971fc SUBS	X3, X3, #1

    (3360) 0x497200 B.NE	4971ec

  (3358) 0x497204 CMP	X26, X14

  (3358) 0x497208 B.GE	4974e0

  (3358) 0x49720c LDR	D0, [X17, X24,LSL #3]

  (3358) 0x497210 STR	X2, [X0, X26,LSL #3]

  (3358) 0x497214 STR	D0, [X1, X26,LSL #3]

  (3358) 0x497218 ADD	X26, X26, #1

  (3358) 0x49721c B	4971a8

  (3358) 0x497220 LDR	X5, [X11, X6,LSL #3]

  (3358) 0x497224 SUBS	X3, X9, X5

  (3358) 0x497228 B.LE	497258

  (3358) 0x49722c ADD	X4, X18, X5,LSL #3

  (3358) 0x497230 ADD	X5, X16, X5,LSL #3

  (3358) 0x497234 HINT	#0

  (3358) 0x497238 HINT	#0

  (3358) 0x49723c HINT	#0

    (3359) 0x497240 LDR	X6, [X5], #8

    (3359) 0x497244 CMP	X6, X2

    (3359) 0x497248 B.EQ	4971a0

    (3359) 0x49724c ADD	X4, X4, #8

    (3359) 0x497250 SUBS	X3, X3, #1

    (3359) 0x497254 B.NE	497240

  (3358) 0x497258 CMP	X21, X12

  (3358) 0x49725c B.GE	497510

  (3358) 0x497260 LDR	D0, [X17, X24,LSL #3]

  (3358) 0x497264 STR	X2, [X16, X21,LSL #3]

  (3358) 0x497268 STR	D0, [X18, X21,LSL #3]

  (3358) 0x49726c ADD	X21, X21, #1

  (3358) 0x497270 B	4971a8

0x4974e0 ADRP	X0,

0x4974e4 ADD	X0, X0, #1111

0x4974e8 MOVZ	W1, #3406

0x4974ec MOVZ	W2, #1

0x4974f0 ORR	X20, XZR, X30

0x4974f4 ORR	X3, XZR, XZR

0x4974f8 BL	4a9360

0x4974fc LDR	X8, [SP, #8]

0x497500 MOVZ	W9, #1

0x497504 ADRP	X0,

0x497508 ADD	X0, X0, #1452

0x49750c B	49753c

0x497510 ADRP	X0,

0x497514 ADD	X0, X0, #1111

0x497518 MOVZ	W1, #3440

0x49751c MOVZ	W2, #1

0x497520 ORR	X20, XZR, X30

0x497524 ORR	X3, XZR, XZR

0x497528 BL	4a9360

0x49752c LDR	X8, [SP, #8]

0x497530 MOVZ	W9, #1

0x497534 ADRP	X0,

0x497538 ADD	X0, X0, #1490

0x49753c LDADD	X9, X8, [X8]

0x497540 LDR	X8, [SP, #16]

0x497544 LDR	X8, [X8]

0x497548 CBZ	X8, 497554

0x49754c ORR	X1, XZR, X25

0x497550 BL	4a6ee0

0x497554 LDUR	X7, [X29, #416]

0x497558 LDP	X5, X6, [X29, #1000]

0x49755c ORR	X30, XZR, X20

0x497560 B	496f28

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c: 3291 - 3484

--------------------------------------------------------------------------------

3291:          for (ii=ns; ii < ne; ii++)

3292:          {

3293:             row = rows[ii];

3294:             n = ncols[ii];

3295:             /* processor owns the row */

3296:             if (row >= row_partitioning[pstart] && row < row_partitioning[pstart+1])

3297:             {

3298:                row_local = row - row_partitioning[pstart];

3299:                /* compute local row number */

3300:                if (need_aux)

[...]

3311:       	             tmp_data = hypre_CTAlloc(HYPRE_Complex,size);

[...]

3376: 	          offd_indx = hypre_AuxParCSRMatrixIndxOffd(aux_matrix)[row_local];

3377: 	          diag_indx = hypre_AuxParCSRMatrixIndxDiag(aux_matrix)[row_local];

[...]

3383:   	          for (i=0; i < n; i++)

3384: 	          {

3385: 	             if (cols[indx] < col_0 || cols[indx] > col_n)

3386:                      /* insert into offd */

3387: 	             {

3388: 	                for (j=offd_i[row_local]; j < offd_indx; j++)

3389: 	                {

3390: 		           if (offd_j[j] == cols[indx])

[...]

3399: 	                   if (cnt_offd < offd_space)

3400: 	                   {

3401: 	                      offd_j[cnt_offd] = cols[indx];

3402: 	                      offd_data[cnt_offd++] = values[indx];

3403: 	                   }

3404: 	                   else

3405: 	 	           {

3406:                               hypre_error(HYPRE_ERROR_GENERIC);

3407: #ifdef HYPRE_USING_OPENMP

3408: #pragma omp atomic

3409: #endif

3410:                               error_flag++;

[...]

3417: 	                }

3418: 	                not_found = 1;

3419: 	             }

3420: 	             else  /* insert into diag */

3421: 	             {

3422: 	                for (j=diag_i[row_local]; j < diag_indx; j++)

3423: 	                {

3424: 		           if (diag_j[j] == cols[indx])

[...]

3433: 	                   if (cnt_diag < diag_space)

3434: 	                   {

3435: 	                      diag_j[cnt_diag] = cols[indx];

3436: 	                      diag_data[cnt_diag++] = values[indx];

3437: 	                   }

3438: 	                   else

3439: 	 	           {

3440:                               hypre_error(HYPRE_ERROR_GENERIC);

3441: #ifdef HYPRE_USING_OPENMP

3442: #pragma omp atomic

3443: #endif

3444:                               error_flag++;

[...]

3454: 	             indx++;

3455: 	          }

3456:

3457:                   hypre_AuxParCSRMatrixIndxDiag(aux_matrix)[row_local] = cnt_diag;

3458:                   hypre_AuxParCSRMatrixIndxOffd(aux_matrix)[row_local] = cnt_offd;

[...]

3466:                indx +=  n;

3467:    	       if (aux_matrix)

3468:                {

3469:                   col_indx = 0;

3470:                   for (i=0; i < off_proc_i_indx; i=i+2)

3471:                   {

3472: 	             row_len = off_proc_i[i+1];

3473: 	             if (off_proc_i[i] == row)

3474: 		     {

3475: 		        for (j=0; j < n; j++)

3476: 		        {

3477: 			   cnt1 = col_indx;

3478: 			   for (k=0; k < row_len; k++)

3479: 			   {

3480: 			      if (off_proc_j[cnt1] == cols[j])

3481: 			      {

3482:                                  off_proc_j[cnt1++] = -1;

3483:                		         /*cancel_indx++;*/

3484: 	                         offproc_cnt[my_thread_num]++;

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.54
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.01
Bottlenecks	P12,
Function	hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15
Source	IJMatrix_parcsr.c:3291-3296,IJMatrix_parcsr.c:3300-3300,IJMatrix_parcsr.c:3311-3311,IJMatrix_parcsr.c:3376-3377,IJMatrix_parcsr.c:3383-3383,IJMatrix_parcsr.c:3406-3406,IJMatrix_parcsr.c:3410-3410,IJMatrix_parcsr.c:3440-3440,IJMatrix_parcsr.c:3444-3444,IJMatrix_parcsr.c:3457-3458,IJMatrix_parcsr.c:3466-3467,IJMatrix_parcsr.c:3484-3484
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.50
CQA cycles if no scalar integer	16.50
CQA cycles if FP arith vectorized	16.50
CQA cycles if fully vectorized	4.67
Front-end cycles	12.63
P0 cycles	7.00
P1 cycles	7.00
P2 cycles	6.92
P3 cycles	6.92
P4 cycles	6.83
P5 cycles	6.83
P6 cycles	6.75
P7 cycles	6.75
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	16.50
P13 cycles	16.17
P14 cycles	16.33
P15 cycles	1.50
P16 cycles	1.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	102.00
Nb uops	101.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	28.12
Bytes prefetched	0.00
Bytes loaded	432.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	47.37
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	45.45

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.54
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.01
Bottlenecks	P12,
Function	hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15
Source	IJMatrix_parcsr.c:3291-3296,IJMatrix_parcsr.c:3300-3300,IJMatrix_parcsr.c:3311-3311,IJMatrix_parcsr.c:3376-3377,IJMatrix_parcsr.c:3383-3383,IJMatrix_parcsr.c:3406-3406,IJMatrix_parcsr.c:3410-3410,IJMatrix_parcsr.c:3440-3440,IJMatrix_parcsr.c:3444-3444,IJMatrix_parcsr.c:3457-3458,IJMatrix_parcsr.c:3466-3467,IJMatrix_parcsr.c:3484-3484
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.50
CQA cycles if no scalar integer	16.50
CQA cycles if FP arith vectorized	16.50
CQA cycles if fully vectorized	4.67
Front-end cycles	12.63
P0 cycles	7.00
P1 cycles	7.00
P2 cycles	6.92
P3 cycles	6.92
P4 cycles	6.83
P5 cycles	6.83
P6 cycles	6.75
P7 cycles	6.75
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	16.50
P13 cycles	16.17
P14 cycles	16.33
P15 cycles	1.50
P16 cycles	1.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	102.00
Nb uops	101.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	28.12
Bytes prefetched	0.00
Bytes loaded	432.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	47.37
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	45.45

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15
Source file and lines	IJMatrix_parcsr.c:3291-3484
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3291-3300,3311,3376-3377,3383-3390,3399-3410,3417-3424,3433-3444,3454-3458,3466-3484.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3291-3296,3300,3311,3376-3377,3383,3406,3410,3440,3444,3457-3458,3466-3467,3484.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 47% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 16.50 to 4.67 cycles (3.54x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 16.50 to 1.50 cycles (11.00x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 432 bytes. The binary loop is storing 32 bytes.

General properties

nb instructions	102
loop length	408
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

12.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	7.00	7.00	6.92	6.92	6.83	6.83	6.75	6.75	0.00	0.00	0.00	0.00	16.50	16.17	16.33	1.50	1.50
cycles	7.00	7.00	6.92	6.92	6.83	6.83	6.75	6.75	0.00	0.00	0.00	0.00	16.50	16.17	16.33	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	12.63
Overall L1	16.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.50 cycles. At this rate:

27% of peak load performance is reached (26.18 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (1.94 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 496f44

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
ORR X21, XZR, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X26, XZR, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X9, X8, [X8, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X21, [X9, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X26, [X8, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X21, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X26, X4, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD X30, X30, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X30, X7	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 497620 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x990>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X9, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X8, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X8, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X20, [X8, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X8, [X28]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X8, X9,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUBS X6, X25, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 49700c <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x37c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X8, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X25, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 49700c <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x37c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X6, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 497134 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x4a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X24, X20, X24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X12, #1, #8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
B.LT 496f44 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x2b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X10, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X9, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 497054 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x3c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X12, X6, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X10, X9, [X8, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X8, [X9, X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X10, X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X20, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 496f20 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x290>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X11, X13, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X16, X18, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X17, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X14, X12, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X10, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X26, XZR, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X21, XZR, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X0, X1, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X15, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X17]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [X18]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X11, X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X13, X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 4971bc <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x52c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4bb4e0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1111	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W1, #3406	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X20, XZR, X30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X3, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 4a9360 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <4bb504>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1452	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 49753c <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x8ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4bb510>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1111	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W1, #3440	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X20, XZR, X30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X3, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 4a9360 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <4bb534>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1490	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDADD X9, X8, [X8]																					N/A
LDR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 497554 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x8c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X1, XZR, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6ee0 <hypre_printf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X7, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X5, X6, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ORR X30, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 496f28 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x298>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15
Source file and lines	IJMatrix_parcsr.c:3291-3484
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3291-3300,3311,3376-3377,3383-3390,3399-3410,3417-3424,3433-3444,3454-3458,3466-3484.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3291-3296,3300,3311,3376-3377,3383,3406,3410,3440,3444,3457-3458,3466-3467,3484.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 47% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 16.50 to 4.67 cycles (3.54x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 16.50 to 1.50 cycles (11.00x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 432 bytes. The binary loop is storing 32 bytes.

General properties

nb instructions	102
loop length	408
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

12.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	7.00	7.00	6.92	6.92	6.83	6.83	6.75	6.75	0.00	0.00	0.00	0.00	16.50	16.17	16.33	1.50	1.50
cycles	7.00	7.00	6.92	6.92	6.83	6.83	6.75	6.75	0.00	0.00	0.00	0.00	16.50	16.17	16.33	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	12.63
Overall L1	16.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.50 cycles. At this rate:

27% of peak load performance is reached (26.18 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (1.94 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 496f44

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
ORR X21, XZR, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X26, XZR, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X9, X8, [X8, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X21, [X9, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X26, [X8, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X21, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X26, X4, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD X30, X30, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X30, X7	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 497620 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x990>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X9, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X8, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X8, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X20, [X8, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X8, [X28]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X8, X9,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUBS X6, X25, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 49700c <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x37c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X8, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X25, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 49700c <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x37c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X6, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 497134 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x4a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X24, X20, X24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X12, #1, #8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
B.LT 496f44 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x2b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X10, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X9, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 497054 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x3c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X12, X6, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X10, X9, [X8, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X8, [X9, X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X10, X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X20, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 496f20 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x290>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X11, X13, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X16, X18, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X17, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X14, X12, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X10, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X26, XZR, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X21, XZR, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X0, X1, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X15, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X17]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [X18]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X11, X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X13, X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 4971bc <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x52c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4bb4e0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1111	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W1, #3406	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X20, XZR, X30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X3, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 4a9360 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <4bb504>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1452	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 49753c <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x8ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4bb510>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1111	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W1, #3440	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X20, XZR, X30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X3, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 4a9360 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <4bb534>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1490	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDADD X9, X8, [X8]																					N/A
LDR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 497554 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x8c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X1, XZR, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6ee0 <hypre_printf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X7, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X5, X6, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ORR X30, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 496f28 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x298>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

▶Scalability Runs Description

Run 1x1	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_NUM_THREADS: 1OMP_PLACES: threads
Run 1x2	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 2OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x4	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 4OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x8	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 8OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x16	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 16OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x24	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 24OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x32	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 32OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x40	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 40OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x48	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 48OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x56	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 56OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x64	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 64OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x72	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 72OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x80	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 80OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x88	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 88OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x96	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 96OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads

(1x1) Efficiency	(1x1) Potential Speed-Up (%)	(1x2) Efficiency	(1x2) Potential Speed-Up (%)	(1x4) Efficiency	(1x4) Potential Speed-Up (%)	(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x16) Efficiency	(1x16) Potential Speed-Up (%)	(1x24) Efficiency	(1x24) Potential Speed-Up (%)	(1x32) Efficiency	(1x32) Potential Speed-Up (%)	(1x40) Efficiency	(1x40) Potential Speed-Up (%)	(1x48) Efficiency	(1x48) Potential Speed-Up (%)	(1x56) Efficiency	(1x56) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)	(1x72) Efficiency	(1x72) Potential Speed-Up (%)	(1x80) Efficiency	(1x80) Potential Speed-Up (%)	(1x88) Efficiency	(1x88) Potential Speed-Up (%)	(1x96) Efficiency	(1x96) Potential Speed-Up (%)
1	0	1.98	0	4.73	0	8.42	0	11.99	0	18.73	0	20.5	0	27.77	0	35.3	0	36.63	0	49.94	0	57.06	0	57.32	0	55.47	0	53.11	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x1	1	1	1	1	0.53999984264374	0.20298540592194
1x2	2	1.98	1.98	2	0.27000004053116	0.19251032173634
1x4	4	4.73	4.73	4	0.13999998569489	0.15115529298782
1x8	8	8.42	8.42	8	0.094999998807907	0.14538067579269
1x16	16	11.99	11.99	16	0.069999992847443	0.15631709992886
1x24	24	18.73	18.73	24	0.054999981075525	0.11639396101236
1x32	32	20.5	20.5	32	0.044999994337559	0.11601667106152
1x40	38	27.77	27.77	40	0.034999996423721	0.080609321594238
1x48	46	35.3	35.3	48	0.029999997466803	0.069017171859741
1x56	49	36.63	36.63	56	0.050000004470348	0.073180057108402
1x64	51	49.94	49.94	64	0.035000000149012	0.055520992726088
1x72	60	57.06	57.06	72	0.025000000372529	0.048658236861229
1x80	61	57.32	57.32	80	0.029999999329448	0.052626524120569
1x88	68	55.47	55.47	88	0.025000002235174	0.049630511552095
1x96	73	53.11	53.11	96	0.024999996647239	0.052047871053219

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency