OV - exec - Function hypre_ParCSRRelaxThreads.omp

	Function: hypre_ParCSRRelaxThreads.omp_outlined.28	Module: exec	Source: ams.c:3662-3682	Coverage (incl. loops): NA% \| (excl. loops): NA%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3662 - 3682

--------------------------------------------------------------------------------

3662: #pragma omp parallel for private(i,ii,jj,res) HYPRE_SMP_SCHEDULE

3663: #endif

3664:       for (i = 0; i < n; i++)

3665:       {

3666:          /*-----------------------------------------------------------

3667:           * If diagonal is nonzero, relax point i; otherwise, skip it.

3668:           *-----------------------------------------------------------*/

3669:          if (A_diag_data[A_diag_i[i]] != zero)

3670:          {

3671:             res = f_data[i];

3672:             for (jj = A_diag_i[i]; jj < A_diag_i[i+1]; jj++)

3673:             {

3674:                ii = A_diag_j[jj];

3675:                res -= A_diag_data[jj] * Vtemp_data[ii];

3676:             }

3677:             for (jj = A_offd_i[i]; jj < A_offd_i[i+1]; jj++)

3678:             {

3679:                ii = A_offd_j[jj];

3680:                res -= A_offd_data[jj] * Vext_data[ii];

3681:             }

3682:             u_data[i] += (relax_weight*res)/l1_norms[i];

0x479540 SUB	SP, SP, #176

0x479544 STP	X29, X30, [SP, #80]

0x479548 STP	X28, X27, [SP, #96]

0x47954c STP	X26, X25, [SP, #112]

0x479550 STP	X24, X23, [SP, #128]

0x479554 STP	X22, X21, [SP, #144]

0x479558 STP	X20, X19, [SP, #160]

0x47955c ADD	X29, SP, #80

0x479560 LDR	X8, [X2]

0x479564 SUBS	X25, X8, #1

0x479568 B.LT	4795e4

0x47956c LDR	W20, [X0]

0x479570 ORR	X21, XZR, X7

0x479574 ORR	X22, XZR, X6

0x479578 ORR	X19, XZR, X5

0x47957c ORR	X23, XZR, X4

0x479580 ORR	X24, XZR, X3

0x479584 MOVZ	W8, #1

0x479588 ADRP	X0,

0x47958c ADD	X0, X0, #896

0x479590 SUB	X3, X29, #28

0x479594 SUB	X4, X29, #8

0x479598 SUB	X5, X29, #16

0x47959c STP	X25, XZR, [X29, #1008]

0x4795a0 STUR	WZR, [X29, #484]

0x4795a4 SUB	X6, X29, #24

0x4795a8 MOVZ	W2, #34

0x4795ac MOVZ	W7, #1

0x4795b0 STUR	X8, [X29, #488]

0x4795b4 STR	X8, [SP]

0x4795b8 ORR	W1, WZR, W20

0x4795bc BL	40fa00

0x4795c0 LDP	X8, X9, [X29, #1008]

0x4795c4 CMP	X8, X25

0x4795c8 CSEL	X1, X8, X25, #11

0x4795cc CMP	X9, X1

0x4795d0 B.LE	479604

  (2666) 0x4795d4 ADRP	X0,

  (2666) 0x4795d8 ADD	X0, X0, #920

  (2666) 0x4795dc ORR	W1, WZR, W20

  (2666) 0x4795e0 BL	40f910

  (2666) 0x4795e4 LDP	X20, X19, [SP, #160]

  (2666) 0x4795e8 LDP	X22, X21, [SP, #144]

  (2666) 0x4795ec LDP	X24, X23, [SP, #128]

  (2666) 0x4795f0 LDP	X26, X25, [SP, #112]

  (2666) 0x4795f4 LDP	X28, X27, [SP, #96]

  (2666) 0x4795f8 LDP	X29, X30, [SP, #80]

  (2666) 0x4795fc ADD	SP, SP, #176

  (2666) 0x479600 RET

  (2666) 0x479604 LDP	X16, X17, [X29, #112]

  (2666) 0x479608 LDP	X8, X0, [X29, #144]

  (2666) 0x47960c LDP	X18, X4, [X29, #128]

  (2666) 0x479610 ADD	X1, X1, #1

  (2666) 0x479614 LDP	X14, X15, [X29, #96]

  (2666) 0x479618 LDR	X10, [X24]

  (2666) 0x47961c ADD	X6, X10, #16

  (2666) 0x479620 LDR	X13, [X21]

  (2666) 0x479624 LDR	X16, [X16]

  (2666) 0x479628 LDR	X17, [X17]

  (2666) 0x47962c LDR	X11, [X23]

  (2666) 0x479630 LDR	X12, [X22]

  (2666) 0x479634 LDR	X14, [X14]

  (2666) 0x479638 LDR	X15, [X15]

  (2666) 0x47963c LDR	X18, [X18]

  (2666) 0x479640 LDR	X0, [X0]

  (2666) 0x479644 LDR	X4, [X4]

  (2666) 0x479648 ADD	X5, X13, #16

  (2666) 0x47964c ADD	X2, X13, #8

  (2666) 0x479650 ADD	X3, X10, #8

  (2666) 0x479654 ADD	X7, X16, #8

  (2666) 0x479658 STP	X5, X6, [SP, #32]

  (2666) 0x47965c ADD	X21, X17, #8

  (2666) 0x479660 ADD	X6, X17, #16

  (2666) 0x479664 ADD	X5, X16, #16

  (2666) 0x479668 STP	X5, X6, [SP, #16]

  (2666) 0x47966c B	4796a8

0x479670 HINT	#0

0x479674 HINT	#0

0x479678 HINT	#0

0x47967c HINT	#0

(2667) 0x479680 LDR	D1, [X8]

(2667) 0x479684 FMUL	D0, D1, D0

(2667) 0x479688 LDR	D1, [X0, X9,LSL #3]

(2667) 0x47968c FDIV	D0, D0, D1

(2667) 0x479690 LDR	D1, [X4, X9,LSL #3]

(2667) 0x479694 FADD	D0, D1, D0

(2667) 0x479698 STR	D0, [X4, X9,LSL #3]

  (2666) 0x47969c ORR	X9, XZR, X24

  (2666) 0x4796a0 CMP	X24, X1

  (2666) 0x4796a4 B.EQ	4795d4

  (2666) 0x4796a8 LDR	X5, [X11, X9,LSL #3]

  (2666) 0x4796ac LDR	D1, [X19]

  (2666) 0x4796b0 LDR	D0, [X10, X5,LSL #3]

  (2666) 0x4796b4 FCMP	D0, D1

  (2666) 0x4796b8 B.EQ	4796e0

(2667) 0x4796bc LDR	D0, [X12, X9,LSL #3]

(2667) 0x4796c0 ADD	X24, X9, #1

(2667) 0x4796c4 LDR	X25, [X11, X24,LSL #3]

(2667) 0x4796c8 SUBS	X27, X25, X5

(2667) 0x4796cc B.LE	4797c0

(2667) 0x4796d0 CMP	X27, #2

(2667) 0x4796d4 B.CS	4796e8

(2667) 0x4796d8 ORR	X26, XZR, X5

(2667) 0x4796dc B	479734

  (2666) 0x4796e0 ADD	X24, X9, #1

  (2666) 0x4796e4 B	47969c

(2667) 0x4796e8 AND	X6, X27, #8127

(2667) 0x4796ec MOVI	D1, #0

(2667) 0x4796f0 ADD	X30, X2, X5,LSL #3

(2667) 0x4796f4 ADD	X26, X5, X6

(2667) 0x4796f8 ADD	X5, X3, X5,LSL #3

(2667) 0x4796fc ORR	X28, XZR, X6

  (2671) 0x479700 LDP	X22, X23, [X30, #1016]

  (2671) 0x479704 LDP	D2, D3, [X5, #1016]

  (2671) 0x479708 SUBS	X28, X28, #2

  (2671) 0x47970c ADD	X30, X30, #16

  (2671) 0x479710 ADD	X5, X5, #16

  (2671) 0x479714 LDR	D4, [X14, X22,LSL #3]

  (2671) 0x479718 LDR	D5, [X14, X23,LSL #3]

  (2671) 0x47971c FMSUB	D0, D4, D2, D0

  (2671) 0x479720 FMSUB	D1, D5, D3, D1

  (2671) 0x479724 B.NE	479700

(2667) 0x479728 FADD	D0, D1, D0

(2667) 0x47972c CMP	X27, X6

(2667) 0x479730 B.EQ	4797c0

(2667) 0x479734 SUB	W5, W25, W26

(2667) 0x479738 ORR	X27, XZR, X26

(2667) 0x47973c ANDS	X5, X5, #4160

(2667) 0x479740 B.EQ	479760

  (2673) 0x479744 LDR	X6, [X13, X27,LSL #3]

  (2673) 0x479748 LDR	D1, [X10, X27,LSL #3]

  (2673) 0x47974c ADD	X27, X27, #1

  (2673) 0x479750 SUBS	X5, X5, #1

  (2673) 0x479754 LDR	D2, [X14, X6,LSL #3]

  (2673) 0x479758 FMSUB	D0, D2, D1, D0

  (2673) 0x47975c B.NE	479744

(2667) 0x479760 SUB	X5, X26, X25

(2667) 0x479764 CMN	X5, #4

(2667) 0x479768 B.HI	4797c0

(2667) 0x47976c LDP	X5, X6, [SP, #32]

(2667) 0x479770 SUB	X25, X25, X27

(2667) 0x479774 ADD	X26, X6, X27,LSL #3

(2667) 0x479778 ADD	X27, X5, X27,LSL #3

(2667) 0x47977c HINT	#0

  (2672) 0x479780 LDP	X5, X6, [X27, #1008]

  (2672) 0x479784 LDP	D2, D3, [X26, #1008]

  (2672) 0x479788 SUBS	X25, X25, #4

  (2672) 0x47978c LDR	D4, [X14, X6,LSL #3]

  (2672) 0x479790 LDR	D1, [X14, X5,LSL #3]

  (2672) 0x479794 LDP	X5, X6, [X27], #32

  (2672) 0x479798 FMUL	D3, D4, D3

  (2672) 0x47979c LDR	D4, [X14, X5,LSL #3]

  (2672) 0x4797a0 FMADD	D1, D1, D2, D3

  (2672) 0x4797a4 LDP	D2, D3, [X26], #32

  (2672) 0x4797a8 FMADD	D1, D4, D2, D1

  (2672) 0x4797ac LDR	D2, [X14, X6,LSL #3]

  (2672) 0x4797b0 FMADD	D1, D2, D3, D1

  (2672) 0x4797b4 FSUB	D0, D0, S1

  (2672) 0x4797b8 B.NE	479780

(2667) 0x4797bc HINT	#0

(2667) 0x4797c0 LDR	X5, [X15, X9,LSL #3]

(2667) 0x4797c4 LDR	X25, [X15, X24,LSL #3]

(2667) 0x4797c8 SUBS	X27, X25, X5

(2667) 0x4797cc B.LE	479680

(2667) 0x4797d0 CMP	X27, #2

(2667) 0x4797d4 B.CS	4797e0

(2667) 0x4797d8 ORR	X26, XZR, X5

(2667) 0x4797dc B	479834

(2667) 0x4797e0 AND	X28, X27, #8127

(2667) 0x4797e4 MOVI	D1, #0

(2667) 0x4797e8 ADD	X30, X7, X5,LSL #3

(2667) 0x4797ec ADD	X26, X5, X28

(2667) 0x4797f0 ADD	X5, X21, X5,LSL #3

(2667) 0x4797f4 ORR	X6, XZR, X28

(2667) 0x4797f8 HINT	#0

(2667) 0x4797fc HINT	#0

  (2668) 0x479800 LDP	X22, X23, [X30, #1016]

  (2668) 0x479804 LDP	D2, D3, [X5, #1016]

  (2668) 0x479808 SUBS	X6, X6, #2

  (2668) 0x47980c ADD	X30, X30, #16

  (2668) 0x479810 ADD	X5, X5, #16

  (2668) 0x479814 LDR	D4, [X18, X22,LSL #3]

  (2668) 0x479818 LDR	D5, [X18, X23,LSL #3]

  (2668) 0x47981c FMSUB	D0, D4, D2, D0

  (2668) 0x479820 FMSUB	D1, D5, D3, D1

  (2668) 0x479824 B.NE	479800

(2667) 0x479828 FADD	D0, D1, D0

(2667) 0x47982c CMP	X27, X28

(2667) 0x479830 B.EQ	479680

(2667) 0x479834 SUB	W5, W25, W26

(2667) 0x479838 ORR	X27, XZR, X26

(2667) 0x47983c ANDS	X5, X5, #4160

(2667) 0x479840 B.EQ	479860

  (2670) 0x479844 LDR	X6, [X16, X27,LSL #3]

  (2670) 0x479848 LDR	D1, [X17, X27,LSL #3]

  (2670) 0x47984c ADD	X27, X27, #1

  (2670) 0x479850 SUBS	X5, X5, #1

  (2670) 0x479854 LDR	D2, [X18, X6,LSL #3]

  (2670) 0x479858 FMSUB	D0, D2, D1, D0

  (2670) 0x47985c B.NE	479844

(2667) 0x479860 SUB	X5, X26, X25

(2667) 0x479864 CMN	X5, #4

(2667) 0x479868 B.HI	479680

(2667) 0x47986c LDP	X5, X6, [SP, #16]

(2667) 0x479870 SUB	X25, X25, X27

(2667) 0x479874 ADD	X26, X6, X27,LSL #3

(2667) 0x479878 ADD	X27, X5, X27,LSL #3

(2667) 0x47987c HINT	#0

  (2669) 0x479880 LDP	X5, X6, [X27, #1008]

  (2669) 0x479884 LDP	D2, D3, [X26, #1008]

  (2669) 0x479888 SUBS	X25, X25, #4

  (2669) 0x47988c LDR	D4, [X18, X6,LSL #3]

  (2669) 0x479890 LDR	D1, [X18, X5,LSL #3]

  (2669) 0x479894 LDP	X5, X6, [X27], #32

  (2669) 0x479898 FMUL	D3, D4, D3

  (2669) 0x47989c LDR	D4, [X18, X5,LSL #3]

  (2669) 0x4798a0 FMADD	D1, D1, D2, D3

  (2669) 0x4798a4 LDP	D2, D3, [X26], #32

  (2669) 0x4798a8 FMADD	D1, D4, D2, D1

  (2669) 0x4798ac LDR	D2, [X18, X6,LSL #3]

  (2669) 0x4798b0 FMADD	D1, D2, D3, D1

  (2669) 0x4798b4 FSUB	D0, D0, S1

  (2669) 0x4798b8 B.NE	479880

(2667) 0x4798bc B	479680

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	ams.c:3662-3682
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662-3682.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 60% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 5.00 to 4.12 cycles (1.21x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.00 to 0.50 cycles (10.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes. The binary function is storing 132 bytes.

General properties

nb instructions	41
loop length	164
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	3.75	3.75	3.67	3.67	3.58	3.58	0.00	0.00	0.00	0.00	5.00	5.00	3.00	5.00	5.00
cycles	1.50	1.50	3.75	3.75	3.67	3.67	3.58	3.58	0.00	0.00	0.00	0.00	5.00	5.00	3.00	5.00	5.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.63
Overall L1	5.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.00 cycles. At this rate:

5% of peak load performance is reached (5.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
55% of peak store performance is reached (26.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 479540

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #176	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #80	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUBS X25, X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 4795e4 <hypre_ParCSRRelaxThreads.omp_outlined.28+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W20, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X21, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X22, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X19, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X23, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X24, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADRP X0, <4de588>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #896	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X3, X29, #28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X4, X29, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X5, X29, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X25, XZR, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR WZR, [X29, #484]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X6, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR W1, WZR, W20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 40fa00 <@plt_start@+0x610>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X9, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
CMP X8, X25	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X1, X8, X25, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X9, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 479604 <hypre_ParCSRRelaxThreads.omp_outlined.28+0xc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	ams.c:3662-3682
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662-3682.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.00 to 0.50 cycles (10.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes. The binary function is storing 132 bytes.

General properties

nb instructions	41
loop length	164
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	3.75	3.75	3.67	3.67	3.58	3.58	0.00	0.00	0.00	0.00	5.00	5.00	3.00	5.00	5.00
cycles	1.50	1.50	3.75	3.75	3.67	3.67	3.58	3.58	0.00	0.00	0.00	0.00	5.00	5.00	3.00	5.00	5.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.63
Overall L1	5.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.00 cycles. At this rate:

5% of peak load performance is reached (5.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
55% of peak store performance is reached (26.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 479540

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #176	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #80	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUBS X25, X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 4795e4 <hypre_ParCSRRelaxThreads.omp_outlined.28+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W20, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X21, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X22, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X19, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X23, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X24, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADRP X0, <4de588>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #896	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X3, X29, #28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X4, X29, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X5, X29, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X25, XZR, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR WZR, [X29, #484]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X6, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR W1, WZR, W20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 40fa00 <@plt_start@+0x610>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X9, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
CMP X8, X25	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X1, X8, X25, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X9, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 479604 <hypre_ParCSRRelaxThreads.omp_outlined.28+0xc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

▶Scalability Runs Description

Run 1x1	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_NUM_THREADS: 1OMP_PLACES: threads
Run 1x2	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 2OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x4	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 4OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x8	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 8OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x16	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 16OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x24	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 24OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x32	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 32OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x40	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 40OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x48	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 48OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x56	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 56OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x64	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 64OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x72	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 72OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x80	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 80OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x88	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 88OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x96	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 96OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads

(1x1) Efficiency	(1x1) Potential Speed-Up (%)	(1x2) Efficiency	(1x2) Potential Speed-Up (%)	(1x4) Efficiency	(1x4) Potential Speed-Up (%)	(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x16) Efficiency	(1x16) Potential Speed-Up (%)	(1x24) Efficiency	(1x24) Potential Speed-Up (%)	(1x32) Efficiency	(1x32) Potential Speed-Up (%)	(1x40) Efficiency	(1x40) Potential Speed-Up (%)	(1x48) Efficiency	(1x48) Potential Speed-Up (%)	(1x56) Efficiency	(1x56) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)	(1x72) Efficiency	(1x72) Potential Speed-Up (%)	(1x80) Efficiency	(1x80) Potential Speed-Up (%)	(1x88) Efficiency	(1x88) Potential Speed-Up (%)	(1x96) Efficiency	(1x96) Potential Speed-Up (%)
		1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x1
1x2	2	1	1	2	50.924995422363	36.224018096924
1x4	4	1	1	4	26.335000991821	35.764362335205
1x8	8	1	1	8	15.1399974823	36.099369049072
1x16	16	1	1	16	9.8400030136108	36.8967628479
1x24	24	1	1	24	8.6149997711182	38.363639831543
1x32	32	1	1	32	8.4700012207031	40.172863006592
1x40	40	1	1	40	8.3999996185303	41.673126220703
1x48	48	1	1	48	8.3649988174438	42.330169677734
1x56	56	1	1	56	7.4700012207031	41.738555908203
1x64	64	1	1	64	7.0949997901917	41.81436920166
1x72	72	1	1	72	6.8300008773804	41.220359802246
1x80	80	1	1	80	6.7749991416931	41.548847198486
1x88	88	1	1	88	6.5799999237061	41.372283935547
1x96	96	1	1	96	6.5249991416931	41.505313873291

Name	Coverage (%)	Time (s)
▼hypre_ParCSRRelaxThreads.omp_outlined.28–	0.00	0.00
▼Loop 2667 - ams.c:3662-3682 - exec–	0.00	0.00
○Loop 2671 - ams.c:3674-3675 - exec	0.00	0.00
○Loop 2672 - ams.c:3672-3675 - exec	0.00	0.00
○Loop 2668 - ams.c:3679-3680 - exec	0.00	0.00
○Loop 2670 - ams.c:3677-3680 - exec	0.00	0.00
○Loop 2673 - ams.c:3672-3675 - exec	0.00	0.00
○Loop 2666 - ams.c:3662-3682 - exec	0.00	0.00
○Loop 2669 - ams.c:3677-3680 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency