OV - exec - Function hypre_ParCSRComputeL1NormsThreads.omp

	Function: hypre_ParCSRComputeL1NormsThreads.omp_outlined	Module: exec	Source: ams.c:3363-3540 [...]	Coverage (incl. loops): NA% \| (excl. loops): NA%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3363 - 3540

--------------------------------------------------------------------------------

3363: #pragma omp parallel for private(i,ii,j,k,ns,ne,rest,size,diag,cf_diag) HYPRE_SMP_SCHEDULE

3364: #endif

3365:    for (k = 0; k < num_threads; k++)

3366:    {

3367:       size = num_rows/num_threads;

3368:       rest = num_rows - size*num_threads;

3369:       if (k < rest)

3370:       {

3371:          ns = k*size+k;

3372:          ne = (k+1)*size+k+1;

3373:       }

3374:       else

3375:       {

3376:          ns = k*size+rest;

3377:          ne = (k+1)*size+rest;

3378:       }

3379:

3380:       if (option == 1)

3381:       {

3382:          for (i = ns; i < ne; i++)

3383:          {

3384:             l1_norm[i] = 0.0;

3385:             if (cf_marker == NULL)

3386:             {

3387:                /* Add the l1 norm of the diag part of the ith row */

3388:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

3389:                   l1_norm[i] += fabs(A_diag_data[j]);

3390:                /* Add the l1 norm of the offd part of the ith row */

3391:                if (num_cols_offd)

3392:                {

3393:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

3394:                      l1_norm[i] += fabs(A_offd_data[j]);

3395:                }

3396:             }

3397:             else

3398:             {

3399:                cf_diag = cf_marker[i];

3400:                /* Add the CF l1 norm of the diag part of the ith row */

3401:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

3402:                   if (cf_diag == cf_marker[A_diag_J[j]])

3403:                      l1_norm[i] += fabs(A_diag_data[j]);

3404:                /* Add the CF l1 norm of the offd part of the ith row */

3405:                if (num_cols_offd)

3406:                {

3407:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

3408:                      if (cf_diag == cf_marker_offd[A_offd_J[j]])

3409:                         l1_norm[i] += fabs(A_offd_data[j]);

[...]

3416:          for (i = ns; i < ne; i++)

3417:          {

3418:             l1_norm[i] = 0.0;

3419:             if (cf_marker == NULL)

3420:             {

3421:                /* Add the diagonal and the local off-thread part of the ith row */

3422:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

3423:                {

3424:                   ii = A_diag_J[j];

3425:                   if (ii == i || ii < ns || ii >= ne)

3426:                      l1_norm[i] += fabs(A_diag_data[j]);

3427:                }

3428:                /* Add the l1 norm of the offd part of the ith row */

3429:                if (num_cols_offd)

3430:                {

3431:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

3432:                      l1_norm[i] += fabs(A_offd_data[j]);

3433:                }

3434:             }

3435:             else

3436:             {

3437:                cf_diag = cf_marker[i];

3438:                /* Add the diagonal and the local off-thread part of the ith row */

3439:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

3440:                {

3441:                   ii = A_diag_J[j];

3442:                   if ((ii == i || ii < ns || ii >= ne) &&

3443:                       (cf_diag == cf_marker[A_diag_J[j]]))

3444:                      l1_norm[i] += fabs(A_diag_data[j]);

3445:                }

3446:                /* Add the CF l1 norm of the offd part of the ith row */

3447:                if (num_cols_offd)

3448:                {

3449:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

3450:                      if (cf_diag == cf_marker_offd[A_offd_J[j]])

3451:                         l1_norm[i] += fabs(A_offd_data[j]);

[...]

3458:          for (i = ns; i < ne; i++)

3459:          {

3460:             l1_norm[i] = 0.0;

3461:             for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

3462:                l1_norm[i] += A_diag_data[j] * A_diag_data[j];

3463:             if (num_cols_offd)

3464:                for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

3465:                   l1_norm[i] += A_offd_data[j] * A_offd_data[j];

3466:          }

3467:       }

3468:       else if (option == 4)

3469:       {

3470:          for (i = ns; i < ne; i++)

3471:          {

3472:             l1_norm[i] = 0.0;

3473:             if (cf_marker == NULL)

3474:             {

3475:                /* Add the diagonal and the local off-thread part of the ith row */

3476:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

3477:                {

3478:                   ii = A_diag_J[j];

3479:                   if (ii == i || ii < ns || ii >= ne)

3480:                   {

3481:                      if (ii == i)

[...]

3493:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

3494:                      l1_norm[i] += 0.5*fabs(A_offd_data[j]);

3495:                }

3496:             }

3497:             else

3498:             {

3499:                cf_diag = cf_marker[i];

3500:                /* Add the diagonal and the local off-thread part of the ith row */

3501:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

3502:                {

3503:                   ii = A_diag_J[j];

3504:                   if ((ii == i || ii < ns || ii >= ne) &&

3505:                       (cf_diag == cf_marker[A_diag_J[j]]))

3506:                   {

3507:                      if (ii == i)

[...]

3517:                if (num_cols_offd)

3518:                {

3519:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

3520:                      if (cf_diag == cf_marker_offd[A_offd_J[j]])

3521:                         l1_norm[i] += 0.5*fabs(A_offd_data[j]);

3522:                }

3523:             }

3524:

3525:             /* Truncate according to Remark 6.2 */

3526:             if (l1_norm[i] <= 4.0/3.0*diag)

3527:                l1_norm[i] = diag;

3528:          }

3529:       }

3530:

3531:       /* Handle negative definite matrices */

3532:       for (i = ns; i < ne; i++)

3533:          if (A_diag_data[A_diag_I[i]] < 0)

3534:             l1_norm[i] = -l1_norm[i];

3535:

3536:       for (i = ns; i < ne; i++)

3537:          /* if (fabs(l1_norm[i]) < DBL_EPSILON) */

3538:          if (fabs(l1_norm[i]) == 0.0)

3539:          {

3540:             hypre_error_in_arg(1);

0x477e80 SUB	SP, SP, #272

0x477e84 STP	D9, D8, [SP, #160]

0x477e88 STP	X29, X30, [SP, #176]

0x477e8c STP	X28, X27, [SP, #192]

0x477e90 STP	X26, X25, [SP, #208]

0x477e94 STP	X24, X23, [SP, #224]

0x477e98 STP	X22, X21, [SP, #240]

0x477e9c STP	X20, X19, [SP, #256]

0x477ea0 ADD	X29, SP, #176

0x477ea4 LDR	X8, [X2]

0x477ea8 STR	X6, [SP, #72]

0x477eac STP	X2, X3, [X29, #952]

0x477eb0 SUBS	X19, X8, #1

0x477eb4 B.LT	477f40

0x477eb8 LDR	W1, [X0]

0x477ebc ORR	X9, XZR, X7

0x477ec0 ORR	X10, XZR, X5

0x477ec4 ORR	X11, XZR, X4

0x477ec8 MOVZ	W8, #1

0x477ecc ADRP	X0,

0x477ed0 ADD	X0, X0, #752

0x477ed4 SUB	X3, X29, #52

0x477ed8 SUB	X4, X29, #32

0x477edc SUB	X5, X29, #40

0x477ee0 STP	X19, XZR, [X29, #984]

0x477ee4 STUR	WZR, [X29, #460]

0x477ee8 STP	X10, X9, [SP, #56]

0x477eec SUB	X6, X29, #48

0x477ef0 MOVZ	W2, #34

0x477ef4 MOVZ	W7, #1

0x477ef8 STUR	X8, [X29, #464]

0x477efc STR	X8, [SP]

0x477f00 STR	X11, [SP, #48]

0x477f04 STR	W1, [SP, #20]

0x477f08 BL	40fa00

0x477f0c LDP	X8, X28, [X29, #984]

0x477f10 LDP	X30, X27, [SP, #48]

0x477f14 LDR	X24, [SP, #64]

0x477f18 CMP	X8, X19

0x477f1c CSEL	X8, X8, X19, #11

0x477f20 STUR	X8, [X29, #472]

0x477f24 STUR	X8, [X29, #432]

0x477f28 CMP	X28, X8

0x477f2c B.LE	477f64

    (2626) 0x477f30 LDR	W1, [SP, #20]

    (2626) 0x477f34 ADRP	X0,

    (2626) 0x477f38 ADD	X0, X0, #776

    (2626) 0x477f3c BL	40f910

    (2626) 0x477f40 LDP	D9, D8, [SP, #160]

    (2626) 0x477f44 LDP	X20, X19, [SP, #256]

    (2626) 0x477f48 LDP	X22, X21, [SP, #240]

    (2626) 0x477f4c LDP	X24, X23, [SP, #224]

    (2626) 0x477f50 LDP	X26, X25, [SP, #208]

    (2626) 0x477f54 LDP	X28, X27, [SP, #192]

    (2626) 0x477f58 LDP	X29, X30, [SP, #176]

    (2626) 0x477f5c ADD	SP, SP, #272

    (2626) 0x477f60 RET

    (2626) 0x477f64 LDR	X8, [X29, #144]

    (2626) 0x477f68 LDR	X26, [X29, #96]

    (2626) 0x477f6c FMOV	D8, #0.5000000

    (2626) 0x477f70 ORR	X20, XZR, #3840

    (2626) 0x477f74 MOVK	X20, #16373

    (2626) 0x477f78 STR	X8, [SP, #40]

    (2626) 0x477f7c LDR	X8, [X29, #136]

    (2626) 0x477f80 STR	X8, [SP, #32]

    (2626) 0x477f84 LDR	X8, [X29, #128]

    (2626) 0x477f88 STR	X8, [SP, #24]

    (2626) 0x477f8c LDP	X8, X25, [X29, #112]

    (2626) 0x477f90 STR	X8, [SP, #88]

    (2626) 0x477f94 LDR	X8, [X29, #104]

    (2626) 0x477f98 STR	X8, [SP, #80]

    (2626) 0x477f9c B	477fd4

  (2628) 0x477fa0 ADRP	X0,

  (2628) 0x477fa4 ADD	X0, X0, #2415

  (2628) 0x477fa8 MOVZ	W1, #3540

  (2628) 0x477fac MOVZ	W2, #12

  (2628) 0x477fb0 ORR	X3, XZR, XZR

  (2628) 0x477fb4 BL	4a9360

  (2628) 0x477fb8 LDP	X30, X27, [SP, #48]

  (2628) 0x477fbc LDR	X24, [SP, #64]

    (2626) 0x477fc0 LDUR	X9, [X29, #432]

    (2626) 0x477fc4 ADD	X8, X28, #1

    (2626) 0x477fc8 CMP	X28, X9

    (2626) 0x477fcc ORR	X28, XZR, X8

    (2626) 0x477fd0 B.EQ	477f30

    (2626) 0x477fd4 LDP	X9, X8, [X29, #952]

    (2626) 0x477fd8 LDR	X8, [X8]

    (2626) 0x477fdc LDR	X9, [X9]

    (2626) 0x477fe0 SDIV	X10, X8, X9

    (2626) 0x477fe4 MSUB	X8, X10, X9, X8

    (2626) 0x477fe8 ADD	X9, X28, #1

    (2626) 0x477fec MADD	X11, X10, X28, X8

    (2626) 0x477ff0 MADD	X12, X10, X9, X8

    (2626) 0x477ff4 CMP	X28, X8

    (2626) 0x477ff8 ADD	X8, X10, #1

    (2626) 0x477ffc MADD	X10, X8, X28, XZR

    (2626) 0x478000 MADD	X9, X9, X8, XZR

    (2626) 0x478004 CSEL	X8, X11, X10, #10

    (2626) 0x478008 LDR	X10, [X30]

    (2626) 0x47800c CSEL	X9, X12, X9, #10

    (2626) 0x478010 CMP	X10, #2

    (2626) 0x478014 B.GT	4783e0

    (2626) 0x478018 CMP	X10, #1

    (2626) 0x47801c B.EQ	478764

    (2626) 0x478020 CMP	X10, #2

    (2626) 0x478024 B.NE	478e68

    (2626) 0x478028 CMP	X9, X8

    (2626) 0x47802c B.LE	478e68

    (2626) 0x478030 LDP	X13, X16, [SP, #24]

    (2626) 0x478034 LDR	X17, [SP, #40]

    (2626) 0x478038 LDP	X11, X14, [SP, #72]

    (2626) 0x47803c ORR	X6, XZR, X8

    (2626) 0x478040 LDR	X15, [SP, #88]

    (2626) 0x478044 LDR	X10, [X27]

    (2626) 0x478048 ADD	X0, X10, #8

    (2626) 0x47804c LDR	X13, [X13]

    (2626) 0x478050 LDR	X17, [X17]

    (2626) 0x478054 LDR	X18, [X25]

    (2626) 0x478058 LDR	X11, [X11]

    (2626) 0x47805c LDR	X12, [X24]

    (2626) 0x478060 LDR	X14, [X14]

    (2626) 0x478064 LDR	X15, [X15]

    (2626) 0x478068 LDR	X16, [X16]

    (2626) 0x47806c ADD	X3, X18, #16

    (2626) 0x478070 ADD	X1, X17, #8

    (2626) 0x478074 ADD	X2, X13, #8

    (2626) 0x478078 B	47808c

0x47807c HINT	#0

      (2652) 0x478080 ORR	X6, XZR, X4

      (2652) 0x478084 CMP	X4, X9

      (2652) 0x478088 B.EQ	478e68

      (2652) 0x47808c ADD	X5, X10, X6,LSL #3

      (2652) 0x478090 STR	XZR, [X5]

      (2652) 0x478094 CBZ	X11, 47812c

      (2652) 0x478098 ADD	X4, X6, #1

      (2652) 0x47809c LDR	X21, [X12, X6,LSL #3]

      (2652) 0x4780a0 LDR	X7, [X11, X6,LSL #3]

      (2652) 0x4780a4 MOVI	D0, #0

      (2652) 0x4780a8 LDR	X19, [X12, X4,LSL #3]

      (2652) 0x4780ac SUBS	X19, X19, X21

      (2652) 0x4780b0 B.LE	478104

      (2652) 0x4780b4 LDR	X23, [X26]

      (2652) 0x4780b8 ADD	X22, X13, X21,LSL #3

      (2652) 0x4780bc ADD	X23, X23, X21,LSL #3

      (2652) 0x4780c0 B	4780d0

        (2658) 0x4780c4 SUBS	X19, X19, #1

        (2658) 0x4780c8 ADD	X23, X23, #8

        (2658) 0x4780cc B.EQ	478104

        (2658) 0x4780d0 LDR	X21, [X22], #8

        (2658) 0x4780d4 CMP	X21, X6

        (2658) 0x4780d8 CCMP	X21, X8, #8, #1

        (2658) 0x4780dc CCMP	X21, X9, #0, #10

        (2658) 0x4780e0 B.LT	4780c4

        (2658) 0x4780e4 LDR	X21, [X11, X21,LSL #3]

        (2658) 0x4780e8 CMP	X7, X21

        (2658) 0x4780ec B.NE	4780c4

        (2658) 0x4780f0 LDR	D1, [X23]

        (2658) 0x4780f4 FABS	D1, D1

        (2658) 0x4780f8 FADD	D0, D0, D1

        (2658) 0x4780fc STR	D0, [X5]

        (2658) 0x478100 B	4780c4

      (2652) 0x478104 CBZ	X14, 478080

      (2652) 0x478108 LDR	X19, [X15, X6,LSL #3]

      (2652) 0x47810c LDR	X6, [X15, X4,LSL #3]

      (2652) 0x478110 CMP	X6, X19

      (2652) 0x478114 B.LE	478080

      (2652) 0x478118 LDR	X22, [X25]

      (2652) 0x47811c SUB	W21, W6, W19

      (2652) 0x478120 TBNZ	W21, #0, 47815c

      (2652) 0x478124 ORR	X21, XZR, X19

      (2652) 0x478128 B	478180

      (2652) 0x47812c ADD	X4, X6, #1

      (2652) 0x478130 LDR	X19, [X12, X6,LSL #3]

      (2652) 0x478134 MOVI	D0, #0

      (2652) 0x478138 LDR	X7, [X12, X4,LSL #3]

      (2652) 0x47813c CMP	X7, X19

      (2652) 0x478140 B.LE	478228

      (2652) 0x478144 LDR	X22, [X26]

      (2652) 0x478148 MOVI	D0, #0

      (2652) 0x47814c SUB	W21, W7, W19

      (2652) 0x478150 TBNZ	W21, #0, 4781f4

      (2652) 0x478154 ORR	X21, XZR, X19

      (2652) 0x478158 B	47821c

      (2652) 0x47815c LDR	X21, [X17, X19,LSL #3]

      (2652) 0x478160 LDR	X21, [X16, X21,LSL #3]

      (2652) 0x478164 CMP	X7, X21

      (2652) 0x478168 B.NE	47817c

      (2652) 0x47816c LDR	D1, [X22, X19,LSL #3]

      (2652) 0x478170 FABS	D1, D1

      (2652) 0x478174 FADD	D0, D0, D1

      (2652) 0x478178 STR	D0, [X5]

      (2652) 0x47817c ADD	X21, X19, #1

      (2652) 0x478180 ADD	X19, X19, #1

      (2652) 0x478184 CMP	X6, X19

      (2652) 0x478188 B.EQ	478080

      (2652) 0x47818c SUB	X6, X6, X21

      (2652) 0x478190 ADD	X19, X1, X21,LSL #3

      (2652) 0x478194 ADD	X21, X22, X21,LSL #3

      (2652) 0x478198 ADD	X22, X21, #8

      (2652) 0x47819c B	4781b0

        (2657) 0x4781a0 SUBS	X6, X6, #2

        (2657) 0x4781a4 ADD	X19, X19, #16

        (2657) 0x4781a8 ADD	X22, X22, #16

        (2657) 0x4781ac B.EQ	478080

        (2657) 0x4781b0 LDUR	X21, [X19, #504]

        (2657) 0x4781b4 LDR	X21, [X16, X21,LSL #3]

        (2657) 0x4781b8 CMP	X7, X21

        (2657) 0x4781bc B.NE	4781d0

        (2657) 0x4781c0 LDUR	D1, [X22, #504]

        (2657) 0x4781c4 FABS	D1, D1

        (2657) 0x4781c8 FADD	D0, D0, D1

        (2657) 0x4781cc STR	D0, [X5]

        (2657) 0x4781d0 LDR	X21, [X19]

        (2657) 0x4781d4 LDR	X21, [X16, X21,LSL #3]

        (2657) 0x4781d8 CMP	X7, X21

        (2657) 0x4781dc B.NE	4781a0

        (2657) 0x4781e0 LDR	D1, [X22]

        (2657) 0x4781e4 FABS	D1, D1

        (2657) 0x4781e8 FADD	D0, D0, D1

        (2657) 0x4781ec STR	D0, [X5]

        (2657) 0x4781f0 B	4781a0

      (2652) 0x4781f4 LDR	X21, [X13, X19,LSL #3]

      (2652) 0x4781f8 MOVI	D0, #0

      (2652) 0x4781fc CMP	X21, X6

      (2652) 0x478200 CCMP	X21, X8, #8, #1

      (2652) 0x478204 CCMP	X21, X9, #0, #10

      (2652) 0x478208 B.LT	478218

      (2652) 0x47820c LDR	D0, [X22, X19,LSL #3]

      (2652) 0x478210 FABS	D0, D0

      (2652) 0x478214 STR	D0, [X5]

      (2652) 0x478218 ADD	X21, X19, #1

      (2652) 0x47821c ADD	X19, X19, #1

      (2652) 0x478220 CMP	X7, X19

      (2652) 0x478224 B.NE	4782b8

      (2652) 0x478228 CBZ	X14, 478080

      (2652) 0x47822c LDR	X23, [X15, X6,LSL #3]

      (2652) 0x478230 LDR	X7, [X15, X4,LSL #3]

      (2652) 0x478234 SUBS	X19, X7, X23

      (2652) 0x478238 B.LE	478080

      (2652) 0x47823c CMP	X19, #6

      (2652) 0x478240 B.CC	478328

      (2652) 0x478244 ADD	X22, X18, X7,LSL #3

      (2652) 0x478248 ADD	X6, X0, X6,LSL #3

      (2652) 0x47824c ADD	X21, X18, X23,LSL #3

      (2652) 0x478250 CMP	X5, X22

      (2652) 0x478254 CCMP	X21, X6, #2, #3

      (2652) 0x478258 B.CC	478328

      (2652) 0x47825c AND	X22, X19, #8062

      (2652) 0x478260 MOVI	V2.2D, #0

      (2652) 0x478264 MOV	V2.D[0], V0.D[0]

      (2652) 0x478268 MOVI	V1.2D, #0

      (2652) 0x47826c ADD	X6, X23, X22

      (2652) 0x478270 ADD	X23, X3, X23,LSL #3

      (2652) 0x478274 ORR	X21, XZR, X22

      (2652) 0x478278 HINT	#0

      (2652) 0x47827c HINT	#0

        (2655) 0x478280 LDP	Q0, Q3, [X23, #2032]

        (2655) 0x478284 ADD	X23, X23, #32

        (2655) 0x478288 SUBS	X21, X21, #4

        (2655) 0x47828c FABS	V3.2D, V3.2D

        (2655) 0x478290 FABS	V0.2D, V0.2D

        (2655) 0x478294 FADD	V1.2D, V1.2D, V3.2D

        (2655) 0x478298 FADD	V2.2D, V2.2D, V0.2D

        (2655) 0x47829c B.NE	478280

      (2652) 0x4782a0 FADD	V0.2D, V1.2D, V2.2D

      (2652) 0x4782a4 FADDP	D0, V0.2D

      (2652) 0x4782a8 STR	D0, [X5]

      (2652) 0x4782ac CMP	X19, X22

      (2652) 0x4782b0 B.EQ	478080

      (2652) 0x4782b4 B	47832c

      (2652) 0x4782b8 SUB	X7, X7, X21

      (2652) 0x4782bc ADD	X19, X2, X21,LSL #3

      (2652) 0x4782c0 ADD	X21, X22, X21,LSL #3

      (2652) 0x4782c4 ADD	X22, X21, #8

      (2652) 0x4782c8 B	4782dc

        (2656) 0x4782cc SUBS	X7, X7, #2

        (2656) 0x4782d0 ADD	X19, X19, #16

        (2656) 0x4782d4 ADD	X22, X22, #16

        (2656) 0x4782d8 B.EQ	478228

        (2656) 0x4782dc LDUR	X21, [X19, #504]

        (2656) 0x4782e0 CMP	X21, X6

        (2656) 0x4782e4 CCMP	X21, X8, #8, #1

        (2656) 0x4782e8 CCMP	X21, X9, #0, #10

        (2656) 0x4782ec B.LT	478300

        (2656) 0x4782f0 LDUR	D1, [X22, #504]

        (2656) 0x4782f4 FABS	D1, D1

        (2656) 0x4782f8 FADD	D0, D0, D1

        (2656) 0x4782fc STR	D0, [X5]

        (2656) 0x478300 LDR	X21, [X19]

        (2656) 0x478304 CMP	X21, X6

        (2656) 0x478308 CCMP	X21, X8, #8, #1

        (2656) 0x47830c CCMP	X21, X9, #0, #10

        (2656) 0x478310 B.LT	4782cc

        (2656) 0x478314 LDR	D1, [X22]

        (2656) 0x478318 FABS	D1, D1

        (2656) 0x47831c FADD	D0, D0, D1

        (2656) 0x478320 STR	D0, [X5]

        (2656) 0x478324 B	4782cc

      (2652) 0x478328 ORR	X6, XZR, X23

      (2652) 0x47832c SUB	W19, W7, W6

      (2652) 0x478330 ANDS	X22, X19, #4160

      (2652) 0x478334 B.EQ	478360

      (2652) 0x478338 ORR	X19, XZR, X6

      (2652) 0x47833c HINT	#0

        (2654) 0x478340 LDR	D1, [X18, X19,LSL #3]

        (2654) 0x478344 ADD	X19, X19, #1

        (2654) 0x478348 SUBS	X22, X22, #1

        (2654) 0x47834c FABS	D1, D1

        (2654) 0x478350 FADD	D0, D0, D1

        (2654) 0x478354 STR	D0, [X5]

        (2654) 0x478358 B.NE	478340

      (2652) 0x47835c B	478364

      (2652) 0x478360 ORR	X19, XZR, X6

      (2652) 0x478364 SUB	X6, X6, X7

      (2652) 0x478368 CMN	X6, #4

      (2652) 0x47836c B.HI	478080

      (2652) 0x478370 SUB	X6, X7, X19

      (2652) 0x478374 ADD	X7, X3, X19,LSL #3

      (2652) 0x478378 HINT	#0

      (2652) 0x47837c HINT	#0

        (2653) 0x478380 LDUR	D1, [X7, #496]

        (2653) 0x478384 SUBS	X6, X6, #4

        (2653) 0x478388 FABS	D1, D1

        (2653) 0x47838c FADD	D0, D0, D1

        (2653) 0x478390 STR	D0, [X5]

        (2653) 0x478394 LDUR	D1, [X7, #504]

        (2653) 0x478398 FABS	D1, D1

        (2653) 0x47839c FADD	D0, D0, D1

        (2653) 0x4783a0 STR	D0, [X5]

        (2653) 0x4783a4 LDR	D1, [X7]

        (2653) 0x4783a8 FABS	D1, D1

        (2653) 0x4783ac FADD	D0, D0, D1

        (2653) 0x4783b0 STR	D0, [X5]

        (2653) 0x4783b4 LDR	D1, [X7, #8]

        (2653) 0x4783b8 ADD	X7, X7, #32

        (2653) 0x4783bc FABS	D1, D1

        (2653) 0x4783c0 FADD	D0, D0, D1

        (2653) 0x4783c4 STR	D0, [X5]

        (2653) 0x4783c8 B.NE	478380

      (2652) 0x4783cc B	478080

0x4783d0 HINT	#0

0x4783d4 HINT	#0

0x4783d8 HINT	#0

0x4783dc HINT	#0

    (2626) 0x4783e0 CMP	X10, #3

    (2626) 0x4783e4 B.EQ	478bb0

    (2626) 0x4783e8 CMP	X10, #4

    (2626) 0x4783ec B.NE	478e68

    (2626) 0x4783f0 CMP	X9, X8

    (2626) 0x4783f4 B.LE	478e68

    (2626) 0x4783f8 LDR	X17, [SP, #40]

    (2626) 0x4783fc LDP	X11, X14, [SP, #72]

    (2626) 0x478400 LDP	X13, X16, [SP, #24]

    (2626) 0x478404 ORR	X4, XZR, X8

    (2626) 0x478408 LDR	X15, [SP, #88]

    (2626) 0x47840c LDR	X10, [X27]

    (2626) 0x478410 ADD	X0, X10, X8,LSL #3

    (2626) 0x478414 LDR	X17, [X17]

    (2626) 0x478418 LDR	X18, [X25]

    (2626) 0x47841c LDR	X11, [X11]

    (2626) 0x478420 LDR	X12, [X24]

    (2626) 0x478424 LDR	X13, [X13]

    (2626) 0x478428 LDR	X14, [X14]

    (2626) 0x47842c LDR	X15, [X15]

    (2626) 0x478430 LDR	X16, [X16]

    (2626) 0x478434 ADD	X1, X10, X9,LSL #3

    (2626) 0x478438 ADD	X3, X18, #16

    (2626) 0x47843c ADD	X2, X17, #8

    (2626) 0x478440 B	478450

      (2636) 0x478444 ADD	X4, X4, #1

      (2636) 0x478448 CMP	X4, X9

      (2636) 0x47844c B.EQ	478e68

      (2636) 0x478450 STR	XZR, [X10, X4,LSL #3]

      (2636) 0x478454 CBZ	X11, 478508

      (2636) 0x478458 ADD	X6, X4, #1

      (2636) 0x47845c LDR	X21, [X12, X4,LSL #3]

      (2636) 0x478460 LDR	X5, [X11, X4,LSL #3]

      (2636) 0x478464 MOVI	D0, #0

      (2636) 0x478468 LDR	X7, [X12, X6,LSL #3]

      (2636) 0x47846c SUBS	X7, X7, X21

      (2636) 0x478470 B.LE	4784e0

      (2636) 0x478474 LDR	X22, [X26]

      (2636) 0x478478 MOVI	D0, #0

      (2636) 0x47847c ADD	X19, X13, X21,LSL #3

      (2636) 0x478480 ADD	X22, X22, X21,LSL #3

      (2636) 0x478484 B	478494

        (2642) 0x478488 SUBS	X7, X7, #1

        (2642) 0x47848c ADD	X22, X22, #8

        (2642) 0x478490 B.EQ	4784e0

        (2642) 0x478494 LDR	X21, [X19], #8

        (2642) 0x478498 CMP	X21, X4

        (2642) 0x47849c CCMP	X21, X8, #8, #1

        (2642) 0x4784a0 CCMP	X21, X9, #0, #10

        (2642) 0x4784a4 B.LT	478488

        (2642) 0x4784a8 LDR	X23, [X11, X21,LSL #3]

        (2642) 0x4784ac CMP	X5, X23

        (2642) 0x4784b0 B.NE	478488

        (2642) 0x4784b4 LDR	D1, [X22]

        (2642) 0x4784b8 CMP	X21, X4

        (2642) 0x4784bc FABS	D1, D1

        (2642) 0x4784c0 FMUL	D2, D1, D8

        (2642) 0x4784c4 FCSEL	D9, D9, D1, #1

        (2642) 0x4784c8 FCSEL	D2, D2, D1, #1

        (2642) 0x4784cc FADD	D0, D2, D0

        (2642) 0x4784d0 STR	D0, [X10, X4,LSL #3]

        (2642) 0x4784d4 B	478488

0x4784d8 HINT	#0

0x4784dc HINT	#0

      (2636) 0x4784e0 CBZ	X14, 47874c

      (2636) 0x4784e4 LDR	X7, [X15, X4,LSL #3]

      (2636) 0x4784e8 LDR	X6, [X15, X6,LSL #3]

      (2636) 0x4784ec CMP	X6, X7

      (2636) 0x4784f0 B.LE	47874c

      (2636) 0x4784f4 LDR	X19, [X25]

      (2636) 0x4784f8 SUB	W21, W6, W7

      (2636) 0x4784fc TBNZ	W21, #0, 47861c

      (2636) 0x478500 ORR	X21, XZR, X7

      (2636) 0x478504 B	478640

      (2636) 0x478508 ADD	X5, X4, #1

      (2636) 0x47850c LDR	X19, [X12, X4,LSL #3]

      (2636) 0x478510 MOVI	D0, #0

      (2636) 0x478514 LDR	X6, [X12, X5,LSL #3]

      (2636) 0x478518 SUBS	X6, X6, X19

      (2636) 0x47851c B.LE	478584

      (2636) 0x478520 LDR	X21, [X26]

      (2636) 0x478524 MOVI	D0, #0

      (2636) 0x478528 ADD	X7, X13, X19,LSL #3

      (2636) 0x47852c ADD	X19, X21, X19,LSL #3

      (2636) 0x478530 B	47854c

0x478534 HINT	#0

0x478538 HINT	#0

0x47853c HINT	#0

        (2640) 0x478540 ADD	X19, X19, #8

        (2640) 0x478544 SUBS	X6, X6, #1

        (2640) 0x478548 B.EQ	478584

        (2640) 0x47854c LDR	X21, [X7], #8

        (2640) 0x478550 CMP	X21, X4

        (2640) 0x478554 CCMP	X21, X8, #8, #1

        (2640) 0x478558 CCMP	X21, X9, #0, #10

        (2640) 0x47855c B.LT	478540

        (2640) 0x478560 LDR	D1, [X19]

        (2640) 0x478564 CMP	X21, X4

        (2640) 0x478568 FABS	D1, D1

        (2640) 0x47856c FMUL	D2, D1, D8

        (2640) 0x478570 FCSEL	D9, D9, D1, #1

        (2640) 0x478574 FCSEL	D2, D2, D1, #1

        (2640) 0x478578 FADD	D0, D2, D0

        (2640) 0x47857c STR	D0, [X10, X4,LSL #3]

        (2640) 0x478580 B	478540

      (2636) 0x478584 CBZ	X14, 47874c

      (2636) 0x478588 LDR	X22, [X15, X4,LSL #3]

      (2636) 0x47858c LDR	X5, [X15, X5,LSL #3]

      (2636) 0x478590 SUBS	X7, X5, X22

      (2636) 0x478594 B.LE	47874c

      (2636) 0x478598 CMP	X7, #4

      (2636) 0x47859c B.CC	4786b4

      (2636) 0x4785a0 ADD	X19, X18, X5,LSL #3

      (2636) 0x4785a4 ADD	X6, X18, X22,LSL #3

      (2636) 0x4785a8 CMP	X0, X19

      (2636) 0x4785ac CCMP	X6, X1, #2, #3

      (2636) 0x4785b0 B.CC	4786b4

      (2636) 0x4785b4 AND	X19, X7, #8062

      (2636) 0x4785b8 MOVI	V2.2D, #0

      (2636) 0x4785bc MOV	V2.D[0], V0.D[0]

      (2636) 0x4785c0 MOVI	V1.2D, #0

      (2636) 0x4785c4 ADD	X6, X22, X19

      (2636) 0x4785c8 ADD	X22, X3, X22,LSL #3

      (2636) 0x4785cc ORR	X23, XZR, X19

      (2636) 0x4785d0 HINT	#0

      (2636) 0x4785d4 HINT	#0

      (2636) 0x4785d8 HINT	#0

      (2636) 0x4785dc HINT	#0

        (2639) 0x4785e0 LDP	Q0, Q3, [X22, #2032]

        (2639) 0x4785e4 FMOV	V4.2D, #0.5000000

        (2639) 0x4785e8 ADD	X22, X22, #32

        (2639) 0x4785ec SUBS	X23, X23, #4

        (2639) 0x4785f0 FABS	V3.2D, V3.2D

        (2639) 0x4785f4 FABS	V0.2D, V0.2D

        (2639) 0x4785f8 FMLA	V1.2D, V4.2D, V3.2D

        (2639) 0x4785fc FMLA	V2.2D, V4.2D, V0.2D

        (2639) 0x478600 B.NE	4785e0

      (2636) 0x478604 FADD	V0.2D, V1.2D, V2.2D

      (2636) 0x478608 FADDP	D0, V0.2D

      (2636) 0x47860c STR	D0, [X10, X4,LSL #3]

      (2636) 0x478610 CMP	X7, X19

      (2636) 0x478614 B.NE	4786b8

      (2636) 0x478618 B	47874c

      (2636) 0x47861c LDR	X21, [X17, X7,LSL #3]

      (2636) 0x478620 LDR	X21, [X16, X21,LSL #3]

      (2636) 0x478624 CMP	X5, X21

      (2636) 0x478628 B.NE	47863c

      (2636) 0x47862c LDR	D1, [X19, X7,LSL #3]

      (2636) 0x478630 FABS	D1, D1

      (2636) 0x478634 FMADD	D0, D1, D8, D0

      (2636) 0x478638 STR	D0, [X10, X4,LSL #3]

      (2636) 0x47863c ADD	X21, X7, #1

      (2636) 0x478640 ADD	X7, X7, #1

      (2636) 0x478644 CMP	X6, X7

      (2636) 0x478648 B.EQ	47874c

      (2636) 0x47864c ADD	X19, X19, X21,LSL #3

      (2636) 0x478650 SUB	X6, X6, X21

      (2636) 0x478654 ADD	X7, X2, X21,LSL #3

      (2636) 0x478658 ADD	X19, X19, #8

      (2636) 0x47865c B	478670

        (2641) 0x478660 SUBS	X6, X6, #2

        (2641) 0x478664 ADD	X7, X7, #16

        (2641) 0x478668 ADD	X19, X19, #16

        (2641) 0x47866c B.EQ	47874c

        (2641) 0x478670 LDUR	X21, [X7, #504]

        (2641) 0x478674 LDR	X21, [X16, X21,LSL #3]

        (2641) 0x478678 CMP	X5, X21

        (2641) 0x47867c B.NE	478690

        (2641) 0x478680 LDUR	D1, [X19, #504]

        (2641) 0x478684 FABS	D1, D1

        (2641) 0x478688 FMADD	D0, D1, D8, D0

        (2641) 0x47868c STR	D0, [X10, X4,LSL #3]

        (2641) 0x478690 LDR	X21, [X7]

        (2641) 0x478694 LDR	X21, [X16, X21,LSL #3]

        (2641) 0x478698 CMP	X5, X21

        (2641) 0x47869c B.NE	478660

        (2641) 0x4786a0 LDR	D1, [X19]

        (2641) 0x4786a4 FABS	D1, D1

        (2641) 0x4786a8 FMADD	D0, D1, D8, D0

        (2641) 0x4786ac STR	D0, [X10, X4,LSL #3]

        (2641) 0x4786b0 B	478660

      (2636) 0x4786b4 ORR	X6, XZR, X22

      (2636) 0x4786b8 SUB	W7, W5, W6

      (2636) 0x4786bc ANDS	X19, X7, #4160

      (2636) 0x4786c0 B.EQ	4786e8

      (2636) 0x4786c4 ORR	X7, XZR, X6

        (2638) 0x4786c8 LDR	D1, [X18, X7,LSL #3]

        (2638) 0x4786cc ADD	X7, X7, #1

        (2638) 0x4786d0 SUBS	X19, X19, #1

        (2638) 0x4786d4 FABS	D1, D1

        (2638) 0x4786d8 FMADD	D0, D1, D8, D0

        (2638) 0x4786dc STR	D0, [X10, X4,LSL #3]

        (2638) 0x4786e0 B.NE	4786c8

      (2636) 0x4786e4 B	4786ec

      (2636) 0x4786e8 ORR	X7, XZR, X6

      (2636) 0x4786ec SUB	X6, X6, X5

      (2636) 0x4786f0 CMN	X6, #4

      (2636) 0x4786f4 B.HI	47874c

      (2636) 0x4786f8 SUB	X5, X5, X7

      (2636) 0x4786fc ADD	X6, X3, X7,LSL #3

        (2637) 0x478700 LDUR	D1, [X6, #496]

        (2637) 0x478704 SUBS	X5, X5, #4

        (2637) 0x478708 FABS	D1, D1

        (2637) 0x47870c FMADD	D0, D1, D8, D0

        (2637) 0x478710 STR	D0, [X10, X4,LSL #3]

        (2637) 0x478714 LDUR	D1, [X6, #504]

        (2637) 0x478718 FABS	D1, D1

        (2637) 0x47871c FMADD	D0, D1, D8, D0

        (2637) 0x478720 STR	D0, [X10, X4,LSL #3]

        (2637) 0x478724 LDR	D1, [X6]

        (2637) 0x478728 FABS	D1, D1

        (2637) 0x47872c FMADD	D0, D1, D8, D0

        (2637) 0x478730 STR	D0, [X10, X4,LSL #3]

        (2637) 0x478734 LDR	D1, [X6, #8]

        (2637) 0x478738 ADD	X6, X6, #32

        (2637) 0x47873c FABS	D1, D1

        (2637) 0x478740 FMADD	D0, D1, D8, D0

        (2637) 0x478744 STR	D0, [X10, X4,LSL #3]

        (2637) 0x478748 B.NE	478700

      (2636) 0x47874c FMOV	D1, X20

      (2636) 0x478750 FMUL	D1, D9, D1

      (2636) 0x478754 FCMP	D0, D1

      (2636) 0x478758 B.GT	478444

      (2636) 0x47875c STR	D9, [X10, X4,LSL #3]

      (2636) 0x478760 B	478444

    (2626) 0x478764 CMP	X9, X8

    (2626) 0x478768 B.LE	478e68

    (2626) 0x47876c LDP	X13, X16, [SP, #24]

    (2626) 0x478770 LDR	X17, [SP, #40]

    (2626) 0x478774 LDP	X11, X14, [SP, #72]

    (2626) 0x478778 ORR	X30, XZR, X8

    (2626) 0x47877c LDR	X15, [SP, #88]

    (2626) 0x478780 LDR	X10, [X27]

    (2626) 0x478784 ADD	X1, X10, #8

    (2626) 0x478788 LDR	X13, [X13]

    (2626) 0x47878c LDR	X17, [X17]

    (2626) 0x478790 LDR	X18, [X26]

    (2626) 0x478794 LDR	X0, [X25]

    (2626) 0x478798 LDR	X11, [X11]

    (2626) 0x47879c LDR	X12, [X24]

    (2626) 0x4787a0 LDR	X14, [X14]

    (2626) 0x4787a4 LDR	X15, [X15]

    (2626) 0x4787a8 LDR	X16, [X16]

    (2626) 0x4787ac ADD	X4, X18, #16

    (2626) 0x4787b0 ADD	X5, X0, #16

    (2626) 0x4787b4 ADD	X2, X13, #8

    (2626) 0x4787b8 ADD	X3, X17, #8

    (2626) 0x4787bc B	4787cc

      (2643) 0x4787c0 ORR	X30, XZR, X6

      (2643) 0x4787c4 CMP	X6, X9

      (2643) 0x4787c8 B.EQ	478e60

      (2643) 0x4787cc ADD	X7, X10, X30,LSL #3

      (2643) 0x4787d0 STR	XZR, [X7]

      (2643) 0x4787d4 CBZ	X11, 478808

      (2643) 0x4787d8 ADD	X6, X30, #1

      (2643) 0x4787dc LDR	X19, [X11, X30,LSL #3]

      (2643) 0x4787e0 LDR	X23, [X12, X30,LSL #3]

      (2643) 0x4787e4 MOVI	D0, #0

      (2643) 0x4787e8 LDR	X22, [X12, X6,LSL #3]

      (2643) 0x4787ec CMP	X22, X23

      (2643) 0x4787f0 B.LE	4789e4

      (2643) 0x4787f4 LDR	X27, [X26]

      (2643) 0x4787f8 SUB	W21, W22, W23

      (2643) 0x4787fc TBNZ	W21, #0, 4789b8

      (2643) 0x478800 ORR	X21, XZR, X23

      (2643) 0x478804 B	4789d8

      (2643) 0x478808 ADD	X6, X30, #1

      (2643) 0x47880c LDR	X22, [X12, X30,LSL #3]

      (2643) 0x478810 MOVI	D0, #0

      (2643) 0x478814 LDR	X19, [X12, X6,LSL #3]

      (2643) 0x478818 SUBS	X23, X19, X22

      (2643) 0x47881c B.LE	47892c

      (2643) 0x478820 MOVI	D0, #0

      (2643) 0x478824 CMP	X23, #6

      (2643) 0x478828 B.CC	478898

      (2643) 0x47882c ADD	X27, X18, X19,LSL #3

      (2643) 0x478830 ADD	X21, X1, X30,LSL #3

      (2643) 0x478834 ADD	X24, X18, X22,LSL #3

      (2643) 0x478838 CMP	X7, X27

      (2643) 0x47883c CCMP	X24, X21, #2, #3

      (2643) 0x478840 B.CC	478898

      (2643) 0x478844 AND	X21, X23, #8062

      (2643) 0x478848 MOVI	V0.2D, #0

      (2643) 0x47884c MOVI	V1.2D, #0

      (2643) 0x478850 ADD	X24, X22, X21

      (2643) 0x478854 ADD	X22, X4, X22,LSL #3

      (2643) 0x478858 ORR	X27, XZR, X21

      (2643) 0x47885c HINT	#0

        (2649) 0x478860 LDP	Q2, Q3, [X22, #2032]

        (2649) 0x478864 ADD	X22, X22, #32

        (2649) 0x478868 SUBS	X27, X27, #4

        (2649) 0x47886c FABS	V3.2D, V3.2D

        (2649) 0x478870 FABS	V2.2D, V2.2D

        (2649) 0x478874 FADD	V1.2D, V1.2D, V3.2D

        (2649) 0x478878 FADD	V0.2D, V0.2D, V2.2D

        (2649) 0x47887c B.NE	478860

      (2643) 0x478880 FADD	V0.2D, V1.2D, V0.2D

      (2643) 0x478884 ORR	X22, XZR, X24

      (2643) 0x478888 FADDP	D0, V0.2D

      (2643) 0x47888c STR	D0, [X7]

      (2643) 0x478890 CMP	X23, X21

      (2643) 0x478894 B.EQ	47892c

      (2643) 0x478898 SUB	W21, W19, W22

      (2643) 0x47889c ORR	X23, XZR, X22

      (2643) 0x4788a0 ANDS	X24, X21, #4160

      (2643) 0x4788a4 B.EQ	4788c4

        (2648) 0x4788a8 LDR	D1, [X18, X23,LSL #3]

        (2648) 0x4788ac ADD	X23, X23, #1

        (2648) 0x4788b0 SUBS	X24, X24, #1

        (2648) 0x4788b4 FABS	D1, D1

        (2648) 0x4788b8 FADD	D0, D0, D1

        (2648) 0x4788bc STR	D0, [X7]

        (2648) 0x4788c0 B.NE	4788a8

      (2643) 0x4788c4 SUB	X21, X22, X19

      (2643) 0x4788c8 CMN	X21, #4

      (2643) 0x4788cc B.HI	47892c

      (2643) 0x4788d0 SUB	X19, X19, X23

      (2643) 0x4788d4 ADD	X22, X4, X23,LSL #3

      (2643) 0x4788d8 HINT	#0

      (2643) 0x4788dc HINT	#0

        (2647) 0x4788e0 LDUR	D1, [X22, #496]

        (2647) 0x4788e4 SUBS	X19, X19, #4

        (2647) 0x4788e8 FABS	D1, D1

        (2647) 0x4788ec FADD	D0, D0, D1

        (2647) 0x4788f0 STR	D0, [X7]

        (2647) 0x4788f4 LDUR	D1, [X22, #504]

        (2647) 0x4788f8 FABS	D1, D1

        (2647) 0x4788fc FADD	D0, D0, D1

        (2647) 0x478900 STR	D0, [X7]

        (2647) 0x478904 LDR	D1, [X22]

        (2647) 0x478908 FABS	D1, D1

        (2647) 0x47890c FADD	D0, D0, D1

        (2647) 0x478910 STR	D0, [X7]

        (2647) 0x478914 LDR	D1, [X22, #8]

        (2647) 0x478918 ADD	X22, X22, #32

        (2647) 0x47891c FABS	D1, D1

        (2647) 0x478920 FADD	D0, D0, D1

        (2647) 0x478924 STR	D0, [X7]

        (2647) 0x478928 B.NE	4788e0

      (2643) 0x47892c CBZ	X14, 4787c0

      (2643) 0x478930 LDR	X24, [X15, X30,LSL #3]

      (2643) 0x478934 LDR	X19, [X15, X6,LSL #3]

      (2643) 0x478938 SUBS	X22, X19, X24

      (2643) 0x47893c B.LE	4787c0

      (2643) 0x478940 CMP	X22, #6

      (2643) 0x478944 B.CC	478b14

      (2643) 0x478948 ADD	X27, X0, X19,LSL #3

      (2643) 0x47894c ADD	X21, X1, X30,LSL #3

      (2643) 0x478950 ADD	X23, X0, X24,LSL #3

      (2643) 0x478954 CMP	X7, X27

      (2643) 0x478958 CCMP	X23, X21, #2, #3

      (2643) 0x47895c B.CC	478b14

      (2643) 0x478960 AND	X23, X22, #8062

      (2643) 0x478964 MOVI	V2.2D, #0

      (2643) 0x478968 MOV	V2.D[0], V0.D[0]

      (2643) 0x47896c MOVI	V1.2D, #0

      (2643) 0x478970 ADD	X30, X24, X23

      (2643) 0x478974 ADD	X24, X5, X24,LSL #3

      (2643) 0x478978 ORR	X21, XZR, X23

      (2643) 0x47897c HINT	#0

        (2646) 0x478980 LDP	Q0, Q3, [X24, #2032]

        (2646) 0x478984 ADD	X24, X24, #32

        (2646) 0x478988 SUBS	X21, X21, #4

        (2646) 0x47898c FABS	V3.2D, V3.2D

        (2646) 0x478990 FABS	V0.2D, V0.2D

        (2646) 0x478994 FADD	V1.2D, V1.2D, V3.2D

        (2646) 0x478998 FADD	V2.2D, V2.2D, V0.2D

        (2646) 0x47899c B.NE	478980

      (2643) 0x4789a0 FADD	V0.2D, V1.2D, V2.2D

      (2643) 0x4789a4 FADDP	D0, V0.2D

      (2643) 0x4789a8 STR	D0, [X7]

      (2643) 0x4789ac CMP	X22, X23

      (2643) 0x4789b0 B.EQ	4787c0

      (2643) 0x4789b4 B	478b18

      (2643) 0x4789b8 LDR	X21, [X13, X23,LSL #3]

      (2643) 0x4789bc LDR	X21, [X11, X21,LSL #3]

      (2643) 0x4789c0 CMP	X19, X21

      (2643) 0x4789c4 B.NE	4789d4

      (2643) 0x4789c8 LDR	D0, [X27, X23,LSL #3]

      (2643) 0x4789cc FABS	D0, D0

      (2643) 0x4789d0 STR	D0, [X7]

      (2643) 0x4789d4 ADD	X21, X23, #1

      (2643) 0x4789d8 ADD	X23, X23, #1

      (2643) 0x4789dc CMP	X22, X23

      (2643) 0x4789e0 B.NE	478a0c

      (2643) 0x4789e4 CBZ	X14, 4787c0

      (2643) 0x4789e8 LDR	X23, [X15, X30,LSL #3]

      (2643) 0x4789ec LDR	X22, [X15, X6,LSL #3]

      (2643) 0x4789f0 CMP	X22, X23

      (2643) 0x4789f4 B.LE	4787c0

      (2643) 0x4789f8 LDR	X27, [X25]

      (2643) 0x4789fc SUB	W21, W22, W23

      (2643) 0x478a00 TBNZ	W21, #0, 478a74

      (2643) 0x478a04 ORR	X21, XZR, X23

      (2643) 0x478a08 B	478a98

      (2643) 0x478a0c SUB	X22, X22, X21

      (2643) 0x478a10 ADD	X23, X2, X21,LSL #3

      (2643) 0x478a14 ADD	X21, X27, X21,LSL #3

      (2643) 0x478a18 ADD	X27, X21, #8

      (2643) 0x478a1c B	478a30

        (2651) 0x478a20 SUBS	X22, X22, #2

        (2651) 0x478a24 ADD	X23, X23, #16

        (2651) 0x478a28 ADD	X27, X27, #16

        (2651) 0x478a2c B.EQ	4789e4

        (2651) 0x478a30 LDUR	X21, [X23, #504]

        (2651) 0x478a34 LDR	X21, [X11, X21,LSL #3]

        (2651) 0x478a38 CMP	X19, X21

        (2651) 0x478a3c B.NE	478a50

        (2651) 0x478a40 LDUR	D1, [X27, #504]

        (2651) 0x478a44 FABS	D1, D1

        (2651) 0x478a48 FADD	D0, D0, D1

        (2651) 0x478a4c STR	D0, [X7]

        (2651) 0x478a50 LDR	X21, [X23]

        (2651) 0x478a54 LDR	X21, [X11, X21,LSL #3]

        (2651) 0x478a58 CMP	X19, X21

        (2651) 0x478a5c B.NE	478a20

        (2651) 0x478a60 LDR	D1, [X27]

        (2651) 0x478a64 FABS	D1, D1

        (2651) 0x478a68 FADD	D0, D0, D1

        (2651) 0x478a6c STR	D0, [X7]

        (2651) 0x478a70 B	478a20

      (2643) 0x478a74 LDR	X21, [X17, X23,LSL #3]

      (2643) 0x478a78 LDR	X21, [X16, X21,LSL #3]

      (2643) 0x478a7c CMP	X19, X21

      (2643) 0x478a80 B.NE	478a94

      (2643) 0x478a84 LDR	D1, [X27, X23,LSL #3]

      (2643) 0x478a88 FABS	D1, D1

      (2643) 0x478a8c FADD	D0, D0, D1

      (2643) 0x478a90 STR	D0, [X7]

      (2643) 0x478a94 ADD	X21, X23, #1

      (2643) 0x478a98 ADD	X23, X23, #1

      (2643) 0x478a9c CMP	X22, X23

      (2643) 0x478aa0 B.EQ	4787c0

      (2643) 0x478aa4 SUB	X22, X22, X21

      (2643) 0x478aa8 ADD	X23, X3, X21,LSL #3

      (2643) 0x478aac ADD	X21, X27, X21,LSL #3

      (2643) 0x478ab0 ADD	X27, X21, #8

      (2643) 0x478ab4 B	478ad0

0x478ab8 HINT	#0

0x478abc HINT	#0

        (2650) 0x478ac0 SUBS	X22, X22, #2

        (2650) 0x478ac4 ADD	X23, X23, #16

        (2650) 0x478ac8 ADD	X27, X27, #16

        (2650) 0x478acc B.EQ	4787c0

        (2650) 0x478ad0 LDUR	X21, [X23, #504]

        (2650) 0x478ad4 LDR	X21, [X16, X21,LSL #3]

        (2650) 0x478ad8 CMP	X19, X21

        (2650) 0x478adc B.NE	478af0

        (2650) 0x478ae0 LDUR	D1, [X27, #504]

        (2650) 0x478ae4 FABS	D1, D1

        (2650) 0x478ae8 FADD	D0, D0, D1

        (2650) 0x478aec STR	D0, [X7]

        (2650) 0x478af0 LDR	X21, [X23]

        (2650) 0x478af4 LDR	X21, [X16, X21,LSL #3]

        (2650) 0x478af8 CMP	X19, X21

        (2650) 0x478afc B.NE	478ac0

        (2650) 0x478b00 LDR	D1, [X27]

        (2650) 0x478b04 FABS	D1, D1

        (2650) 0x478b08 FADD	D0, D0, D1

        (2650) 0x478b0c STR	D0, [X7]

        (2650) 0x478b10 B	478ac0

      (2643) 0x478b14 ORR	X30, XZR, X24

      (2643) 0x478b18 SUB	W21, W19, W30

      (2643) 0x478b1c ORR	X22, XZR, X30

      (2643) 0x478b20 ANDS	X23, X21, #4160

      (2643) 0x478b24 B.EQ	478b44

        (2645) 0x478b28 LDR	D1, [X0, X22,LSL #3]

        (2645) 0x478b2c ADD	X22, X22, #1

        (2645) 0x478b30 SUBS	X23, X23, #1

        (2645) 0x478b34 FABS	D1, D1

        (2645) 0x478b38 FADD	D0, D0, D1

        (2645) 0x478b3c STR	D0, [X7]

        (2645) 0x478b40 B.NE	478b28

      (2643) 0x478b44 SUB	X21, X30, X19

      (2643) 0x478b48 CMN	X21, #4

      (2643) 0x478b4c B.HI	4787c0

      (2643) 0x478b50 SUB	X19, X19, X22

      (2643) 0x478b54 ADD	X22, X5, X22,LSL #3

      (2643) 0x478b58 HINT	#0

      (2643) 0x478b5c HINT	#0

        (2644) 0x478b60 LDUR	D1, [X22, #496]

        (2644) 0x478b64 SUBS	X19, X19, #4

        (2644) 0x478b68 FABS	D1, D1

        (2644) 0x478b6c FADD	D0, D0, D1

        (2644) 0x478b70 STR	D0, [X7]

        (2644) 0x478b74 LDUR	D1, [X22, #504]

        (2644) 0x478b78 FABS	D1, D1

        (2644) 0x478b7c FADD	D0, D0, D1

        (2644) 0x478b80 STR	D0, [X7]

        (2644) 0x478b84 LDR	D1, [X22]

        (2644) 0x478b88 FABS	D1, D1

        (2644) 0x478b8c FADD	D0, D0, D1

        (2644) 0x478b90 STR	D0, [X7]

        (2644) 0x478b94 LDR	D1, [X22, #8]

        (2644) 0x478b98 ADD	X22, X22, #32

        (2644) 0x478b9c FABS	D1, D1

        (2644) 0x478ba0 FADD	D0, D0, D1

        (2644) 0x478ba4 STR	D0, [X7]

        (2644) 0x478ba8 B.NE	478b60

      (2643) 0x478bac B	4787c0

    (2626) 0x478bb0 CMP	X9, X8

    (2626) 0x478bb4 B.LE	478e68

    (2626) 0x478bb8 LDR	X11, [X24]

    (2626) 0x478bbc LDP	X13, X14, [SP, #80]

    (2626) 0x478bc0 LDR	X10, [X27]

    (2626) 0x478bc4 UBFM	X16, X8, #61, #60

    (2626) 0x478bc8 ORR	X2, XZR, X8

    (2626) 0x478bcc ADD	X17, X10, X9,LSL #3

    (2626) 0x478bd0 LDR	X12, [X26]

    (2626) 0x478bd4 LDR	X15, [X25]

    (2626) 0x478bd8 LDR	X13, [X13]

    (2626) 0x478bdc LDR	X14, [X14]

    (2626) 0x478be0 LDR	X0, [X11, X16]

    (2626) 0x478be4 ADD	X16, X10, X8,LSL #3

    (2626) 0x478be8 ADD	X18, X12, #16

    (2626) 0x478bec ADD	X1, X15, #16

    (2626) 0x478bf0 B	478c08

0x478bf4 HINT	#0

0x478bf8 HINT	#0

0x478bfc HINT	#0

      (2629) 0x478c00 CMP	X2, X9

      (2629) 0x478c04 B.EQ	478e68

      (2629) 0x478c08 ORR	X3, XZR, X2

      (2629) 0x478c0c STR	XZR, [X10, X2,LSL #3]

      (2629) 0x478c10 ADD	X2, X2, #1

      (2629) 0x478c14 ORR	X7, XZR, X0

      (2629) 0x478c18 MOVI	D0, #0

      (2629) 0x478c1c LDR	X0, [X11, X2,LSL #3]

      (2629) 0x478c20 SUBS	X5, X0, X7

      (2629) 0x478c24 B.LE	478d3c

      (2629) 0x478c28 MOVI	D0, #0

      (2629) 0x478c2c CMP	X5, #4

      (2629) 0x478c30 B.CC	478ca0

      (2629) 0x478c34 ADD	X6, X12, X0,LSL #3

      (2629) 0x478c38 ADD	X4, X12, X7,LSL #3

      (2629) 0x478c3c CMP	X16, X6

      (2629) 0x478c40 CCMP	X4, X17, #2, #3

      (2629) 0x478c44 B.CC	478ca0

      (2629) 0x478c48 AND	X6, X5, #8062

      (2629) 0x478c4c MOVI	V0.2D, #0

      (2629) 0x478c50 MOVI	V1.2D, #0

      (2629) 0x478c54 ADD	X4, X7, X6

      (2629) 0x478c58 ADD	X7, X18, X7,LSL #3

      (2629) 0x478c5c ORR	X19, XZR, X6

        (2635) 0x478c60 LDP	Q2, Q3, [X7, #2032]

        (2635) 0x478c64 ADD	X7, X7, #32

        (2635) 0x478c68 SUBS	X19, X19, #4

        (2635) 0x478c6c FMLA	V1.2D, V3.2D, V3.2D

        (2635) 0x478c70 FMLA	V0.2D, V2.2D, V2.2D

        (2635) 0x478c74 B.NE	478c60

      (2629) 0x478c78 FADD	V0.2D, V1.2D, V0.2D

      (2629) 0x478c7c FADDP	D0, V0.2D

      (2629) 0x478c80 STR	D0, [X10, X3,LSL #3]

      (2629) 0x478c84 CMP	X5, X6

      (2629) 0x478c88 B.NE	478ca4

      (2629) 0x478c8c B	478d3c

0x478c90 HINT	#0

0x478c94 HINT	#0

0x478c98 HINT	#0

0x478c9c HINT	#0

      (2629) 0x478ca0 ORR	X4, XZR, X7

      (2629) 0x478ca4 SUB	W5, W0, W4

      (2629) 0x478ca8 ANDS	X6, X5, #4160

      (2629) 0x478cac B.EQ	478cdc

      (2629) 0x478cb0 ORR	X5, XZR, X4

      (2629) 0x478cb4 HINT	#0

      (2629) 0x478cb8 HINT	#0

      (2629) 0x478cbc HINT	#0

        (2634) 0x478cc0 LDR	D1, [X12, X5,LSL #3]

        (2634) 0x478cc4 ADD	X5, X5, #1

        (2634) 0x478cc8 SUBS	X6, X6, #1

        (2634) 0x478ccc FMADD	D0, D1, D1, D0

        (2634) 0x478cd0 STR	D0, [X10, X3,LSL #3]

        (2634) 0x478cd4 B.NE	478cc0

      (2629) 0x478cd8 B	478ce0

      (2629) 0x478cdc ORR	X5, XZR, X4

      (2629) 0x478ce0 SUB	X4, X4, X0

      (2629) 0x478ce4 CMN	X4, #4

      (2629) 0x478ce8 B.HI	478d3c

      (2629) 0x478cec SUB	X4, X0, X5

      (2629) 0x478cf0 ADD	X5, X18, X5,LSL #3

      (2629) 0x478cf4 HINT	#0

      (2629) 0x478cf8 HINT	#0

      (2629) 0x478cfc HINT	#0

        (2633) 0x478d00 LDUR	D1, [X5, #496]

        (2633) 0x478d04 SUBS	X4, X4, #4

        (2633) 0x478d08 FMADD	D0, D1, D1, D0

        (2633) 0x478d0c STR	D0, [X10, X3,LSL #3]

        (2633) 0x478d10 LDUR	D1, [X5, #504]

        (2633) 0x478d14 FMADD	D0, D1, D1, D0

        (2633) 0x478d18 STR	D0, [X10, X3,LSL #3]

        (2633) 0x478d1c LDR	D1, [X5]

        (2633) 0x478d20 FMADD	D0, D1, D1, D0

        (2633) 0x478d24 STR	D0, [X10, X3,LSL #3]

        (2633) 0x478d28 LDR	D1, [X5, #8]

        (2633) 0x478d2c ADD	X5, X5, #32

        (2633) 0x478d30 FMADD	D0, D1, D1, D0

        (2633) 0x478d34 STR	D0, [X10, X3,LSL #3]

        (2633) 0x478d38 B.NE	478d00

      (2629) 0x478d3c CBZ	X13, 478c00

      (2629) 0x478d40 LDR	X19, [X14, X3,LSL #3]

      (2629) 0x478d44 LDR	X4, [X14, X2,LSL #3]

      (2629) 0x478d48 SUBS	X6, X4, X19

      (2629) 0x478d4c B.LE	478c00

      (2629) 0x478d50 CMP	X6, #4

      (2629) 0x478d54 B.CC	478dc0

      (2629) 0x478d58 ADD	X7, X15, X4,LSL #3

      (2629) 0x478d5c ADD	X5, X15, X19,LSL #3

      (2629) 0x478d60 CMP	X16, X7

      (2629) 0x478d64 CCMP	X5, X17, #2, #3

      (2629) 0x478d68 B.CC	478dc0

      (2629) 0x478d6c AND	X7, X6, #8062

      (2629) 0x478d70 MOVI	V2.2D, #0

      (2629) 0x478d74 MOV	V2.D[0], V0.D[0]

      (2629) 0x478d78 MOVI	V1.2D, #0

      (2629) 0x478d7c ADD	X5, X19, X7

      (2629) 0x478d80 ADD	X19, X1, X19,LSL #3

      (2629) 0x478d84 ORR	X21, XZR, X7

        (2632) 0x478d88 LDP	Q0, Q3, [X19, #2032]

        (2632) 0x478d8c ADD	X19, X19, #32

        (2632) 0x478d90 SUBS	X21, X21, #4

        (2632) 0x478d94 FMLA	V1.2D, V3.2D, V3.2D

        (2632) 0x478d98 FMLA	V2.2D, V0.2D, V0.2D

        (2632) 0x478d9c B.NE	478d88

      (2629) 0x478da0 FADD	V0.2D, V1.2D, V2.2D

      (2629) 0x478da4 FADDP	D0, V0.2D

      (2629) 0x478da8 STR	D0, [X10, X3,LSL #3]

      (2629) 0x478dac CMP	X6, X7

      (2629) 0x478db0 B.EQ	478c00

      (2629) 0x478db4 B	478dc4

0x478db8 HINT	#0

0x478dbc HINT	#0

      (2629) 0x478dc0 ORR	X5, XZR, X19

      (2629) 0x478dc4 SUB	W6, W4, W5

      (2629) 0x478dc8 ANDS	X7, X6, #4160

      (2629) 0x478dcc B.EQ	478dfc

      (2629) 0x478dd0 ORR	X6, XZR, X5

      (2629) 0x478dd4 HINT	#0

      (2629) 0x478dd8 HINT	#0

      (2629) 0x478ddc HINT	#0

        (2631) 0x478de0 LDR	D1, [X15, X6,LSL #3]

        (2631) 0x478de4 ADD	X6, X6, #1

        (2631) 0x478de8 SUBS	X7, X7, #1

        (2631) 0x478dec FMADD	D0, D1, D1, D0

        (2631) 0x478df0 STR	D0, [X10, X3,LSL #3]

        (2631) 0x478df4 B.NE	478de0

      (2629) 0x478df8 B	478e00

      (2629) 0x478dfc ORR	X6, XZR, X5

      (2629) 0x478e00 SUB	X5, X5, X4

      (2629) 0x478e04 CMN	X5, #4

      (2629) 0x478e08 B.HI	478c00

      (2629) 0x478e0c SUB	X4, X4, X6

      (2629) 0x478e10 ADD	X5, X1, X6,LSL #3

      (2629) 0x478e14 HINT	#0

      (2629) 0x478e18 HINT	#0

      (2629) 0x478e1c HINT	#0

        (2630) 0x478e20 LDUR	D1, [X5, #496]

        (2630) 0x478e24 SUBS	X4, X4, #4

        (2630) 0x478e28 FMADD	D0, D1, D1, D0

        (2630) 0x478e2c STR	D0, [X10, X3,LSL #3]

        (2630) 0x478e30 LDUR	D1, [X5, #504]

        (2630) 0x478e34 FMADD	D0, D1, D1, D0

        (2630) 0x478e38 STR	D0, [X10, X3,LSL #3]

        (2630) 0x478e3c LDR	D1, [X5]

        (2630) 0x478e40 FMADD	D0, D1, D1, D0

        (2630) 0x478e44 STR	D0, [X10, X3,LSL #3]

        (2630) 0x478e48 LDR	D1, [X5, #8]

        (2630) 0x478e4c ADD	X5, X5, #32

        (2630) 0x478e50 FMADD	D0, D1, D1, D0

        (2630) 0x478e54 STR	D0, [X10, X3,LSL #3]

        (2630) 0x478e58 B.NE	478e20

      (2629) 0x478e5c B	478c00

    (2626) 0x478e60 LDP	X27, X24, [SP, #56]

    (2626) 0x478e64 LDR	X30, [SP, #48]

    (2626) 0x478e68 SUBS	X10, X9, X8

    (2626) 0x478e6c B.LE	477fc0

  (2628) 0x478e70 LDR	X11, [X26]

  (2628) 0x478e74 LDR	X13, [X24]

  (2628) 0x478e78 LDR	X14, [X27]

  (2628) 0x478e7c ORR	X15, XZR, X8

  (2628) 0x478e80 TBZ	W10, #0, 478ea4

  (2628) 0x478e84 LDR	X12, [X13, X8,LSL #3]

  (2628) 0x478e88 LDR	D0, [X11, X12,LSL #3]

  (2628) 0x478e8c FCMP	D0, #0

  (2628) 0x478e90 B.GE	478ea0

  (2628) 0x478e94 LDR	D0, [X14, X8,LSL #3]

  (2628) 0x478e98 FNEG	D0, D0

  (2628) 0x478e9c STR	D0, [X14, X8,LSL #3]

  (2628) 0x478ea0 ADD	X15, X8, #1

  (2628) 0x478ea4 ADD	X12, X8, #1

  (2628) 0x478ea8 CMP	X9, X12

  (2628) 0x478eac B.NE	478ee0

  (2628) 0x478eb0 CMP	X9, X8

  (2628) 0x478eb4 B.LE	477fc0

  (2628) 0x478eb8 LDR	X9, [X27]

  (2628) 0x478ebc ADD	X8, X9, X8,LSL #3

    (2659) 0x478ec0 LDR	D0, [X8]

    (2659) 0x478ec4 FCMP	D0, #0

    (2659) 0x478ec8 B.EQ	477fa0

    (2659) 0x478ecc ADD	X8, X8, #8

    (2659) 0x478ed0 SUBS	X10, X10, #1

    (2659) 0x478ed4 B.NE	478ec0

  (2628) 0x478ed8 B	477fc0

0x478edc HINT	#0

(2627) 0x478ee0 ADD	X13, X13, X15,LSL #3

(2627) 0x478ee4 ADD	X14, X14, X15,LSL #3

(2627) 0x478ee8 SUB	X12, X9, X15

(2627) 0x478eec ADD	X13, X13, #8

(2627) 0x478ef0 ADD	X14, X14, #8

(2627) 0x478ef4 B	478f10

0x478ef8 HINT	#0

0x478efc HINT	#0

(2627) 0x478f00 SUBS	X12, X12, #2

(2627) 0x478f04 ADD	X13, X13, #16

(2627) 0x478f08 ADD	X14, X14, #16

(2627) 0x478f0c B.EQ	478eb0

(2627) 0x478f10 LDUR	X15, [X13, #504]

(2627) 0x478f14 LDR	D0, [X11, X15,LSL #3]

(2627) 0x478f18 FCMP	D0, #0

(2627) 0x478f1c B.GE	478f2c

(2627) 0x478f20 LDUR	D0, [X14, #504]

(2627) 0x478f24 FNEG	D0, D0

(2627) 0x478f28 STUR	D0, [X14, #504]

(2627) 0x478f2c LDR	X15, [X13]

(2627) 0x478f30 LDR	D0, [X11, X15,LSL #3]

(2627) 0x478f34 FCMP	D0, #0

(2627) 0x478f38 B.GE	478f00

(2627) 0x478f3c LDR	D0, [X14]

(2627) 0x478f40 FNEG	D0, D0

(2627) 0x478f44 STR	D0, [X14]

(2627) 0x478f48 B	478f00

0x478f4c HINT	#0

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	ams.c:3363-3540
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3363-3409,3416-3451,3458-3481,3493-3507,3517-3540.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.00 to 1.17 cycles (7.71x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 64% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 9.00 to 6.75 cycles (1.33x speedup).

Details

3% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
5% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 9.00 to 0.50 cycles (18.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 52 bytes. The binary function is storing 216 bytes.

General properties

nb instructions	69
loop length	276
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	3.25	3.25	3.17	3.17	3.08	3.08	0.50	0.50	0.00	0.00	9.00	9.00	5.00	8.50	8.50
cycles	1.50	1.50	3.25	3.25	3.17	3.17	3.08	3.08	0.50	0.50	0.00	0.00	9.00	9.00	5.00	8.50	8.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.50
Overall L1	9.00

Vectorization ratios

all	3%
load	0%
store	5%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.00 cycles. At this rate:

6% of peak load performance is reached (5.78 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
50% of peak store performance is reached (24.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 477e80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #272	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP D9, D8, [SP, #160]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP X29, X30, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #176	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X6, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X2, X3, [X29, #952]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUBS X19, X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 477f40 <hypre_ParCSRComputeL1NormsThreads.omp_outlined+0xc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X9, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X10, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X11, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <4deecc>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #752	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X3, X29, #52	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X4, X29, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X5, X29, #40	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, XZR, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR WZR, [X29, #460]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X10, X9, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB X6, X29, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X11, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR W1, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 40fa00 <@plt_start@+0x610>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X28, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X30, X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X24, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X8, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X8, X8, X19, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X28, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 477f64 <hypre_ParCSRComputeL1NormsThreads.omp_outlined+0xe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	ams.c:3363-3540
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3363-3409,3416-3451,3458-3481,3493-3507,3517-3540.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.00 to 1.17 cycles (7.71x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

3% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
5% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 9.00 to 0.50 cycles (18.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 52 bytes. The binary function is storing 216 bytes.

General properties

nb instructions	69
loop length	276
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	3.25	3.25	3.17	3.17	3.08	3.08	0.50	0.50	0.00	0.00	9.00	9.00	5.00	8.50	8.50
cycles	1.50	1.50	3.25	3.25	3.17	3.17	3.08	3.08	0.50	0.50	0.00	0.00	9.00	9.00	5.00	8.50	8.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.50
Overall L1	9.00

Vectorization ratios

all	3%
load	0%
store	5%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.00 cycles. At this rate:

6% of peak load performance is reached (5.78 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
50% of peak store performance is reached (24.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 477e80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #272	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP D9, D8, [SP, #160]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP X29, X30, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #176	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X6, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X2, X3, [X29, #952]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUBS X19, X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 477f40 <hypre_ParCSRComputeL1NormsThreads.omp_outlined+0xc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X9, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X10, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X11, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <4deecc>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #752	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X3, X29, #52	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X4, X29, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X5, X29, #40	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, XZR, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR WZR, [X29, #460]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X10, X9, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB X6, X29, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X11, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR W1, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 40fa00 <@plt_start@+0x610>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X28, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X30, X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X24, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X8, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X8, X8, X19, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X28, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 477f64 <hypre_ParCSRComputeL1NormsThreads.omp_outlined+0xe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
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HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

▶Scalability Runs Description

Run 1x1	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_NUM_THREADS: 1OMP_PLACES: threads
Run 1x2	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 2OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x4	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 4OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x8	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 8OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x16	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 16OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x24	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 24OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x32	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 32OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x40	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 40OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x48	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 48OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x56	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 56OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x64	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 64OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x72	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 72OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x80	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 80OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x88	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 88OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x96	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 96OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads

(1x1) Efficiency	(1x1) Potential Speed-Up (%)	(1x2) Efficiency	(1x2) Potential Speed-Up (%)	(1x4) Efficiency	(1x4) Potential Speed-Up (%)	(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x16) Efficiency	(1x16) Potential Speed-Up (%)	(1x24) Efficiency	(1x24) Potential Speed-Up (%)	(1x32) Efficiency	(1x32) Potential Speed-Up (%)	(1x40) Efficiency	(1x40) Potential Speed-Up (%)	(1x48) Efficiency	(1x48) Potential Speed-Up (%)	(1x56) Efficiency	(1x56) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)	(1x72) Efficiency	(1x72) Potential Speed-Up (%)	(1x80) Efficiency	(1x80) Potential Speed-Up (%)	(1x88) Efficiency	(1x88) Potential Speed-Up (%)	(1x96) Efficiency	(1x96) Potential Speed-Up (%)
		1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x1
1x2	2	1	1	2	0.42999997735023	0.28698295354843
1x4	4	1	1	4	0.23499995470047	0.2938187122345
1x8	8	1	1	8	0.14500001072884	0.30874660611153
1x16	16	1	1	16	0.084999985992908	0.27118647098541
1x24	24	1	1	24	0.069999992847443	0.26590815186501
1x32	32	1	1	32	0.064999990165234	0.26160621643066
1x40	40	1	1	40	0.064999997615814	0.26953741908073
1x48	48	1	1	48	0.059999998658895	0.28269430994987
1x56	56	1	1	56	0.055000003427267	0.27493339776993
1x64	64	1	1	64	0.054999999701977	0.27337029576302
1x72	72	1	1	72	0.050000004470348	0.27701047062874
1x80	80	1	1	80	0.050000004470348	0.27777311205864
1x88	88	1	1	88	0.050000004470348	0.27169990539551
1x96	96	1	1	96	0.045000001788139	0.25218030810356

Name	Coverage (%)	Time (s)
▼hypre_ParCSRComputeL1NormsThreads.omp_outlined–	0.00	0.00
▼Loop 2627 - ams.c:3363-3540 - exec–	0.00	0.00
▼Loop 2628 - ams.c:3363-3540 - exec–	0.00	0.00
▼Loop 2626 - ams.c:3363-3540 - exec–	0.00	0.00
▼Loop 2652 - ams.c:3416-3451 - exec–	0.00	0.00
○Loop 2655 - ams.c:3432-3432 - exec	0.00	0.00
○Loop 2657 - ams.c:3449-3451 - exec	0.00	0.00
○Loop 2658 - ams.c:3439-3444 - exec	0.00	0.00
○Loop 2653 - ams.c:3431-3432 - exec	0.00	0.00
○Loop 2656 - ams.c:3422-3426 - exec	0.00	0.00
○Loop 2654 - ams.c:3431-3432 - exec	0.00	0.00
▼Loop 2636 - ams.c:3470-3527 - exec–	0.00	0.00
○Loop 2642 - ams.c:3501-3507 - exec	0.00	0.00
○Loop 2637 - ams.c:3493-3494 - exec	0.00	0.00
○Loop 2638 - ams.c:3493-3494 - exec	0.00	0.00
○Loop 2641 - ams.c:3519-3521 - exec	0.00	0.00
○Loop 2640 - ams.c:3476-3481 - exec	0.00	0.00
○Loop 2639 - ams.c:3494-3494 - exec	0.00	0.00
▼Loop 2643 - ams.c:3382-3409 - exec–	0.00	0.00
○Loop 2646 - ams.c:3394-3394 - exec	0.00	0.00
○Loop 2647 - ams.c:3388-3389 - exec	0.00	0.00
○Loop 2644 - ams.c:3393-3394 - exec	0.00	0.00
○Loop 2649 - ams.c:3389-3389 - exec	0.00	0.00
○Loop 2651 - ams.c:3401-3403 - exec	0.00	0.00
○Loop 2648 - ams.c:3388-3389 - exec	0.00	0.00
○Loop 2645 - ams.c:3393-3394 - exec	0.00	0.00
○Loop 2650 - ams.c:3407-3409 - exec	0.00	0.00
▼Loop 2629 - ams.c:3458-3465 - exec–	0.00	0.00
○Loop 2632 - ams.c:3465-3465 - exec	0.00	0.00
○Loop 2634 - ams.c:3461-3462 - exec	0.00	0.00
○Loop 2630 - ams.c:3464-3465 - exec	0.00	0.00
○Loop 2633 - ams.c:3461-3462 - exec	0.00	0.00
○Loop 2635 - ams.c:3462-3462 - exec	0.00	0.00
○Loop 2631 - ams.c:3464-3465 - exec	0.00	0.00
○Loop 2659 - ams.c:3536-3538 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency