| Function: hypre_ParCSRComputeL1Norms | Module: exec | Source: ams.c:547-738 [...] | Coverage (incl. loops): 0.30% | (excl. loops): 0.00% |
|---|
| Function: hypre_ParCSRComputeL1Norms | Module: exec | Source: ams.c:547-738 [...] | Coverage (incl. loops): 0.30% | (excl. loops): 0.00% |
|---|
/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 547 - 738 |
-------------------------------------------------------------------------------- |
547: { |
548: HYPRE_Int i, j; |
549: HYPRE_Int num_rows = hypre_ParCSRMatrixNumRows(A); |
550: |
551: hypre_CSRMatrix *A_diag = hypre_ParCSRMatrixDiag(A); |
552: HYPRE_Int *A_diag_I = hypre_CSRMatrixI(A_diag); |
553: HYPRE_Int *A_diag_J = hypre_CSRMatrixJ(A_diag); |
554: HYPRE_Real *A_diag_data = hypre_CSRMatrixData(A_diag); |
555: |
556: hypre_CSRMatrix *A_offd = hypre_ParCSRMatrixOffd(A); |
557: HYPRE_Int *A_offd_I = hypre_CSRMatrixI(A_offd); |
558: HYPRE_Int *A_offd_J = hypre_CSRMatrixJ(A_offd); |
559: HYPRE_Real *A_offd_data = hypre_CSRMatrixData(A_offd); |
560: HYPRE_Int num_cols_offd = hypre_CSRMatrixNumCols(A_offd); |
561: |
562: HYPRE_Real diag; |
563: HYPRE_Real *l1_norm = hypre_TAlloc(HYPRE_Real, num_rows); |
[...] |
569: if (cf_marker != NULL) |
[...] |
576: hypre_ParCSRCommPkg *comm_pkg = hypre_ParCSRMatrixCommPkg(A); |
577: hypre_ParCSRCommHandle *comm_handle; |
578: |
579: if (num_cols_offd) |
580: cf_marker_offd = hypre_CTAlloc(HYPRE_Int, num_cols_offd); |
581: num_sends = hypre_ParCSRCommPkgNumSends(comm_pkg); |
582: if (hypre_ParCSRCommPkgSendMapStart(comm_pkg, num_sends)) |
583: int_buf_data = hypre_CTAlloc(HYPRE_Int, |
584: hypre_ParCSRCommPkgSendMapStart(comm_pkg, num_sends)); |
585: index = 0; |
586: for (i = 0; i < num_sends; i++) |
587: { |
588: start = hypre_ParCSRCommPkgSendMapStart(comm_pkg, i); |
589: for (j = start; j < hypre_ParCSRCommPkgSendMapStart(comm_pkg, i+1); j++) |
590: { |
591: int_buf_data[index++] = cf_marker[hypre_ParCSRCommPkgSendMapElmt(comm_pkg,j)]; |
592: } |
593: } |
594: comm_handle = hypre_ParCSRCommHandleCreate(11, comm_pkg, int_buf_data, |
595: cf_marker_offd); |
596: hypre_ParCSRCommHandleDestroy(comm_handle); |
597: hypre_TFree(int_buf_data); |
598: } |
599: |
600: if (option == 1) |
601: { |
602: for (i = 0; i < num_rows; i++) |
603: { |
604: l1_norm[i] = 0.0; |
605: if (cf_marker == NULL) |
606: { |
607: /* Add the l1 norm of the diag part of the ith row */ |
608: for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++) |
609: l1_norm[i] += fabs(A_diag_data[j]); |
610: /* Add the l1 norm of the offd part of the ith row */ |
611: if (num_cols_offd) |
612: { |
613: for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++) |
614: l1_norm[i] += fabs(A_offd_data[j]); |
615: } |
616: } |
617: else |
618: { |
619: cf_diag = cf_marker[i]; |
620: /* Add the CF l1 norm of the diag part of the ith row */ |
621: for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++) |
622: if (cf_diag == cf_marker[A_diag_J[j]]) |
623: l1_norm[i] += fabs(A_diag_data[j]); |
624: /* Add the CF l1 norm of the offd part of the ith row */ |
625: if (num_cols_offd) |
626: { |
627: for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++) |
628: if (cf_diag == cf_marker_offd[A_offd_J[j]]) |
629: l1_norm[i] += fabs(A_offd_data[j]); |
[...] |
636: for (i = 0; i < num_rows; i++) |
637: { |
638: /* Add the diag element of the ith row */ |
639: l1_norm[i] = fabs(A_diag_data[A_diag_I[i]]); |
640: if (cf_marker == NULL) |
641: { |
642: /* Add the l1 norm of the offd part of the ith row */ |
643: if (num_cols_offd) |
644: { |
645: for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++) |
646: l1_norm[i] += fabs(A_offd_data[j]); |
[...] |
653: if (num_cols_offd) |
654: { |
655: for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++) |
656: if (cf_diag == cf_marker_offd[A_offd_J[j]]) |
657: l1_norm[i] += fabs(A_offd_data[j]); |
[...] |
664: for (i = 0; i < num_rows; i++) |
665: { |
666: l1_norm[i] = 0.0; |
667: for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++) |
668: l1_norm[i] += A_diag_data[j] * A_diag_data[j]; |
669: if (num_cols_offd) |
670: for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++) |
671: l1_norm[i] += A_offd_data[j] * A_offd_data[j]; |
672: } |
673: } |
674: else if (option == 4) |
675: { |
676: for (i = 0; i < num_rows; i++) |
677: { |
678: /* Add the diag element of the ith row */ |
679: diag = l1_norm[i] = fabs(A_diag_data[A_diag_I[i]]); |
680: if (cf_marker == NULL) |
681: { |
682: /* Add the scaled l1 norm of the offd part of the ith row */ |
683: if (num_cols_offd) |
684: { |
685: for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++) |
686: l1_norm[i] += 0.5*fabs(A_offd_data[j]); |
[...] |
693: if (num_cols_offd) |
694: { |
695: for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++) |
696: if (cf_diag == cf_marker_offd[A_offd_J[j]]) |
697: l1_norm[i] += 0.5*fabs(A_offd_data[j]); |
698: } |
699: } |
700: |
701: /* Truncate according to Remark 6.2 */ |
702: if (l1_norm[i] <= 4.0/3.0*diag) |
703: l1_norm[i] = diag; |
704: } |
705: } |
706: else if (option == 5) /*stores diagonal of A for Jacobi using matvec, rlx 7 */ |
707: { |
708: for (i = 0; i < num_rows; i++) |
709: { |
710: diag = A_diag_data[A_diag_I[i]]; |
711: if (diag != 0.0) l1_norm[i] = diag; |
[...] |
720: for (i = 0; i < num_rows; i++) |
721: if (A_diag_data[A_diag_I[i]] < 0) |
722: l1_norm[i] = -l1_norm[i]; |
723: |
724: for (i = 0; i < num_rows; i++) |
725: /* if (fabs(l1_norm[i]) < DBL_EPSILON) */ |
726: if (fabs(l1_norm[i]) == 0.0) |
727: { |
728: hypre_error_in_arg(1); |
729: break; |
730: } |
731: |
732: //for (i = 0; i < num_rows; i++) l1_norm[i]=1.0/l1_norm[i]; |
733: hypre_TFree(cf_marker_offd); |
734: |
735: *l1_norm_ptr = l1_norm; |
736: |
737: return hypre_error_flag; |
738: } |
0x471d80 SUB SP, SP, #144 |
0x471d84 STP X29, X30, [SP, #48] |
0x471d88 STP X28, X27, [SP, #64] |
0x471d8c STP X26, X25, [SP, #80] |
0x471d90 STP X24, X23, [SP, #96] |
0x471d94 STP X22, X21, [SP, #112] |
0x471d98 STP X20, X19, [SP, #128] |
0x471d9c ADD X29, SP, #48 |
0x471da0 LDP X8, X9, [X0, #56] |
0x471da4 ORR X21, XZR, X0 |
0x471da8 ORR X24, XZR, X3 |
0x471dac ORR X23, XZR, X2 |
0x471db0 STUR X1, [X29, #496] |
0x471db4 LDP X10, X27, [X8, #8] |
0x471db8 LDR X28, [X8] |
0x471dbc LDR X19, [X8, #48] |
0x471dc0 LDP X25, X8, [X9] |
0x471dc4 LDR X22, [X9, #48] |
0x471dc8 LDR X26, [X9, #24] |
0x471dcc UBFM X0, X27, #61, #60 |
0x471dd0 STR X10, [SP, #24] |
0x471dd4 STUR X8, [X29, #504] |
0x471dd8 BL 4a6c20 |
0x471ddc ORR X20, XZR, X0 |
0x471de0 CBZ X23, 471e04 |
0x471de4 STP X25, X24, [SP, #8] |
0x471de8 LDR X25, [X21, #112] |
0x471dec CBZ X26, 471e0c |
0x471df0 MOVZ W1, #8 |
0x471df4 ORR X0, XZR, X26 |
0x471df8 BL 4a6c90 |
0x471dfc ORR X21, XZR, X0 |
0x471e00 B 471e10 |
0x471e04 ORR X21, XZR, XZR |
0x471e08 B 471ecc |
0x471e0c ORR X21, XZR, XZR |
0x471e10 LDR X24, [X25, #8] |
0x471e14 LDR X8, [X25, #24] |
0x471e18 STR X26, [SP] |
0x471e1c LDR X0, [X8, X24,LSL #3] |
0x471e20 CBZ X0, 471e3c |
0x471e24 MOVZ W1, #8 |
0x471e28 BL 4a6c90 |
0x471e2c ORR X26, XZR, X0 |
0x471e30 CMP X24, #1 |
0x471e34 B.GE 471e48 |
0x471e38 B 471ea4 |
0x471e3c ORR X26, XZR, XZR |
0x471e40 CMP X24, #1 |
0x471e44 B.LT 471ea4 |
0x471e48 LDR X9, [X25, #24] |
0x471e4c ORR X8, XZR, XZR |
0x471e50 ORR X10, XZR, XZR |
0x471e54 LDR X11, [X9] |
0x471e58 B 471e6c |
0x471e5c HINT #0 |
(2510) 0x471e60 ORR X11, XZR, X12 |
(2510) 0x471e64 CMP X8, X24 |
(2510) 0x471e68 B.EQ 471ea4 |
(2510) 0x471e6c ADD X8, X8, #1 |
(2510) 0x471e70 LDR X12, [X9, X8,LSL #3] |
(2510) 0x471e74 CMP X11, X12 |
(2510) 0x471e78 B.GE 471e60 |
(2510) 0x471e7c LDR X13, [X25, #32] |
(2511) 0x471e80 LDR X12, [X13, X11,LSL #3] |
(2511) 0x471e84 ADD X11, X11, #1 |
(2511) 0x471e88 LDR X12, [X23, X12,LSL #3] |
(2511) 0x471e8c STR X12, [X26, X10,LSL #3] |
(2511) 0x471e90 ADD X10, X10, #1 |
(2511) 0x471e94 LDR X12, [X9, X8,LSL #3] |
(2511) 0x471e98 CMP X11, X12 |
(2511) 0x471e9c B.LT 471e80 |
(2510) 0x471ea0 B 471e60 |
0x471ea4 MOVZ W0, #11 |
0x471ea8 ORR X1, XZR, X25 |
0x471eac ORR X2, XZR, X26 |
0x471eb0 ORR X3, XZR, X21 |
0x471eb4 BL 480c50 |
0x471eb8 BL 481040 |
0x471ebc ORR X0, XZR, X26 |
0x471ec0 BL 4a6d90 |
0x471ec4 LDP X25, X24, [SP, #8] |
0x471ec8 LDR X26, [SP] |
0x471ecc LDP X8, X5, [X29, #1008] |
0x471ed0 CMP X8, #2 |
0x471ed4 B.LE 471f74 |
0x471ed8 CMP X8, #3 |
0x471edc B.EQ 4721b0 |
0x471ee0 CMP X8, #4 |
0x471ee4 B.EQ 472440 |
0x471ee8 CMP X8, #5 |
0x471eec B.NE 472af0 |
0x471ef0 CMP X27, #1 |
0x471ef4 B.LT 472b7c |
0x471ef8 ORR X8, XZR, XZR |
0x471efc B.EQ 471f54 |
0x471f00 FMOV D0, #1.0000000 |
0x471f04 AND X9, X27, #8063 |
0x471f08 ADD X10, X28, #8 |
0x471f0c ADD X11, X20, #8 |
0x471f10 HINT #0 |
0x471f14 HINT #0 |
0x471f18 HINT #0 |
0x471f1c HINT #0 |
(2509) 0x471f20 LDUR X12, [X10, #504] |
(2509) 0x471f24 ADD X8, X8, #2 |
(2509) 0x471f28 LDR D1, [X19, X12,LSL #3] |
(2509) 0x471f2c FCMP D1, #0 |
(2509) 0x471f30 FCSEL D1, D1, D0, #1 |
(2509) 0x471f34 STUR D1, [X11, #504] |
(2509) 0x471f38 LDR X12, [X10], #16 |
(2509) 0x471f3c LDR D1, [X19, X12,LSL #3] |
(2509) 0x471f40 FCMP D1, #0 |
(2509) 0x471f44 FCSEL D1, D1, D0, #1 |
(2509) 0x471f48 STR D1, [X11], #16 |
(2509) 0x471f4c CMP X9, X8 |
(2509) 0x471f50 B.NE 471f20 |
0x471f54 TBZ W27, #0, 472b7c |
0x471f58 LDR X9, [X28, X8,LSL #3] |
0x471f5c FMOV D1, #1.0000000 |
0x471f60 LDR D0, [X19, X9,LSL #3] |
0x471f64 FCMP D0, #0 |
0x471f68 FCSEL D0, D0, D1, #1 |
0x471f6c STR D0, [X20, X8,LSL #3] |
0x471f70 B 472b7c |
0x471f74 CMP X8, #1 |
0x471f78 B.EQ 4726c0 |
0x471f7c CMP X8, #2 |
0x471f80 B.NE 472af0 |
0x471f84 CMP X27, #1 |
0x471f88 B.LT 472b74 |
0x471f8c ADD X9, X20, X27,LSL #3 |
0x471f90 ADD X10, X22, #8 |
0x471f94 ADD X11, X5, #8 |
0x471f98 ADD X12, X22, #16 |
0x471f9c ORR X8, XZR, XZR |
0x471fa0 B 471fb0 |
(2504) 0x471fa4 ADD X8, X8, #1 |
(2504) 0x471fa8 CMP X8, X27 |
(2504) 0x471fac B.EQ 472af0 |
(2504) 0x471fb0 LDR X13, [X28, X8,LSL #3] |
(2504) 0x471fb4 LDR D0, [X19, X13,LSL #3] |
(2504) 0x471fb8 FABS D0, D0 |
(2504) 0x471fbc STR D0, [X20, X8,LSL #3] |
(2504) 0x471fc0 CBZ X23, 471fec |
(2504) 0x471fc4 CBZ X26, 471fa4 |
(2504) 0x471fc8 ADD X13, X25, X8,LSL #3 |
(2504) 0x471fcc LDP X15, X14, [X13] |
(2504) 0x471fd0 CMP X14, X15 |
(2504) 0x471fd4 B.LE 471fa4 |
(2504) 0x471fd8 LDR X13, [X23, X8,LSL #3] |
(2504) 0x471fdc SUB W16, W14, W15 |
(2504) 0x471fe0 TBNZ W16, #0, 472078 |
(2504) 0x471fe4 ORR X16, XZR, X15 |
(2504) 0x471fe8 B 47209c |
(2504) 0x471fec CBZ X26, 471fa4 |
(2504) 0x471ff0 ADD X13, X25, X8,LSL #3 |
(2504) 0x471ff4 LDP X17, X13, [X13] |
(2504) 0x471ff8 SUBS X15, X13, X17 |
(2504) 0x471ffc B.LE 471fa4 |
(2504) 0x472000 CMP X15, #4 |
(2504) 0x472004 B.CC 472114 |
(2504) 0x472008 ADD X16, X22, X13,LSL #3 |
(2504) 0x47200c ADD X14, X22, X17,LSL #3 |
(2504) 0x472010 CMP X20, X16 |
(2504) 0x472014 CCMP X14, X9, #2, #3 |
(2504) 0x472018 B.CC 472114 |
(2504) 0x47201c AND X16, X15, #8062 |
(2504) 0x472020 MOVI V2.2D, #0 |
(2504) 0x472024 MOV V2.D[0], V0.D[0] |
(2504) 0x472028 MOVI V1.2D, #0 |
(2504) 0x47202c ADD X14, X17, X16 |
(2504) 0x472030 ADD X17, X12, X17,LSL #3 |
(2504) 0x472034 ORR X18, XZR, X16 |
(2504) 0x472038 HINT #0 |
(2504) 0x47203c HINT #0 |
(2507) 0x472040 LDP Q0, Q3, [X17, #2032] |
(2507) 0x472044 ADD X17, X17, #32 |
(2507) 0x472048 SUBS X18, X18, #4 |
(2507) 0x47204c FABS V3.2D, V3.2D |
(2507) 0x472050 FABS V0.2D, V0.2D |
(2507) 0x472054 FADD V1.2D, V1.2D, V3.2D |
(2507) 0x472058 FADD V2.2D, V2.2D, V0.2D |
(2507) 0x47205c B.NE 472040 |
(2504) 0x472060 FADD V0.2D, V1.2D, V2.2D |
(2504) 0x472064 FADDP D0, V0.2D |
(2504) 0x472068 STR D0, [X20, X8,LSL #3] |
(2504) 0x47206c CMP X15, X16 |
(2504) 0x472070 B.EQ 471fa4 |
(2504) 0x472074 B 472118 |
(2504) 0x472078 LDR X16, [X5, X15,LSL #3] |
(2504) 0x47207c LDR X16, [X21, X16,LSL #3] |
(2504) 0x472080 CMP X13, X16 |
(2504) 0x472084 B.NE 472098 |
(2504) 0x472088 LDR D1, [X22, X15,LSL #3] |
(2504) 0x47208c FABS D1, D1 |
(2504) 0x472090 FADD D0, D0, D1 |
(2504) 0x472094 STR D0, [X20, X8,LSL #3] |
(2504) 0x472098 ADD X16, X15, #1 |
(2504) 0x47209c ADD X15, X15, #1 |
(2504) 0x4720a0 CMP X14, X15 |
(2504) 0x4720a4 B.EQ 471fa4 |
(2508) 0x4720a8 SUB X14, X14, X16 |
(2508) 0x4720ac ADD X15, X10, X16,LSL #3 |
(2508) 0x4720b0 ADD X16, X11, X16,LSL #3 |
(2508) 0x4720b4 B 4720d0 |
0x4720b8 HINT #0 |
0x4720bc HINT #0 |
(2508) 0x4720c0 SUBS X14, X14, #2 |
(2508) 0x4720c4 ADD X15, X15, #16 |
(2508) 0x4720c8 ADD X16, X16, #16 |
(2508) 0x4720cc B.EQ 471fa4 |
(2508) 0x4720d0 LDUR X17, [X16, #504] |
(2508) 0x4720d4 LDR X17, [X21, X17,LSL #3] |
(2508) 0x4720d8 CMP X13, X17 |
(2508) 0x4720dc B.NE 4720f0 |
(2508) 0x4720e0 LDUR D1, [X15, #504] |
(2508) 0x4720e4 FABS D1, D1 |
(2508) 0x4720e8 FADD D0, D0, D1 |
(2508) 0x4720ec STR D0, [X20, X8,LSL #3] |
(2508) 0x4720f0 LDR X17, [X16] |
(2508) 0x4720f4 LDR X17, [X21, X17,LSL #3] |
(2508) 0x4720f8 CMP X13, X17 |
(2508) 0x4720fc B.NE 4720c0 |
(2508) 0x472100 LDR D1, [X15] |
(2508) 0x472104 FABS D1, D1 |
(2508) 0x472108 FADD D0, D0, D1 |
(2508) 0x47210c STR D0, [X20, X8,LSL #3] |
(2508) 0x472110 B 4720c0 |
(2504) 0x472114 ORR X14, XZR, X17 |
(2504) 0x472118 SUB W15, W13, W14 |
(2504) 0x47211c ANDS X16, X15, #4160 |
(2504) 0x472120 B.EQ 472148 |
(2504) 0x472124 ORR X15, XZR, X14 |
(2506) 0x472128 LDR D1, [X22, X15,LSL #3] |
(2506) 0x47212c ADD X15, X15, #1 |
(2506) 0x472130 SUBS X16, X16, #1 |
(2506) 0x472134 FABS D1, D1 |
(2506) 0x472138 FADD D0, D0, D1 |
(2506) 0x47213c STR D0, [X20, X8,LSL #3] |
(2506) 0x472140 B.NE 472128 |
(2504) 0x472144 B 47214c |
(2504) 0x472148 ORR X15, XZR, X14 |
(2504) 0x47214c SUB X14, X14, X13 |
(2504) 0x472150 CMN X14, #4 |
(2504) 0x472154 B.HI 471fa4 |
(2504) 0x472158 SUB X13, X13, X15 |
(2504) 0x47215c ADD X14, X12, X15,LSL #3 |
(2505) 0x472160 LDUR D1, [X14, #496] |
(2505) 0x472164 SUBS X13, X13, #4 |
(2505) 0x472168 FABS D1, D1 |
(2505) 0x47216c FADD D0, D0, D1 |
(2505) 0x472170 STR D0, [X20, X8,LSL #3] |
(2505) 0x472174 LDUR D1, [X14, #504] |
(2505) 0x472178 FABS D1, D1 |
(2505) 0x47217c FADD D0, D0, D1 |
(2505) 0x472180 STR D0, [X20, X8,LSL #3] |
(2505) 0x472184 LDR D1, [X14] |
(2505) 0x472188 FABS D1, D1 |
(2505) 0x47218c FADD D0, D0, D1 |
(2505) 0x472190 STR D0, [X20, X8,LSL #3] |
(2505) 0x472194 LDR D1, [X14, #8] |
(2505) 0x472198 ADD X14, X14, #32 |
(2505) 0x47219c FABS D1, D1 |
(2505) 0x4721a0 FADD D0, D0, D1 |
(2505) 0x4721a4 STR D0, [X20, X8,LSL #3] |
(2505) 0x4721a8 B.NE 472160 |
(2504) 0x4721ac B 471fa4 |
0x4721b0 CMP X27, #1 |
0x4721b4 B.LT 472b74 |
0x4721b8 LDR X11, [X28] |
0x4721bc ADD X8, X20, X27,LSL #3 |
0x4721c0 ADD X10, X19, #16 |
0x4721c4 ADD X12, X22, #16 |
0x4721c8 ORR X9, XZR, XZR |
0x4721cc B 4721e8 |
0x4721d0 HINT #0 |
0x4721d4 HINT #0 |
0x4721d8 HINT #0 |
0x4721dc HINT #0 |
(2495) 0x4721e0 CMP X9, X27 |
(2495) 0x4721e4 B.EQ 472af0 |
(2495) 0x4721e8 ORR X13, XZR, X9 |
(2495) 0x4721ec STR XZR, [X20, X9,LSL #3] |
(2495) 0x4721f0 ADD X9, X9, #1 |
(2495) 0x4721f4 ORR X17, XZR, X11 |
(2495) 0x4721f8 MOVI D0, #0 |
(2495) 0x4721fc LDR X11, [X28, X9,LSL #3] |
(2495) 0x472200 SUBS X15, X11, X17 |
(2495) 0x472204 B.LE 47231c |
(2495) 0x472208 MOVI D0, #0 |
(2495) 0x47220c CMP X15, #4 |
(2495) 0x472210 B.CC 472280 |
(2495) 0x472214 ADD X16, X19, X11,LSL #3 |
(2495) 0x472218 ADD X14, X19, X17,LSL #3 |
(2495) 0x47221c CMP X20, X16 |
(2495) 0x472220 CCMP X14, X8, #2, #3 |
(2495) 0x472224 B.CC 472280 |
(2495) 0x472228 AND X16, X15, #8062 |
(2495) 0x47222c MOVI V0.2D, #0 |
(2495) 0x472230 MOVI V1.2D, #0 |
(2495) 0x472234 ADD X14, X17, X16 |
(2495) 0x472238 ADD X17, X10, X17,LSL #3 |
(2495) 0x47223c ORR X18, XZR, X16 |
(2501) 0x472240 LDP Q2, Q3, [X17, #2032] |
(2501) 0x472244 ADD X17, X17, #32 |
(2501) 0x472248 SUBS X18, X18, #4 |
(2501) 0x47224c FMLA V1.2D, V3.2D, V3.2D |
(2501) 0x472250 FMLA V0.2D, V2.2D, V2.2D |
(2501) 0x472254 B.NE 472240 |
(2495) 0x472258 FADD V0.2D, V1.2D, V0.2D |
(2495) 0x47225c FADDP D0, V0.2D |
(2495) 0x472260 STR D0, [X20, X13,LSL #3] |
(2495) 0x472264 CMP X15, X16 |
(2495) 0x472268 B.NE 472284 |
(2495) 0x47226c B 47231c |
0x472270 HINT #0 |
0x472274 HINT #0 |
0x472278 HINT #0 |
0x47227c HINT #0 |
(2495) 0x472280 ORR X14, XZR, X17 |
(2495) 0x472284 SUB W15, W11, W14 |
(2495) 0x472288 ANDS X16, X15, #4160 |
(2495) 0x47228c B.EQ 4722bc |
(2495) 0x472290 ORR X15, XZR, X14 |
(2495) 0x472294 HINT #0 |
(2495) 0x472298 HINT #0 |
(2495) 0x47229c HINT #0 |
(2500) 0x4722a0 LDR D1, [X19, X15,LSL #3] |
(2500) 0x4722a4 ADD X15, X15, #1 |
(2500) 0x4722a8 SUBS X16, X16, #1 |
(2500) 0x4722ac FMADD D0, D1, D1, D0 |
(2500) 0x4722b0 STR D0, [X20, X13,LSL #3] |
(2500) 0x4722b4 B.NE 4722a0 |
(2495) 0x4722b8 B 4722c0 |
(2495) 0x4722bc ORR X15, XZR, X14 |
(2495) 0x4722c0 SUB X14, X14, X11 |
(2495) 0x4722c4 CMN X14, #4 |
(2495) 0x4722c8 B.HI 47231c |
(2495) 0x4722cc SUB X14, X11, X15 |
(2495) 0x4722d0 ADD X15, X10, X15,LSL #3 |
(2495) 0x4722d4 HINT #0 |
(2495) 0x4722d8 HINT #0 |
(2495) 0x4722dc HINT #0 |
(2499) 0x4722e0 LDUR D1, [X15, #496] |
(2499) 0x4722e4 SUBS X14, X14, #4 |
(2499) 0x4722e8 FMADD D0, D1, D1, D0 |
(2499) 0x4722ec STR D0, [X20, X13,LSL #3] |
(2499) 0x4722f0 LDUR D1, [X15, #504] |
(2499) 0x4722f4 FMADD D0, D1, D1, D0 |
(2499) 0x4722f8 STR D0, [X20, X13,LSL #3] |
(2499) 0x4722fc LDR D1, [X15] |
(2499) 0x472300 FMADD D0, D1, D1, D0 |
(2499) 0x472304 STR D0, [X20, X13,LSL #3] |
(2499) 0x472308 LDR D1, [X15, #8] |
(2499) 0x47230c ADD X15, X15, #32 |
(2499) 0x472310 FMADD D0, D1, D1, D0 |
(2499) 0x472314 STR D0, [X20, X13,LSL #3] |
(2499) 0x472318 B.NE 4722e0 |
(2495) 0x47231c CBZ X26, 4721e0 |
(2495) 0x472320 LDR X18, [X25, X13,LSL #3] |
(2495) 0x472324 LDR X14, [X25, X9,LSL #3] |
(2495) 0x472328 SUBS X16, X14, X18 |
(2495) 0x47232c B.LE 4721e0 |
(2495) 0x472330 CMP X16, #4 |
(2495) 0x472334 B.CC 4723a0 |
(2495) 0x472338 ADD X17, X22, X14,LSL #3 |
(2495) 0x47233c ADD X15, X22, X18,LSL #3 |
(2495) 0x472340 CMP X20, X17 |
(2495) 0x472344 CCMP X15, X8, #2, #3 |
(2495) 0x472348 B.CC 4723a0 |
(2495) 0x47234c AND X17, X16, #8062 |
(2495) 0x472350 MOVI V2.2D, #0 |
(2495) 0x472354 MOV V2.D[0], V0.D[0] |
(2495) 0x472358 MOVI V1.2D, #0 |
(2495) 0x47235c ADD X15, X18, X17 |
(2495) 0x472360 ADD X18, X12, X18,LSL #3 |
(2495) 0x472364 ORR X0, XZR, X17 |
(2497) 0x472368 LDP Q0, Q3, [X18, #2032] |
(2497) 0x47236c ADD X18, X18, #32 |
(2497) 0x472370 SUBS X0, X0, #4 |
(2497) 0x472374 FMLA V1.2D, V3.2D, V3.2D |
(2497) 0x472378 FMLA V2.2D, V0.2D, V0.2D |
(2497) 0x47237c B.NE 472368 |
(2495) 0x472380 FADD V0.2D, V1.2D, V2.2D |
(2495) 0x472384 FADDP D0, V0.2D |
(2495) 0x472388 STR D0, [X20, X13,LSL #3] |
(2495) 0x47238c CMP X16, X17 |
(2495) 0x472390 B.EQ 4721e0 |
(2498) 0x472394 B 4723a4 |
0x472398 HINT #0 |
0x47239c HINT #0 |
(2496) 0x4723a0 ORR X15, XZR, X18 |
(2498) 0x4723a4 SUB W16, W14, W15 |
(2498) 0x4723a8 ANDS X17, X16, #4160 |
(2498) 0x4723ac B.EQ 4723dc |
(2496) 0x4723b0 ORR X16, XZR, X15 |
(2496) 0x4723b4 HINT #0 |
(2496) 0x4723b8 HINT #0 |
(2496) 0x4723bc HINT #0 |
(2503) 0x4723c0 LDR D1, [X22, X16,LSL #3] |
(2503) 0x4723c4 ADD X16, X16, #1 |
(2503) 0x4723c8 SUBS X17, X17, #1 |
(2503) 0x4723cc FMADD D0, D1, D1, D0 |
(2503) 0x4723d0 STR D0, [X20, X13,LSL #3] |
(2503) 0x4723d4 B.NE 4723c0 |
(2496) 0x4723d8 B 4723e0 |
(2496) 0x4723dc ORR X16, XZR, X15 |
(2496) 0x4723e0 SUB X15, X15, X14 |
(2496) 0x4723e4 CMN X15, #4 |
(2496) 0x4723e8 B.HI 4721e0 |
(2496) 0x4723ec SUB X14, X14, X16 |
(2496) 0x4723f0 ADD X15, X12, X16,LSL #3 |
(2496) 0x4723f4 HINT #0 |
(2496) 0x4723f8 HINT #0 |
(2496) 0x4723fc HINT #0 |
(2502) 0x472400 LDUR D1, [X15, #496] |
(2502) 0x472404 SUBS X14, X14, #4 |
(2502) 0x472408 FMADD D0, D1, D1, D0 |
(2502) 0x47240c STR D0, [X20, X13,LSL #3] |
(2502) 0x472410 LDUR D1, [X15, #504] |
(2502) 0x472414 FMADD D0, D1, D1, D0 |
(2502) 0x472418 STR D0, [X20, X13,LSL #3] |
(2502) 0x47241c LDR D1, [X15] |
(2502) 0x472420 FMADD D0, D1, D1, D0 |
(2502) 0x472424 STR D0, [X20, X13,LSL #3] |
(2502) 0x472428 LDR D1, [X15, #8] |
(2502) 0x47242c ADD X15, X15, #32 |
(2502) 0x472430 FMADD D0, D1, D1, D0 |
(2502) 0x472434 STR D0, [X20, X13,LSL #3] |
(2502) 0x472438 B.NE 472400 |
(2496) 0x47243c B 4721e0 |
0x472440 CMP X27, #1 |
0x472444 B.LT 472b74 |
0x472448 ORR X13, XZR, #3840 |
0x47244c FMOV D0, #0.5000000 |
0x472450 FMOV V1.2D, #0.5000000 |
0x472454 ADD X9, X20, X27,LSL #3 |
0x472458 ADD X10, X22, #8 |
0x47245c ADD X11, X5, #8 |
0x472460 ADD X12, X22, #16 |
0x472464 ORR X8, XZR, XZR |
0x472468 MOVK X13, #16373 |
0x47246c FMOV D2, X13 |
0x472470 B 47248c |
0x472474 HINT #0 |
0x472478 HINT #0 |
0x47247c HINT #0 |
(2490) 0x472480 ADD X8, X8, #1 |
(2490) 0x472484 CMP X8, X27 |
(2490) 0x472488 B.EQ 472af0 |
(2490) 0x47248c LDR X13, [X28, X8,LSL #3] |
(2490) 0x472490 LDR D3, [X19, X13,LSL #3] |
(2490) 0x472494 FABS D3, D3 |
(2490) 0x472498 FMOV D4, D3 |
(2490) 0x47249c STR D3, [X20, X8,LSL #3] |
(2490) 0x4724a0 CBZ X23, 4724e0 |
(2490) 0x4724a4 CBZ X26, 4726ac |
(2490) 0x4724a8 ADD X13, X25, X8,LSL #3 |
(2490) 0x4724ac FMOV D4, D3 |
(2490) 0x4724b0 LDP X15, X14, [X13] |
(2490) 0x4724b4 CMP X14, X15 |
(2490) 0x4724b8 B.LE 4726ac |
(2490) 0x4724bc LDR X13, [X23, X8,LSL #3] |
(2490) 0x4724c0 SUB W16, W14, W15 |
(2490) 0x4724c4 TBNZ W16, #0, 472508 |
(2490) 0x4724c8 FMOV D4, D3 |
(2490) 0x4724cc ORR X16, XZR, X15 |
(2490) 0x4724d0 B 472530 |
0x4724d4 HINT #0 |
0x4724d8 HINT #0 |
0x4724dc HINT #0 |
(2489) 0x4724e0 CBZ X26, 4726ac |
(2489) 0x4724e4 ADD X13, X25, X8,LSL #3 |
(2489) 0x4724e8 FMOV D4, D3 |
(2489) 0x4724ec LDP X14, X13, [X13] |
(2489) 0x4724f0 SUBS X15, X13, X14 |
(2489) 0x4724f4 B.LE 4726ac |
(2489) 0x4724f8 CMP X15, #4 |
(2489) 0x4724fc B.CS 4725a0 |
(2489) 0x472500 FMOV D4, D3 |
(2489) 0x472504 B 472618 |
(2490) 0x472508 LDR X16, [X5, X15,LSL #3] |
(2490) 0x47250c FMOV D4, D3 |
(2490) 0x472510 LDR X16, [X21, X16,LSL #3] |
(2490) 0x472514 CMP X13, X16 |
(2490) 0x472518 B.NE 47252c |
(2490) 0x47251c LDR D4, [X22, X15,LSL #3] |
(2490) 0x472520 FABS D4, D4 |
(2490) 0x472524 FMADD D4, D4, D0, D3 |
(2490) 0x472528 STR D4, [X20, X8,LSL #3] |
(2490) 0x47252c ADD X16, X15, #1 |
(2490) 0x472530 ADD X15, X15, #1 |
(2490) 0x472534 CMP X14, X15 |
(2490) 0x472538 B.EQ 4726ac |
(2490) 0x47253c SUB X14, X14, X16 |
(2490) 0x472540 ADD X15, X10, X16,LSL #3 |
(2490) 0x472544 ADD X16, X11, X16,LSL #3 |
(2490) 0x472548 B 47255c |
(2491) 0x47254c SUBS X14, X14, #2 |
(2491) 0x472550 ADD X15, X15, #16 |
(2491) 0x472554 ADD X16, X16, #16 |
(2491) 0x472558 B.EQ 4726ac |
(2491) 0x47255c LDUR X17, [X16, #504] |
(2491) 0x472560 LDR X17, [X21, X17,LSL #3] |
(2491) 0x472564 CMP X13, X17 |
(2491) 0x472568 B.NE 47257c |
(2491) 0x47256c LDUR D5, [X15, #504] |
(2491) 0x472570 FABS D5, D5 |
(2491) 0x472574 FMADD D4, D5, D0, D4 |
(2491) 0x472578 STR D4, [X20, X8,LSL #3] |
(2491) 0x47257c LDR X17, [X16] |
(2491) 0x472580 LDR X17, [X21, X17,LSL #3] |
(2491) 0x472584 CMP X13, X17 |
(2491) 0x472588 B.NE 47254c |
(2491) 0x47258c LDR D5, [X15] |
(2491) 0x472590 FABS D5, D5 |
(2491) 0x472594 FMADD D4, D5, D0, D4 |
(2491) 0x472598 STR D4, [X20, X8,LSL #3] |
(2491) 0x47259c B 47254c |
(2489) 0x4725a0 ADD X17, X22, X13,LSL #3 |
(2489) 0x4725a4 ADD X16, X22, X14,LSL #3 |
(2489) 0x4725a8 FMOV D4, D3 |
(2489) 0x4725ac CMP X20, X17 |
(2489) 0x4725b0 CCMP X16, X9, #2, #3 |
(2489) 0x4725b4 B.CC 472618 |
(2489) 0x4725b8 AND X16, X15, #8062 |
(2489) 0x4725bc MOVI V5.2D, #0 |
(2489) 0x4725c0 MOV V5.D[0], V3.D[0] |
(2489) 0x4725c4 MOVI V4.2D, #0 |
(2489) 0x4725c8 ADD X17, X14, X16 |
(2489) 0x4725cc ADD X14, X12, X14,LSL #3 |
(2489) 0x4725d0 ORR X18, XZR, X16 |
(2489) 0x4725d4 HINT #0 |
(2489) 0x4725d8 HINT #0 |
(2489) 0x4725dc HINT #0 |
(2494) 0x4725e0 LDP Q6, Q7, [X14, #2032] |
(2494) 0x4725e4 ADD X14, X14, #32 |
(2494) 0x4725e8 SUBS X18, X18, #4 |
(2494) 0x4725ec FABS V7.2D, V7.2D |
(2494) 0x4725f0 FABS V6.2D, V6.2D |
(2494) 0x4725f4 FMLA V4.2D, V1.2D, V7.2D |
(2494) 0x4725f8 FMLA V5.2D, V1.2D, V6.2D |
(2494) 0x4725fc B.NE 4725e0 |
(2489) 0x472600 FADD V4.2D, V4.2D, V5.2D |
(2489) 0x472604 ORR X14, XZR, X17 |
(2489) 0x472608 FADDP D4, V4.2D |
(2489) 0x47260c STR D4, [X20, X8,LSL #3] |
(2489) 0x472610 CMP X15, X16 |
(2489) 0x472614 B.EQ 4726ac |
(2489) 0x472618 SUB W15, W13, W14 |
(2489) 0x47261c ANDS X16, X15, #4160 |
(2489) 0x472620 B.EQ 472648 |
(2489) 0x472624 ORR X15, XZR, X14 |
(2493) 0x472628 LDR D5, [X22, X15,LSL #3] |
(2493) 0x47262c ADD X15, X15, #1 |
(2493) 0x472630 SUBS X16, X16, #1 |
(2493) 0x472634 FABS D5, D5 |
(2493) 0x472638 FMADD D4, D5, D0, D4 |
(2493) 0x47263c STR D4, [X20, X8,LSL #3] |
(2493) 0x472640 B.NE 472628 |
(2489) 0x472644 B 47264c |
(2489) 0x472648 ORR X15, XZR, X14 |
(2489) 0x47264c SUB X14, X14, X13 |
(2489) 0x472650 CMN X14, #4 |
(2489) 0x472654 B.HI 4726ac |
(2489) 0x472658 SUB X13, X13, X15 |
(2489) 0x47265c ADD X14, X12, X15,LSL #3 |
(2492) 0x472660 LDUR D5, [X14, #496] |
(2492) 0x472664 SUBS X13, X13, #4 |
(2492) 0x472668 FABS D5, D5 |
(2492) 0x47266c FMADD D4, D5, D0, D4 |
(2492) 0x472670 STR D4, [X20, X8,LSL #3] |
(2492) 0x472674 LDUR D5, [X14, #504] |
(2492) 0x472678 FABS D5, D5 |
(2492) 0x47267c FMADD D4, D5, D0, D4 |
(2492) 0x472680 STR D4, [X20, X8,LSL #3] |
(2492) 0x472684 LDR D5, [X14] |
(2492) 0x472688 FABS D5, D5 |
(2492) 0x47268c FMADD D4, D5, D0, D4 |
(2492) 0x472690 STR D4, [X20, X8,LSL #3] |
(2492) 0x472694 LDR D5, [X14, #8] |
(2492) 0x472698 ADD X14, X14, #32 |
(2492) 0x47269c FABS D5, D5 |
(2492) 0x4726a0 FMADD D4, D5, D0, D4 |
(2492) 0x4726a4 STR D4, [X20, X8,LSL #3] |
(2492) 0x4726a8 B.NE 472660 |
(2490) 0x4726ac FMUL D5, D3, D2 |
(2490) 0x4726b0 FCMP D4, D5 |
(2490) 0x4726b4 B.GT 472480 |
(2490) 0x4726b8 STR D3, [X20, X8,LSL #3] |
(2490) 0x4726bc B 472480 |
0x4726c0 CMP X27, #1 |
0x4726c4 B.LT 472b74 |
0x4726c8 LDR X10, [SP, #24] |
0x4726cc ADD X8, X20, #8 |
0x4726d0 ADD X9, X19, #8 |
0x4726d4 ADD X11, X22, #8 |
0x4726d8 ADD X12, X5, #8 |
0x4726dc ADD X13, X19, #16 |
0x4726e0 ADD X14, X22, #16 |
0x4726e4 ORR X17, XZR, XZR |
0x4726e8 ADD X10, X10, #8 |
0x4726ec B 47270c |
0x4726f0 HINT #0 |
0x4726f4 HINT #0 |
0x4726f8 HINT #0 |
0x4726fc HINT #0 |
(2480) 0x472700 ORR X17, XZR, X15 |
(2480) 0x472704 CMP X15, X27 |
(2480) 0x472708 B.EQ 472af0 |
(2480) 0x47270c ADD X16, X20, X17,LSL #3 |
(2480) 0x472710 STR XZR, [X16] |
(2480) 0x472714 CBZ X23, 472744 |
(2480) 0x472718 ADD X15, X17, #1 |
(2480) 0x47271c LDR X18, [X23, X17,LSL #3] |
(2480) 0x472720 LDR X1, [X28, X17,LSL #3] |
(2480) 0x472724 MOVI D0, #0 |
(2480) 0x472728 LDR X0, [X28, X15,LSL #3] |
(2480) 0x47272c CMP X0, X1 |
(2480) 0x472730 B.LE 472838 |
(2480) 0x472734 SUB W2, W0, W1 |
(2480) 0x472738 TBNZ W2, #0, 472808 |
(2480) 0x47273c ORR X2, XZR, X1 |
(2480) 0x472740 B 47282c |
(2480) 0x472744 ADD X15, X17, #1 |
(2480) 0x472748 LDR X0, [X28, X17,LSL #3] |
(2480) 0x47274c MOVI D0, #0 |
(2480) 0x472750 LDR X18, [X28, X15,LSL #3] |
(2480) 0x472754 SUBS X1, X18, X0 |
(2480) 0x472758 B.LE 4729b8 |
(2480) 0x47275c MOVI D0, #0 |
(2480) 0x472760 CMP X1, #6 |
(2480) 0x472764 B.CC 4727d8 |
(2480) 0x472768 ADD X4, X19, X18,LSL #3 |
(2480) 0x47276c ADD X2, X8, X17,LSL #3 |
(2480) 0x472770 ADD X3, X19, X0,LSL #3 |
(2480) 0x472774 CMP X16, X4 |
(2480) 0x472778 CCMP X3, X2, #2, #3 |
(2480) 0x47277c B.CC 4727d8 |
(2480) 0x472780 AND X2, X1, #8062 |
(2480) 0x472784 MOVI V0.2D, #0 |
(2480) 0x472788 MOVI V1.2D, #0 |
(2480) 0x47278c ADD X3, X0, X2 |
(2480) 0x472790 ADD X0, X13, X0,LSL #3 |
(2480) 0x472794 ORR X4, XZR, X2 |
(2480) 0x472798 HINT #0 |
(2480) 0x47279c HINT #0 |
(2486) 0x4727a0 LDP Q2, Q3, [X0, #2032] |
(2486) 0x4727a4 ADD X0, X0, #32 |
(2486) 0x4727a8 SUBS X4, X4, #4 |
(2486) 0x4727ac FABS V3.2D, V3.2D |
(2486) 0x4727b0 FABS V2.2D, V2.2D |
(2486) 0x4727b4 FADD V1.2D, V1.2D, V3.2D |
(2486) 0x4727b8 FADD V0.2D, V0.2D, V2.2D |
(2486) 0x4727bc B.NE 4727a0 |
(2480) 0x4727c0 FADD V0.2D, V1.2D, V0.2D |
(2480) 0x4727c4 ORR X0, XZR, X3 |
(2480) 0x4727c8 FADDP D0, V0.2D |
(2480) 0x4727cc STR D0, [X16] |
(2480) 0x4727d0 CMP X1, X2 |
(2480) 0x4727d4 B.EQ 4729b8 |
(2480) 0x4727d8 SUB W1, W18, W0 |
(2480) 0x4727dc ANDS X2, X1, #4160 |
(2480) 0x4727e0 B.EQ 472954 |
(2480) 0x4727e4 ORR X1, XZR, X0 |
(2485) 0x4727e8 LDR D1, [X19, X1,LSL #3] |
(2485) 0x4727ec ADD X1, X1, #1 |
(2485) 0x4727f0 SUBS X2, X2, #1 |
(2485) 0x4727f4 FABS D1, D1 |
(2485) 0x4727f8 FADD D0, D0, D1 |
(2485) 0x4727fc STR D0, [X16] |
(2485) 0x472800 B.NE 4727e8 |
(2480) 0x472804 B 472958 |
(2480) 0x472808 LDR X2, [SP, #24] |
(2480) 0x47280c LDR X2, [X2, X1,LSL #3] |
(2480) 0x472810 LDR X2, [X23, X2,LSL #3] |
(2480) 0x472814 CMP X18, X2 |
(2480) 0x472818 B.NE 472828 |
(2480) 0x47281c LDR D0, [X19, X1,LSL #3] |
(2480) 0x472820 FABS D0, D0 |
(2480) 0x472824 STR D0, [X16] |
(2480) 0x472828 ADD X2, X1, #1 |
(2480) 0x47282c ADD X1, X1, #1 |
(2480) 0x472830 CMP X0, X1 |
(2480) 0x472834 B.NE 47285c |
(2480) 0x472838 CBZ X26, 472700 |
(2480) 0x47283c LDR X0, [X25, X17,LSL #3] |
(2480) 0x472840 LDR X17, [X25, X15,LSL #3] |
(2480) 0x472844 CMP X17, X0 |
(2480) 0x472848 B.LE 472700 |
(2480) 0x47284c SUB W1, W17, W0 |
(2480) 0x472850 TBNZ W1, #0, 4728c0 |
(2480) 0x472854 ORR X1, XZR, X0 |
(2480) 0x472858 B 4728e4 |
(2480) 0x47285c SUB X0, X0, X2 |
(2480) 0x472860 ADD X1, X9, X2,LSL #3 |
(2480) 0x472864 ADD X2, X10, X2,LSL #3 |
(2480) 0x472868 B 47287c |
(2488) 0x47286c SUBS X0, X0, #2 |
(2488) 0x472870 ADD X1, X1, #16 |
(2488) 0x472874 ADD X2, X2, #16 |
(2488) 0x472878 B.EQ 472838 |
(2488) 0x47287c LDUR X3, [X2, #504] |
(2488) 0x472880 LDR X3, [X23, X3,LSL #3] |
(2488) 0x472884 CMP X18, X3 |
(2488) 0x472888 B.NE 47289c |
(2488) 0x47288c LDUR D1, [X1, #504] |
(2488) 0x472890 FABS D1, D1 |
(2488) 0x472894 FADD D0, D0, D1 |
(2488) 0x472898 STR D0, [X16] |
(2488) 0x47289c LDR X3, [X2] |
(2488) 0x4728a0 LDR X3, [X23, X3,LSL #3] |
(2488) 0x4728a4 CMP X18, X3 |
(2488) 0x4728a8 B.NE 47286c |
(2488) 0x4728ac LDR D1, [X1] |
(2488) 0x4728b0 FABS D1, D1 |
(2488) 0x4728b4 FADD D0, D0, D1 |
(2488) 0x4728b8 STR D0, [X16] |
(2488) 0x4728bc B 47286c |
(2480) 0x4728c0 LDR X1, [X5, X0,LSL #3] |
(2480) 0x4728c4 LDR X1, [X21, X1,LSL #3] |
(2480) 0x4728c8 CMP X18, X1 |
(2480) 0x4728cc B.NE 4728e0 |
(2480) 0x4728d0 LDR D1, [X22, X0,LSL #3] |
(2480) 0x4728d4 FABS D1, D1 |
(2480) 0x4728d8 FADD D0, D0, D1 |
(2480) 0x4728dc STR D0, [X16] |
(2480) 0x4728e0 ADD X1, X0, #1 |
(2480) 0x4728e4 ADD X0, X0, #1 |
(2480) 0x4728e8 CMP X17, X0 |
(2480) 0x4728ec B.EQ 472700 |
(2480) 0x4728f0 SUB X17, X17, X1 |
(2480) 0x4728f4 ADD X0, X11, X1,LSL #3 |
(2480) 0x4728f8 ADD X1, X12, X1,LSL #3 |
(2480) 0x4728fc B 472910 |
(2487) 0x472900 SUBS X17, X17, #2 |
(2487) 0x472904 ADD X0, X0, #16 |
(2487) 0x472908 ADD X1, X1, #16 |
(2487) 0x47290c B.EQ 472700 |
(2487) 0x472910 LDUR X2, [X1, #504] |
(2487) 0x472914 LDR X2, [X21, X2,LSL #3] |
(2487) 0x472918 CMP X18, X2 |
(2487) 0x47291c B.NE 472930 |
(2487) 0x472920 LDUR D1, [X0, #504] |
(2487) 0x472924 FABS D1, D1 |
(2487) 0x472928 FADD D0, D0, D1 |
(2487) 0x47292c STR D0, [X16] |
(2487) 0x472930 LDR X2, [X1] |
(2487) 0x472934 LDR X2, [X21, X2,LSL #3] |
(2487) 0x472938 CMP X18, X2 |
(2487) 0x47293c B.NE 472900 |
(2487) 0x472940 LDR D1, [X0] |
(2487) 0x472944 FABS D1, D1 |
(2487) 0x472948 FADD D0, D0, D1 |
(2487) 0x47294c STR D0, [X16] |
(2487) 0x472950 B 472900 |
(2480) 0x472954 ORR X1, XZR, X0 |
(2480) 0x472958 SUB X0, X0, X18 |
(2480) 0x47295c CMN X0, #4 |
(2480) 0x472960 B.HI 4729b8 |
(2480) 0x472964 SUB X18, X18, X1 |
(2480) 0x472968 ADD X0, X13, X1,LSL #3 |
(2484) 0x47296c LDUR D1, [X0, #496] |
(2484) 0x472970 SUBS X18, X18, #4 |
(2484) 0x472974 FABS D1, D1 |
(2484) 0x472978 FADD D0, D0, D1 |
(2484) 0x47297c STR D0, [X16] |
(2484) 0x472980 LDUR D1, [X0, #504] |
(2484) 0x472984 FABS D1, D1 |
(2484) 0x472988 FADD D0, D0, D1 |
(2484) 0x47298c STR D0, [X16] |
(2484) 0x472990 LDR D1, [X0] |
(2484) 0x472994 FABS D1, D1 |
(2484) 0x472998 FADD D0, D0, D1 |
(2484) 0x47299c STR D0, [X16] |
(2484) 0x4729a0 LDR D1, [X0, #8] |
(2484) 0x4729a4 ADD X0, X0, #32 |
(2484) 0x4729a8 FABS D1, D1 |
(2484) 0x4729ac FADD D0, D0, D1 |
(2484) 0x4729b0 STR D0, [X16] |
(2484) 0x4729b4 B.NE 47296c |
(2480) 0x4729b8 CBZ X26, 472700 |
(2480) 0x4729bc LDR X2, [X25, X17,LSL #3] |
(2480) 0x4729c0 LDR X18, [X25, X15,LSL #3] |
(2480) 0x4729c4 SUBS X0, X18, X2 |
(2480) 0x4729c8 B.LE 472700 |
(2480) 0x4729cc CMP X0, #6 |
(2480) 0x4729d0 B.CC 472a40 |
(2480) 0x4729d4 ADD X3, X22, X18,LSL #3 |
(2480) 0x4729d8 ADD X17, X8, X17,LSL #3 |
(2480) 0x4729dc ADD X1, X22, X2,LSL #3 |
(2480) 0x4729e0 CMP X16, X3 |
(2480) 0x4729e4 CCMP X1, X17, #2, #3 |
(2480) 0x4729e8 B.CC 472a40 |
(2480) 0x4729ec AND X1, X0, #8062 |
(2480) 0x4729f0 MOVI V2.2D, #0 |
(2480) 0x4729f4 MOV V2.D[0], V0.D[0] |
(2480) 0x4729f8 MOVI V1.2D, #0 |
(2480) 0x4729fc ADD X17, X2, X1 |
(2480) 0x472a00 ADD X2, X14, X2,LSL #3 |
(2480) 0x472a04 ORR X3, XZR, X1 |
(2483) 0x472a08 LDP Q0, Q3, [X2, #2032] |
(2483) 0x472a0c ADD X2, X2, #32 |
(2483) 0x472a10 SUBS X3, X3, #4 |
(2483) 0x472a14 FABS V3.2D, V3.2D |
(2483) 0x472a18 FABS V0.2D, V0.2D |
(2483) 0x472a1c FADD V1.2D, V1.2D, V3.2D |
(2483) 0x472a20 FADD V2.2D, V2.2D, V0.2D |
(2483) 0x472a24 B.NE 472a08 |
(2480) 0x472a28 FADD V0.2D, V1.2D, V2.2D |
(2480) 0x472a2c FADDP D0, V0.2D |
(2480) 0x472a30 STR D0, [X16] |
(2480) 0x472a34 CMP X0, X1 |
(2480) 0x472a38 B.EQ 472700 |
(2480) 0x472a3c B 472a44 |
(2480) 0x472a40 ORR X17, XZR, X2 |
(2480) 0x472a44 SUB W0, W18, W17 |
(2480) 0x472a48 ANDS X1, X0, #4160 |
(2480) 0x472a4c B.EQ 472a80 |
(2480) 0x472a50 ORR X0, XZR, X17 |
(2480) 0x472a54 HINT #0 |
(2480) 0x472a58 HINT #0 |
(2480) 0x472a5c HINT #0 |
(2482) 0x472a60 LDR D1, [X22, X0,LSL #3] |
(2482) 0x472a64 ADD X0, X0, #1 |
(2482) 0x472a68 SUBS X1, X1, #1 |
(2482) 0x472a6c FABS D1, D1 |
(2482) 0x472a70 FADD D0, D0, D1 |
(2482) 0x472a74 STR D0, [X16] |
(2482) 0x472a78 B.NE 472a60 |
(2480) 0x472a7c B 472a84 |
(2480) 0x472a80 ORR X0, XZR, X17 |
(2480) 0x472a84 SUB X17, X17, X18 |
(2480) 0x472a88 CMN X17, #4 |
(2480) 0x472a8c B.HI 472700 |
(2480) 0x472a90 SUB X17, X18, X0 |
(2480) 0x472a94 ADD X18, X14, X0,LSL #3 |
(2480) 0x472a98 HINT #0 |
(2480) 0x472a9c HINT #0 |
(2481) 0x472aa0 LDUR D1, [X18, #496] |
(2481) 0x472aa4 SUBS X17, X17, #4 |
(2481) 0x472aa8 FABS D1, D1 |
(2481) 0x472aac FADD D0, D0, D1 |
(2481) 0x472ab0 STR D0, [X16] |
(2481) 0x472ab4 LDUR D1, [X18, #504] |
(2481) 0x472ab8 FABS D1, D1 |
(2481) 0x472abc FADD D0, D0, D1 |
(2481) 0x472ac0 STR D0, [X16] |
(2481) 0x472ac4 LDR D1, [X18] |
(2481) 0x472ac8 FABS D1, D1 |
(2481) 0x472acc FADD D0, D0, D1 |
(2481) 0x472ad0 STR D0, [X16] |
(2481) 0x472ad4 LDR D1, [X18, #8] |
(2481) 0x472ad8 ADD X18, X18, #32 |
(2481) 0x472adc FABS D1, D1 |
(2481) 0x472ae0 FADD D0, D0, D1 |
(2481) 0x472ae4 STR D0, [X16] |
(2481) 0x472ae8 B.NE 472aa0 |
(2480) 0x472aec B 472700 |
0x472af0 CMP X27, #1 |
0x472af4 B.LT 472b74 |
0x472af8 ORR X8, XZR, X20 |
0x472afc ORR X9, XZR, X27 |
0x472b00 B 472b10 |
(2479) 0x472b04 SUBS X9, X9, #1 |
(2479) 0x472b08 ADD X8, X8, #8 |
(2479) 0x472b0c B.EQ 472b30 |
(2479) 0x472b10 LDR X10, [X28], #8 |
(2479) 0x472b14 LDR D0, [X19, X10,LSL #3] |
(2479) 0x472b18 FCMP D0, #0 |
(2479) 0x472b1c B.GE 472b04 |
(2479) 0x472b20 LDR D0, [X8] |
(2479) 0x472b24 FNEG D0, D0 |
(2479) 0x472b28 STR D0, [X8] |
(2479) 0x472b2c B 472b04 |
0x472b30 CMP X27, #1 |
0x472b34 B.LT 472b74 |
0x472b38 ORR X8, XZR, X20 |
0x472b3c HINT #0 |
(2478) 0x472b40 LDR D0, [X8] |
(2478) 0x472b44 FCMP D0, #0 |
(2478) 0x472b48 B.EQ 472b5c |
(2478) 0x472b4c SUBS X27, X27, #1 |
(2478) 0x472b50 ADD X8, X8, #8 |
(2478) 0x472b54 B.NE 472b40 |
0x472b58 B 472b74 |
0x472b5c ADRP X0, |
0x472b60 ADD X0, X0, #2415 |
0x472b64 MOVZ W1, #728 |
0x472b68 MOVZ W2, #12 |
0x472b6c ORR X3, XZR, XZR |
0x472b70 BL 4a9360 |
0x472b74 ORR X0, XZR, X21 |
0x472b78 BL 4a6d90 |
0x472b7c STR X20, [X24] |
0x472b80 ADRP X8, |
0x472b84 LDR X8, [X8, #3872] |
0x472b88 LDR X0, [X8] |
0x472b8c LDP X20, X19, [SP, #128] |
0x472b90 LDP X22, X21, [SP, #112] |
0x472b94 LDP X24, X23, [SP, #96] |
0x472b98 LDP X26, X25, [SP, #80] |
0x472b9c LDP X28, X27, [SP, #64] |
0x472ba0 LDP X29, X30, [SP, #48] |
0x472ba4 ADD SP, SP, #144 |
0x472ba8 RET |
0x472bac HINT #0 |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►100.00+ | hypre_BoomerAMGSetup | par_amg_setup.c:1386 | exec |
| ○ | hypre_PCGSetup | pcg.c:234 | exec |
| ○ | main | amg.c:398 | exec |
| ○ | __libc_start_call_main | libc.so.6 | |
| ○ | __libc_start_main | libc.so.6 | |
| ○ | _start | exec |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| Path / |
The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1
| Source file and lines | ams.c:547-738 |
| Module | exec |
| nb instructions | 193 |
| loop length | 772 |
| nb stack references | 0 |
| front end | 20.50 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | P16 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 20.00 | 20.00 | 14.08 | 14.08 | 14.00 | 14.00 | 13.92 | 13.92 | 2.00 | 2.00 | 2.00 | 2.00 | 13.83 | 13.50 | 13.67 | 6.00 | 6.00 |
| cycles | 20.00 | 20.00 | 14.08 | 14.08 | 14.00 | 14.00 | 13.92 | 13.92 | 2.00 | 2.00 | 2.00 | 2.00 | 13.83 | 13.50 | 13.67 | 6.00 | 6.00 |
| Cycles executing div or sqrt instructions | NA |
| Front-end | 20.50 |
| Overall L1 | 20.50 |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 14% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 14% |
| all | 1% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 2% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | P16 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| SUB SP, SP, #144 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| STP X29, X30, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (100.0%) |
| STP X28, X27, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (100.0%) |
| STP X26, X25, [SP, #80] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (100.0%) |
| STP X24, X23, [SP, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (100.0%) |
| STP X22, X21, [SP, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (100.0%) |
| STP X20, X19, [SP, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (100.0%) |
| ADD X29, SP, #48 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| LDP X8, X9, [X0, #56] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.50 | N/A |
| ORR X21, XZR, X0 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| ORR X24, XZR, X3 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| ORR X23, XZR, X2 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| STUR X1, [X29, #496] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| LDP X10, X27, [X8, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.50 | scal (100.0%) |
| LDR X28, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR X19, [X8, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDP X25, X8, [X9] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.50 | N/A |
| LDR X22, [X9, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (50.0%) |
| LDR X26, [X9, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (50.0%) |
| UBFM X0, X27, #61, #60 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| STR X10, [SP, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| STUR X8, [X29, #504] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| BL 4a6c20 <hypre_MAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ORR X20, XZR, X0 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| CBZ X23, 471e04 <hypre_ParCSRComputeL1Norms+0x84> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| STP X25, X24, [SP, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (100.0%) |
| LDR X25, [X21, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| CBZ X26, 471e0c <hypre_ParCSRComputeL1Norms+0x8c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (25.0%) |
| ORR X0, XZR, X26 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| BL 4a6c90 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ORR X21, XZR, X0 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| B 471e10 <hypre_ParCSRComputeL1Norms+0x90> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ORR X21, XZR, XZR | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| B 471ecc <hypre_ParCSRComputeL1Norms+0x14c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ORR X21, XZR, XZR | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| LDR X24, [X25, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR X8, [X25, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| STR X26, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| LDR X0, [X8, X24,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| CBZ X0, 471e3c <hypre_ParCSRComputeL1Norms+0xbc> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (25.0%) |
| BL 4a6c90 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ORR X26, XZR, X0 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| CMP X24, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (50.0%) |
| B.GE 471e48 <hypre_ParCSRComputeL1Norms+0xc8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| B 471ea4 <hypre_ParCSRComputeL1Norms+0x124> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ORR X26, XZR, XZR | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| CMP X24, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (50.0%) |
| B.LT 471ea4 <hypre_ParCSRComputeL1Norms+0x124> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR X9, [X25, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| ORR X8, XZR, XZR | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| ORR X10, XZR, XZR | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| LDR X11, [X9] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (50.0%) |
| B 471e6c <hypre_ParCSRComputeL1Norms+0xec> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| HINT #0 | N/A | ||||||||||||||||||||
| MOVZ W0, #11 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| ORR X1, XZR, X25 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| ORR X2, XZR, X26 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| ORR X3, XZR, X21 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| BL 480c50 <hypre_ParCSRCommHandleCreate> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| BL 481040 <hypre_ParCSRCommHandleDestroy> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ORR X0, XZR, X26 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| BL 4a6d90 <hypre_Free> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDP X25, X24, [SP, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.50 | N/A |
| LDR X26, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (50.0%) |
| LDP X8, X5, [X29, #1008] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.50 | N/A |
| CMP X8, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (50.0%) |
| B.LE 471f74 <hypre_ParCSRComputeL1Norms+0x1f4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X8, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (50.0%) |
| B.EQ 4721b0 <hypre_ParCSRComputeL1Norms+0x430> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X8, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (50.0%) |
| B.EQ 472440 <hypre_ParCSRComputeL1Norms+0x6c0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X8, #5 | 1 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (50.0%) |
| B.NE 472af0 <hypre_ParCSRComputeL1Norms+0xd70> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X27, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (50.0%) |
| B.LT 472b7c <hypre_ParCSRComputeL1Norms+0xdfc> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ORR X8, XZR, XZR | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| B.EQ 471f54 <hypre_ParCSRComputeL1Norms+0x1d4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| FMOV D0, #1.0000000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (50.0%) |
| AND X9, X27, #8063 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| ADD X10, X28, #8 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| ADD X11, X20, #8 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| HINT #0 | N/A | ||||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||||
| TBZ W27, #0, 472b7c <hypre_ParCSRComputeL1Norms+0xdfc> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR X9, [X28, X8,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| FMOV D1, #1.0000000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (50.0%) |
| LDR D0, [X19, X9,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (50.0%) |
| FCMP D0, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (50.0%) |
| FCSEL D0, D0, D1, #1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (50.0%) |
| STR D0, [X20, X8,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | scal (50.0%) |
| B 472b7c <hypre_ParCSRComputeL1Norms+0xdfc> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (50.0%) |
| B.EQ 4726c0 <hypre_ParCSRComputeL1Norms+0x940> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X8, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (50.0%) |
| B.NE 472af0 <hypre_ParCSRComputeL1Norms+0xd70> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X27, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (50.0%) |
| B.LT 472b74 <hypre_ParCSRComputeL1Norms+0xdf4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ADD X9, X20, X27,LSL #3 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| ADD X10, X22, #8 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| ADD X11, X5, #8 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| ADD X12, X22, #16 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| ORR X8, XZR, XZR | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| B 471fb0 <hypre_ParCSRComputeL1Norms+0x230> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| HINT #0 | N/A | ||||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||||
| CMP X27, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (50.0%) |
| B.LT 472b74 <hypre_ParCSRComputeL1Norms+0xdf4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR X11, [X28] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (50.0%) |
| ADD X8, X20, X27,LSL #3 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| ADD X10, X19, #16 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| ADD X12, X22, #16 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| ORR X9, XZR, XZR | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| B 4721e8 <hypre_ParCSRComputeL1Norms+0x468> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| HINT #0 | N/A | ||||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||||
| CMP X27, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (50.0%) |
| B.LT 472b74 <hypre_ParCSRComputeL1Norms+0xdf4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ORR X13, XZR, #3840 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| FMOV D0, #0.5000000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (50.0%) |
| FMOV V1.2D, #0.5000000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | vect (100.0%) |
| ADD X9, X20, X27,LSL #3 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| ADD X10, X22, #8 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| ADD X11, X5, #8 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| ADD X12, X22, #16 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| ORR X8, XZR, XZR | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| MOVK X13, #16373 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| FMOV D2, X13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (50.0%) |
| B 47248c <hypre_ParCSRComputeL1Norms+0x70c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| HINT #0 | N/A | ||||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||||
| CMP X27, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (50.0%) |
| B.LT 472b74 <hypre_ParCSRComputeL1Norms+0xdf4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR X10, [SP, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (50.0%) |
| ADD X8, X20, #8 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| ADD X9, X19, #8 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| ADD X11, X22, #8 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| ADD X12, X5, #8 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| ADD X13, X19, #16 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| ADD X14, X22, #16 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| ORR X17, XZR, XZR | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| ADD X10, X10, #8 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| B 47270c <hypre_ParCSRComputeL1Norms+0x98c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| HINT #0 | N/A | ||||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||||
| CMP X27, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (50.0%) |
| B.LT 472b74 <hypre_ParCSRComputeL1Norms+0xdf4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ORR X8, XZR, X20 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| ORR X9, XZR, X27 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| B 472b10 <hypre_ParCSRComputeL1Norms+0xd90> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X27, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (50.0%) |
| B.LT 472b74 <hypre_ParCSRComputeL1Norms+0xdf4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ORR X8, XZR, X20 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| HINT #0 | N/A | ||||||||||||||||||||
| B 472b74 <hypre_ParCSRComputeL1Norms+0xdf4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ADRP X0, <4b8b5c> | 1 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD X0, X0, #2415 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| MOVZ W1, #728 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (25.0%) |
| MOVZ W2, #12 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (25.0%) |
| ORR X3, XZR, XZR | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| BL 4a9360 <hypre_error_handler> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ORR X0, XZR, X21 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| BL 4a6d90 <hypre_Free> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| STR X20, [X24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| ADRP X8, <4dfb80> | 1 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR X8, [X8, #3872] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR X0, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDP X20, X19, [SP, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.50 | N/A |
| LDP X22, X21, [SP, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.50 | N/A |
| LDP X24, X23, [SP, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.50 | N/A |
| LDP X26, X25, [SP, #80] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.50 | N/A |
| LDP X28, X27, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.50 | N/A |
| LDP X29, X30, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.50 | N/A |
| ADD SP, SP, #144 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| RET | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| HINT #0 | N/A |
The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1
| Source file and lines | ams.c:547-738 |
| Module | exec |
| nb instructions | 193 |
| loop length | 772 |
| nb stack references | 0 |
| front end | 20.50 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | P16 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 20.00 | 20.00 | 14.08 | 14.08 | 14.00 | 14.00 | 13.92 | 13.92 | 2.00 | 2.00 | 2.00 | 2.00 | 13.83 | 13.50 | 13.67 | 6.00 | 6.00 |
| cycles | 20.00 | 20.00 | 14.08 | 14.08 | 14.00 | 14.00 | 13.92 | 13.92 | 2.00 | 2.00 | 2.00 | 2.00 | 13.83 | 13.50 | 13.67 | 6.00 | 6.00 |
| Cycles executing div or sqrt instructions | NA |
| Front-end | 20.50 |
| Overall L1 | 20.50 |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 14% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 14% |
| all | 1% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 2% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | P16 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| SUB SP, SP, #144 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| STP X29, X30, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (100.0%) |
| STP X28, X27, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (100.0%) |
| STP X26, X25, [SP, #80] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (100.0%) |
| STP X24, X23, [SP, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (100.0%) |
| STP X22, X21, [SP, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (100.0%) |
| STP X20, X19, [SP, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (100.0%) |
| ADD X29, SP, #48 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| LDP X8, X9, [X0, #56] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.50 | N/A |
| ORR X21, XZR, X0 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| ORR X24, XZR, X3 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| ORR X23, XZR, X2 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| STUR X1, [X29, #496] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| LDP X10, X27, [X8, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.50 | scal (100.0%) |
| LDR X28, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR X19, [X8, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDP X25, X8, [X9] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.50 | N/A |
| LDR X22, [X9, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (50.0%) |
| LDR X26, [X9, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (50.0%) |
| UBFM X0, X27, #61, #60 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| STR X10, [SP, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| STUR X8, [X29, #504] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| BL 4a6c20 <hypre_MAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ORR X20, XZR, X0 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| CBZ X23, 471e04 <hypre_ParCSRComputeL1Norms+0x84> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| STP X25, X24, [SP, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (100.0%) |
| LDR X25, [X21, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| CBZ X26, 471e0c <hypre_ParCSRComputeL1Norms+0x8c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (25.0%) |
| ORR X0, XZR, X26 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| BL 4a6c90 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ORR X21, XZR, X0 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| B 471e10 <hypre_ParCSRComputeL1Norms+0x90> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ORR X21, XZR, XZR | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| B 471ecc <hypre_ParCSRComputeL1Norms+0x14c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ORR X21, XZR, XZR | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| LDR X24, [X25, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR X8, [X25, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| STR X26, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| LDR X0, [X8, X24,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| CBZ X0, 471e3c <hypre_ParCSRComputeL1Norms+0xbc> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (25.0%) |
| BL 4a6c90 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ORR X26, XZR, X0 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| CMP X24, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (50.0%) |
| B.GE 471e48 <hypre_ParCSRComputeL1Norms+0xc8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| B 471ea4 <hypre_ParCSRComputeL1Norms+0x124> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ORR X26, XZR, XZR | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| CMP X24, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (50.0%) |
| B.LT 471ea4 <hypre_ParCSRComputeL1Norms+0x124> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR X9, [X25, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| ORR X8, XZR, XZR | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| ORR X10, XZR, XZR | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| LDR X11, [X9] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (50.0%) |
| B 471e6c <hypre_ParCSRComputeL1Norms+0xec> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| HINT #0 | N/A | ||||||||||||||||||||
| MOVZ W0, #11 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| ORR X1, XZR, X25 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| ORR X2, XZR, X26 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| ORR X3, XZR, X21 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| BL 480c50 <hypre_ParCSRCommHandleCreate> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| BL 481040 <hypre_ParCSRCommHandleDestroy> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ORR X0, XZR, X26 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| BL 4a6d90 <hypre_Free> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDP X25, X24, [SP, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.50 | N/A |
| LDR X26, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (50.0%) |
| LDP X8, X5, [X29, #1008] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.50 | N/A |
| CMP X8, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (50.0%) |
| B.LE 471f74 <hypre_ParCSRComputeL1Norms+0x1f4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X8, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (50.0%) |
| B.EQ 4721b0 <hypre_ParCSRComputeL1Norms+0x430> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X8, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (50.0%) |
| B.EQ 472440 <hypre_ParCSRComputeL1Norms+0x6c0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X8, #5 | 1 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (50.0%) |
| B.NE 472af0 <hypre_ParCSRComputeL1Norms+0xd70> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X27, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (50.0%) |
| B.LT 472b7c <hypre_ParCSRComputeL1Norms+0xdfc> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ORR X8, XZR, XZR | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| B.EQ 471f54 <hypre_ParCSRComputeL1Norms+0x1d4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| FMOV D0, #1.0000000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (50.0%) |
| AND X9, X27, #8063 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| ADD X10, X28, #8 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| ADD X11, X20, #8 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| HINT #0 | N/A | ||||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||||
| TBZ W27, #0, 472b7c <hypre_ParCSRComputeL1Norms+0xdfc> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR X9, [X28, X8,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| FMOV D1, #1.0000000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (50.0%) |
| LDR D0, [X19, X9,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (50.0%) |
| FCMP D0, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (50.0%) |
| FCSEL D0, D0, D1, #1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (50.0%) |
| STR D0, [X20, X8,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | scal (50.0%) |
| B 472b7c <hypre_ParCSRComputeL1Norms+0xdfc> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (50.0%) |
| B.EQ 4726c0 <hypre_ParCSRComputeL1Norms+0x940> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X8, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (50.0%) |
| B.NE 472af0 <hypre_ParCSRComputeL1Norms+0xd70> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X27, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (50.0%) |
| B.LT 472b74 <hypre_ParCSRComputeL1Norms+0xdf4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ADD X9, X20, X27,LSL #3 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| ADD X10, X22, #8 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| ADD X11, X5, #8 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| ADD X12, X22, #16 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| ORR X8, XZR, XZR | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| B 471fb0 <hypre_ParCSRComputeL1Norms+0x230> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| HINT #0 | N/A | ||||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||||
| CMP X27, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (50.0%) |
| B.LT 472b74 <hypre_ParCSRComputeL1Norms+0xdf4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR X11, [X28] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (50.0%) |
| ADD X8, X20, X27,LSL #3 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| ADD X10, X19, #16 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| ADD X12, X22, #16 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| ORR X9, XZR, XZR | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| B 4721e8 <hypre_ParCSRComputeL1Norms+0x468> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| HINT #0 | N/A | ||||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||||
| CMP X27, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (50.0%) |
| B.LT 472b74 <hypre_ParCSRComputeL1Norms+0xdf4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ORR X13, XZR, #3840 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| FMOV D0, #0.5000000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (50.0%) |
| FMOV V1.2D, #0.5000000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | vect (100.0%) |
| ADD X9, X20, X27,LSL #3 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| ADD X10, X22, #8 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| ADD X11, X5, #8 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| ADD X12, X22, #16 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| ORR X8, XZR, XZR | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| MOVK X13, #16373 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| FMOV D2, X13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (50.0%) |
| B 47248c <hypre_ParCSRComputeL1Norms+0x70c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| HINT #0 | N/A | ||||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||||
| CMP X27, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (50.0%) |
| B.LT 472b74 <hypre_ParCSRComputeL1Norms+0xdf4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR X10, [SP, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (50.0%) |
| ADD X8, X20, #8 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| ADD X9, X19, #8 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| ADD X11, X22, #8 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| ADD X12, X5, #8 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| ADD X13, X19, #16 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| ADD X14, X22, #16 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| ORR X17, XZR, XZR | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| ADD X10, X10, #8 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| B 47270c <hypre_ParCSRComputeL1Norms+0x98c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| HINT #0 | N/A | ||||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||||
| CMP X27, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (50.0%) |
| B.LT 472b74 <hypre_ParCSRComputeL1Norms+0xdf4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ORR X8, XZR, X20 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| ORR X9, XZR, X27 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| B 472b10 <hypre_ParCSRComputeL1Norms+0xd90> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X27, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (50.0%) |
| B.LT 472b74 <hypre_ParCSRComputeL1Norms+0xdf4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ORR X8, XZR, X20 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| HINT #0 | N/A | ||||||||||||||||||||
| B 472b74 <hypre_ParCSRComputeL1Norms+0xdf4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ADRP X0, <4b8b5c> | 1 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD X0, X0, #2415 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| MOVZ W1, #728 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (25.0%) |
| MOVZ W2, #12 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (25.0%) |
| ORR X3, XZR, XZR | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (50.0%) |
| BL 4a9360 <hypre_error_handler> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ORR X0, XZR, X21 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| BL 4a6d90 <hypre_Free> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| STR X20, [X24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| ADRP X8, <4dfb80> | 1 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR X8, [X8, #3872] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR X0, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDP X20, X19, [SP, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.50 | N/A |
| LDP X22, X21, [SP, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.50 | N/A |
| LDP X24, X23, [SP, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.50 | N/A |
| LDP X26, X25, [SP, #80] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.50 | N/A |
| LDP X28, X27, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.50 | N/A |
| LDP X29, X30, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.50 | N/A |
| ADD SP, SP, #144 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| RET | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| HINT #0 | N/A |
| Run 1x1 | Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_NUM_THREADS: 1OMP_PLACES: threads |
|---|---|
| Run 1x2 | Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 2OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads |
| Run 1x4 | Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 4OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads |
| Run 1x8 | Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 8OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads |
| Run 1x16 | Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 16OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads |
| Run 1x24 | Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 24OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads |
| Run 1x32 | Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 32OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads |
| Run 1x40 | Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 40OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads |
| Run 1x48 | Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 48OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads |
| Run 1x56 | Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 56OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads |
| Run 1x64 | Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 64OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads |
| Run 1x72 | Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 72OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads |
| Run 1x80 | Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 80OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads |
| Run 1x88 | Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 88OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads |
| Run 1x96 | Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 96OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads |
| (1x1) Efficiency | (1x1) Potential Speed-Up (%) | (1x2) Efficiency | (1x2) Potential Speed-Up (%) | (1x4) Efficiency | (1x4) Potential Speed-Up (%) | (1x8) Efficiency | (1x8) Potential Speed-Up (%) | (1x16) Efficiency | (1x16) Potential Speed-Up (%) | (1x24) Efficiency | (1x24) Potential Speed-Up (%) | (1x32) Efficiency | (1x32) Potential Speed-Up (%) | (1x40) Efficiency | (1x40) Potential Speed-Up (%) | (1x48) Efficiency | (1x48) Potential Speed-Up (%) | (1x56) Efficiency | (1x56) Potential Speed-Up (%) | (1x64) Efficiency | (1x64) Potential Speed-Up (%) | (1x72) Efficiency | (1x72) Potential Speed-Up (%) | (1x80) Efficiency | (1x80) Potential Speed-Up (%) | (1x88) Efficiency | (1x88) Potential Speed-Up (%) | (1x96) Efficiency | (1x96) Potential Speed-Up (%) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 1 | 0 |
| Run | Number of threads | Efficiency (ideal is 1) | Speedup | Ideal Speedup | Time (s) | Coverage (%) |
|---|---|---|---|---|---|---|
| 1x1 | 1 | 1 | 1 | 1 | 0.80999982357025 | 0.30447813868523 |
| 1x2 | ||||||
| 1x4 | ||||||
| 1x8 | ||||||
| 1x16 | ||||||
| 1x24 | ||||||
| 1x32 | ||||||
| 1x40 | ||||||
| 1x48 | ||||||
| 1x56 | ||||||
| 1x64 | ||||||
| 1x72 | ||||||
| 1x80 | ||||||
| 1x88 | ||||||
| 1x96 |
| Name | Coverage (%) | Time (s) |
|---|---|---|
| ▼hypre_ParCSRComputeL1Norms– | 0.30 | 0.81 |
| ○Loop 2479 - ams.c:720-722 - exec | 0.09 | 0.25 |
| ▼Loop 2480 - ams.c:602-629 - exec– | 0.03 | 0.08 |
| ○Loop 2486 - ams.c:609-609 - exec | 0.13 | 0.33 |
| ○Loop 2485 - ams.c:608-609 - exec | 0.04 | 0.10 |
| ○Loop 2481 - ams.c:613-614 - exec | 0.00 | 0.00 |
| ○Loop 2482 - ams.c:613-614 - exec | 0.00 | 0.00 |
| ○Loop 2488 - ams.c:621-623 - exec | 0.00 | 0.00 |
| ○Loop 2487 - ams.c:627-629 - exec | 0.00 | 0.00 |
| ○Loop 2483 - ams.c:614-614 - exec | 0.00 | 0.00 |
| ○Loop 2484 - ams.c:608-609 - exec | 0.00 | 0.00 |
| ○Loop 2478 - ams.c:724-726 - exec | 0.01 | 0.03 |
| ○Loop 2509 - ams.c:708-711 - exec | 0.00 | 0.00 |
| ▼Loop 2496 - ams.c:664-671 - exec– | 0.00 | 0.00 |
| ○Loop 2498 - ams.c:670-670 - exec | 0.00 | 0.00 |
| ○Loop 2502 - ams.c:670-671 - exec | 0.00 | 0.00 |
| ▼Loop 2495 - ams.c:664-671 - exec– | 0.00 | 0.00 |
| ○Loop 2501 - ams.c:668-668 - exec | 0.00 | 0.00 |
| ○Loop 2500 - ams.c:667-668 - exec | 0.00 | 0.00 |
| ○Loop 2499 - ams.c:667-668 - exec | 0.00 | 0.00 |
| ○Loop 2497 - ams.c:671-671 - exec | 0.00 | 0.00 |
| ○Loop 2503 - ams.c:670-671 - exec | 0.00 | 0.00 |
| ▼Loop 2489 - ams.c:676-703 - exec– | 0.00 | 0.00 |
| ○Loop 2494 - ams.c:686-686 - exec | 0.00 | 0.00 |
| ▼Loop 2490 - ams.c:676-703 - exec– | 0.00 | 0.00 |
| ○Loop 2491 - ams.c:695-697 - exec | 0.00 | 0.00 |
| ○Loop 2492 - ams.c:685-686 - exec | 0.00 | 0.00 |
| ○Loop 2493 - ams.c:685-686 - exec | 0.00 | 0.00 |
| ▼Loop 2508 - ams.c:636-657 - exec– | 0.00 | 0.00 |
| ▼Loop 2504 - ams.c:636-657 - exec– | 0.00 | 0.00 |
| ○Loop 2505 - ams.c:645-646 - exec | 0.00 | 0.00 |
| ○Loop 2506 - ams.c:645-646 - exec | 0.00 | 0.00 |
| ○Loop 2507 - ams.c:646-646 - exec | 0.00 | 0.00 |
| ▼Loop 2510 - ams.c:586-591 - exec– | 0.00 | 0.00 |
| ○Loop 2511 - ams.c:589-591 - exec | 0.00 | 0.00 |