OV - exec - Function hypre

	Function: hypre_ParCSRRelax	Module: exec	Source: ams.c:63-330 [...]	Coverage (incl. loops): 2.08% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 63 - 330

--------------------------------------------------------------------------------

63: {

[...]

70:    for (sweep = 0; sweep < relax_times; sweep++)

71:    {

72:       if (relax_type == 1) /* l1-scaled Jacobi */

73:       {

74: 	 HYPRE_Int i, num_rows = hypre_ParCSRMatrixNumRows(A);

75:          hypre_ParVectorCopy(f,v);

76:          hypre_ParCSRMatrixMatvec(-relax_weight, A, u, relax_weight, v);

77:          /* u += w D^{-1}(f - A u), where D_ii = ||A(i,:)||_1 */

78:          for (i = 0; i < num_rows; i++)

79:             u_data[i] += v_data[i] / l1_norms[i];

80:       }

81:       else if (relax_type == 2 || relax_type == 4) /* offd-l1-scaled block GS */

82:       {

83:          hypre_CSRMatrix *A_diag = hypre_ParCSRMatrixDiag(A);

84:          HYPRE_Real *A_diag_data = hypre_CSRMatrixData(A_diag);

85:          HYPRE_Int *A_diag_I = hypre_CSRMatrixI(A_diag);

86:          HYPRE_Int *A_diag_J = hypre_CSRMatrixJ(A_diag);

87:

88:          hypre_CSRMatrix *A_offd = hypre_ParCSRMatrixOffd(A);

89:          HYPRE_Int *A_offd_I = hypre_CSRMatrixI(A_offd);

90:          HYPRE_Int *A_offd_J = hypre_CSRMatrixJ(A_offd);

91:          HYPRE_Real *A_offd_data = hypre_CSRMatrixData(A_offd);

92:

93:          HYPRE_Int i, j;

94:          HYPRE_Int num_rows = hypre_CSRMatrixNumRows(A_diag);

95:          HYPRE_Int num_cols_offd = hypre_CSRMatrixNumCols(A_offd);

96:          HYPRE_Real *u_offd_data = hypre_TAlloc(HYPRE_Real,num_cols_offd);

97:

98:          HYPRE_Real res;

99:

100:          HYPRE_Int num_procs;

101:          hypre_MPI_Comm_size(hypre_ParCSRMatrixComm(A), &num_procs);

102:

103:          /* Copy off-diagonal values of u to the current processor */

104:          if (num_procs > 1)

105:          {

106:             hypre_ParCSRCommPkg *comm_pkg = hypre_ParCSRMatrixCommPkg(A);

[...]

113:             if (!comm_pkg)

114:             {

115:                hypre_MatvecCommPkgCreate(A);

116:                comm_pkg = hypre_ParCSRMatrixCommPkg(A);

117:             }

118:

119:             num_sends = hypre_ParCSRCommPkgNumSends(comm_pkg);

120:             u_buf_data = hypre_TAlloc(HYPRE_Real,

121:                                       hypre_ParCSRCommPkgSendMapStart(comm_pkg, num_sends));

122:

123:             for (i = 0; i < num_sends; i++)

124:             {

125:                start = hypre_ParCSRCommPkgSendMapStart(comm_pkg, i);

126:                for (j = start; j < hypre_ParCSRCommPkgSendMapStart(comm_pkg,i+1); j++)

127:                   u_buf_data[index++] = u_data[hypre_ParCSRCommPkgSendMapElmt(comm_pkg,j)];

128:             }

129:             comm_handle = hypre_ParCSRCommHandleCreate(1,comm_pkg,u_buf_data,u_offd_data);

130:             hypre_ParCSRCommHandleDestroy(comm_handle);

131:

132:             hypre_TFree(u_buf_data);

133:          }

134:

135:          if (relax_weight == 1.0 && omega == 1.0) /* symmetric Gauss-Seidel */

136:          {

137:             /* Forward local pass */

138:             for (i = 0; i < num_rows; i++)

139:             {

140:                res = f_data[i];

141:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

142:                   res -= A_diag_data[j] * u_data[A_diag_J[j]];

143:                if (num_cols_offd)

144:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

145:                      res -= A_offd_data[j] * u_offd_data[A_offd_J[j]];

146:                u_data[i] += res / l1_norms[i];

147:             }

148:             /* Backward local pass */

149:             for (i = num_rows-1; i > -1; i--)

150:             {

151:                res = f_data[i];

152:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

153:                   res -= A_diag_data[j] * u_data[A_diag_J[j]];

154:                if (num_cols_offd)

155:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

156:                      res -= A_offd_data[j] * u_offd_data[A_offd_J[j]];

157:                u_data[i] += res / l1_norms[i];

158:             }

159:          }

160:          else if (relax_weight == 1.0) /* SSOR */

161:          {

162:             /* Forward local pass */

163:             for (i = 0; i < num_rows; i++)

164:             {

165:                res = f_data[i];

166:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

167:                   res -= A_diag_data[j] * u_data[A_diag_J[j]];

168:                if (num_cols_offd)

169:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

170:                      res -= A_offd_data[j] * u_offd_data[A_offd_J[j]];

171:                u_data[i] += omega * res / l1_norms[i];

172:             }

173:             /* Backward local pass */

174:             for (i = num_rows-1; i > -1; i--)

175:             {

176:                res = f_data[i];

177:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

178:                   res -= A_diag_data[j] * u_data[A_diag_J[j]];

179:                if (num_cols_offd)

180:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

181:                      res -= A_offd_data[j] * u_offd_data[A_offd_J[j]];

182:                u_data[i] += omega * res / l1_norms[i];

[...]

192:             for (i = 0; i < num_rows; i++)

193:             {

194:                dif = 0.0;

195:                v_data[i] = u_data[i];

196:                res = f_data[i];

197:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

198:                {

199:                   res -= A_diag_data[j] * u_data[A_diag_J[j]];

200:                   if (A_diag_J[j] < i)

201:                      dif += A_diag_data[j] * (v_data[A_diag_J[j]] - u_data[A_diag_J[j]]);

202:                }

203:                if (num_cols_offd)

204:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

205:                      res -= A_offd_data[j] * u_offd_data[A_offd_J[j]];

206:                u_data[i] += (c1 * res + c2 * dif) / l1_norms[i];

207:             }

208:             /* Backward local pass */

209:             for (i = num_rows-1; i > -1; i--)

210:             {

211:                dif = 0.0;

212:                res = f_data[i];

213:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

214:                {

215:                   res -= A_diag_data[j] * u_data[A_diag_J[j]];

216:                   if (A_diag_J[j] > i)

217:                      dif += A_diag_data[j] * (v_data[A_diag_J[j]] - u_data[A_diag_J[j]]);

218:                }

219:                if (num_cols_offd)

220:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

221:                      res -= A_offd_data[j] * u_offd_data[A_offd_J[j]];

222:                u_data[i] += (c1 * res + c2 * dif) / l1_norms[i];

[...]

230:          hypre_CSRMatrix *A_diag = hypre_ParCSRMatrixDiag(A);

231:          HYPRE_Real *A_diag_data = hypre_CSRMatrixData(A_diag);

232:          HYPRE_Int *A_diag_I = hypre_CSRMatrixI(A_diag);

233:          HYPRE_Int *A_diag_J = hypre_CSRMatrixJ(A_diag);

234:

235:          hypre_CSRMatrix *A_offd = hypre_ParCSRMatrixOffd(A);

236:          HYPRE_Int *A_offd_I = hypre_CSRMatrixI(A_offd);

237:          HYPRE_Int *A_offd_J = hypre_CSRMatrixJ(A_offd);

238:          HYPRE_Real *A_offd_data = hypre_CSRMatrixData(A_offd);

239:

240:          HYPRE_Int i, j;

241:          HYPRE_Int num_rows = hypre_CSRMatrixNumRows(A_diag);

242:          HYPRE_Int num_cols_offd = hypre_CSRMatrixNumCols(A_offd);

243:          HYPRE_Real *u_offd_data = hypre_TAlloc(HYPRE_Real,num_cols_offd);

244:

245:          HYPRE_Real res;

246:

247:          HYPRE_Int num_procs;

248:          hypre_MPI_Comm_size(hypre_ParCSRMatrixComm(A), &num_procs);

249:

250:          /* Copy off-diagonal values of u to the current processor */

251:          if (num_procs > 1)

252:          {

253:             hypre_ParCSRCommPkg *comm_pkg = hypre_ParCSRMatrixCommPkg(A);

[...]

260:             if (!comm_pkg)

261:             {

262:                hypre_MatvecCommPkgCreate(A);

263:                comm_pkg = hypre_ParCSRMatrixCommPkg(A);

264:             }

265:

266:             num_sends = hypre_ParCSRCommPkgNumSends(comm_pkg);

267:             u_buf_data = hypre_TAlloc(HYPRE_Real,

268:                                       hypre_ParCSRCommPkgSendMapStart(comm_pkg, num_sends));

269:

270:             for (i = 0; i < num_sends; i++)

271:             {

272:                start = hypre_ParCSRCommPkgSendMapStart(comm_pkg, i);

273:                for (j = start; j < hypre_ParCSRCommPkgSendMapStart(comm_pkg,i+1); j++)

274:                   u_buf_data[index++] = u_data[hypre_ParCSRCommPkgSendMapElmt(comm_pkg,j)];

275:             }

276:             comm_handle = hypre_ParCSRCommHandleCreate(1,comm_pkg,u_buf_data,u_offd_data);

277:             hypre_ParCSRCommHandleDestroy(comm_handle);

278:

279:             hypre_TFree(u_buf_data);

280:          }

281:

282:          /* Forward local pass */

283:          for (i = 0; i < num_rows; i++)

284:          {

285:             res = f_data[i];

286:             for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

287:                res -= A_diag_data[j] * u_data[A_diag_J[j]];

288:             if (num_cols_offd)

289:                for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

290:                   res -= A_offd_data[j] * u_offd_data[A_offd_J[j]];

291:             res /= l1_norms[i];

292:             for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

293:                u_data[A_diag_J[j]] += omega * res * A_diag_data[j];

294:          }

295:

296:          /* Backward local pass */

297:          for (i = num_rows-1; i > -1; i--)

298:          {

299:             res = f_data[i];

300:             for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

301:                res -= A_diag_data[j] * u_data[A_diag_J[j]];

302:             if (num_cols_offd)

303:                for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

304:                   res -= A_offd_data[j] * u_offd_data[A_offd_J[j]];

305:             res /= l1_norms[i];

306:             for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

307:                u_data[A_diag_J[j]] += omega * res * A_diag_data[j];

[...]

316:             hypre_ParCSRRelax_Cheby(A,

[...]

326:             hypre_BoomerAMGRelax(A, f, NULL, hypre_abs(relax_type), 0, relax_weight,

327:                                  omega, l1_norms, u, v, z);

328:       }

329:    }

330:    return hypre_error_flag;

0x46f420 SUB	SP, SP, #384

0x46f424 STP	D15, D14, [SP, #224]

0x46f428 STP	D13, D12, [SP, #240]

0x46f42c STP	D11, D10, [SP, #256]

0x46f430 STP	D9, D8, [SP, #272]

0x46f434 STP	X29, X30, [SP, #288]

0x46f438 STP	X28, X27, [SP, #304]

0x46f43c STP	X26, X25, [SP, #320]

0x46f440 STP	X24, X23, [SP, #336]

0x46f444 STP	X22, X21, [SP, #352]

0x46f448 STP	X20, X19, [SP, #368]

0x46f44c ADD	X29, SP, #288

0x46f450 STP	X1, X6, [SP, #136]

0x46f454 STR	X5, [SP, #80]

0x46f458 STUR	X0, [X29, #392]

0x46f45c CMP	X3, #1

0x46f460 B.LT	470ec0

0x46f464 LDR	X8, [X29, #96]

0x46f468 FMOV	D14, #1.0000000

0x46f46c FMSUB	D13, D0, D1, D1

0x46f470 FMUL	D15, D1, D0

0x46f474 FMOV	D8, D4

0x46f478 ORR	X27, XZR, X7

0x46f47c ORR	X5, XZR, X4

0x46f480 ORR	X20, XZR, X3

0x46f484 ORR	X21, XZR, X2

0x46f488 ORR	X23, XZR, XZR

0x46f48c STR	X7, [SP, #88]

0x46f490 STUR	X4, [X29, #400]

0x46f494 STP	X2, X3, [SP, #120]

0x46f498 FMOV	D9, D3

0x46f49c FMOV	D10, D2

0x46f4a0 FMOV	D11, D1

0x46f4a4 FMOV	D12, D0

0x46f4a8 STR	X8, [SP, #104]

0x46f4ac LDR	X8, [SP, #144]

0x46f4b0 FCMP	D0, D14

0x46f4b4 FNEG	D0, D0

0x46f4b8 STR	D0, [SP, #64]

0x46f4bc LDR	X8, [X8, #48]

0x46f4c0 LDR	X25, [X8]

0x46f4c4 LDR	X8, [SP, #136]

0x46f4c8 LDR	X8, [X8, #48]

0x46f4cc LDR	X8, [X8]

0x46f4d0 STUR	X8, [X29, #408]

0x46f4d4 LDR	X8, [X7, #48]

0x46f4d8 LDR	X10, [X8]

0x46f4dc CSINC	W8, WZR, WZR, #1

0x46f4e0 FCMP	D1, D14

0x46f4e4 CSINC	W9, WZR, WZR, #1

0x46f4e8 CMP	X2, #0

0x46f4ec AND	W8, W8, W9

0x46f4f0 STR	W8, [SP, #100]

0x46f4f4 CSNEG	X8, X2, X2, #5

0x46f4f8 ADD	X9, X10, #16

0x46f4fc STR	X10, [SP, #112]

0x46f500 STR	X8, [SP, #72]

0x46f504 ADD	X8, X4, #16

0x46f508 STP	X8, X9, [SP, #24]

0x46f50c ADD	X8, X25, #16

0x46f510 ADD	X9, X25, #8

0x46f514 STR	X8, [SP, #16]

0x46f518 ADD	X8, X4, #8

0x46f51c STP	X8, X9, [SP, #48]

0x46f520 ADD	X8, X10, #8

0x46f524 STR	X8, [SP, #40]

0x46f528 B	46f54c

    (2376) 0x46f52c ORR	X0, XZR, X28

    (2376) 0x46f530 BL	4a6d90

    (2376) 0x46f534 LDUR	X5, [X29, #400]

    (2376) 0x46f538 LDP	X21, X20, [SP, #120]

    (2376) 0x46f53c LDUR	X23, [X29, #384]

      (2373) 0x46f540 ADD	X23, X23, #1

      (2373) 0x46f544 CMP	X23, X20

      (2373) 0x46f548 B.EQ	470ec0

      (2373) 0x46f54c CMP	X21, #2

      (2373) 0x46f550 B.LE	46f5a0

      (2373) 0x46f554 CMP	X21, #3

      (2373) 0x46f558 B.EQ	46f730

      (2373) 0x46f55c CMP	X21, #4

      (2373) 0x46f560 B.EQ	46f5b0

      (2373) 0x46f564 CMP	X21, #16

      (2373) 0x46f568 B.NE	46fea4

      (2373) 0x46f56c LDUR	X0, [X29, #392]

      (2373) 0x46f570 LDP	X1, X5, [SP, #136]

      (2373) 0x46f574 LDR	X2, [SP, #80]

      (2373) 0x46f578 FMOV	D0, D10

      (2373) 0x46f57c FMOV	D1, D9

      (2373) 0x46f580 FMOV	D2, D8

      (2373) 0x46f584 MOVZ	W3, #1

      (2373) 0x46f588 ORR	X4, XZR, XZR

      (2373) 0x46f58c ORR	X6, XZR, X27

      (2373) 0x46f590 LDR	X7, [SP, #104]

      (2373) 0x46f594 BL	460030

      (2373) 0x46f598 B	46fed0

0x46f59c HINT	#0

      (2373) 0x46f5a0 CMP	X21, #1

      (2373) 0x46f5a4 B.EQ	46f8ac

      (2373) 0x46f5a8 CMP	X21, #2

      (2373) 0x46f5ac B.NE	46fea4

    (2376) 0x46f5b0 LDUR	X21, [X29, #392]

    (2376) 0x46f5b4 LDP	X8, X9, [X21, #56]

    (2376) 0x46f5b8 LDP	X10, X20, [X8]

    (2376) 0x46f5bc LDR	X26, [X8, #48]

    (2376) 0x46f5c0 LDR	X24, [X9, #48]

    (2376) 0x46f5c4 STP	X10, X23, [X29, #888]

    (2376) 0x46f5c8 LDR	X23, [X8, #16]

    (2376) 0x46f5cc LDR	X8, [X9, #24]

    (2376) 0x46f5d0 LDP	X10, X19, [X9]

    (2376) 0x46f5d4 UBFM	X0, X8, #61, #60

    (2376) 0x46f5d8 STP	X8, X10, [X29, #928]

    (2376) 0x46f5dc BL	4a6c20

    (2376) 0x46f5e0 ORR	X28, XZR, X0

    (2376) 0x46f5e4 LDR	X0, [X21]

    (2376) 0x46f5e8 SUB	X1, X29, #80

    (2376) 0x46f5ec BL	4a7e70

    (2376) 0x46f5f0 LDUR	X8, [X29, #432]

    (2376) 0x46f5f4 CMP	X8, #2

    (2376) 0x46f5f8 B.LT	46f99c

    (2376) 0x46f5fc LDUR	X8, [X29, #392]

    (2376) 0x46f600 LDR	X21, [X8, #112]

    (2376) 0x46f604 CBNZ	X21, 46f618

    (2376) 0x46f608 LDUR	X21, [X29, #392]

    (2376) 0x46f60c ORR	X0, XZR, X21

    (2376) 0x46f610 BL	481820

    (2376) 0x46f614 LDR	X21, [X21, #112]

    (2376) 0x46f618 LDR	X22, [X21, #8]

    (2376) 0x46f61c LDR	X8, [X21, #24]

    (2376) 0x46f620 LDR	X8, [X8, X22,LSL #3]

    (2376) 0x46f624 UBFM	X0, X8, #61, #60

    (2376) 0x46f628 BL	4a6c20

    (2376) 0x46f62c ORR	X27, XZR, X0

    (2376) 0x46f630 CMP	X22, #1

    (2376) 0x46f634 B.LT	46f978

    (2376) 0x46f638 LDR	X9, [X21, #24]

    (2376) 0x46f63c ORR	X8, XZR, XZR

    (2376) 0x46f640 ORR	X14, XZR, XZR

    (2376) 0x46f644 ADD	X10, X27, #16

    (2376) 0x46f648 LDR	X11, [X9]

    (2376) 0x46f64c B	46f670

0x46f650 HINT	#0

0x46f654 HINT	#0

0x46f658 HINT	#0

0x46f65c HINT	#0

      (2412) 0x46f660 ORR	X12, XZR, X14

      (2412) 0x46f664 ORR	X14, XZR, X12

      (2412) 0x46f668 CMP	X8, X22

      (2412) 0x46f66c B.EQ	46f978

      (2412) 0x46f670 ADD	X8, X8, #1

      (2412) 0x46f674 ORR	X13, XZR, X11

      (2412) 0x46f678 LDR	X11, [X9, X8,LSL #3]

      (2412) 0x46f67c SUBS	X16, X13, X11

      (2412) 0x46f680 B.GE	46f660

      (2412) 0x46f684 LDR	X15, [X21, #32]

      (2412) 0x46f688 SUB	W12, W11, W13

      (2412) 0x46f68c ANDS	X17, X12, #4160

      (2412) 0x46f690 B.EQ	46f6cc

      (2412) 0x46f694 HINT	#0

      (2412) 0x46f698 HINT	#0

      (2412) 0x46f69c HINT	#0

        (2414) 0x46f6a0 LDR	X12, [X15, X13,LSL #3]

        (2414) 0x46f6a4 ADD	X13, X13, #1

        (2414) 0x46f6a8 SUBS	X17, X17, #1

        (2414) 0x46f6ac LDR	D0, [X25, X12,LSL #3]

        (2414) 0x46f6b0 ADD	X12, X14, #1

        (2414) 0x46f6b4 STR	D0, [X27, X14,LSL #3]

        (2414) 0x46f6b8 ORR	X14, XZR, X12

        (2414) 0x46f6bc B.NE	46f6a0

      (2412) 0x46f6c0 CMN	X16, #4

      (2412) 0x46f6c4 B.HI	46f664

      (2412) 0x46f6c8 B	46f6d8

      (2412) 0x46f6cc ORR	X12, XZR, X14

      (2412) 0x46f6d0 CMN	X16, #4

      (2412) 0x46f6d4 B.HI	46f664

      (2412) 0x46f6d8 ADD	X15, X15, X13,LSL #3

      (2412) 0x46f6dc ADD	X14, X10, X12,LSL #3

      (2412) 0x46f6e0 SUB	X13, X11, X13

      (2412) 0x46f6e4 ADD	X15, X15, #16

        (2413) 0x46f6e8 LDUR	X16, [X15, #496]

        (2413) 0x46f6ec ADD	X12, X12, #4

        (2413) 0x46f6f0 SUBS	X13, X13, #4

        (2413) 0x46f6f4 LDR	D0, [X25, X16,LSL #3]

        (2413) 0x46f6f8 STUR	D0, [X14, #496]

        (2413) 0x46f6fc LDUR	X16, [X15, #504]

        (2413) 0x46f700 LDR	D0, [X25, X16,LSL #3]

        (2413) 0x46f704 STUR	D0, [X14, #504]

        (2413) 0x46f708 LDR	X16, [X15]

        (2413) 0x46f70c LDR	D0, [X25, X16,LSL #3]

        (2413) 0x46f710 STR	D0, [X14]

        (2413) 0x46f714 LDR	X16, [X15, #8]

        (2413) 0x46f718 ADD	X15, X15, #32

        (2413) 0x46f71c LDR	D0, [X25, X16,LSL #3]

        (2413) 0x46f720 STR	D0, [X14, #8]

        (2413) 0x46f724 ADD	X14, X14, #32

        (2413) 0x46f728 B.NE	46f6e8

      (2412) 0x46f72c B	46f664

    (2376) 0x46f730 LDUR	X21, [X29, #392]

    (2376) 0x46f734 STUR	X23, [X29, #384]

    (2376) 0x46f738 LDP	X8, X9, [X21, #56]

    (2376) 0x46f73c LDR	X19, [X8, #48]

    (2376) 0x46f740 LDP	X23, X22, [X8]

    (2376) 0x46f744 LDR	X20, [X8, #16]

    (2376) 0x46f748 LDR	X8, [X9, #24]

    (2376) 0x46f74c LDP	X10, X24, [X9]

    (2376) 0x46f750 LDR	X26, [X9, #48]

    (2376) 0x46f754 UBFM	X0, X8, #61, #60

    (2376) 0x46f758 STP	X8, X10, [X29, #928]

    (2376) 0x46f75c BL	4a6c20

    (2376) 0x46f760 ORR	X28, XZR, X0

    (2376) 0x46f764 LDR	X0, [X21]

    (2376) 0x46f768 SUB	X1, X29, #80

    (2376) 0x46f76c BL	4a7e70

    (2376) 0x46f770 LDUR	X8, [X29, #432]

    (2376) 0x46f774 STUR	X23, [X29, #376]

    (2376) 0x46f778 CMP	X8, #1

    (2376) 0x46f77c B.LE	47016c

    (2376) 0x46f780 LDUR	X8, [X29, #392]

    (2376) 0x46f784 LDR	X21, [X8, #112]

    (2376) 0x46f788 CBNZ	X21, 46f79c

    (2376) 0x46f78c LDUR	X21, [X29, #392]

    (2376) 0x46f790 ORR	X0, XZR, X21

    (2376) 0x46f794 BL	481820

    (2376) 0x46f798 LDR	X21, [X21, #112]

    (2376) 0x46f79c LDR	X23, [X21, #8]

    (2376) 0x46f7a0 LDR	X8, [X21, #24]

    (2376) 0x46f7a4 LDR	X8, [X8, X23,LSL #3]

    (2376) 0x46f7a8 UBFM	X0, X8, #61, #60

    (2376) 0x46f7ac BL	4a6c20

    (2376) 0x46f7b0 ORR	X27, XZR, X0

    (2376) 0x46f7b4 CMP	X23, #1

    (2376) 0x46f7b8 B.LT	470144

    (2376) 0x46f7bc LDR	X9, [X21, #24]

    (2376) 0x46f7c0 ORR	X12, XZR, XZR

    (2376) 0x46f7c4 ORR	X8, XZR, XZR

    (2376) 0x46f7c8 ADD	X10, X27, #16

    (2376) 0x46f7cc LDR	X11, [X9]

    (2376) 0x46f7d0 B	46f7ec

0x46f7d4 HINT	#0

0x46f7d8 HINT	#0

0x46f7dc HINT	#0

      (2431) 0x46f7e0 ORR	X12, XZR, X14

      (2431) 0x46f7e4 CMP	X8, X23

      (2431) 0x46f7e8 B.EQ	470144

      (2431) 0x46f7ec ADD	X8, X8, #1

      (2431) 0x46f7f0 ORR	X13, XZR, X11

      (2431) 0x46f7f4 LDR	X11, [X9, X8,LSL #3]

      (2431) 0x46f7f8 SUBS	X15, X13, X11

      (2431) 0x46f7fc B.GE	46f7e4

      (2431) 0x46f800 LDR	X16, [X21, #32]

      (2431) 0x46f804 SUB	W14, W11, W13

      (2431) 0x46f808 ORR	X17, XZR, X12

      (2431) 0x46f80c ORR	X18, XZR, X13

      (2431) 0x46f810 ANDS	X14, X14, #4160

      (2431) 0x46f814 B.EQ	46f840

      (2431) 0x46f818 ORR	X0, XZR, X12

      (2431) 0x46f81c ORR	X18, XZR, X13

        (2433) 0x46f820 LDR	X17, [X16, X18,LSL #3]

        (2433) 0x46f824 ADD	X18, X18, #1

        (2433) 0x46f828 SUBS	X14, X14, #1

        (2433) 0x46f82c LDR	D0, [X25, X17,LSL #3]

        (2433) 0x46f830 ADD	X17, X0, #1

        (2433) 0x46f834 STR	D0, [X27, X0,LSL #3]

        (2433) 0x46f838 ORR	X0, XZR, X17

        (2433) 0x46f83c B.NE	46f820

      (2431) 0x46f840 ADD	X14, X12, X11

      (2431) 0x46f844 SUB	X14, X14, X13

      (2431) 0x46f848 CMN	X15, #4

      (2431) 0x46f84c B.HI	46f7e0

      (2431) 0x46f850 ADD	X12, X12, X11

      (2431) 0x46f854 ADD	X15, X16, X18,LSL #3

      (2431) 0x46f858 ADD	X16, X10, X17,LSL #3

      (2431) 0x46f85c SUB	X12, X12, X17

      (2431) 0x46f860 ADD	X15, X15, #16

      (2431) 0x46f864 SUB	X12, X12, X13

        (2432) 0x46f868 LDUR	X13, [X15, #496]

        (2432) 0x46f86c SUBS	X12, X12, #4

        (2432) 0x46f870 LDR	D0, [X25, X13,LSL #3]

        (2432) 0x46f874 STUR	D0, [X16, #496]

        (2432) 0x46f878 LDUR	X13, [X15, #504]

        (2432) 0x46f87c LDR	D0, [X25, X13,LSL #3]

        (2432) 0x46f880 STUR	D0, [X16, #504]

        (2432) 0x46f884 LDR	X13, [X15]

        (2432) 0x46f888 LDR	D0, [X25, X13,LSL #3]

        (2432) 0x46f88c STR	D0, [X16]

        (2432) 0x46f890 LDR	X13, [X15, #8]

        (2432) 0x46f894 ADD	X15, X15, #32

        (2432) 0x46f898 LDR	D0, [X25, X13,LSL #3]

        (2432) 0x46f89c STR	D0, [X16, #8]

        (2432) 0x46f8a0 ADD	X16, X16, #32

        (2432) 0x46f8a4 B.NE	46f868

      (2431) 0x46f8a8 B	46f7e0

      (2373) 0x46f8ac LDUR	X22, [X29, #392]

      (2373) 0x46f8b0 LDR	X0, [SP, #136]

      (2373) 0x46f8b4 ORR	X1, XZR, X27

      (2373) 0x46f8b8 LDR	X8, [X22, #56]

      (2373) 0x46f8bc LDR	X19, [X8, #16]

      (2373) 0x46f8c0 BL	48ee00

      (2373) 0x46f8c4 LDR	D0, [SP, #64]

      (2373) 0x46f8c8 LDR	X1, [SP, #144]

      (2373) 0x46f8cc FMOV	D1, D12

      (2373) 0x46f8d0 ORR	X0, XZR, X22

      (2373) 0x46f8d4 ORR	X2, XZR, X27

      (2373) 0x46f8d8 BL	48df20

      (2373) 0x46f8dc LDR	X13, [SP, #112]

      (2373) 0x46f8e0 LDUR	X5, [X29, #400]

      (2373) 0x46f8e4 CMP	X19, #1

      (2373) 0x46f8e8 B.LT	46f540

      (2373) 0x46f8ec CMP	X19, #4

      (2373) 0x46f8f0 B.CS	470c04

      (2373) 0x46f8f4 ORR	X8, XZR, XZR

      (2373) 0x46f8f8 ORR	X9, X8, #4096

      (2373) 0x46f8fc TBZ	W19, #0, 46f91c

      (2373) 0x46f900 LDR	D0, [X13, X8,LSL #3]

      (2373) 0x46f904 LDR	D1, [X5, X8,LSL #3]

      (2373) 0x46f908 FDIV	D0, D0, D1

      (2373) 0x46f90c LDR	D1, [X25, X8,LSL #3]

      (2373) 0x46f910 FADD	D0, D1, D0

      (2373) 0x46f914 STR	D0, [X25, X8,LSL #3]

      (2373) 0x46f918 ORR	X8, XZR, X9

      (2373) 0x46f91c CMP	X19, X9

      (2373) 0x46f920 B.EQ	46f540

      (2373) 0x46f924 LDP	X11, X10, [SP, #48]

      (2373) 0x46f928 LDR	X12, [SP, #40]

      (2373) 0x46f92c SUB	X9, X19, X8

      (2373) 0x46f930 ADD	X10, X10, X8,LSL #3

      (2373) 0x46f934 ADD	X11, X11, X8,LSL #3

      (2373) 0x46f938 ADD	X8, X12, X8,LSL #3

      (2373) 0x46f93c HINT	#0

        (2374) 0x46f940 LDUR	D0, [X8, #504]

        (2374) 0x46f944 LDUR	D1, [X11, #504]

        (2374) 0x46f948 SUBS	X9, X9, #2

        (2374) 0x46f94c FDIV	D0, D0, D1

        (2374) 0x46f950 LDP	D1, D2, [X10, #1016]

        (2374) 0x46f954 FADD	D0, D1, D0

        (2374) 0x46f958 STUR	D0, [X10, #504]

        (2374) 0x46f95c LDR	D0, [X8], #16

        (2374) 0x46f960 LDR	D1, [X11], #16

        (2374) 0x46f964 FDIV	D0, D0, D1

        (2374) 0x46f968 FADD	D0, D2, D0

        (2374) 0x46f96c STR	D0, [X10], #16

        (2374) 0x46f970 B.NE	46f940

      (2373) 0x46f974 B	46f540

    (2376) 0x46f978 MOVZ	W0, #1

    (2376) 0x46f97c ORR	X1, XZR, X21

    (2376) 0x46f980 ORR	X2, XZR, X27

    (2376) 0x46f984 ORR	X3, XZR, X28

    (2376) 0x46f988 BL	480c50

    (2376) 0x46f98c BL	481040

    (2376) 0x46f990 ORR	X0, XZR, X27

    (2376) 0x46f994 BL	4a6d90

    (2376) 0x46f998 LDR	X27, [SP, #88]

    (2376) 0x46f99c LDUR	X22, [X29, #400]

    (2376) 0x46f9a0 LDR	X7, [SP, #112]

    (2376) 0x46f9a4 LDR	W8, [SP, #100]

    (2376) 0x46f9a8 LDUR	X30, [X29, #376]

    (2376) 0x46f9ac LDUR	X6, [X29, #416]

    (2376) 0x46f9b0 CBZ	W8, 46fc24

    (2376) 0x46f9b4 LDUR	X21, [X29, #408]

    (2376) 0x46f9b8 CMP	X23, #1

    (2376) 0x46f9bc B.LT	46f52c

    (2376) 0x46f9c0 LDR	X11, [X30]

    (2376) 0x46f9c4 ADD	X8, X26, #8

    (2376) 0x46f9c8 ADD	X10, X20, #8

    (2376) 0x46f9cc ADD	X12, X20, #16

    (2376) 0x46f9d0 ADD	X13, X26, #16

    (2376) 0x46f9d4 ADD	X14, X24, #8

    (2376) 0x46f9d8 ADD	X15, X19, #8

    (2376) 0x46f9dc ORR	X9, XZR, XZR

    (2376) 0x46f9e0 ADD	X16, X19, #16

    (2376) 0x46f9e4 ADD	X17, X24, #16

    (2376) 0x46f9e8 B	46fa08

      (2405) 0x46f9ec LDR	D1, [X22, X18,LSL #3]

      (2405) 0x46f9f0 FDIV	D0, D0, D1

      (2405) 0x46f9f4 LDR	D1, [X25, X18,LSL #3]

      (2405) 0x46f9f8 FADD	D0, D1, D0

      (2405) 0x46f9fc STR	D0, [X25, X18,LSL #3]

      (2405) 0x46fa00 CMP	X9, X23

      (2405) 0x46fa04 B.EQ	46fed8

      (2405) 0x46fa08 ORR	X18, XZR, X9

      (2405) 0x46fa0c LDR	D0, [X21, X9,LSL #3]

      (2405) 0x46fa10 ADD	X9, X9, #1

      (2405) 0x46fa14 ORR	X4, XZR, X11

      (2405) 0x46fa18 LDR	X11, [X30, X9,LSL #3]

      (2405) 0x46fa1c SUBS	X1, X11, X4

      (2405) 0x46fa20 B.LE	46fb20

      (2405) 0x46fa24 CMP	X1, #2

      (2405) 0x46fa28 B.CS	46fa40

      (2405) 0x46fa2c ORR	X0, XZR, X4

      (2405) 0x46fa30 B	46fa98

0x46fa34 HINT	#0

0x46fa38 HINT	#0

0x46fa3c HINT	#0

      (2405) 0x46fa40 AND	X2, X1, #8127

      (2405) 0x46fa44 MOVI	D1, #0

      (2405) 0x46fa48 ADD	X3, X8, X4,LSL #3

      (2405) 0x46fa4c ADD	X0, X4, X2

      (2405) 0x46fa50 ADD	X4, X10, X4,LSL #3

      (2405) 0x46fa54 ORR	X5, XZR, X2

      (2405) 0x46fa58 HINT	#0

      (2405) 0x46fa5c HINT	#0

        (2409) 0x46fa60 LDP	X6, X7, [X4, #1016]

        (2409) 0x46fa64 LDP	D2, D3, [X3, #1016]

        (2409) 0x46fa68 SUBS	X5, X5, #2

        (2409) 0x46fa6c ADD	X3, X3, #16

        (2409) 0x46fa70 ADD	X4, X4, #16

        (2409) 0x46fa74 LDR	D4, [X25, X6,LSL #3]

        (2409) 0x46fa78 LDR	D5, [X25, X7,LSL #3]

        (2409) 0x46fa7c FMSUB	D0, D4, D2, D0

        (2409) 0x46fa80 FMSUB	D1, D5, D3, D1

        (2409) 0x46fa84 B.NE	46fa60

      (2405) 0x46fa88 LDUR	X6, [X29, #416]

      (2405) 0x46fa8c FADD	D0, D1, D0

      (2405) 0x46fa90 CMP	X1, X2

      (2405) 0x46fa94 B.EQ	46fb20

      (2405) 0x46fa98 SUB	W1, W11, W0

      (2405) 0x46fa9c ORR	X2, XZR, X0

      (2405) 0x46faa0 ANDS	X1, X1, #4160

      (2405) 0x46faa4 B.EQ	46fac4

        (2411) 0x46faa8 LDR	X3, [X20, X2,LSL #3]

        (2411) 0x46faac LDR	D1, [X26, X2,LSL #3]

        (2411) 0x46fab0 ADD	X2, X2, #1

        (2411) 0x46fab4 SUBS	X1, X1, #1

        (2411) 0x46fab8 LDR	D2, [X25, X3,LSL #3]

        (2411) 0x46fabc FMSUB	D0, D2, D1, D0

        (2411) 0x46fac0 B.NE	46faa8

      (2405) 0x46fac4 SUB	X0, X0, X11

      (2405) 0x46fac8 CMN	X0, #4

      (2405) 0x46facc B.HI	46fb20

      (2405) 0x46fad0 SUB	X0, X11, X2

      (2405) 0x46fad4 ADD	X1, X12, X2,LSL #3

      (2405) 0x46fad8 ADD	X2, X13, X2,LSL #3

      (2405) 0x46fadc HINT	#0

        (2410) 0x46fae0 LDP	X3, X4, [X1, #1008]

        (2410) 0x46fae4 LDP	D2, D3, [X2, #1008]

        (2410) 0x46fae8 SUBS	X0, X0, #4

        (2410) 0x46faec LDR	D4, [X25, X4,LSL #3]

        (2410) 0x46faf0 LDR	D1, [X25, X3,LSL #3]

        (2410) 0x46faf4 LDP	X3, X4, [X1], #32

        (2410) 0x46faf8 FMUL	D3, D4, D3

        (2410) 0x46fafc LDR	D4, [X25, X3,LSL #3]

        (2410) 0x46fb00 FMADD	D1, D1, D2, D3

        (2410) 0x46fb04 LDP	D2, D3, [X2], #32

        (2410) 0x46fb08 FMADD	D1, D4, D2, D1

        (2410) 0x46fb0c LDR	D2, [X25, X4,LSL #3]

        (2410) 0x46fb10 FMADD	D1, D2, D3, D1

        (2410) 0x46fb14 FSUB	D0, D0, S1

        (2410) 0x46fb18 B.NE	46fae0

      (2405) 0x46fb1c HINT	#0

      (2405) 0x46fb20 CBZ	X6, 46f9ec

      (2405) 0x46fb24 LDUR	X0, [X29, #424]

      (2405) 0x46fb28 LDR	X5, [X0, X18,LSL #3]

      (2405) 0x46fb2c LDR	X0, [X0, X9,LSL #3]

      (2405) 0x46fb30 SUBS	X2, X0, X5

      (2405) 0x46fb34 B.LE	46f9ec

      (2405) 0x46fb38 CMP	X2, #2

      (2405) 0x46fb3c B.CS	46fb48

      (2405) 0x46fb40 ORR	X1, XZR, X5

      (2405) 0x46fb44 B	46fb98

      (2405) 0x46fb48 AND	X3, X2, #8127

      (2405) 0x46fb4c MOVI	D1, #0

      (2405) 0x46fb50 ADD	X4, X14, X5,LSL #3

      (2405) 0x46fb54 ADD	X1, X5, X3

      (2405) 0x46fb58 ADD	X5, X15, X5,LSL #3

      (2405) 0x46fb5c ORR	X6, XZR, X3

        (2406) 0x46fb60 LDP	X7, X21, [X5, #1016]

        (2406) 0x46fb64 LDP	D2, D3, [X4, #1016]

        (2406) 0x46fb68 SUBS	X6, X6, #2

        (2406) 0x46fb6c ADD	X4, X4, #16

        (2406) 0x46fb70 ADD	X5, X5, #16

        (2406) 0x46fb74 LDR	D4, [X28, X7,LSL #3]

        (2406) 0x46fb78 LDR	D5, [X28, X21,LSL #3]

        (2406) 0x46fb7c FMSUB	D0, D4, D2, D0

        (2406) 0x46fb80 FMSUB	D1, D5, D3, D1

        (2406) 0x46fb84 B.NE	46fb60

      (2405) 0x46fb88 LDP	X21, X6, [X29, #920]

      (2405) 0x46fb8c FADD	D0, D1, D0

      (2405) 0x46fb90 CMP	X2, X3

      (2405) 0x46fb94 B.EQ	46f9ec

      (2405) 0x46fb98 SUB	W2, W0, W1

      (2405) 0x46fb9c ANDS	X3, X2, #4160

      (2405) 0x46fba0 B.EQ	46fbc8

      (2405) 0x46fba4 ORR	X2, XZR, X1

        (2408) 0x46fba8 LDR	X4, [X19, X2,LSL #3]

        (2408) 0x46fbac LDR	D1, [X24, X2,LSL #3]

        (2408) 0x46fbb0 ADD	X2, X2, #1

        (2408) 0x46fbb4 SUBS	X3, X3, #1

        (2408) 0x46fbb8 LDR	D2, [X28, X4,LSL #3]

        (2408) 0x46fbbc FMSUB	D0, D2, D1, D0

        (2408) 0x46fbc0 B.NE	46fba8

      (2405) 0x46fbc4 B	46fbcc

      (2405) 0x46fbc8 ORR	X2, XZR, X1

      (2405) 0x46fbcc SUB	X1, X1, X0

      (2405) 0x46fbd0 CMN	X1, #4

      (2405) 0x46fbd4 B.HI	46f9ec

      (2405) 0x46fbd8 SUB	X0, X0, X2

      (2405) 0x46fbdc ADD	X1, X16, X2,LSL #3

      (2405) 0x46fbe0 ADD	X2, X17, X2,LSL #3

        (2407) 0x46fbe4 LDP	X3, X4, [X1, #1008]

        (2407) 0x46fbe8 LDP	D2, D3, [X2, #1008]

        (2407) 0x46fbec SUBS	X0, X0, #4

        (2407) 0x46fbf0 LDR	D4, [X28, X4,LSL #3]

        (2407) 0x46fbf4 LDR	D1, [X28, X3,LSL #3]

        (2407) 0x46fbf8 LDP	X3, X4, [X1], #32

        (2407) 0x46fbfc FMUL	D3, D4, D3

        (2407) 0x46fc00 LDR	D4, [X28, X3,LSL #3]

        (2407) 0x46fc04 FMADD	D1, D1, D2, D3

        (2407) 0x46fc08 LDP	D2, D3, [X2], #32

        (2407) 0x46fc0c FMADD	D1, D4, D2, D1

        (2407) 0x46fc10 LDR	D2, [X28, X4,LSL #3]

        (2407) 0x46fc14 FMADD	D1, D2, D3, D1

        (2407) 0x46fc18 FSUB	D0, D0, S1

        (2407) 0x46fc1c B.NE	46fbe4

      (2405) 0x46fc20 B	46f9ec

    (2376) 0x46fc24 LDUR	X21, [X29, #408]

    (2376) 0x46fc28 FCMP	D12, D14

    (2376) 0x46fc2c B.NE	4709a4

    (2376) 0x46fc30 CMP	X23, #1

    (2376) 0x46fc34 B.LT	46f52c

    (2376) 0x46fc38 LDR	X11, [X30]

    (2376) 0x46fc3c ADD	X8, X26, #8

    (2376) 0x46fc40 ADD	X10, X20, #8

    (2376) 0x46fc44 ADD	X12, X20, #16

    (2376) 0x46fc48 ADD	X13, X26, #16

    (2376) 0x46fc4c ADD	X14, X24, #8

    (2376) 0x46fc50 ADD	X15, X19, #8

    (2376) 0x46fc54 ORR	X9, XZR, XZR

    (2376) 0x46fc58 ADD	X16, X19, #16

    (2376) 0x46fc5c ADD	X17, X24, #16

    (2376) 0x46fc60 B	46fc84

      (2391) 0x46fc64 LDR	D1, [X22, X18,LSL #3]

      (2391) 0x46fc68 FMUL	D0, D0, D11

      (2391) 0x46fc6c FDIV	D0, D0, D1

      (2391) 0x46fc70 LDR	D1, [X25, X18,LSL #3]

      (2391) 0x46fc74 FADD	D0, D1, D0

      (2391) 0x46fc78 STR	D0, [X25, X18,LSL #3]

      (2391) 0x46fc7c CMP	X9, X23

      (2391) 0x46fc80 B.EQ	47073c

      (2391) 0x46fc84 ORR	X18, XZR, X9

      (2391) 0x46fc88 LDR	D0, [X21, X9,LSL #3]

      (2391) 0x46fc8c ADD	X9, X9, #1

      (2391) 0x46fc90 ORR	X4, XZR, X11

      (2391) 0x46fc94 LDR	X11, [X30, X9,LSL #3]

      (2391) 0x46fc98 SUBS	X1, X11, X4

      (2391) 0x46fc9c B.LE	46fda0

      (2391) 0x46fca0 CMP	X1, #2

      (2391) 0x46fca4 B.CS	46fcc0

      (2391) 0x46fca8 ORR	X0, XZR, X4

      (2391) 0x46fcac B	46fd18

0x46fcb0 HINT	#0

0x46fcb4 HINT	#0

0x46fcb8 HINT	#0

0x46fcbc HINT	#0

      (2391) 0x46fcc0 AND	X2, X1, #8127

      (2391) 0x46fcc4 MOVI	D1, #0

      (2391) 0x46fcc8 ADD	X3, X8, X4,LSL #3

      (2391) 0x46fccc ADD	X0, X4, X2

      (2391) 0x46fcd0 ADD	X4, X10, X4,LSL #3

      (2391) 0x46fcd4 ORR	X5, XZR, X2

      (2391) 0x46fcd8 HINT	#0

      (2391) 0x46fcdc HINT	#0

        (2395) 0x46fce0 LDP	X6, X7, [X4, #1016]

        (2395) 0x46fce4 LDP	D2, D3, [X3, #1016]

        (2395) 0x46fce8 SUBS	X5, X5, #2

        (2395) 0x46fcec ADD	X3, X3, #16

        (2395) 0x46fcf0 ADD	X4, X4, #16

        (2395) 0x46fcf4 LDR	D4, [X25, X6,LSL #3]

        (2395) 0x46fcf8 LDR	D5, [X25, X7,LSL #3]

        (2395) 0x46fcfc FMSUB	D0, D4, D2, D0

        (2395) 0x46fd00 FMSUB	D1, D5, D3, D1

        (2395) 0x46fd04 B.NE	46fce0

      (2391) 0x46fd08 LDUR	X6, [X29, #416]

      (2391) 0x46fd0c FADD	D0, D1, D0

      (2391) 0x46fd10 CMP	X1, X2

      (2391) 0x46fd14 B.EQ	46fda0

      (2391) 0x46fd18 SUB	W1, W11, W0

      (2391) 0x46fd1c ORR	X2, XZR, X0

      (2391) 0x46fd20 ANDS	X1, X1, #4160

      (2391) 0x46fd24 B.EQ	46fd44

        (2397) 0x46fd28 LDR	X3, [X20, X2,LSL #3]

        (2397) 0x46fd2c LDR	D1, [X26, X2,LSL #3]

        (2397) 0x46fd30 ADD	X2, X2, #1

        (2397) 0x46fd34 SUBS	X1, X1, #1

        (2397) 0x46fd38 LDR	D2, [X25, X3,LSL #3]

        (2397) 0x46fd3c FMSUB	D0, D2, D1, D0

        (2397) 0x46fd40 B.NE	46fd28

      (2391) 0x46fd44 SUB	X0, X0, X11

      (2391) 0x46fd48 CMN	X0, #4

      (2391) 0x46fd4c B.HI	46fda0

      (2391) 0x46fd50 SUB	X0, X11, X2

      (2391) 0x46fd54 ADD	X1, X12, X2,LSL #3

      (2391) 0x46fd58 ADD	X2, X13, X2,LSL #3

      (2391) 0x46fd5c HINT	#0

        (2396) 0x46fd60 LDP	X3, X4, [X1, #1008]

        (2396) 0x46fd64 LDP	D2, D3, [X2, #1008]

        (2396) 0x46fd68 SUBS	X0, X0, #4

        (2396) 0x46fd6c LDR	D4, [X25, X4,LSL #3]

        (2396) 0x46fd70 LDR	D1, [X25, X3,LSL #3]

        (2396) 0x46fd74 LDP	X3, X4, [X1], #32

        (2396) 0x46fd78 FMUL	D3, D4, D3

        (2396) 0x46fd7c LDR	D4, [X25, X3,LSL #3]

        (2396) 0x46fd80 FMADD	D1, D1, D2, D3

        (2396) 0x46fd84 LDP	D2, D3, [X2], #32

        (2396) 0x46fd88 FMADD	D1, D4, D2, D1

        (2396) 0x46fd8c LDR	D2, [X25, X4,LSL #3]

        (2396) 0x46fd90 FMADD	D1, D2, D3, D1

        (2396) 0x46fd94 FSUB	D0, D0, S1

        (2396) 0x46fd98 B.NE	46fd60

      (2391) 0x46fd9c HINT	#0

      (2391) 0x46fda0 CBZ	X6, 46fc64

      (2391) 0x46fda4 LDUR	X0, [X29, #424]

      (2391) 0x46fda8 LDR	X5, [X0, X18,LSL #3]

      (2391) 0x46fdac LDR	X0, [X0, X9,LSL #3]

      (2391) 0x46fdb0 SUBS	X2, X0, X5

      (2391) 0x46fdb4 B.LE	46fc64

      (2391) 0x46fdb8 CMP	X2, #2

      (2391) 0x46fdbc B.CS	46fdc8

      (2391) 0x46fdc0 ORR	X1, XZR, X5

      (2391) 0x46fdc4 B	46fe18

      (2391) 0x46fdc8 AND	X3, X2, #8127

      (2391) 0x46fdcc MOVI	D1, #0

      (2391) 0x46fdd0 ADD	X4, X14, X5,LSL #3

      (2391) 0x46fdd4 ADD	X1, X5, X3

      (2391) 0x46fdd8 ADD	X5, X15, X5,LSL #3

      (2391) 0x46fddc ORR	X6, XZR, X3

        (2392) 0x46fde0 LDP	X7, X21, [X5, #1016]

        (2392) 0x46fde4 LDP	D2, D3, [X4, #1016]

        (2392) 0x46fde8 SUBS	X6, X6, #2

        (2392) 0x46fdec ADD	X4, X4, #16

        (2392) 0x46fdf0 ADD	X5, X5, #16

        (2392) 0x46fdf4 LDR	D4, [X28, X7,LSL #3]

        (2392) 0x46fdf8 LDR	D5, [X28, X21,LSL #3]

        (2392) 0x46fdfc FMSUB	D0, D4, D2, D0

        (2392) 0x46fe00 FMSUB	D1, D5, D3, D1

        (2392) 0x46fe04 B.NE	46fde0

      (2391) 0x46fe08 LDP	X21, X6, [X29, #920]

      (2391) 0x46fe0c FADD	D0, D1, D0

      (2391) 0x46fe10 CMP	X2, X3

      (2391) 0x46fe14 B.EQ	46fc64

      (2391) 0x46fe18 SUB	W2, W0, W1

      (2391) 0x46fe1c ANDS	X3, X2, #4160

      (2391) 0x46fe20 B.EQ	46fe48

      (2391) 0x46fe24 ORR	X2, XZR, X1

        (2394) 0x46fe28 LDR	X4, [X19, X2,LSL #3]

        (2394) 0x46fe2c LDR	D1, [X24, X2,LSL #3]

        (2394) 0x46fe30 ADD	X2, X2, #1

        (2394) 0x46fe34 SUBS	X3, X3, #1

        (2394) 0x46fe38 LDR	D2, [X28, X4,LSL #3]

        (2394) 0x46fe3c FMSUB	D0, D2, D1, D0

        (2394) 0x46fe40 B.NE	46fe28

      (2391) 0x46fe44 B	46fe4c

      (2391) 0x46fe48 ORR	X2, XZR, X1

      (2391) 0x46fe4c SUB	X1, X1, X0

      (2391) 0x46fe50 CMN	X1, #4

      (2391) 0x46fe54 B.HI	46fc64

      (2391) 0x46fe58 SUB	X0, X0, X2

      (2391) 0x46fe5c ADD	X1, X16, X2,LSL #3

      (2391) 0x46fe60 ADD	X2, X17, X2,LSL #3

        (2393) 0x46fe64 LDP	X3, X4, [X1, #1008]

        (2393) 0x46fe68 LDP	D2, D3, [X2, #1008]

        (2393) 0x46fe6c SUBS	X0, X0, #4

        (2393) 0x46fe70 LDR	D4, [X28, X4,LSL #3]

        (2393) 0x46fe74 LDR	D1, [X28, X3,LSL #3]

        (2393) 0x46fe78 LDP	X3, X4, [X1], #32

        (2393) 0x46fe7c FMUL	D3, D4, D3

        (2393) 0x46fe80 LDR	D4, [X28, X3,LSL #3]

        (2393) 0x46fe84 FMADD	D1, D1, D2, D3

        (2393) 0x46fe88 LDP	D2, D3, [X2], #32

        (2393) 0x46fe8c FMADD	D1, D4, D2, D1

        (2393) 0x46fe90 LDR	D2, [X28, X4,LSL #3]

        (2393) 0x46fe94 FMADD	D1, D2, D3, D1

        (2393) 0x46fe98 FSUB	D0, D0, S1

        (2393) 0x46fe9c B.NE	46fe64

      (2391) 0x46fea0 B	46fc64

      (2373) 0x46fea4 LDR	X8, [SP, #104]

      (2373) 0x46fea8 LDUR	X0, [X29, #392]

      (2373) 0x46feac LDP	X1, X6, [SP, #136]

      (2373) 0x46feb0 FMOV	D0, D12

      (2373) 0x46feb4 FMOV	D1, D11

      (2373) 0x46feb8 ORR	X2, XZR, XZR

      (2373) 0x46febc ORR	X4, XZR, XZR

      (2373) 0x46fec0 ORR	X7, XZR, X27

      (2373) 0x46fec4 LDR	X3, [SP, #72]

      (2373) 0x46fec8 STR	X8, [SP]

      (2373) 0x46fecc BL	44a620

      (2373) 0x46fed0 LDUR	X5, [X29, #400]

      (2373) 0x46fed4 B	46f540

    (2376) 0x46fed8 CMP	X23, #1

    (2376) 0x46fedc B.LT	46f52c

    (2376) 0x46fee0 LDR	X12, [X30, X23,LSL #3]

    (2376) 0x46fee4 ADD	X8, X26, #8

    (2376) 0x46fee8 ADD	X9, X20, #8

    (2376) 0x46feec ADD	X10, X20, #16

    (2376) 0x46fef0 ADD	X11, X26, #16

    (2376) 0x46fef4 ADD	X13, X24, #8

    (2376) 0x46fef8 ADD	X14, X19, #8

    (2376) 0x46fefc ADD	X15, X19, #16

    (2376) 0x46ff00 ADD	X16, X24, #16

    (2376) 0x46ff04 B	46ff24

      (2398) 0x46ff08 LDR	D1, [X22, X23,LSL #3]

      (2398) 0x46ff0c FDIV	D0, D0, D1

      (2398) 0x46ff10 LDR	D1, [X25, X23,LSL #3]

      (2398) 0x46ff14 FADD	D0, D1, D0

      (2398) 0x46ff18 STR	D0, [X25, X23,LSL #3]

      (2398) 0x46ff1c CMP	X17, #1

      (2398) 0x46ff20 B.LE	46f52c

      (2398) 0x46ff24 ORR	X17, XZR, X23

      (2398) 0x46ff28 SUB	X23, X23, #1

      (2398) 0x46ff2c ORR	X18, XZR, X12

      (2398) 0x46ff30 LDR	D0, [X21, X23,LSL #3]

      (2398) 0x46ff34 LDR	X12, [X30, X23,LSL #3]

      (2398) 0x46ff38 SUBS	X1, X18, X12

      (2398) 0x46ff3c B.LE	470040

      (2398) 0x46ff40 CMP	X1, #2

      (2398) 0x46ff44 B.CS	46ff60

      (2398) 0x46ff48 ORR	X0, XZR, X12

      (2398) 0x46ff4c B	46ffb8

0x46ff50 HINT	#0

0x46ff54 HINT	#0

0x46ff58 HINT	#0

0x46ff5c HINT	#0

      (2398) 0x46ff60 AND	X2, X1, #8127

      (2398) 0x46ff64 MOVI	D1, #0

      (2398) 0x46ff68 ADD	X3, X8, X12,LSL #3

      (2398) 0x46ff6c ADD	X4, X9, X12,LSL #3

      (2398) 0x46ff70 ADD	X0, X12, X2

      (2398) 0x46ff74 ORR	X5, XZR, X2

      (2398) 0x46ff78 HINT	#0

      (2398) 0x46ff7c HINT	#0

        (2402) 0x46ff80 LDP	X6, X7, [X4, #1016]

        (2402) 0x46ff84 LDP	D2, D3, [X3, #1016]

        (2402) 0x46ff88 SUBS	X5, X5, #2

        (2402) 0x46ff8c ADD	X3, X3, #16

        (2402) 0x46ff90 ADD	X4, X4, #16

        (2402) 0x46ff94 LDR	D4, [X25, X6,LSL #3]

        (2402) 0x46ff98 LDR	D5, [X25, X7,LSL #3]

        (2402) 0x46ff9c FMSUB	D0, D4, D2, D0

        (2402) 0x46ffa0 FMSUB	D1, D5, D3, D1

        (2402) 0x46ffa4 B.NE	46ff80

      (2398) 0x46ffa8 LDUR	X6, [X29, #416]

      (2398) 0x46ffac FADD	D0, D1, D0

      (2398) 0x46ffb0 CMP	X1, X2

      (2398) 0x46ffb4 B.EQ	470040

      (2398) 0x46ffb8 SUB	W1, W18, W0

      (2398) 0x46ffbc ANDS	X2, X1, #4160

      (2398) 0x46ffc0 B.EQ	46ffe8

      (2398) 0x46ffc4 ORR	X1, XZR, X0

        (2404) 0x46ffc8 LDR	X3, [X20, X1,LSL #3]

        (2404) 0x46ffcc LDR	D1, [X26, X1,LSL #3]

        (2404) 0x46ffd0 ADD	X1, X1, #1

        (2404) 0x46ffd4 SUBS	X2, X2, #1

        (2404) 0x46ffd8 LDR	D2, [X25, X3,LSL #3]

        (2404) 0x46ffdc FMSUB	D0, D2, D1, D0

        (2404) 0x46ffe0 B.NE	46ffc8

      (2398) 0x46ffe4 B	46ffec

      (2398) 0x46ffe8 ORR	X1, XZR, X0

      (2398) 0x46ffec SUB	X0, X0, X18

      (2398) 0x46fff0 CMN	X0, #4

      (2398) 0x46fff4 B.HI	470040

      (2398) 0x46fff8 SUB	X18, X18, X1

      (2398) 0x46fffc ADD	X0, X10, X1,LSL #3

      (2398) 0x470000 ADD	X1, X11, X1,LSL #3

        (2403) 0x470004 LDP	X2, X3, [X0, #1008]

        (2403) 0x470008 LDP	D2, D3, [X1, #1008]

        (2403) 0x47000c SUBS	X18, X18, #4

        (2403) 0x470010 LDR	D4, [X25, X3,LSL #3]

        (2403) 0x470014 LDR	D1, [X25, X2,LSL #3]

        (2403) 0x470018 LDP	X2, X3, [X0], #32

        (2403) 0x47001c FMUL	D3, D4, D3

        (2403) 0x470020 LDR	D4, [X25, X2,LSL #3]

        (2403) 0x470024 FMADD	D1, D1, D2, D3

        (2403) 0x470028 LDP	D2, D3, [X1], #32

        (2403) 0x47002c FMADD	D1, D4, D2, D1

        (2403) 0x470030 LDR	D2, [X25, X3,LSL #3]

        (2403) 0x470034 FMADD	D1, D2, D3, D1

        (2403) 0x470038 FSUB	D0, D0, S1

        (2403) 0x47003c B.NE	470004

      (2398) 0x470040 CBZ	X6, 46ff08

      (2398) 0x470044 LDUR	X18, [X29, #424]

      (2398) 0x470048 LDR	X4, [X18, X23,LSL #3]

      (2398) 0x47004c LDR	X18, [X18, X17,LSL #3]

      (2398) 0x470050 SUBS	X1, X18, X4

      (2398) 0x470054 B.LE	46ff08

      (2398) 0x470058 CMP	X1, #2

      (2398) 0x47005c B.CS	470068

      (2398) 0x470060 ORR	X0, XZR, X4

      (2398) 0x470064 B	4700b8

      (2398) 0x470068 AND	X2, X1, #8127

      (2398) 0x47006c MOVI	D1, #0

      (2398) 0x470070 ADD	X3, X13, X4,LSL #3

      (2398) 0x470074 ADD	X0, X4, X2

      (2398) 0x470078 ADD	X4, X14, X4,LSL #3

      (2398) 0x47007c ORR	X5, XZR, X2

        (2399) 0x470080 LDP	X6, X7, [X4, #1016]

        (2399) 0x470084 LDP	D2, D3, [X3, #1016]

        (2399) 0x470088 SUBS	X5, X5, #2

        (2399) 0x47008c ADD	X3, X3, #16

        (2399) 0x470090 ADD	X4, X4, #16

        (2399) 0x470094 LDR	D4, [X28, X6,LSL #3]

        (2399) 0x470098 LDR	D5, [X28, X7,LSL #3]

        (2399) 0x47009c FMSUB	D0, D4, D2, D0

        (2399) 0x4700a0 FMSUB	D1, D5, D3, D1

        (2399) 0x4700a4 B.NE	470080

      (2398) 0x4700a8 LDUR	X6, [X29, #416]

      (2398) 0x4700ac FADD	D0, D1, D0

      (2398) 0x4700b0 CMP	X1, X2

      (2398) 0x4700b4 B.EQ	46ff08

      (2398) 0x4700b8 SUB	W1, W18, W0

      (2398) 0x4700bc ANDS	X2, X1, #4160

      (2398) 0x4700c0 B.EQ	4700e8

      (2398) 0x4700c4 ORR	X1, XZR, X0

        (2401) 0x4700c8 LDR	X3, [X19, X1,LSL #3]

        (2401) 0x4700cc LDR	D1, [X24, X1,LSL #3]

        (2401) 0x4700d0 ADD	X1, X1, #1

        (2401) 0x4700d4 SUBS	X2, X2, #1

        (2401) 0x4700d8 LDR	D2, [X28, X3,LSL #3]

        (2401) 0x4700dc FMSUB	D0, D2, D1, D0

        (2401) 0x4700e0 B.NE	4700c8

      (2398) 0x4700e4 B	4700ec

      (2398) 0x4700e8 ORR	X1, XZR, X0

      (2398) 0x4700ec SUB	X0, X0, X18

      (2398) 0x4700f0 CMN	X0, #4

      (2398) 0x4700f4 B.HI	46ff08

      (2398) 0x4700f8 SUB	X18, X18, X1

      (2398) 0x4700fc ADD	X0, X15, X1,LSL #3

      (2398) 0x470100 ADD	X1, X16, X1,LSL #3

        (2400) 0x470104 LDP	X2, X3, [X0, #1008]

        (2400) 0x470108 LDP	D2, D3, [X1, #1008]

        (2400) 0x47010c SUBS	X18, X18, #4

        (2400) 0x470110 LDR	D4, [X28, X3,LSL #3]

        (2400) 0x470114 LDR	D1, [X28, X2,LSL #3]

        (2400) 0x470118 LDP	X2, X3, [X0], #32

        (2400) 0x47011c FMUL	D3, D4, D3

        (2400) 0x470120 LDR	D4, [X28, X2,LSL #3]

        (2400) 0x470124 FMADD	D1, D1, D2, D3

        (2400) 0x470128 LDP	D2, D3, [X1], #32

        (2400) 0x47012c FMADD	D1, D4, D2, D1

        (2400) 0x470130 LDR	D2, [X28, X3,LSL #3]

        (2400) 0x470134 FMADD	D1, D2, D3, D1

        (2400) 0x470138 FSUB	D0, D0, S1

        (2400) 0x47013c B.NE	470104

      (2398) 0x470140 B	46ff08

    (2376) 0x470144 MOVZ	W0, #1

    (2376) 0x470148 ORR	X1, XZR, X21

    (2376) 0x47014c ORR	X2, XZR, X27

    (2376) 0x470150 ORR	X3, XZR, X28

    (2376) 0x470154 BL	480c50

    (2376) 0x470158 BL	481040

    (2376) 0x47015c ORR	X0, XZR, X27

    (2376) 0x470160 BL	4a6d90

    (2376) 0x470164 LDR	X27, [SP, #88]

    (2376) 0x470168 LDUR	X23, [X29, #376]

    (2376) 0x47016c LDP	X30, X21, [X29, #912]

    (2376) 0x470170 LDUR	X7, [X29, #416]

    (2376) 0x470174 CMP	X20, #1

    (2376) 0x470178 B.LT	46f52c

    (2376) 0x47017c LDR	X11, [X23]

    (2376) 0x470180 ADD	X9, X19, #8

    (2376) 0x470184 ADD	X10, X22, #8

    (2376) 0x470188 ADD	X12, X22, #16

    (2376) 0x47018c ADD	X13, X19, #16

    (2376) 0x470190 ADD	X14, X26, #8

    (2376) 0x470194 ADD	X15, X24, #8

    (2376) 0x470198 ORR	X8, XZR, XZR

    (2376) 0x47019c ADD	X16, X24, #16

    (2376) 0x4701a0 ADD	X17, X26, #16

    (2376) 0x4701a4 B	4701b0

      (2423) 0x4701a8 CMP	X8, X20

      (2423) 0x4701ac B.EQ	47045c

      (2423) 0x4701b0 ORR	X0, XZR, X8

      (2423) 0x4701b4 LDR	D0, [X21, X8,LSL #3]

      (2423) 0x4701b8 ADD	X8, X8, #1

      (2423) 0x4701bc ORR	X18, XZR, X11

      (2423) 0x4701c0 LDR	X11, [X23, X8,LSL #3]

      (2423) 0x4701c4 SUBS	X2, X11, X18

      (2423) 0x4701c8 B.LE	4702c0

      (2423) 0x4701cc CMP	X2, #2

      (2423) 0x4701d0 B.CS	4701e0

      (2423) 0x4701d4 ORR	X1, XZR, X18

      (2423) 0x4701d8 B	470238

0x4701dc HINT	#0

      (2423) 0x4701e0 AND	X3, X2, #8127

      (2423) 0x4701e4 MOVI	D1, #0

      (2423) 0x4701e8 ADD	X4, X9, X18,LSL #3

      (2423) 0x4701ec ADD	X5, X10, X18,LSL #3

      (2423) 0x4701f0 ADD	X1, X18, X3

      (2423) 0x4701f4 ORR	X6, XZR, X3

      (2423) 0x4701f8 HINT	#0

      (2423) 0x4701fc HINT	#0

        (2428) 0x470200 LDP	X7, X21, [X5, #1016]

        (2428) 0x470204 LDP	D2, D3, [X4, #1016]

        (2428) 0x470208 SUBS	X6, X6, #2

        (2428) 0x47020c ADD	X4, X4, #16

        (2428) 0x470210 ADD	X5, X5, #16

        (2428) 0x470214 LDR	D4, [X25, X7,LSL #3]

        (2428) 0x470218 LDR	D5, [X25, X21,LSL #3]

        (2428) 0x47021c FMSUB	D0, D4, D2, D0

        (2428) 0x470220 FMSUB	D1, D5, D3, D1

        (2428) 0x470224 B.NE	470200

      (2423) 0x470228 LDP	X21, X7, [X29, #920]

      (2423) 0x47022c FADD	D0, D1, D0

      (2423) 0x470230 CMP	X2, X3

      (2423) 0x470234 B.EQ	4702c0

      (2423) 0x470238 SUB	W2, W11, W1

      (2423) 0x47023c ORR	X3, XZR, X1

      (2423) 0x470240 ANDS	X2, X2, #4160

      (2423) 0x470244 B.EQ	470264

        (2430) 0x470248 LDR	X4, [X22, X3,LSL #3]

        (2430) 0x47024c LDR	D1, [X19, X3,LSL #3]

        (2430) 0x470250 ADD	X3, X3, #1

        (2430) 0x470254 SUBS	X2, X2, #1

        (2430) 0x470258 LDR	D2, [X25, X4,LSL #3]

        (2430) 0x47025c FMSUB	D0, D2, D1, D0

        (2430) 0x470260 B.NE	470248

      (2423) 0x470264 SUB	X1, X1, X11

      (2423) 0x470268 CMN	X1, #4

      (2423) 0x47026c B.HI	4702c0

      (2423) 0x470270 SUB	X1, X11, X3

      (2423) 0x470274 ADD	X2, X12, X3,LSL #3

      (2423) 0x470278 ADD	X3, X13, X3,LSL #3

      (2423) 0x47027c HINT	#0

        (2429) 0x470280 LDP	X4, X5, [X2, #1008]

        (2429) 0x470284 LDP	D2, D3, [X3, #1008]

        (2429) 0x470288 SUBS	X1, X1, #4

        (2429) 0x47028c LDR	D4, [X25, X5,LSL #3]

        (2429) 0x470290 LDR	D1, [X25, X4,LSL #3]

        (2429) 0x470294 LDP	X4, X5, [X2], #32

        (2429) 0x470298 FMUL	D3, D4, D3

        (2429) 0x47029c LDR	D4, [X25, X4,LSL #3]

        (2429) 0x4702a0 FMADD	D1, D1, D2, D3

        (2429) 0x4702a4 LDP	D2, D3, [X3], #32

        (2429) 0x4702a8 FMADD	D1, D4, D2, D1

        (2429) 0x4702ac LDR	D2, [X25, X5,LSL #3]

        (2429) 0x4702b0 FMADD	D1, D2, D3, D1

        (2429) 0x4702b4 FSUB	D0, D0, S1

        (2429) 0x4702b8 B.NE	470280

      (2423) 0x4702bc HINT	#0

      (2423) 0x4702c0 CBZ	X7, 4703c4

      (2423) 0x4702c4 LDUR	X1, [X29, #424]

      (2423) 0x4702c8 LDR	X6, [X1, X0,LSL #3]

      (2423) 0x4702cc LDR	X1, [X1, X8,LSL #3]

      (2423) 0x4702d0 SUBS	X3, X1, X6

      (2423) 0x4702d4 B.LE	4703c4

      (2423) 0x4702d8 CMP	X3, #2

      (2423) 0x4702dc B.CS	4702e8

      (2423) 0x4702e0 ORR	X2, XZR, X6

      (2423) 0x4702e4 B	47033c

      (2423) 0x4702e8 AND	X4, X3, #8127

      (2423) 0x4702ec MOVI	D1, #0

      (2423) 0x4702f0 ADD	X5, X14, X6,LSL #3

      (2423) 0x4702f4 ADD	X2, X6, X4

      (2423) 0x4702f8 ADD	X6, X15, X6,LSL #3

      (2423) 0x4702fc ORR	X7, XZR, X4

        (2425) 0x470300 LDP	X21, X23, [X6, #1016]

        (2425) 0x470304 LDP	D2, D3, [X5, #1016]

        (2425) 0x470308 SUBS	X7, X7, #2

        (2425) 0x47030c ADD	X5, X5, #16

        (2425) 0x470310 ADD	X6, X6, #16

        (2425) 0x470314 LDR	D4, [X28, X21,LSL #3]

        (2425) 0x470318 LDR	D5, [X28, X23,LSL #3]

        (2425) 0x47031c FMSUB	D0, D4, D2, D0

        (2425) 0x470320 FMSUB	D1, D5, D3, D1

        (2425) 0x470324 B.NE	470300

      (2423) 0x470328 LDP	X21, X7, [X29, #920]

      (2423) 0x47032c LDUR	X23, [X29, #376]

      (2423) 0x470330 FADD	D0, D1, D0

      (2423) 0x470334 CMP	X3, X4

      (2423) 0x470338 B.EQ	4703c4

      (2423) 0x47033c SUB	W3, W1, W2

      (2423) 0x470340 ANDS	X4, X3, #4160

      (2423) 0x470344 B.EQ	47036c

      (2423) 0x470348 ORR	X3, XZR, X2

        (2427) 0x47034c LDR	X5, [X24, X3,LSL #3]

        (2427) 0x470350 LDR	D1, [X26, X3,LSL #3]

        (2427) 0x470354 ADD	X3, X3, #1

        (2427) 0x470358 SUBS	X4, X4, #1

        (2427) 0x47035c LDR	D2, [X28, X5,LSL #3]

        (2427) 0x470360 FMSUB	D0, D2, D1, D0

        (2427) 0x470364 B.NE	47034c

      (2423) 0x470368 B	470370

      (2423) 0x47036c ORR	X3, XZR, X2

      (2423) 0x470370 SUB	X2, X2, X1

      (2423) 0x470374 CMN	X2, #4

      (2423) 0x470378 B.HI	4703c4

      (2423) 0x47037c SUB	X1, X1, X3

      (2423) 0x470380 ADD	X2, X16, X3,LSL #3

      (2423) 0x470384 ADD	X3, X17, X3,LSL #3

        (2426) 0x470388 LDP	X4, X5, [X2, #1008]

        (2426) 0x47038c LDP	D2, D3, [X3, #1008]

        (2426) 0x470390 SUBS	X1, X1, #4

        (2426) 0x470394 LDR	D4, [X28, X5,LSL #3]

        (2426) 0x470398 LDR	D1, [X28, X4,LSL #3]

        (2426) 0x47039c LDP	X4, X5, [X2], #32

        (2426) 0x4703a0 FMUL	D3, D4, D3

        (2426) 0x4703a4 LDR	D4, [X28, X4,LSL #3]

        (2426) 0x4703a8 FMADD	D1, D1, D2, D3

        (2426) 0x4703ac LDP	D2, D3, [X3], #32

        (2426) 0x4703b0 FMADD	D1, D4, D2, D1

        (2426) 0x4703b4 LDR	D2, [X28, X5,LSL #3]

        (2426) 0x4703b8 FMADD	D1, D2, D3, D1

        (2426) 0x4703bc FSUB	D0, D0, S1

        (2426) 0x4703c0 B.NE	470388

      (2423) 0x4703c4 CMP	X11, X18

      (2423) 0x4703c8 B.LE	4701a8

      (2423) 0x4703cc LDR	D1, [X30, X0,LSL #3]

      (2423) 0x4703d0 FMUL	D0, D0, D11

      (2423) 0x4703d4 SUB	W1, W11, W18

      (2423) 0x4703d8 ADD	X0, X18, #1

      (2423) 0x4703dc TBZ	W1, #0, 470400

      (2423) 0x4703e0 LDR	D2, [X19, X18,LSL #3]

      (2423) 0x4703e4 LDR	X18, [X22, X18,LSL #3]

      (2423) 0x4703e8 LDR	D3, [X25, X18,LSL #3]

      (2423) 0x4703ec FMUL	D2, D0, D2

      (2423) 0x4703f0 FDIV	D2, D2, D1

      (2423) 0x4703f4 FADD	D2, D3, D2

      (2423) 0x4703f8 STR	D2, [X25, X18,LSL #3]

      (2423) 0x4703fc ORR	X18, XZR, X0

      (2423) 0x470400 CMP	X11, X0

      (2423) 0x470404 B.EQ	4701a8

      (2423) 0x470408 FDIV	D1, D14, D1

      (2423) 0x47040c SUB	X0, X11, X18

      (2423) 0x470410 ADD	X1, X10, X18,LSL #3

      (2423) 0x470414 ADD	X18, X9, X18,LSL #3

      (2423) 0x470418 HINT	#0

      (2423) 0x47041c HINT	#0

        (2424) 0x470420 LDUR	X2, [X1, #504]

        (2424) 0x470424 LDUR	D2, [X18, #504]

        (2424) 0x470428 SUBS	X0, X0, #2

        (2424) 0x47042c LDR	D3, [X25, X2,LSL #3]

        (2424) 0x470430 FMUL	D2, D0, D2

        (2424) 0x470434 FMADD	D2, D2, D1, D3

        (2424) 0x470438 STR	D2, [X25, X2,LSL #3]

        (2424) 0x47043c LDR	X2, [X1], #16

        (2424) 0x470440 LDR	D2, [X18], #16

        (2424) 0x470444 LDR	D3, [X25, X2,LSL #3]

        (2424) 0x470448 FMUL	D2, D0, D2

        (2424) 0x47044c FMADD	D2, D2, D1, D3

        (2424) 0x470450 STR	D2, [X25, X2,LSL #3]

        (2424) 0x470454 B.NE	470420

      (2423) 0x470458 B	4701a8

    (2376) 0x47045c CMP	X20, #1

    (2376) 0x470460 B.LT	46f52c

    (2376) 0x470464 LDR	X12, [X23, X20,LSL #3]

    (2376) 0x470468 ADD	X8, X19, #8

    (2376) 0x47046c ADD	X9, X22, #8

    (2376) 0x470470 ADD	X10, X22, #16

    (2376) 0x470474 ADD	X11, X19, #16

    (2376) 0x470478 ADD	X13, X26, #8

    (2376) 0x47047c ADD	X14, X24, #8

    (2376) 0x470480 ADD	X15, X24, #16

    (2376) 0x470484 ADD	X16, X26, #16

    (2376) 0x470488 B	470494

      (2415) 0x47048c CMP	X17, #2

      (2415) 0x470490 B.LT	46f52c

      (2415) 0x470494 ORR	X17, XZR, X20

      (2415) 0x470498 SUB	X20, X20, #1

      (2415) 0x47049c ORR	X18, XZR, X12

      (2415) 0x4704a0 LDR	D0, [X21, X20,LSL #3]

      (2415) 0x4704a4 LDR	X12, [X23, X20,LSL #3]

      (2415) 0x4704a8 SUBS	X1, X18, X12

      (2415) 0x4704ac B.LE	4705a0

      (2415) 0x4704b0 CMP	X1, #2

      (2415) 0x4704b4 B.CS	4704c0

      (2415) 0x4704b8 ORR	X0, XZR, X12

      (2415) 0x4704bc B	470518

      (2415) 0x4704c0 AND	X2, X1, #8127

      (2415) 0x4704c4 MOVI	D1, #0

      (2415) 0x4704c8 ADD	X3, X8, X12,LSL #3

      (2415) 0x4704cc ADD	X4, X9, X12,LSL #3

      (2415) 0x4704d0 ADD	X0, X12, X2

      (2415) 0x4704d4 ORR	X5, XZR, X2

      (2415) 0x4704d8 HINT	#0

      (2415) 0x4704dc HINT	#0

        (2420) 0x4704e0 LDP	X6, X7, [X4, #1016]

        (2420) 0x4704e4 LDP	D2, D3, [X3, #1016]

        (2420) 0x4704e8 SUBS	X5, X5, #2

        (2420) 0x4704ec ADD	X3, X3, #16

        (2420) 0x4704f0 ADD	X4, X4, #16

        (2420) 0x4704f4 LDR	D4, [X25, X6,LSL #3]

        (2420) 0x4704f8 LDR	D5, [X25, X7,LSL #3]

        (2420) 0x4704fc FMSUB	D0, D4, D2, D0

        (2420) 0x470500 FMSUB	D1, D5, D3, D1

        (2420) 0x470504 B.NE	4704e0

      (2415) 0x470508 LDUR	X7, [X29, #416]

      (2415) 0x47050c FADD	D0, D1, D0

      (2415) 0x470510 CMP	X1, X2

      (2415) 0x470514 B.EQ	4705a0

      (2415) 0x470518 SUB	W1, W18, W0

      (2415) 0x47051c ORR	X2, XZR, X0

      (2415) 0x470520 ANDS	X1, X1, #4160

      (2415) 0x470524 B.EQ	470544

        (2422) 0x470528 LDR	X3, [X22, X2,LSL #3]

        (2422) 0x47052c LDR	D1, [X19, X2,LSL #3]

        (2422) 0x470530 ADD	X2, X2, #1

        (2422) 0x470534 SUBS	X1, X1, #1

        (2422) 0x470538 LDR	D2, [X25, X3,LSL #3]

        (2422) 0x47053c FMSUB	D0, D2, D1, D0

        (2422) 0x470540 B.NE	470528

      (2415) 0x470544 SUB	X0, X0, X18

      (2415) 0x470548 CMN	X0, #4

      (2415) 0x47054c B.HI	4705a0

      (2415) 0x470550 SUB	X0, X18, X2

      (2415) 0x470554 ADD	X1, X10, X2,LSL #3

      (2415) 0x470558 ADD	X2, X11, X2,LSL #3

      (2415) 0x47055c HINT	#0

        (2421) 0x470560 LDP	X3, X4, [X1, #1008]

        (2421) 0x470564 LDP	D2, D3, [X2, #1008]

        (2421) 0x470568 SUBS	X0, X0, #4

        (2421) 0x47056c LDR	D4, [X25, X4,LSL #3]

        (2421) 0x470570 LDR	D1, [X25, X3,LSL #3]

        (2421) 0x470574 LDP	X3, X4, [X1], #32

        (2421) 0x470578 FMUL	D3, D4, D3

        (2421) 0x47057c LDR	D4, [X25, X3,LSL #3]

        (2421) 0x470580 FMADD	D1, D1, D2, D3

        (2421) 0x470584 LDP	D2, D3, [X2], #32

        (2421) 0x470588 FMADD	D1, D4, D2, D1

        (2421) 0x47058c LDR	D2, [X25, X4,LSL #3]

        (2421) 0x470590 FMADD	D1, D2, D3, D1

        (2421) 0x470594 FSUB	D0, D0, S1

        (2421) 0x470598 B.NE	470560

      (2415) 0x47059c HINT	#0

      (2415) 0x4705a0 CBZ	X7, 4706a0

      (2415) 0x4705a4 LDUR	X0, [X29, #424]

      (2415) 0x4705a8 LDR	X5, [X0, X20,LSL #3]

      (2415) 0x4705ac LDR	X0, [X0, X17,LSL #3]

      (2415) 0x4705b0 SUBS	X2, X0, X5

      (2415) 0x4705b4 B.LE	4706a0

      (2415) 0x4705b8 CMP	X2, #2

      (2415) 0x4705bc B.CS	4705c8

      (2415) 0x4705c0 ORR	X1, XZR, X5

      (2415) 0x4705c4 B	470618

      (2415) 0x4705c8 AND	X3, X2, #8127

      (2415) 0x4705cc MOVI	D1, #0

      (2415) 0x4705d0 ADD	X4, X13, X5,LSL #3

      (2415) 0x4705d4 ADD	X1, X5, X3

      (2415) 0x4705d8 ADD	X5, X14, X5,LSL #3

      (2415) 0x4705dc ORR	X6, XZR, X3

        (2417) 0x4705e0 LDP	X7, X21, [X5, #1016]

        (2417) 0x4705e4 LDP	D2, D3, [X4, #1016]

        (2417) 0x4705e8 SUBS	X6, X6, #2

        (2417) 0x4705ec ADD	X4, X4, #16

        (2417) 0x4705f0 ADD	X5, X5, #16

        (2417) 0x4705f4 LDR	D4, [X28, X7,LSL #3]

        (2417) 0x4705f8 LDR	D5, [X28, X21,LSL #3]

        (2417) 0x4705fc FMSUB	D0, D4, D2, D0

        (2417) 0x470600 FMSUB	D1, D5, D3, D1

        (2417) 0x470604 B.NE	4705e0

      (2415) 0x470608 LDP	X21, X7, [X29, #920]

      (2415) 0x47060c FADD	D0, D1, D0

      (2415) 0x470610 CMP	X2, X3

      (2415) 0x470614 B.EQ	4706a0

      (2415) 0x470618 SUB	W2, W0, W1

      (2415) 0x47061c ANDS	X3, X2, #4160

      (2415) 0x470620 B.EQ	470648

      (2415) 0x470624 ORR	X2, XZR, X1

        (2419) 0x470628 LDR	X4, [X24, X2,LSL #3]

        (2419) 0x47062c LDR	D1, [X26, X2,LSL #3]

        (2419) 0x470630 ADD	X2, X2, #1

        (2419) 0x470634 SUBS	X3, X3, #1

        (2419) 0x470638 LDR	D2, [X28, X4,LSL #3]

        (2419) 0x47063c FMSUB	D0, D2, D1, D0

        (2419) 0x470640 B.NE	470628

      (2415) 0x470644 B	47064c

      (2415) 0x470648 ORR	X2, XZR, X1

      (2415) 0x47064c SUB	X1, X1, X0

      (2415) 0x470650 CMN	X1, #4

      (2415) 0x470654 B.HI	4706a0

      (2415) 0x470658 SUB	X0, X0, X2

      (2415) 0x47065c ADD	X1, X15, X2,LSL #3

      (2415) 0x470660 ADD	X2, X16, X2,LSL #3

        (2418) 0x470664 LDP	X3, X4, [X1, #1008]

        (2418) 0x470668 LDP	D2, D3, [X2, #1008]

        (2418) 0x47066c SUBS	X0, X0, #4

        (2418) 0x470670 LDR	D4, [X28, X4,LSL #3]

        (2418) 0x470674 LDR	D1, [X28, X3,LSL #3]

        (2418) 0x470678 LDP	X3, X4, [X1], #32

        (2418) 0x47067c FMUL	D3, D4, D3

        (2418) 0x470680 LDR	D4, [X28, X3,LSL #3]

        (2418) 0x470684 FMADD	D1, D1, D2, D3

        (2418) 0x470688 LDP	D2, D3, [X2], #32

        (2418) 0x47068c FMADD	D1, D4, D2, D1

        (2418) 0x470690 LDR	D2, [X28, X4,LSL #3]

        (2418) 0x470694 FMADD	D1, D2, D3, D1

        (2418) 0x470698 FSUB	D0, D0, S1

        (2418) 0x47069c B.NE	470664

      (2415) 0x4706a0 CMP	X18, X12

      (2415) 0x4706a4 B.LE	47048c

      (2415) 0x4706a8 LDR	D1, [X30, X20,LSL #3]

      (2415) 0x4706ac FMUL	D0, D0, D11

      (2415) 0x4706b0 SUB	W2, W18, W12

      (2415) 0x4706b4 ADD	X0, X12, #1

      (2415) 0x4706b8 ORR	X1, XZR, X12

      (2415) 0x4706bc TBZ	W2, #0, 4706e0

      (2415) 0x4706c0 LDR	D2, [X19, X12,LSL #3]

      (2415) 0x4706c4 LDR	X1, [X22, X12,LSL #3]

      (2415) 0x4706c8 LDR	D3, [X25, X1,LSL #3]

      (2415) 0x4706cc FMUL	D2, D0, D2

      (2415) 0x4706d0 FDIV	D2, D2, D1

      (2415) 0x4706d4 FADD	D2, D3, D2

      (2415) 0x4706d8 STR	D2, [X25, X1,LSL #3]

      (2415) 0x4706dc ORR	X1, XZR, X0

      (2415) 0x4706e0 CMP	X18, X0

      (2415) 0x4706e4 B.EQ	47048c

      (2415) 0x4706e8 FDIV	D1, D14, D1

      (2415) 0x4706ec SUB	X18, X18, X1

      (2415) 0x4706f0 ADD	X0, X9, X1,LSL #3

      (2415) 0x4706f4 ADD	X1, X8, X1,LSL #3

      (2415) 0x4706f8 HINT	#0

      (2415) 0x4706fc HINT	#0

        (2416) 0x470700 LDUR	X2, [X0, #504]

        (2416) 0x470704 LDUR	D2, [X1, #504]

        (2416) 0x470708 SUBS	X18, X18, #2

        (2416) 0x47070c LDR	D3, [X25, X2,LSL #3]

        (2416) 0x470710 FMUL	D2, D0, D2

        (2416) 0x470714 FMADD	D2, D2, D1, D3

        (2416) 0x470718 STR	D2, [X25, X2,LSL #3]

        (2416) 0x47071c LDR	X2, [X0], #16

        (2416) 0x470720 LDR	D2, [X1], #16

        (2416) 0x470724 LDR	D3, [X25, X2,LSL #3]

        (2416) 0x470728 FMUL	D2, D0, D2

        (2416) 0x47072c FMADD	D2, D2, D1, D3

        (2416) 0x470730 STR	D2, [X25, X2,LSL #3]

        (2416) 0x470734 B.NE	470700

      (2415) 0x470738 B	47048c

    (2376) 0x47073c CMP	X23, #1

    (2376) 0x470740 B.LT	46f52c

    (2376) 0x470744 LDR	X12, [X30, X23,LSL #3]

    (2376) 0x470748 ADD	X8, X26, #8

    (2376) 0x47074c ADD	X9, X20, #8

    (2376) 0x470750 ADD	X10, X20, #16

    (2376) 0x470754 ADD	X11, X26, #16

    (2376) 0x470758 ADD	X13, X24, #8

    (2376) 0x47075c ADD	X14, X19, #8

    (2376) 0x470760 ADD	X15, X19, #16

    (2376) 0x470764 ADD	X16, X24, #16

    (2376) 0x470768 B	47078c

      (2384) 0x47076c LDR	D1, [X22, X23,LSL #3]

      (2384) 0x470770 FMUL	D0, D0, D11

      (2384) 0x470774 FDIV	D0, D0, D1

      (2384) 0x470778 LDR	D1, [X25, X23,LSL #3]

      (2384) 0x47077c FADD	D0, D1, D0

      (2384) 0x470780 STR	D0, [X25, X23,LSL #3]

      (2384) 0x470784 CMP	X17, #1

      (2384) 0x470788 B.LE	46f52c

      (2384) 0x47078c ORR	X17, XZR, X23

      (2384) 0x470790 SUB	X23, X23, #1

      (2384) 0x470794 ORR	X18, XZR, X12

      (2384) 0x470798 LDR	D0, [X21, X23,LSL #3]

      (2384) 0x47079c LDR	X12, [X30, X23,LSL #3]

      (2384) 0x4707a0 SUBS	X1, X18, X12

      (2384) 0x4707a4 B.LE	4708a0

      (2384) 0x4707a8 CMP	X1, #2

      (2384) 0x4707ac B.CS	4707c0

      (2384) 0x4707b0 ORR	X0, XZR, X12

      (2384) 0x4707b4 B	470818

0x4707b8 HINT	#0

0x4707bc HINT	#0

      (2384) 0x4707c0 AND	X2, X1, #8127

      (2384) 0x4707c4 MOVI	D1, #0

      (2384) 0x4707c8 ADD	X3, X8, X12,LSL #3

      (2384) 0x4707cc ADD	X4, X9, X12,LSL #3

      (2384) 0x4707d0 ADD	X0, X12, X2

      (2384) 0x4707d4 ORR	X5, XZR, X2

      (2384) 0x4707d8 HINT	#0

      (2384) 0x4707dc HINT	#0

        (2388) 0x4707e0 LDP	X6, X7, [X4, #1016]

        (2388) 0x4707e4 LDP	D2, D3, [X3, #1016]

        (2388) 0x4707e8 SUBS	X5, X5, #2

        (2388) 0x4707ec ADD	X3, X3, #16

        (2388) 0x4707f0 ADD	X4, X4, #16

        (2388) 0x4707f4 LDR	D4, [X25, X6,LSL #3]

        (2388) 0x4707f8 LDR	D5, [X25, X7,LSL #3]

        (2388) 0x4707fc FMSUB	D0, D4, D2, D0

        (2388) 0x470800 FMSUB	D1, D5, D3, D1

        (2388) 0x470804 B.NE	4707e0

      (2384) 0x470808 LDUR	X6, [X29, #416]

      (2384) 0x47080c FADD	D0, D1, D0

      (2384) 0x470810 CMP	X1, X2

      (2384) 0x470814 B.EQ	4708a0

      (2384) 0x470818 SUB	W1, W18, W0

      (2384) 0x47081c ANDS	X2, X1, #4160

      (2384) 0x470820 B.EQ	470848

      (2384) 0x470824 ORR	X1, XZR, X0

        (2390) 0x470828 LDR	X3, [X20, X1,LSL #3]

        (2390) 0x47082c LDR	D1, [X26, X1,LSL #3]

        (2390) 0x470830 ADD	X1, X1, #1

        (2390) 0x470834 SUBS	X2, X2, #1

        (2390) 0x470838 LDR	D2, [X25, X3,LSL #3]

        (2390) 0x47083c FMSUB	D0, D2, D1, D0

        (2390) 0x470840 B.NE	470828

      (2384) 0x470844 B	47084c

      (2384) 0x470848 ORR	X1, XZR, X0

      (2384) 0x47084c SUB	X0, X0, X18

      (2384) 0x470850 CMN	X0, #4

      (2384) 0x470854 B.HI	4708a0

      (2384) 0x470858 SUB	X18, X18, X1

      (2384) 0x47085c ADD	X0, X10, X1,LSL #3

      (2384) 0x470860 ADD	X1, X11, X1,LSL #3

        (2389) 0x470864 LDP	X2, X3, [X0, #1008]

        (2389) 0x470868 LDP	D2, D3, [X1, #1008]

        (2389) 0x47086c SUBS	X18, X18, #4

        (2389) 0x470870 LDR	D4, [X25, X3,LSL #3]

        (2389) 0x470874 LDR	D1, [X25, X2,LSL #3]

        (2389) 0x470878 LDP	X2, X3, [X0], #32

        (2389) 0x47087c FMUL	D3, D4, D3

        (2389) 0x470880 LDR	D4, [X25, X2,LSL #3]

        (2389) 0x470884 FMADD	D1, D1, D2, D3

        (2389) 0x470888 LDP	D2, D3, [X1], #32

        (2389) 0x47088c FMADD	D1, D4, D2, D1

        (2389) 0x470890 LDR	D2, [X25, X3,LSL #3]

        (2389) 0x470894 FMADD	D1, D2, D3, D1

        (2389) 0x470898 FSUB	D0, D0, S1

        (2389) 0x47089c B.NE	470864

      (2384) 0x4708a0 CBZ	X6, 47076c

      (2384) 0x4708a4 LDUR	X18, [X29, #424]

      (2384) 0x4708a8 LDR	X4, [X18, X23,LSL #3]

      (2384) 0x4708ac LDR	X18, [X18, X17,LSL #3]

      (2384) 0x4708b0 SUBS	X1, X18, X4

      (2384) 0x4708b4 B.LE	47076c

      (2384) 0x4708b8 CMP	X1, #2

      (2384) 0x4708bc B.CS	4708c8

      (2384) 0x4708c0 ORR	X0, XZR, X4

      (2384) 0x4708c4 B	470918

      (2384) 0x4708c8 AND	X2, X1, #8127

      (2384) 0x4708cc MOVI	D1, #0

      (2384) 0x4708d0 ADD	X3, X13, X4,LSL #3

      (2384) 0x4708d4 ADD	X0, X4, X2

      (2384) 0x4708d8 ADD	X4, X14, X4,LSL #3

      (2384) 0x4708dc ORR	X5, XZR, X2

        (2385) 0x4708e0 LDP	X6, X7, [X4, #1016]

        (2385) 0x4708e4 LDP	D2, D3, [X3, #1016]

        (2385) 0x4708e8 SUBS	X5, X5, #2

        (2385) 0x4708ec ADD	X3, X3, #16

        (2385) 0x4708f0 ADD	X4, X4, #16

        (2385) 0x4708f4 LDR	D4, [X28, X6,LSL #3]

        (2385) 0x4708f8 LDR	D5, [X28, X7,LSL #3]

        (2385) 0x4708fc FMSUB	D0, D4, D2, D0

        (2385) 0x470900 FMSUB	D1, D5, D3, D1

        (2385) 0x470904 B.NE	4708e0

      (2384) 0x470908 LDUR	X6, [X29, #416]

      (2384) 0x47090c FADD	D0, D1, D0

      (2384) 0x470910 CMP	X1, X2

      (2384) 0x470914 B.EQ	47076c

      (2384) 0x470918 SUB	W1, W18, W0

      (2384) 0x47091c ANDS	X2, X1, #4160

      (2384) 0x470920 B.EQ	470948

      (2384) 0x470924 ORR	X1, XZR, X0

        (2387) 0x470928 LDR	X3, [X19, X1,LSL #3]

        (2387) 0x47092c LDR	D1, [X24, X1,LSL #3]

        (2387) 0x470930 ADD	X1, X1, #1

        (2387) 0x470934 SUBS	X2, X2, #1

        (2387) 0x470938 LDR	D2, [X28, X3,LSL #3]

        (2387) 0x47093c FMSUB	D0, D2, D1, D0

        (2387) 0x470940 B.NE	470928

      (2384) 0x470944 B	47094c

      (2384) 0x470948 ORR	X1, XZR, X0

      (2384) 0x47094c SUB	X0, X0, X18

      (2384) 0x470950 CMN	X0, #4

      (2384) 0x470954 B.HI	47076c

      (2384) 0x470958 SUB	X18, X18, X1

      (2384) 0x47095c ADD	X0, X15, X1,LSL #3

      (2384) 0x470960 ADD	X1, X16, X1,LSL #3

        (2386) 0x470964 LDP	X2, X3, [X0, #1008]

        (2386) 0x470968 LDP	D2, D3, [X1, #1008]

        (2386) 0x47096c SUBS	X18, X18, #4

        (2386) 0x470970 LDR	D4, [X28, X3,LSL #3]

        (2386) 0x470974 LDR	D1, [X28, X2,LSL #3]

        (2386) 0x470978 LDP	X2, X3, [X0], #32

        (2386) 0x47097c FMUL	D3, D4, D3

        (2386) 0x470980 LDR	D4, [X28, X2,LSL #3]

        (2386) 0x470984 FMADD	D1, D1, D2, D3

        (2386) 0x470988 LDP	D2, D3, [X1], #32

        (2386) 0x47098c FMADD	D1, D4, D2, D1

        (2386) 0x470990 LDR	D2, [X28, X3,LSL #3]

        (2386) 0x470994 FMADD	D1, D2, D3, D1

        (2386) 0x470998 FSUB	D0, D0, S1

        (2386) 0x47099c B.NE	470964

      (2384) 0x4709a0 B	47076c

    (2376) 0x4709a4 CMP	X23, #1

    (2376) 0x4709a8 B.LT	46f52c

    (2376) 0x4709ac LDR	X13, [X30]

    (2376) 0x4709b0 ADD	X8, X20, #8

    (2376) 0x4709b4 ADD	X9, X26, #8

    (2376) 0x4709b8 ADD	X10, X24, #8

    (2376) 0x4709bc ADD	X12, X19, #8

    (2376) 0x4709c0 ADD	X14, X19, #16

    (2376) 0x4709c4 ADD	X15, X24, #16

    (2376) 0x4709c8 ORR	X11, XZR, XZR

    (2376) 0x4709cc B	470a00

0x4709d0 HINT	#0

0x4709d4 HINT	#0

0x4709d8 HINT	#0

0x4709dc HINT	#0

      (2379) 0x4709e0 FMUL	D2, D2, D13

      (2379) 0x4709e4 FMADD	D1, D1, D15, D2

      (2379) 0x4709e8 LDR	D2, [X22, X16,LSL #3]

      (2379) 0x4709ec FDIV	D1, D1, D2

      (2379) 0x4709f0 FADD	D0, D1, D0

      (2379) 0x4709f4 STR	D0, [X25, X16,LSL #3]

      (2379) 0x4709f8 CMP	X11, X23

      (2379) 0x4709fc B.EQ	470c80

      (2379) 0x470a00 LDR	D0, [X25, X11,LSL #3]

      (2379) 0x470a04 ORR	X16, XZR, X11

      (2379) 0x470a08 ORR	X17, XZR, X13

      (2379) 0x470a0c MOVI	D2, #0

      (2379) 0x470a10 STR	D0, [X7, X11,LSL #3]

      (2379) 0x470a14 LDR	D1, [X21, X11,LSL #3]

      (2379) 0x470a18 ADD	X11, X11, #1

      (2379) 0x470a1c LDR	X13, [X30, X11,LSL #3]

      (2379) 0x470a20 CMP	X13, X17

      (2379) 0x470a24 B.LE	470a74

      (2379) 0x470a28 SUB	W18, W13, W17

      (2379) 0x470a2c TBNZ	W18, #0, 470a40

      (2379) 0x470a30 ORR	X0, XZR, X17

      (2379) 0x470a34 B	470a68

0x470a38 HINT	#0

0x470a3c HINT	#0

      (2379) 0x470a40 LDR	X18, [X20, X17,LSL #3]

      (2379) 0x470a44 LDR	D3, [X26, X17,LSL #3]

      (2379) 0x470a48 LDR	D4, [X25, X18,LSL #3]

      (2379) 0x470a4c CMP	X18, X16

      (2379) 0x470a50 B.GE	470a60

      (2379) 0x470a54 LDR	D2, [X7, X18,LSL #3]

      (2379) 0x470a58 FSUB	D2, D2, S4

      (2379) 0x470a5c FMUL	D2, D2, D3

      (2379) 0x470a60 FMSUB	D1, D4, D3, D1

      (2379) 0x470a64 ADD	X0, X17, #1

      (2379) 0x470a68 ADD	X17, X17, #1

      (2379) 0x470a6c CMP	X13, X17

      (2379) 0x470a70 B.NE	470aa0

      (2379) 0x470a74 CBZ	X6, 4709e0

      (2379) 0x470a78 LDUR	X17, [X29, #424]

      (2379) 0x470a7c LDR	X3, [X17, X16,LSL #3]

      (2379) 0x470a80 LDR	X17, [X17, X11,LSL #3]

      (2379) 0x470a84 SUBS	X0, X17, X3

      (2379) 0x470a88 B.LE	4709e0

      (2379) 0x470a8c CMP	X0, #2

      (2379) 0x470a90 B.CS	470b20

      (2379) 0x470a94 ORR	X18, XZR, X3

      (2379) 0x470a98 B	470b78

0x470a9c HINT	#0

      (2379) 0x470aa0 SUB	X17, X13, X0

      (2379) 0x470aa4 ADD	X18, X8, X0,LSL #3

      (2379) 0x470aa8 ADD	X0, X9, X0,LSL #3

      (2379) 0x470aac B	470adc

0x470ab0 HINT	#0

0x470ab4 HINT	#0

0x470ab8 HINT	#0

0x470abc HINT	#0

        (2383) 0x470ac0 FMUL	D3, D4, D3

        (2383) 0x470ac4 ADD	X18, X18, #16

        (2383) 0x470ac8 SUBS	X17, X17, #2

        (2383) 0x470acc ADD	X0, X0, #16

        (2383) 0x470ad0 FMADD	D3, D6, D5, D3

        (2383) 0x470ad4 FSUB	D1, D1, S3

        (2383) 0x470ad8 B.EQ	470a74

        (2383) 0x470adc LDUR	X1, [X18, #504]

        (2383) 0x470ae0 LDUR	D3, [X0, #504]

        (2383) 0x470ae4 LDR	D4, [X25, X1,LSL #3]

        (2383) 0x470ae8 CMP	X1, X16

        (2383) 0x470aec B.GE	470afc

        (2383) 0x470af0 LDR	D5, [X7, X1,LSL #3]

        (2383) 0x470af4 FSUB	D5, D5, S4

        (2383) 0x470af8 FMADD	D2, D5, D3, D2

        (2383) 0x470afc LDR	X1, [X18]

        (2383) 0x470b00 LDR	D5, [X0]

        (2383) 0x470b04 LDR	D6, [X25, X1,LSL #3]

        (2383) 0x470b08 CMP	X1, X16

        (2383) 0x470b0c B.GE	470ac0

        (2383) 0x470b10 LDR	D7, [X7, X1,LSL #3]

        (2383) 0x470b14 FSUB	D7, D7, S6

        (2383) 0x470b18 FMADD	D2, D7, D5, D2

        (2383) 0x470b1c B	470ac0

      (2379) 0x470b20 AND	X1, X0, #8127

      (2379) 0x470b24 MOVI	D3, #0

      (2379) 0x470b28 ADD	X2, X10, X3,LSL #3

      (2379) 0x470b2c ADD	X18, X3, X1

      (2379) 0x470b30 ADD	X3, X12, X3,LSL #3

      (2379) 0x470b34 ORR	X4, XZR, X1

      (2379) 0x470b38 HINT	#0

      (2379) 0x470b3c HINT	#0

        (2380) 0x470b40 LDP	X5, X6, [X3, #1016]

        (2380) 0x470b44 LDP	D4, D5, [X2, #1016]

        (2380) 0x470b48 SUBS	X4, X4, #2

        (2380) 0x470b4c ADD	X2, X2, #16

        (2380) 0x470b50 ADD	X3, X3, #16

        (2380) 0x470b54 LDR	D6, [X28, X5,LSL #3]

        (2380) 0x470b58 LDR	D7, [X28, X6,LSL #3]

        (2380) 0x470b5c FMSUB	D1, D6, D4, D1

        (2380) 0x470b60 FMSUB	D3, D7, D5, D3

        (2380) 0x470b64 B.NE	470b40

      (2379) 0x470b68 LDUR	X6, [X29, #416]

      (2379) 0x470b6c FADD	D1, D3, D1

      (2379) 0x470b70 CMP	X0, X1

      (2379) 0x470b74 B.EQ	4709e0

      (2379) 0x470b78 SUB	W0, W17, W18

      (2379) 0x470b7c ANDS	X1, X0, #4160

      (2379) 0x470b80 B.EQ	470ba8

      (2379) 0x470b84 ORR	X0, XZR, X18

        (2382) 0x470b88 LDR	X2, [X19, X0,LSL #3]

        (2382) 0x470b8c LDR	D3, [X24, X0,LSL #3]

        (2382) 0x470b90 ADD	X0, X0, #1

        (2382) 0x470b94 SUBS	X1, X1, #1

        (2382) 0x470b98 LDR	D4, [X28, X2,LSL #3]

        (2382) 0x470b9c FMSUB	D1, D4, D3, D1

        (2382) 0x470ba0 B.NE	470b88

      (2379) 0x470ba4 B	470bac

      (2379) 0x470ba8 ORR	X0, XZR, X18

      (2379) 0x470bac SUB	X18, X18, X17

      (2379) 0x470bb0 CMN	X18, #4

      (2379) 0x470bb4 B.HI	4709e0

      (2379) 0x470bb8 SUB	X17, X17, X0

      (2379) 0x470bbc ADD	X18, X14, X0,LSL #3

      (2379) 0x470bc0 ADD	X0, X15, X0,LSL #3

        (2381) 0x470bc4 LDP	X1, X2, [X18, #1008]

        (2381) 0x470bc8 LDP	D4, D5, [X0, #1008]

        (2381) 0x470bcc SUBS	X17, X17, #4

        (2381) 0x470bd0 LDR	D6, [X28, X2,LSL #3]

        (2381) 0x470bd4 LDR	D3, [X28, X1,LSL #3]

        (2381) 0x470bd8 LDP	X1, X2, [X18], #32

        (2381) 0x470bdc FMUL	D5, D6, D5

        (2381) 0x470be0 LDR	D6, [X28, X1,LSL #3]

        (2381) 0x470be4 FMADD	D3, D3, D4, D5

        (2381) 0x470be8 LDP	D4, D5, [X0], #32

        (2381) 0x470bec FMADD	D3, D6, D4, D3

        (2381) 0x470bf0 LDR	D4, [X28, X2,LSL #3]

        (2381) 0x470bf4 FMADD	D3, D4, D5, D3

        (2381) 0x470bf8 FSUB	D1, D1, S3

        (2381) 0x470bfc B.NE	470bc4

      (2379) 0x470c00 B	4709e0

      (2373) 0x470c04 ADD	X9, X5, X19,LSL #3

      (2373) 0x470c08 ADD	X10, X25, X19,LSL #3

      (2373) 0x470c0c ADD	X11, X13, X19,LSL #3

      (2373) 0x470c10 ORR	X8, XZR, XZR

      (2373) 0x470c14 CMP	X25, X9

      (2373) 0x470c18 CCMP	X10, X5, #0, #3

      (2373) 0x470c1c CSINC	W9, WZR, WZR, #9

      (2373) 0x470c20 CMP	X13, X10

      (2373) 0x470c24 CCMP	X25, X11, #2, #3

      (2373) 0x470c28 B.CC	46f8f8

      (2373) 0x470c2c TBNZ	W9, #0, 46f8f8

      (2373) 0x470c30 LDP	X10, X11, [SP, #16]

      (2373) 0x470c34 LDR	X12, [SP, #32]

      (2373) 0x470c38 AND	X8, X19, #7998

      (2373) 0x470c3c ORR	X9, XZR, X8

        (2375) 0x470c40 LDP	Q0, Q1, [X12, #2032]

        (2375) 0x470c44 LDP	Q2, Q3, [X11, #2032]

        (2375) 0x470c48 ADD	X12, X12, #32

        (2375) 0x470c4c ADD	X11, X11, #32

        (2375) 0x470c50 SUBS	X9, X9, #4

        (2375) 0x470c54 FDIV	V1.2D, V1.2D, V3.2D

        (2375) 0x470c58 FDIV	V0.2D, V0.2D, V2.2D

        (2375) 0x470c5c LDP	Q2, Q3, [X10, #2032]

        (2375) 0x470c60 FADD	V1.2D, V3.2D, V1.2D

        (2375) 0x470c64 FADD	V0.2D, V2.2D, V0.2D

        (2375) 0x470c68 STP	Q0, Q1, [X10, #2032]

        (2375) 0x470c6c ADD	X10, X10, #32

        (2375) 0x470c70 B.NE	470c40

      (2373) 0x470c74 CMP	X19, X8

      (2373) 0x470c78 B.EQ	46f540

      (2373) 0x470c7c B	46f8f8

    (2376) 0x470c80 CMP	X23, #1

    (2376) 0x470c84 B.LT	46f52c

  (2377) 0x470c88 LDR	X10, [X30, X23,LSL #3]

  (2377) 0x470c8c ADD	X8, X20, #8

  (2377) 0x470c90 ADD	X9, X26, #8

  (2377) 0x470c94 ADD	X11, X24, #8

  (2377) 0x470c98 ADD	X12, X19, #8

  (2377) 0x470c9c ADD	X13, X19, #16

  (2377) 0x470ca0 ADD	X14, X24, #16

  (2377) 0x470ca4 B	470ccc

  (2377) 0x470ca8 FMUL	D1, D1, D13

  (2377) 0x470cac FMADD	D0, D0, D15, D1

  (2377) 0x470cb0 LDR	D1, [X22, X23,LSL #3]

  (2377) 0x470cb4 FDIV	D0, D0, D1

  (2377) 0x470cb8 LDR	D1, [X25, X23,LSL #3]

  (2377) 0x470cbc FADD	D0, D0, D1

  (2377) 0x470cc0 STR	D0, [X25, X23,LSL #3]

  (2377) 0x470cc4 CMP	X15, #1

  (2377) 0x470cc8 B.LE	46f52c

  (2377) 0x470ccc ORR	X15, XZR, X23

  (2377) 0x470cd0 SUB	X23, X23, #1

  (2377) 0x470cd4 ORR	X16, XZR, X10

  (2377) 0x470cd8 MOVI	D1, #0

  (2377) 0x470cdc LDR	D0, [X21, X23,LSL #3]

  (2377) 0x470ce0 LDR	X10, [X30, X23,LSL #3]

  (2377) 0x470ce4 CMP	X16, X10

  (2377) 0x470ce8 B.LE	470d34

  (2377) 0x470cec SUB	W17, W16, W10

  (2377) 0x470cf0 TBNZ	W17, #0, 470d00

  (2377) 0x470cf4 ORR	X18, XZR, X10

  (2377) 0x470cf8 B	470d28

0x470cfc HINT	#0

  (2377) 0x470d00 LDR	X17, [X20, X10,LSL #3]

  (2377) 0x470d04 LDR	D2, [X26, X10,LSL #3]

  (2377) 0x470d08 LDR	D3, [X25, X17,LSL #3]

  (2377) 0x470d0c CMP	X17, X15

  (2377) 0x470d10 B.LT	470d20

  (2377) 0x470d14 LDR	D1, [X7, X17,LSL #3]

  (2377) 0x470d18 FSUB	D1, D1, S3

  (2377) 0x470d1c FMUL	D1, D1, D2

  (2377) 0x470d20 FMSUB	D0, D3, D2, D0

  (2377) 0x470d24 ADD	X18, X10, #1

  (2377) 0x470d28 ADD	X17, X10, #1

  (2377) 0x470d2c CMP	X16, X17

  (2377) 0x470d30 B.NE	470d60

  (2377) 0x470d34 CBZ	X6, 470ca8

  (2377) 0x470d38 LDUR	X16, [X29, #424]

  (2377) 0x470d3c LDR	X2, [X16, X23,LSL #3]

  (2377) 0x470d40 LDR	X16, [X16, X15,LSL #3]

  (2377) 0x470d44 SUBS	X18, X16, X2

  (2377) 0x470d48 B.LE	470ca8

  (2377) 0x470d4c CMP	X18, #2

  (2377) 0x470d50 B.CS	470de0

  (2377) 0x470d54 ORR	X17, XZR, X2

  (2377) 0x470d58 B	470e34

0x470d5c HINT	#0

(2378) 0x470d60 SUB	X16, X16, X18

(2378) 0x470d64 ADD	X17, X8, X18,LSL #3

(2378) 0x470d68 ADD	X18, X9, X18,LSL #3

(2378) 0x470d6c B	470d9c

0x470d70 HINT	#0

0x470d74 HINT	#0

0x470d78 HINT	#0

0x470d7c HINT	#0

(2378) 0x470d80 FMUL	D2, D3, D2

(2378) 0x470d84 ADD	X17, X17, #16

(2378) 0x470d88 SUBS	X16, X16, #2

(2378) 0x470d8c ADD	X18, X18, #16

(2378) 0x470d90 FMADD	D2, D5, D4, D2

(2378) 0x470d94 FSUB	D0, D0, S2

(2378) 0x470d98 B.EQ	470d34

(2378) 0x470d9c LDUR	X0, [X17, #504]

(2378) 0x470da0 LDUR	D2, [X18, #504]

(2378) 0x470da4 LDR	D3, [X25, X0,LSL #3]

(2378) 0x470da8 CMP	X0, X15

(2378) 0x470dac B.LT	470dbc

(2378) 0x470db0 LDR	D4, [X7, X0,LSL #3]

(2378) 0x470db4 FSUB	D4, D4, S3

(2378) 0x470db8 FMADD	D1, D4, D2, D1

(2378) 0x470dbc LDR	X0, [X17]

(2378) 0x470dc0 LDR	D4, [X18]

(2378) 0x470dc4 LDR	D5, [X25, X0,LSL #3]

(2378) 0x470dc8 CMP	X0, X15

(2378) 0x470dcc B.LT	470d80

(2378) 0x470dd0 LDR	D6, [X7, X0,LSL #3]

(2378) 0x470dd4 FSUB	D6, D6, S5

(2378) 0x470dd8 FMADD	D1, D6, D4, D1

(2378) 0x470ddc B	470d80

  (2377) 0x470de0 AND	X0, X18, #8127

  (2377) 0x470de4 MOVI	D2, #0

  (2377) 0x470de8 ADD	X1, X11, X2,LSL #3

  (2377) 0x470dec ADD	X17, X2, X0

  (2377) 0x470df0 ADD	X2, X12, X2,LSL #3

  (2377) 0x470df4 ORR	X3, XZR, X0

  (2377) 0x470df8 HINT	#0

  (2377) 0x470dfc HINT	#0

    (2434) 0x470e00 LDP	X4, X5, [X2, #1016]

    (2434) 0x470e04 LDP	D3, D4, [X1, #1016]

    (2434) 0x470e08 SUBS	X3, X3, #2

    (2434) 0x470e0c ADD	X1, X1, #16

    (2434) 0x470e10 ADD	X2, X2, #16

    (2434) 0x470e14 LDR	D5, [X28, X4,LSL #3]

    (2434) 0x470e18 LDR	D6, [X28, X5,LSL #3]

    (2434) 0x470e1c FMSUB	D0, D5, D3, D0

    (2434) 0x470e20 FMSUB	D2, D6, D4, D2

    (2434) 0x470e24 B.NE	470e00

  (2377) 0x470e28 FADD	D0, D2, D0

  (2377) 0x470e2c CMP	X18, X0

  (2377) 0x470e30 B.EQ	470ca8

  (2377) 0x470e34 SUB	W18, W16, W17

  (2377) 0x470e38 ANDS	X0, X18, #4160

  (2377) 0x470e3c B.EQ	470e64

  (2377) 0x470e40 ORR	X18, XZR, X17

    (2436) 0x470e44 LDR	X1, [X19, X18,LSL #3]

    (2436) 0x470e48 LDR	D2, [X24, X18,LSL #3]

    (2436) 0x470e4c ADD	X18, X18, #1

    (2436) 0x470e50 SUBS	X0, X0, #1

    (2436) 0x470e54 LDR	D3, [X28, X1,LSL #3]

    (2436) 0x470e58 FMSUB	D0, D3, D2, D0

    (2436) 0x470e5c B.NE	470e44

  (2377) 0x470e60 B	470e68

  (2377) 0x470e64 ORR	X18, XZR, X17

  (2377) 0x470e68 SUB	X17, X17, X16

  (2377) 0x470e6c CMN	X17, #4

  (2377) 0x470e70 B.HI	470ca8

  (2377) 0x470e74 SUB	X16, X16, X18

  (2377) 0x470e78 ADD	X17, X13, X18,LSL #3

  (2377) 0x470e7c ADD	X18, X14, X18,LSL #3

    (2435) 0x470e80 LDP	X0, X1, [X17, #1008]

    (2435) 0x470e84 LDP	D3, D4, [X18, #1008]

    (2435) 0x470e88 SUBS	X16, X16, #4

    (2435) 0x470e8c LDR	D5, [X28, X1,LSL #3]

    (2435) 0x470e90 LDR	D2, [X28, X0,LSL #3]

    (2435) 0x470e94 LDP	X0, X1, [X17], #32

    (2435) 0x470e98 FMUL	D4, D5, D4

    (2435) 0x470e9c LDR	D5, [X28, X0,LSL #3]

    (2435) 0x470ea0 FMADD	D2, D2, D3, D4

    (2435) 0x470ea4 LDP	D3, D4, [X18], #32

    (2435) 0x470ea8 FMADD	D2, D5, D3, D2

    (2435) 0x470eac LDR	D3, [X28, X1,LSL #3]

    (2435) 0x470eb0 FMADD	D2, D3, D4, D2

    (2435) 0x470eb4 FSUB	D0, D0, S2

    (2435) 0x470eb8 B.NE	470e80

  (2377) 0x470ebc B	470ca8

0x470ec0 ADRP	X8,

0x470ec4 LDR	X8, [X8, #3872]

0x470ec8 LDR	X0, [X8]

0x470ecc LDP	D9, D8, [SP, #272]

0x470ed0 LDP	D11, D10, [SP, #256]

0x470ed4 LDP	D13, D12, [SP, #240]

0x470ed8 LDP	D15, D14, [SP, #224]

0x470edc LDP	X20, X19, [SP, #368]

0x470ee0 LDP	X22, X21, [SP, #352]

0x470ee4 LDP	X24, X23, [SP, #336]

0x470ee8 LDP	X26, X25, [SP, #320]

0x470eec LDP	X28, X27, [SP, #304]

0x470ef0 LDP	X29, X30, [SP, #288]

0x470ef4 ADD	SP, SP, #384

0x470ef8 RET

0x470efc HINT	#0

Coverage (%)	Name	Source Location	Module
►95.85+	hypre_BoomerAMGCycle	par_cycle.c:322	exec
○	hypre_BoomerAMGSolve	par_amg_solve.c:243	exec
○	hypre_PCGSolve	pcg.c:545	exec
○	main	amg.c:419	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►4.15+	hypre_BoomerAMGCycle	par_cycle.c:322	exec
○	hypre_BoomerAMGSolve	par_amg_solve.c:243	exec
○	hypre_PCGSolve	pcg.c:424	exec
○	main	amg.c:419	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	ams.c:63-330
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:63,70-106,113-182,192-222,230-253,260-307,316,326-330.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.67 to 3.17 cycles (4.95x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 68% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 15.67 to 13.21 cycles (1.19x speedup).

Details

13% of VPU instructions are used in vector version (process two or more data elements in vector registers):

33% of VPU loads are used in vector version.
15% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 1 FMA (fused multiply-add) operations.

Matching between your function (in the source code) and the binary function

The binary function is composed of 3 FP arithmetical operations:

1: addition or subtraction (all inside FMA instructions)
2: multiply (1 inside FMA instructions)

The binary function is loading 248 bytes. The binary function is storing 316 bytes.

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	122
loop length	488
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

10.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	3.58	3.58	3.50	3.50	3.42	3.42	4.00	4.00	4.00	4.00	15.67	15.67	15.67	10.50	10.50
cycles	1.50	1.50	3.58	3.58	3.50	3.50	3.42	3.42	4.00	4.00	4.00	4.00	15.67	15.67	15.67	10.50	10.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.25
Overall L1	15.67

Vectorization ratios

INT

all	16%
load	33%
store	15%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	13%
load	33%
store	15%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.67 cycles. At this rate:

16% of peak load performance is reached (15.83 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
42% of peak store performance is reached (20.17 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 46f420

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #384	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP D15, D14, [SP, #224]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D13, D12, [SP, #240]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D11, D10, [SP, #256]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D9, D8, [SP, #272]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP X29, X30, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #288	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X1, X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X5, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X0, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X3, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 470ec0 <hypre_ParCSRRelax+0x1aa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMOV D14, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMSUB D13, D0, D1, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
FMUL D15, D1, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FMOV D8, D4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ORR X27, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X5, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X20, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X21, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X23, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X7, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X4, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X2, X3, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
FMOV D9, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMOV D10, D2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMOV D11, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMOV D12, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FCMP D0, D14	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FNEG D0, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D0, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR X8, [X8, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X7, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CSINC W8, WZR, WZR, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FCMP D1, D14	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
CSINC W9, WZR, WZR, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP X2, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
AND W8, W8, W9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR W8, [SP, #100]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CSNEG X8, X2, X2, #5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X9, X10, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X10, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X8, X4, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X8, X9, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X8, X25, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X9, X25, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X8, X4, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X8, X9, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X8, X10, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 46f54c <hypre_ParCSRRelax+0x12c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ADRP X8, <4dfec0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X8, #3872]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP D9, D8, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D11, D10, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D13, D12, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D15, D14, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP X20, X19, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X22, X21, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X24, X23, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X26, X25, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X28, X27, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #384	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	ams.c:63-330
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.67 to 3.17 cycles (4.95x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

13% of VPU instructions are used in vector version (process two or more data elements in vector registers):

33% of VPU loads are used in vector version.
15% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 1 FMA (fused multiply-add) operations.

Matching between your function (in the source code) and the binary function

The binary function is composed of 3 FP arithmetical operations:

1: addition or subtraction (all inside FMA instructions)
2: multiply (1 inside FMA instructions)

The binary function is loading 248 bytes. The binary function is storing 316 bytes.

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	122
loop length	488
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

10.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	3.58	3.58	3.50	3.50	3.42	3.42	4.00	4.00	4.00	4.00	15.67	15.67	15.67	10.50	10.50
cycles	1.50	1.50	3.58	3.58	3.50	3.50	3.42	3.42	4.00	4.00	4.00	4.00	15.67	15.67	15.67	10.50	10.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.25
Overall L1	15.67

Vectorization ratios

INT

all	16%
load	33%
store	15%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	13%
load	33%
store	15%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.67 cycles. At this rate:

16% of peak load performance is reached (15.83 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
42% of peak store performance is reached (20.17 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 46f420

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #384	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP D15, D14, [SP, #224]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D13, D12, [SP, #240]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D11, D10, [SP, #256]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D9, D8, [SP, #272]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP X29, X30, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #288	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X1, X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X5, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X0, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X3, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 470ec0 <hypre_ParCSRRelax+0x1aa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMOV D14, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMSUB D13, D0, D1, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
FMUL D15, D1, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FMOV D8, D4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ORR X27, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X5, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X20, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X21, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X23, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X7, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X4, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X2, X3, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
FMOV D9, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMOV D10, D2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMOV D11, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMOV D12, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FCMP D0, D14	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FNEG D0, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D0, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR X8, [X8, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X7, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CSINC W8, WZR, WZR, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FCMP D1, D14	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
CSINC W9, WZR, WZR, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP X2, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
AND W8, W8, W9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR W8, [SP, #100]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CSNEG X8, X2, X2, #5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X9, X10, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X10, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X8, X4, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X8, X9, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X8, X25, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X9, X25, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X8, X4, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X8, X9, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X8, X10, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 46f54c <hypre_ParCSRRelax+0x12c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ADRP X8, <4dfec0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X8, #3872]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP D9, D8, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D11, D10, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D13, D12, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D15, D14, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP X20, X19, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X22, X21, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X24, X23, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X26, X25, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X28, X27, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #384	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

▶Scalability Runs Description

Run 1x1	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_NUM_THREADS: 1OMP_PLACES: threads
Run 1x2	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 2OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x4	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 4OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x8	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 8OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x16	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 16OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x24	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 24OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x32	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 32OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x40	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 40OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x48	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 48OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x56	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 56OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x64	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 64OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x72	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 72OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x80	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 80OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x88	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 88OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x96	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 96OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads

(1x1) Efficiency	(1x1) Potential Speed-Up (%)	(1x2) Efficiency	(1x2) Potential Speed-Up (%)	(1x4) Efficiency	(1x4) Potential Speed-Up (%)	(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x16) Efficiency	(1x16) Potential Speed-Up (%)	(1x24) Efficiency	(1x24) Potential Speed-Up (%)	(1x32) Efficiency	(1x32) Potential Speed-Up (%)	(1x40) Efficiency	(1x40) Potential Speed-Up (%)	(1x48) Efficiency	(1x48) Potential Speed-Up (%)	(1x56) Efficiency	(1x56) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)	(1x72) Efficiency	(1x72) Potential Speed-Up (%)	(1x80) Efficiency	(1x80) Potential Speed-Up (%)	(1x88) Efficiency	(1x88) Potential Speed-Up (%)	(1x96) Efficiency	(1x96) Potential Speed-Up (%)
1	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x1	1	1	1	1	5.5399994850159	2.0824801921844
1x2
1x4
1x8
1x16
1x24
1x32
1x40
1x48
1x56
1x64
1x72
1x80
1x88
1x96

Name	Coverage (%)	Time (s)
▼hypre_ParCSRRelax–	2.08	5.54
▼Loop 2378 - ams.c:70-326 - exec–	0.00	0.00
▼Loop 2377 - ams.c:70-326 - exec–	0.00	0.00
○Loop 2436 - ams.c:220-221 - exec	0.00	0.00
○Loop 2434 - ams.c:221-221 - exec	0.00	0.00
▼Loop 2376 - ams.c:70-326 - exec–	0.00	0.00
▼Loop 2412 - ams.c:123-127 - exec–	0.00	0.00
○Loop 2414 - ams.c:126-127 - exec	0.00	0.00
○Loop 2413 - ams.c:126-127 - exec	0.00	0.00
▼Loop 2423 - ams.c:283-293 - exec–	0.00	0.00
○Loop 2427 - ams.c:289-290 - exec	0.00	0.00
○Loop 2430 - ams.c:286-287 - exec	0.00	0.00
○Loop 2425 - ams.c:290-290 - exec	0.00	0.00
○Loop 2424 - ams.c:292-293 - exec	0.00	0.00
○Loop 2428 - ams.c:287-287 - exec	0.00	0.00
○Loop 2429 - ams.c:286-287 - exec	0.00	0.00
○Loop 2426 - ams.c:289-290 - exec	0.00	0.00
▼Loop 2373 - ams.c:70-326 - exec–	0.00	0.00
○Loop 2375 - ams.c:78-79 - exec	2.08	5.54
○Loop 2374 - ams.c:78-79 - exec	0.00	0.00
▼Loop 2398 - ams.c:149-157 - exec–	0.00	0.00
○Loop 2403 - ams.c:152-153 - exec	0.00	0.00
○Loop 2402 - ams.c:153-153 - exec	0.00	0.00
○Loop 2401 - ams.c:155-156 - exec	0.00	0.00
○Loop 2400 - ams.c:155-156 - exec	0.00	0.00
○Loop 2404 - ams.c:152-153 - exec	0.00	0.00
○Loop 2399 - ams.c:156-156 - exec	0.00	0.00
▼Loop 2384 - ams.c:174-182 - exec–	0.00	0.00
○Loop 2389 - ams.c:177-178 - exec	0.00	0.00
○Loop 2388 - ams.c:178-178 - exec	0.00	0.00
○Loop 2390 - ams.c:177-178 - exec	0.00	0.00
○Loop 2387 - ams.c:180-181 - exec	0.00	0.00
○Loop 2386 - ams.c:180-181 - exec	0.00	0.00
○Loop 2385 - ams.c:181-181 - exec	0.00	0.00
▼Loop 2391 - ams.c:163-171 - exec–	0.00	0.00
○Loop 2395 - ams.c:167-167 - exec	0.00	0.00
○Loop 2397 - ams.c:166-167 - exec	0.00	0.00
○Loop 2392 - ams.c:170-170 - exec	0.00	0.00
○Loop 2393 - ams.c:169-170 - exec	0.00	0.00
○Loop 2396 - ams.c:166-167 - exec	0.00	0.00
○Loop 2394 - ams.c:169-170 - exec	0.00	0.00
▼Loop 2405 - ams.c:138-146 - exec–	0.00	0.00
○Loop 2407 - ams.c:144-145 - exec	0.00	0.00
○Loop 2411 - ams.c:141-142 - exec	0.00	0.00
○Loop 2410 - ams.c:141-142 - exec	0.00	0.00
○Loop 2408 - ams.c:144-145 - exec	0.00	0.00
○Loop 2409 - ams.c:142-142 - exec	0.00	0.00
○Loop 2406 - ams.c:145-145 - exec	0.00	0.00
▼Loop 2415 - ams.c:297-307 - exec–	0.00	0.00
○Loop 2420 - ams.c:301-301 - exec	0.00	0.00
○Loop 2418 - ams.c:303-304 - exec	0.00	0.00
○Loop 2422 - ams.c:300-301 - exec	0.00	0.00
○Loop 2417 - ams.c:304-304 - exec	0.00	0.00
○Loop 2421 - ams.c:300-301 - exec	0.00	0.00
○Loop 2416 - ams.c:306-307 - exec	0.00	0.00
○Loop 2419 - ams.c:303-304 - exec	0.00	0.00
▼Loop 2379 - ams.c:192-206 - exec–	0.00	0.00
○Loop 2382 - ams.c:204-205 - exec	0.00	0.00
○Loop 2380 - ams.c:205-205 - exec	0.00	0.00
○Loop 2383 - ams.c:197-201 - exec	0.00	0.00
○Loop 2381 - ams.c:204-205 - exec	0.00	0.00
▼Loop 2431 - ams.c:270-274 - exec–	0.00	0.00
○Loop 2432 - ams.c:273-274 - exec	0.00	0.00
○Loop 2433 - ams.c:273-274 - exec	0.00	0.00
○Loop 2435 - ams.c:220-221 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency