OV - exec - Function hypre_BoomerAMGCreate2ndS.omp

	Function: hypre_BoomerAMGCreate2ndS.omp_outlined.16	Module: exec	Source: par_strength.c:1668-2230 [...]	Coverage (incl. loops): 5.81% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 1668 - 2230

--------------------------------------------------------------------------------

1668: #pragma omp parallel private(i1,i2,i3,jj1,jj2,index)

1669: #endif

1670:    {

1671:       HYPRE_Int my_thread_num = hypre_GetThreadNum();

1672:

1673:       HYPRE_Int i1_begin, i1_end;

1674:       hypre_GetSimpleThreadPartition(&i1_begin, &i1_end, num_cols_diag_S);

1675:

1676:       HYPRE_Int *C_temp_diag_j = NULL, *C_temp_offd_j = NULL;

1677:       HYPRE_Int *C_temp_diag_data = NULL, *C_temp_offd_data = NULL;

1678:

1679:       if (num_paths > 1)

1680:       {

1681:          C_temp_diag_j = C_temp_diag_j_array + num_coarse*my_thread_num;

1682:          C_temp_offd_j = C_temp_offd_j_array + num_cols_offd_C*my_thread_num;

1683:

1684:          C_temp_diag_data = C_temp_diag_data_array + num_coarse*my_thread_num;

1685:          C_temp_offd_data = C_temp_offd_data_array + num_cols_offd_C*my_thread_num;

1686:       }

1687:

1688:       HYPRE_Int *S_marker = NULL, *S_marker_offd = NULL;

1689:       if (num_coarse) S_marker = S_marker_array + num_coarse*my_thread_num;

1690:       if (num_cols_offd_C) S_marker_offd = S_marker_offd_array + num_cols_offd_C*my_thread_num;

1691:       for (i1 = 0; i1 < num_coarse; i1++)

1692:       {

1693:          S_marker[i1] = -1;

1694:       }

1695:       for (i1 = 0; i1 < num_cols_offd_C; i1++)

1696:       {

1697:          S_marker_offd[i1] = -1;

[...]

1705:       HYPRE_Int num_nonzeros_diag = 0;

1706:       HYPRE_Int num_nonzeros_offd = 0;

1707:

1708:       HYPRE_Int ic_begin = num_coarse_prefix_sum[my_thread_num];

1709:       HYPRE_Int ic_end = num_coarse_prefix_sum[my_thread_num + 1];

1710:       HYPRE_Int ic;

1711:

1712:       if (num_paths == 1)

1713:       {

1714:          for (ic = ic_begin; ic < ic_end; ic++)

[...]

1720:              HYPRE_Int i1 = coarse_to_fine[ic];

1721:

1722:              HYPRE_Int jj_row_begin_diag = num_nonzeros_diag;

1723:              HYPRE_Int jj_row_begin_offd = num_nonzeros_offd;

1724:

1725:              C_diag_i[ic] = num_nonzeros_diag;

1726:              if (num_cols_offd_C)

1727:              {

1728:                 C_offd_i[ic] = num_nonzeros_offd;

1729:              }

1730:

1731:              for (jj1 = S_diag_i[i1]; jj1 < S_diag_i[i1+1]; jj1++)

1732:              {

1733:                  i2 = S_diag_j[jj1];

1734:                  if (CF_marker[i2] > 0)

1735:                  {

1736:                     index = fine_to_coarse[i2];

1737:                     if (S_marker[index] < jj_row_begin_diag)

1738:                     {

1739:                        S_marker[index] = num_nonzeros_diag;

1740:                        num_nonzeros_diag++;

1741:                     }

1742:                  }

1743:                  for (jj2 = S_diag_i[i2]; jj2 < S_diag_i[i2+1]; jj2++)

1744:                  {

1745:                     i3 = S_diag_j[jj2];

1746:                     if (CF_marker[i3] > 0)

1747:                     {

1748:                        index = fine_to_coarse[i3];

1749:                        if (index != ic && S_marker[index] < jj_row_begin_diag)

1750:                        {

1751:                           S_marker[index] = num_nonzeros_diag;

1752:                           num_nonzeros_diag++;

1753:                        }

1754:                     }

1755:                  }

1756:                  for (jj2 = S_offd_i[i2]; jj2 < S_offd_i[i2+1]; jj2++)

1757:                  {

1758:                     i3 = S_offd_j[jj2];

1759:                     if (CF_marker_offd[i3] > 0)

1760:                     {

1761:                        index = map_S_to_C[i3];

1762:                        if (S_marker_offd[index] < jj_row_begin_offd)

1763:                        {

1764:                           S_marker_offd[index] = num_nonzeros_offd;

1765:                           num_nonzeros_offd++;

1766:                        }

1767:                     }

1768:                  }

1769:              }

1770:              for (jj1 = S_offd_i[i1]; jj1 < S_offd_i[i1+1]; jj1++)

1771:              {

1772:                  i2 = S_offd_j[jj1];

1773:                  if (CF_marker_offd[i2] > 0)

1774:                  {

1775:                     index = map_S_to_C[i2];

1776:                     if (S_marker_offd[index] < jj_row_begin_offd)

1777:                     {

1778:                        S_marker_offd[index] = num_nonzeros_offd;

1779:                        num_nonzeros_offd++;

1780:                     }

1781:                  }

1782:                  for (jj2 = S_ext_diag_i[i2]; jj2 < S_ext_diag_i[i2+1]; jj2++)

1783:                  {

1784:                     i3 = S_ext_diag_j[jj2];

1785:                     if (i3 != ic && S_marker[i3] < jj_row_begin_diag)

1786:                     {

1787:                        S_marker[i3] = num_nonzeros_diag;

1788:                        num_nonzeros_diag++;

1789:                     }

1790:                  }

1791:                  for (jj2 = S_ext_offd_i[i2]; jj2 < S_ext_offd_i[i2+1]; jj2++)

1792:                  {

1793:                     i3 = S_ext_offd_j[jj2];

1794:                     if (S_marker_offd[i3] < jj_row_begin_offd)

1795:                     {

1796:                        S_marker_offd[i3] = num_nonzeros_offd;

1797:                        num_nonzeros_offd++;

[...]

1806:          for (ic = ic_begin; ic < ic_end; ic++)

[...]

1812:              HYPRE_Int i1 = coarse_to_fine[ic];

1813:

1814:              HYPRE_Int jj_row_begin_diag = jj_count_diag;

1815:              HYPRE_Int jj_row_begin_offd = jj_count_offd;

1816:

1817:              C_diag_i[ic] = num_nonzeros_diag;

1818:              if (num_cols_offd_C)

1819:              {

1820:                 C_offd_i[ic] = num_nonzeros_offd;

1821:              }

1822:

1823:              for (jj1 = S_diag_i[i1]; jj1 < S_diag_i[i1+1]; jj1++)

1824:              {

1825:                  i2 = S_diag_j[jj1];

1826:                  if (CF_marker[i2] > 0)

1827:                  {

1828:                     index = fine_to_coarse[i2];

1829:                     if (S_marker[index] < jj_row_begin_diag)

1830:                     {

1831:                        S_marker[index] = jj_count_diag;

1832:                        C_temp_diag_data[jj_count_diag - jj_row_begin_diag] = 2;

1833:                        jj_count_diag++;

1834:                     }

1835:                     else

1836:                     {

1837:                        C_temp_diag_data[S_marker[index] - jj_row_begin_diag] += 2;

1838:                     }

1839:                  }

1840:                  for (jj2 = S_diag_i[i2]; jj2 < S_diag_i[i2+1]; jj2++)

1841:                  {

1842:                     i3 = S_diag_j[jj2];

1843:                     if (CF_marker[i3] > 0 && fine_to_coarse[i3] != ic)

1844:                     {

1845:                        index = fine_to_coarse[i3];

1846:                        if (S_marker[index] < jj_row_begin_diag)

1847:                        {

1848:                           S_marker[index] = jj_count_diag;

1849:                           C_temp_diag_data[jj_count_diag - jj_row_begin_diag] = 1;

1850:                           jj_count_diag++;

1851:                        }

1852:                        else

1853:                        {

1854:                           C_temp_diag_data[S_marker[index] - jj_row_begin_diag]++;

1855:                        }

1856:                     }

1857:                  }

1858:                  for (jj2 = S_offd_i[i2]; jj2 < S_offd_i[i2+1]; jj2++)

1859:                  {

1860:                     i3 = S_offd_j[jj2];

1861:                     if (CF_marker_offd[i3] > 0)

1862:                     {

1863:                        index = map_S_to_C[i3];

1864:                        if (S_marker_offd[index] < jj_row_begin_offd)

1865:                        {

1866:                           S_marker_offd[index] = jj_count_offd;

1867:                           C_temp_offd_data[jj_count_offd - jj_row_begin_offd] = 1;

1868:                           jj_count_offd++;

1869:                        }

1870:                        else

1871:                        {

1872:                           C_temp_offd_data[S_marker_offd[index] - jj_row_begin_offd]++;

1873:                        }

1874:                     }

1875:                  }

1876:              }

1877:              for (jj1 = S_offd_i[i1]; jj1 < S_offd_i[i1+1]; jj1++)

1878:              {

1879:                  i2 = S_offd_j[jj1];

1880:                  if (CF_marker_offd[i2] > 0)

1881:                  {

1882:                     index = map_S_to_C[i2];

1883:                     if (S_marker_offd[index] < jj_row_begin_offd)

1884:                     {

1885:                        S_marker_offd[index] = jj_count_offd;

1886:                        C_temp_offd_data[jj_count_offd - jj_row_begin_offd] = 2;

1887:                        jj_count_offd++;

1888:                     }

1889:                     else

1890:                     {

1891:                        C_temp_offd_data[S_marker_offd[index] - jj_row_begin_offd] += 2;

1892:                     }

1893:                  }

1894:                  for (jj2 = S_ext_diag_i[i2]; jj2 < S_ext_diag_i[i2+1]; jj2++)

1895:                  {

1896:                     i3 = S_ext_diag_j[jj2];

1897:                     if (i3 != ic)

1898:                     {

1899:                        if (S_marker[i3] < jj_row_begin_diag)

1900:                        {

1901:                           S_marker[i3] = jj_count_diag;

1902:                           C_temp_diag_data[jj_count_diag - jj_row_begin_diag] = 1;

1903:                           jj_count_diag++;

1904:                        }

1905:                        else

1906:                        {

1907:                           C_temp_diag_data[S_marker[i3] - jj_row_begin_diag]++;

1908:                        }

1909:                     }

1910:                  }

1911:                  for (jj2 = S_ext_offd_i[i2]; jj2 < S_ext_offd_i[i2+1]; jj2++)

1912:                  {

1913:                     i3 = S_ext_offd_j[jj2];

1914:                     if (S_marker_offd[i3] < jj_row_begin_offd)

1915:                     {

1916:                        S_marker_offd[i3] = jj_count_offd;

1917:                        C_temp_offd_data[jj_count_offd - jj_row_begin_offd] = 1;

1918:                        jj_count_offd++;

1919:                     }

1920:                     else

1921:                     {

1922:                        C_temp_offd_data[S_marker_offd[i3] - jj_row_begin_offd]++;

1923:                     }

1924:                  }

1925:              }

1926:

1927:              for (jj1 = jj_row_begin_diag; jj1 < jj_count_diag; jj1++)

1928:              {

1929:                  if (C_temp_diag_data[jj1 - jj_row_begin_diag] >= num_paths)

1930:                  {

1931:                     ++num_nonzeros_diag;

1932:                  }

1933:                  C_temp_diag_data[jj1 - jj_row_begin_diag] = 0;

1934:              }

1935:              for (jj1 = jj_row_begin_offd; jj1 < jj_count_offd; jj1++)

1936:              {

1937:                  if (C_temp_offd_data[jj1 - jj_row_begin_offd] >= num_paths)

1938:                  {

1939:                     ++num_nonzeros_offd;

1940:                  }

1941:                  C_temp_offd_data[jj1 - jj_row_begin_offd] = 0;

1942:              }

1943:          } /* for each row */

1944:       } /* num_paths > 1 */

1945:

1946:       hypre_prefix_sum_pair(

1947:          &num_nonzeros_diag, &C_diag_i[num_coarse],

1948:          &num_nonzeros_offd, &C_offd_i[num_coarse],

1949:          prefix_sum_workspace);

1950:

1951:       for (i1 = 0; i1 < num_coarse; i1++)

1952:       {

1953:          S_marker[i1] = -1;

1954:       }

1955:       for (i1 = 0; i1 < num_cols_offd_C; i1++)

1956:       {

1957:          S_marker_offd[i1] = -1;

1958:       }

1959:

1960: #ifdef HYPRE_USING_OPENMP

1961: #pragma omp barrier

1962: #pragma omp master

1963: #endif

1964:       {

1965:          if (C_diag_i[num_coarse])

1966:          {

1967:             C_diag_j = hypre_TAlloc(HYPRE_Int, C_diag_i[num_coarse]);

1968:          }

1969:          if (C_offd_i[num_coarse])

1970:          {

1971:             C_offd_j = hypre_TAlloc(HYPRE_Int, C_offd_i[num_coarse]);

1972:          }

1973:       }

1974: #ifdef HYPRE_USING_OPENMP

1975: #pragma omp barrier

1976: #endif

1977:

1978:       for (ic = ic_begin; ic < ic_end - 1; ic++)

1979:       {

1980:          if (C_diag_i[ic+1] == C_diag_i[ic] && C_offd_i[ic+1] == C_offd_i[ic])

1981:             CF_marker[coarse_to_fine[ic]] = 2;

1982:

1983:          C_diag_i[ic] += num_nonzeros_diag;

1984:          C_offd_i[ic] += num_nonzeros_offd;

1985:       }

1986:       if (ic_begin < ic_end)

1987:       {

1988:          C_diag_i[ic] += num_nonzeros_diag;

1989:          C_offd_i[ic] += num_nonzeros_offd;

1990:

1991:          HYPRE_Int next_C_diag_i = prefix_sum_workspace[2*(my_thread_num + 1)];

1992:          HYPRE_Int next_C_offd_i = prefix_sum_workspace[2*(my_thread_num + 1) + 1];

1993:

1994:          if (next_C_diag_i == C_diag_i[ic] && next_C_offd_i == C_offd_i[ic])

1995:             CF_marker[coarse_to_fine[ic]] = 2;

1996:       }

1997:

1998:       if (num_paths == 1)

1999:       {

2000:          for (ic = ic_begin; ic < ic_end; ic++)

[...]

2006:              HYPRE_Int i1 = coarse_to_fine[ic];

2007:

2008:              HYPRE_Int jj_row_begin_diag = num_nonzeros_diag;

2009:              HYPRE_Int jj_row_begin_offd = num_nonzeros_offd;

2010:

2011:              for (jj1 = S_diag_i[i1]; jj1 < S_diag_i[i1+1]; jj1++)

2012:              {

2013:                  i2 = S_diag_j[jj1];

2014:                  if (CF_marker[i2] > 0)

2015:                  {

2016:                     index = fine_to_coarse[i2];

2017:                     if (S_marker[index] < jj_row_begin_diag)

2018:                     {

2019:                        S_marker[index] = num_nonzeros_diag;

2020:                        C_diag_j[num_nonzeros_diag] = index;

2021:                        num_nonzeros_diag++;

2022:                     }

2023:                  }

2024:                  for (jj2 = S_diag_i[i2]; jj2 < S_diag_i[i2+1]; jj2++)

2025:                  {

2026:                     i3 = S_diag_j[jj2];

2027:                     if (CF_marker[i3] > 0)

2028:                     {

2029:                        index = fine_to_coarse[i3];

2030:                        if (index != ic && S_marker[index] < jj_row_begin_diag)

2031:                        {

2032:                           S_marker[index] = num_nonzeros_diag;

2033:                           C_diag_j[num_nonzeros_diag] = index;

2034:                           num_nonzeros_diag++;

2035:                        }

2036:                     }

2037:                  }

2038:                  for (jj2 = S_offd_i[i2]; jj2 < S_offd_i[i2+1]; jj2++)

2039:                  {

2040:                     i3 = S_offd_j[jj2];

2041:                     if (CF_marker_offd[i3] > 0)

2042:                     {

2043:                        index = map_S_to_C[i3];

2044:                        if (S_marker_offd[index] < jj_row_begin_offd)

2045:                        {

2046:                           S_marker_offd[index] = num_nonzeros_offd;

2047:                           C_offd_j[num_nonzeros_offd] = index;

2048:                           num_nonzeros_offd++;

2049:                        }

2050:                     }

2051:                  }

2052:              }

2053:              for (jj1 = S_offd_i[i1]; jj1 < S_offd_i[i1+1]; jj1++)

2054:              {

2055:                  i2 = S_offd_j[jj1];

2056:                  if (CF_marker_offd[i2] > 0)

2057:                  {

2058:                     index = map_S_to_C[i2];

2059:                     if (S_marker_offd[index] < jj_row_begin_offd)

2060:                     {

2061:                        S_marker_offd[index] = num_nonzeros_offd;

2062:                        C_offd_j[num_nonzeros_offd] = index;

2063:                        num_nonzeros_offd++;

2064:                     }

2065:                  }

2066:                  for (jj2 = S_ext_diag_i[i2]; jj2 < S_ext_diag_i[i2+1]; jj2++)

2067:                  {

2068:                     i3 = S_ext_diag_j[jj2];

2069:                     if (i3 != ic && S_marker[i3] < jj_row_begin_diag)

2070:                     {

2071:                        S_marker[i3] = num_nonzeros_diag;

2072:                        C_diag_j[num_nonzeros_diag] = i3;

2073:                        num_nonzeros_diag++;

2074:                     }

2075:                  }

2076:                  for (jj2 = S_ext_offd_i[i2]; jj2 < S_ext_offd_i[i2+1]; jj2++)

2077:                  {

2078:                     i3 = S_ext_offd_j[jj2];

2079:                     if (S_marker_offd[i3] < jj_row_begin_offd)

2080:                     {

2081:                        S_marker_offd[i3] = num_nonzeros_offd;

2082:                        C_offd_j[num_nonzeros_offd] = i3;

2083:                        num_nonzeros_offd++;

[...]

2093:          jj_count_offd = num_nonzeros_offd;

2094:

2095:          for (ic = ic_begin; ic < ic_end; ic++)

[...]

2101:              HYPRE_Int i1 = coarse_to_fine[ic];

2102:

2103:              HYPRE_Int jj_row_begin_diag = jj_count_diag;

2104:              HYPRE_Int jj_row_begin_offd = jj_count_offd;

2105:

2106:              for (jj1 = S_diag_i[i1]; jj1 < S_diag_i[i1+1]; jj1++)

2107:              {

2108:                  i2 = S_diag_j[jj1];

2109:                  if (CF_marker[i2] > 0)

2110:                  {

2111:                     index = fine_to_coarse[i2];

2112:                     if (S_marker[index] < jj_row_begin_diag)

2113:                     {

2114:                        S_marker[index] = jj_count_diag;

2115:                        C_temp_diag_j[jj_count_diag - jj_row_begin_diag] = index;

2116:                        C_temp_diag_data[jj_count_diag - jj_row_begin_diag] = 2;

2117:                        jj_count_diag++;

2118:                     }

2119:                     else

2120:                     {

2121:                        C_temp_diag_data[S_marker[index] - jj_row_begin_diag] += 2;

2122:                     }

2123:                  }

2124:                  for (jj2 = S_diag_i[i2]; jj2 < S_diag_i[i2+1]; jj2++)

2125:                  {

2126:                     i3 = S_diag_j[jj2];

2127:                     if (CF_marker[i3] > 0 && fine_to_coarse[i3] != ic)

2128:                     {

2129:                        index = fine_to_coarse[i3];

2130:                        if (S_marker[index] < jj_row_begin_diag)

2131:                        {

2132:                           S_marker[index] = jj_count_diag;

2133:                           C_temp_diag_j[jj_count_diag - jj_row_begin_diag] = index;

2134:                           C_temp_diag_data[jj_count_diag - jj_row_begin_diag] = 1;

2135:                           jj_count_diag++;

2136:                        }

2137:                        else

2138:                        {

2139:                           C_temp_diag_data[S_marker[index] - jj_row_begin_diag]++;

2140:                        }

2141:                     }

2142:                  }

2143:                  for (jj2 = S_offd_i[i2]; jj2 < S_offd_i[i2+1]; jj2++)

2144:                  {

2145:                     i3 = S_offd_j[jj2];

2146:                     if (CF_marker_offd[i3] > 0)

2147:                     {

2148:                        index = map_S_to_C[i3];

2149:                        if (S_marker_offd[index] < jj_row_begin_offd)

2150:                        {

2151:                           S_marker_offd[index] = jj_count_offd;

2152:                           C_temp_offd_j[jj_count_offd - jj_row_begin_offd] = index;

2153:                           C_temp_offd_data[jj_count_offd - jj_row_begin_offd] = 1;

2154:                           jj_count_offd++;

2155:                        }

2156:                        else

2157:                        {

2158:                           C_temp_offd_data[S_marker_offd[index] - jj_row_begin_offd]++;

2159:                        }

2160:                     }

2161:                  }

2162:              }

2163:              for (jj1 = S_offd_i[i1]; jj1 < S_offd_i[i1+1]; jj1++)

2164:              {

2165:                  i2 = S_offd_j[jj1];

2166:                  if (CF_marker_offd[i2] > 0)

2167:                  {

2168:                     index = map_S_to_C[i2];

2169:                     if (S_marker_offd[index] < jj_row_begin_offd)

2170:                     {

2171:                        S_marker_offd[index] = jj_count_offd;

2172:                        C_temp_offd_j[jj_count_offd - jj_row_begin_offd] = index;

2173:                        C_temp_offd_data[jj_count_offd - jj_row_begin_offd] = 2;

2174:                        jj_count_offd++;

2175:                     }

2176:                     else

2177:                     {

2178:                        C_temp_offd_data[S_marker_offd[index] - jj_row_begin_offd] += 2;

2179:                     }

2180:                  }

2181:                  for (jj2 = S_ext_diag_i[i2]; jj2 < S_ext_diag_i[i2+1]; jj2++)

2182:                  {

2183:                     i3 = S_ext_diag_j[jj2];

2184:                     if (i3 != ic)

2185:                     {

2186:                        if (S_marker[i3] < jj_row_begin_diag)

2187:                        {

2188:                           S_marker[i3] = jj_count_diag;

2189:                           C_temp_diag_j[jj_count_diag - jj_row_begin_diag] = i3;

2190:                           C_temp_diag_data[jj_count_diag - jj_row_begin_diag] = 1;

2191:                           jj_count_diag++;

2192:                        }

2193:                        else

2194:                        {

2195:                           C_temp_diag_data[S_marker[i3] - jj_row_begin_diag]++;

2196:                        }

2197:                     }

2198:                  }

2199:                  for (jj2 = S_ext_offd_i[i2]; jj2 < S_ext_offd_i[i2+1]; jj2++)

2200:                  {

2201:                     i3 = S_ext_offd_j[jj2];

2202:                     if (S_marker_offd[i3] < jj_row_begin_offd)

2203:                     {

2204:                        S_marker_offd[i3] = jj_count_offd;

2205:                        C_temp_offd_j[jj_count_offd - jj_row_begin_offd] = i3;

2206:                        C_temp_offd_data[jj_count_offd - jj_row_begin_offd] = 1;

2207:                        jj_count_offd++;

2208:                     }

2209:                     else

2210:                     {

2211:                        C_temp_offd_data[S_marker_offd[i3] - jj_row_begin_offd]++;

2212:                     }

2213:                  }

2214:              }

2215:

2216:              for (jj1 = jj_row_begin_diag; jj1 < jj_count_diag; jj1++)

2217:              {

2218:                  if (C_temp_diag_data[jj1 - jj_row_begin_diag] >= num_paths)

2219:                  {

2220:                     C_diag_j[num_nonzeros_diag++] = C_temp_diag_j[jj1 - jj_row_begin_diag];

2221:                  }

2222:                  C_temp_diag_data[jj1 - jj_row_begin_diag] = 0;

2223:              }

2224:              for (jj1 = jj_row_begin_offd; jj1 < jj_count_offd; jj1++)

2225:              {

2226:                  if (C_temp_offd_data[jj1 - jj_row_begin_offd] >= num_paths)

2227:                  {

2228:                     C_offd_j[num_nonzeros_offd++] = C_temp_offd_j[jj1 - jj_row_begin_offd];

2229:                  }

2230:                  C_temp_offd_data[jj1 - jj_row_begin_offd] = 0;

0x468a40 SUB	SP, SP, #384

0x468a44 STP	X29, X30, [SP, #288]

0x468a48 STP	X28, X27, [SP, #304]

0x468a4c STP	X26, X25, [SP, #320]

0x468a50 STP	X24, X23, [SP, #336]

0x468a54 STP	X22, X21, [SP, #352]

0x468a58 STP	X20, X19, [SP, #368]

0x468a5c ADD	X29, SP, #288

0x468a60 LDP	X27, X22, [X29, #112]

0x468a64 ORR	X21, XZR, X7

0x468a68 ORR	X24, XZR, X6

0x468a6c ORR	X20, XZR, X5

0x468a70 ORR	X25, XZR, X4

0x468a74 ORR	X19, XZR, X3

0x468a78 ORR	X26, XZR, X2

0x468a7c STR	X0, [SP, #56]

0x468a80 BL	4a8a10

0x468a84 LDR	X2, [X26]

0x468a88 ORR	X28, XZR, X0

0x468a8c SUB	X0, X29, #16

0x468a90 SUB	X1, X29, #24

0x468a94 BL	4a8a30

0x468a98 LDR	X10, [X20]

0x468a9c LDR	X8, [X19]

0x468aa0 LDR	X9, [X21]

0x468aa4 ORR	X15, XZR, X20

0x468aa8 MADD	X11, X10, X28, XZR

0x468aac STUR	X21, [X29, #416]

0x468ab0 CMP	X8, #1

0x468ab4 B.LE	468ae4

0x468ab8 LDP	X13, X8, [X29, #96]

0x468abc LDR	X12, [X25]

0x468ac0 LDR	X14, [X24]

0x468ac4 ADD	X26, X12, X11,LSL #3

0x468ac8 LDR	X13, [X13]

0x468acc LDR	X8, [X8]

0x468ad0 MADD	X12, X9, X28, XZR

0x468ad4 ADD	X23, X14, X12,LSL #3

0x468ad8 ADD	X20, X13, X11,LSL #3

0x468adc ADD	X21, X8, X12,LSL #3

0x468ae0 B	468af8

0x468ae4 ORR	X21, XZR, XZR

0x468ae8 ORR	X20, XZR, XZR

0x468aec ORR	X23, XZR, XZR

0x468af0 ORR	X26, XZR, XZR

0x468af4 MADD	X12, X9, X28, XZR

0x468af8 LDR	X13, [X27]

0x468afc CMP	X10, #0

0x468b00 LDR	X14, [X29, #144]

0x468b04 LDR	X8, [X29, #128]

0x468b08 ADD	X11, X13, X11,LSL #3

0x468b0c CSEL	X24, XZR, X11, #0

0x468b10 LDR	X11, [X22]

0x468b14 CMP	X9, #0

0x468b18 ADD	X11, X11, X12,LSL #3

0x468b1c CSEL	X25, XZR, X11, #0

0x468b20 CMP	X10, #1

0x468b24 B.LT	468b5c

0x468b28 LDUR	X27, [X29, #416]

0x468b2c MOVN	X10, #0

0x468b30 ORR	X9, XZR, XZR

0x468b34 HINT	#0

0x468b38 HINT	#0

0x468b3c HINT	#0

(2230) 0x468b40 STR	X10, [X24, X9,LSL #3]

(2230) 0x468b44 ADD	X9, X9, #1

(2230) 0x468b48 LDR	X11, [X15]

(2230) 0x468b4c CMP	X9, X11

(2230) 0x468b50 B.LT	468b40

0x468b54 LDR	X9, [X27]

0x468b58 B	468b60

0x468b5c LDUR	X27, [X29, #416]

0x468b60 LDR	X10, [X29, #256]

0x468b64 STR	X15, [SP, #104]

0x468b68 STR	X10, [SP, #96]

0x468b6c LDP	X10, X11, [X29, #240]

0x468b70 STR	X10, [SP, #48]

0x468b74 LDR	X10, [X29, #232]

0x468b78 STUR	X11, [X29, #376]

0x468b7c STR	X10, [SP, #144]

0x468b80 LDR	X10, [X29, #224]

0x468b84 STR	X10, [SP, #40]

0x468b88 LDP	X10, X11, [X29, #208]

0x468b8c STUR	X11, [X29, #464]

0x468b90 STUR	X10, [X29, #392]

0x468b94 LDP	X10, X11, [X29, #192]

0x468b98 STUR	X11, [X29, #384]

0x468b9c STR	X10, [SP, #32]

0x468ba0 LDP	X10, X11, [X29, #176]

0x468ba4 STR	X10, [SP, #88]

0x468ba8 LDR	X10, [X29, #168]

0x468bac STUR	X11, [X29, #456]

0x468bb0 STR	X10, [SP, #24]

0x468bb4 LDR	X10, [X29, #160]

0x468bb8 STR	X10, [SP, #16]

0x468bbc LDR	X10, [X29, #152]

0x468bc0 STR	X10, [SP, #120]

0x468bc4 LDR	X10, [X29, #136]

0x468bc8 STR	X10, [SP, #80]

0x468bcc CMP	X9, #1

0x468bd0 B.LT	468bf4

0x468bd4 MOVN	X10, #0

0x468bd8 ORR	X9, XZR, XZR

0x468bdc HINT	#0

(2229) 0x468be0 STR	X10, [X25, X9,LSL #3]

(2229) 0x468be4 ADD	X9, X9, #1

(2229) 0x468be8 LDR	X11, [X27]

(2229) 0x468bec CMP	X9, X11

(2229) 0x468bf0 B.LT	468be0

0x468bf4 LDR	X8, [X8]

0x468bf8 STP	XZR, XZR, [X29, #984]

0x468bfc ADD	X9, X28, #1

0x468c00 LDR	X10, [X14]

0x468c04 STUR	X19, [X29, #448]

0x468c08 STR	X14, [SP, #112]

0x468c0c STR	X9, [SP, #8]

0x468c10 LDR	X22, [X8, X28,LSL #3]

0x468c14 LDR	X9, [X8, X9,LSL #3]

0x468c18 LDR	X8, [X19]

0x468c1c STUR	X10, [X29, #408]

0x468c20 STUR	X9, [X29, #424]

0x468c24 CMP	X8, #1

0x468c28 B.NE	468f20

0x468c2c CMP	X22, X9

0x468c30 B.GE	46942c

0x468c34 LDR	X8, [SP, #80]

0x468c38 ORR	X18, XZR, X22

0x468c3c LDR	X8, [X8]

0x468c40 STUR	X8, [X29, #432]

0x468c44 LDR	X8, [SP, #120]

0x468c48 LDR	X8, [X8]

0x468c4c STUR	X8, [X29, #400]

0x468c50 LDP	X9, X8, [SP, #16]

0x468c54 LDR	X12, [X8]

0x468c58 LDR	X8, [SP, #88]

0x468c5c LDR	X11, [X9]

0x468c60 LDR	X13, [X8]

0x468c64 LDR	X8, [SP, #32]

0x468c68 LDR	X14, [X8]

0x468c6c LDP	X9, X8, [X29, #896]

0x468c70 LDR	X15, [X9]

0x468c74 LDR	X16, [X8]

0x468c78 LDP	X9, X8, [SP, #40]

0x468c7c LDR	X17, [X9]

0x468c80 LDR	X0, [X8]

0x468c84 B	468c98

  (2222) 0x468c88 LDP	X27, X8, [X29, #928]

  (2222) 0x468c8c ADD	X18, X18, #1

  (2222) 0x468c90 CMP	X18, X8

  (2222) 0x468c94 B.EQ	46942c

  (2222) 0x468c98 LDUR	X8, [X29, #432]

  (2222) 0x468c9c LDP	X2, X1, [X29, #984]

  (2222) 0x468ca0 LDR	X10, [X8, X18,LSL #3]

  (2222) 0x468ca4 LDUR	X8, [X29, #408]

  (2222) 0x468ca8 STR	X1, [X8, X18,LSL #3]

  (2222) 0x468cac LDR	X9, [X27]

  (2222) 0x468cb0 CBZ	X9, 468cc0

  (2222) 0x468cb4 LDUR	X9, [X29, #472]

  (2222) 0x468cb8 LDUR	X8, [X29, #400]

  (2222) 0x468cbc STR	X9, [X8, X18,LSL #3]

  (2222) 0x468cc0 ADD	X3, X10, #1

  (2222) 0x468cc4 LDR	X4, [X11, X10,LSL #3]

  (2222) 0x468cc8 STUR	X10, [X29, #440]

  (2222) 0x468ccc LDR	X9, [X11, X3,LSL #3]

  (2222) 0x468cd0 CMP	X4, X9

  (2222) 0x468cd4 B.GE	468e0c

  (2222) 0x468cd8 LDUR	X8, [X29, #456]

  (2222) 0x468cdc LDR	X5, [X8]

  (2222) 0x468ce0 LDP	X9, X8, [X29, #896]

  (2222) 0x468ce4 LDR	X6, [X9]

  (2222) 0x468ce8 LDR	X7, [X8]

  (2222) 0x468cec B	468d10

0x468cf0 HINT	#0

0x468cf4 HINT	#0

0x468cf8 HINT	#0

0x468cfc HINT	#0

    (2225) 0x468d00 LDR	X8, [X11, X3,LSL #3]

    (2225) 0x468d04 ADD	X4, X4, #1

    (2225) 0x468d08 CMP	X4, X8

    (2225) 0x468d0c B.GE	468e0c

    (2225) 0x468d10 LDR	X27, [X12, X4,LSL #3]

    (2225) 0x468d14 LDR	X9, [X13, X27,LSL #3]

    (2225) 0x468d18 CMP	X9, #1

    (2225) 0x468d1c B.LT	468d40

    (2225) 0x468d20 LDR	X9, [X5, X27,LSL #3]

    (2225) 0x468d24 LDR	X10, [X24, X9,LSL #3]

    (2225) 0x468d28 CMP	X10, X1

    (2225) 0x468d2c B.GE	468d40

    (2225) 0x468d30 LDUR	X10, [X29, #480]

    (2225) 0x468d34 STR	X10, [X24, X9,LSL #3]

    (2225) 0x468d38 ADD	X9, X10, #1

    (2225) 0x468d3c STUR	X9, [X29, #480]

    (2225) 0x468d40 ADD	X28, X27, #1

    (2225) 0x468d44 LDR	X30, [X11, X27,LSL #3]

    (2225) 0x468d48 LDR	X19, [X11, X28,LSL #3]

    (2225) 0x468d4c CMP	X30, X19

    (2225) 0x468d50 B.GE	468dac

    (2225) 0x468d54 LDUR	X8, [X29, #456]

    (2225) 0x468d58 LDR	X10, [X8]

    (2225) 0x468d5c B	468d6c

      (2227) 0x468d60 ADD	X30, X30, #1

      (2227) 0x468d64 CMP	X30, X19

      (2227) 0x468d68 B.GE	468dac

      (2227) 0x468d6c LDR	X9, [X12, X30,LSL #3]

      (2227) 0x468d70 LDR	X8, [X13, X9,LSL #3]

      (2227) 0x468d74 CMP	X8, #1

      (2227) 0x468d78 B.LT	468d60

      (2227) 0x468d7c LDR	X9, [X10, X9,LSL #3]

      (2227) 0x468d80 CMP	X9, X18

      (2227) 0x468d84 B.EQ	468d60

      (2227) 0x468d88 LDR	X8, [X24, X9,LSL #3]

      (2227) 0x468d8c CMP	X8, X1

      (2227) 0x468d90 B.GE	468d60

      (2227) 0x468d94 LDUR	X8, [X29, #480]

      (2227) 0x468d98 STR	X8, [X24, X9,LSL #3]

      (2227) 0x468d9c ADD	X8, X8, #1

      (2227) 0x468da0 STUR	X8, [X29, #480]

      (2227) 0x468da4 LDR	X19, [X11, X28,LSL #3]

      (2227) 0x468da8 B	468d60

    (2225) 0x468dac LDR	X19, [X14, X27,LSL #3]

    (2225) 0x468db0 LDR	X10, [X14, X28,LSL #3]

    (2225) 0x468db4 CMP	X19, X10

    (2225) 0x468db8 B.GE	468d00

    (2225) 0x468dbc LDUR	X8, [X29, #464]

    (2225) 0x468dc0 LDR	X27, [X8]

    (2225) 0x468dc4 B	468dd4

      (2226) 0x468dc8 ADD	X19, X19, #1

      (2226) 0x468dcc CMP	X19, X10

      (2226) 0x468dd0 B.GE	468d00

      (2226) 0x468dd4 LDR	X9, [X6, X19,LSL #3]

      (2226) 0x468dd8 LDR	X8, [X7, X9,LSL #3]

      (2226) 0x468ddc CMP	X8, #1

      (2226) 0x468de0 B.LT	468dc8

      (2226) 0x468de4 LDR	X9, [X27, X9,LSL #3]

      (2226) 0x468de8 LDR	X8, [X25, X9,LSL #3]

      (2226) 0x468dec CMP	X8, X2

      (2226) 0x468df0 B.GE	468dc8

      (2226) 0x468df4 LDUR	X8, [X29, #472]

      (2226) 0x468df8 STR	X8, [X25, X9,LSL #3]

      (2226) 0x468dfc ADD	X8, X8, #1

      (2226) 0x468e00 STUR	X8, [X29, #472]

      (2226) 0x468e04 LDR	X10, [X14, X28,LSL #3]

      (2226) 0x468e08 B	468dc8

  (2222) 0x468e0c LDUR	X8, [X29, #440]

  (2222) 0x468e10 LDR	X9, [X14, X3,LSL #3]

  (2222) 0x468e14 LDR	X8, [X14, X8,LSL #3]

  (2222) 0x468e18 CMP	X8, X9

  (2222) 0x468e1c B.GE	468c88

(2223) 0x468e20 LDUR	X9, [X29, #464]

(2223) 0x468e24 LDR	X4, [X9]

(2223) 0x468e28 LDR	X9, [SP, #144]

(2223) 0x468e2c LDR	X5, [X9]

(2223) 0x468e30 LDUR	X9, [X29, #376]

(2223) 0x468e34 LDR	X6, [X9]

(2223) 0x468e38 B	468e50

0x468e3c HINT	#0

(2223) 0x468e40 LDR	X9, [X14, X3,LSL #3]

(2223) 0x468e44 ADD	X8, X8, #1

(2223) 0x468e48 CMP	X8, X9

(2223) 0x468e4c B.GE	468c88

(2223) 0x468e50 LDR	X27, [X15, X8,LSL #3]

(2223) 0x468e54 LDR	X9, [X16, X27,LSL #3]

(2223) 0x468e58 CMP	X9, #1

(2223) 0x468e5c B.LT	468e80

(2223) 0x468e60 LDR	X9, [X4, X27,LSL #3]

(2223) 0x468e64 LDR	X10, [X25, X9,LSL #3]

(2223) 0x468e68 CMP	X10, X2

(2223) 0x468e6c B.GE	468e80

(2223) 0x468e70 LDUR	X10, [X29, #472]

(2223) 0x468e74 STR	X10, [X25, X9,LSL #3]

(2223) 0x468e78 ADD	X9, X10, #1

(2223) 0x468e7c STUR	X9, [X29, #472]

(2223) 0x468e80 ADD	X7, X27, #1

(2223) 0x468e84 LDR	X10, [X17, X27,LSL #3]

(2223) 0x468e88 LDR	X19, [X17, X7,LSL #3]

(2223) 0x468e8c B	468ea4

0x468e90 HINT	#0

0x468e94 HINT	#0

0x468e98 HINT	#0

0x468e9c HINT	#0

  (2224) 0x468ea0 ADD	X10, X10, #1

  (2224) 0x468ea4 CMP	X10, X19

  (2224) 0x468ea8 B.GE	468ee0

  (2224) 0x468eac LDR	X9, [X5, X10,LSL #3]

  (2224) 0x468eb0 CMP	X9, X18

  (2224) 0x468eb4 B.EQ	468ea0

  (2224) 0x468eb8 LDR	X28, [X24, X9,LSL #3]

  (2224) 0x468ebc CMP	X28, X1

  (2224) 0x468ec0 B.GE	468ea0

  (2224) 0x468ec4 LDUR	X19, [X29, #480]

  (2224) 0x468ec8 STR	X19, [X24, X9,LSL #3]

  (2224) 0x468ecc ADD	X9, X19, #1

  (2224) 0x468ed0 STUR	X9, [X29, #480]

  (2224) 0x468ed4 LDR	X19, [X17, X7,LSL #3]

  (2224) 0x468ed8 B	468ea0

0x468edc HINT	#0

(2223) 0x468ee0 LDR	X10, [X0, X27,LSL #3]

(2223) 0x468ee4 LDR	X19, [X0, X7,LSL #3]

(2223) 0x468ee8 B	468ef0

  (2228) 0x468eec ADD	X10, X10, #1

  (2228) 0x468ef0 CMP	X10, X19

  (2228) 0x468ef4 B.GE	468e40

  (2228) 0x468ef8 LDR	X9, [X6, X10,LSL #3]

  (2228) 0x468efc LDR	X27, [X25, X9,LSL #3]

  (2228) 0x468f00 CMP	X27, X2

  (2228) 0x468f04 B.GE	468eec

  (2228) 0x468f08 LDUR	X19, [X29, #472]

  (2228) 0x468f0c STR	X19, [X25, X9,LSL #3]

  (2228) 0x468f10 ADD	X9, X19, #1

  (2228) 0x468f14 STUR	X9, [X29, #472]

  (2228) 0x468f18 LDR	X19, [X0, X7,LSL #3]

  (2228) 0x468f1c B	468eec

0x468f20 CMP	X22, X9

0x468f24 B.GE	46942c

0x468f28 LDR	X8, [SP, #80]

0x468f2c MOVZ	W3, #1

0x468f30 ORR	X2, XZR, XZR

0x468f34 ORR	X4, XZR, XZR

0x468f38 ORR	X5, XZR, X22

0x468f3c LDR	X9, [X8]

0x468f40 LDR	X8, [SP, #120]

0x468f44 LDR	X8, [X8]

0x468f48 STP	X8, X9, [SP, #128]

0x468f4c LDP	X9, X8, [SP, #16]

0x468f50 LDR	X12, [X8]

0x468f54 LDR	X8, [SP, #88]

0x468f58 LDR	X11, [X9]

0x468f5c LDR	X13, [X8]

0x468f60 LDR	X8, [SP, #32]

0x468f64 LDR	X14, [X8]

0x468f68 LDUR	X8, [X29, #384]

0x468f6c LDR	X9, [X8]

0x468f70 LDUR	X8, [X29, #392]

0x468f74 LDR	X8, [X8]

0x468f78 STP	X8, X9, [X29, #944]

0x468f7c ADD	X9, X20, #8

0x468f80 ADD	X8, X21, #8

0x468f84 STP	X8, X9, [SP, #64]

0x468f88 LDP	X9, X8, [SP, #40]

0x468f8c LDR	X0, [X9]

0x468f90 LDR	X6, [X8]

0x468f94 B	468fb0

0x468f98 HINT	#0

0x468f9c HINT	#0

  (2213) 0x468fa0 LDUR	X8, [X29, #424]

  (2213) 0x468fa4 ADD	X5, X5, #1

  (2213) 0x468fa8 CMP	X5, X8

  (2213) 0x468fac B.EQ	46942c

  (2213) 0x468fb0 LDR	X8, [SP, #136]

  (2213) 0x468fb4 LDUR	X9, [X29, #408]

  (2213) 0x468fb8 ORR	X7, XZR, X4

  (2213) 0x468fbc ORR	X30, XZR, X2

  (2213) 0x468fc0 LDR	X15, [X8, X5,LSL #3]

  (2213) 0x468fc4 LDUR	X8, [X29, #480]

  (2213) 0x468fc8 STR	X8, [X9, X5,LSL #3]

  (2213) 0x468fcc LDR	X8, [X27]

  (2213) 0x468fd0 CBZ	X8, 468fe0

  (2213) 0x468fd4 LDUR	X8, [X29, #472]

  (2213) 0x468fd8 LDR	X9, [SP, #128]

  (2213) 0x468fdc STR	X8, [X9, X5,LSL #3]

  (2213) 0x468fe0 ADD	X17, X15, #1

  (2213) 0x468fe4 LDR	X10, [X11, X15,LSL #3]

  (2213) 0x468fe8 STUR	X15, [X29, #400]

  (2213) 0x468fec ORR	X4, XZR, X7

  (2213) 0x468ff0 ORR	X2, XZR, X30

  (2213) 0x468ff4 LDR	X8, [X11, X17,LSL #3]

  (2213) 0x468ff8 CMP	X10, X8

  (2213) 0x468ffc B.GE	469160

  (2213) 0x469000 LDUR	X8, [X29, #456]

  (2213) 0x469004 ORR	X2, XZR, X30

  (2213) 0x469008 ORR	X4, XZR, X7

  (2213) 0x46900c LDR	X9, [X8]

  (2213) 0x469010 LDP	X8, X15, [X29, #896]

  (2213) 0x469014 LDR	X8, [X8]

  (2213) 0x469018 LDR	X1, [X15]

  (2213) 0x46901c B	469030

    (2218) 0x469020 LDR	X15, [X11, X17,LSL #3]

    (2218) 0x469024 ADD	X10, X10, #1

    (2218) 0x469028 CMP	X10, X15

    (2218) 0x46902c B.GE	469160

    (2218) 0x469030 LDR	X27, [X12, X10,LSL #3]

    (2218) 0x469034 LDR	X15, [X13, X27,LSL #3]

    (2218) 0x469038 CMP	X15, #1

    (2218) 0x46903c B.LT	469074

    (2218) 0x469040 LDR	X15, [X9, X27,LSL #3]

    (2218) 0x469044 LDR	X16, [X24, X15,LSL #3]

    (2218) 0x469048 SUBS	X18, X16, X30

    (2218) 0x46904c B.GE	469068

    (2218) 0x469050 STR	X2, [X24, X15,LSL #3]

    (2218) 0x469054 SUB	X15, X2, X30

    (2218) 0x469058 MOVZ	W16, #2

    (2218) 0x46905c ADD	X2, X2, #1

    (2218) 0x469060 STR	X16, [X20, X15,LSL #3]

    (2218) 0x469064 B	469074

    (2218) 0x469068 LDR	X15, [X20, X18,LSL #3]

    (2218) 0x46906c ADD	X15, X15, #2

    (2218) 0x469070 STR	X15, [X20, X18,LSL #3]

    (2218) 0x469074 ADD	X28, X27, #1

    (2218) 0x469078 LDR	X18, [X11, X27,LSL #3]

    (2218) 0x46907c LDR	X15, [X11, X28,LSL #3]

    (2218) 0x469080 CMP	X18, X15

    (2218) 0x469084 B.GE	4690ec

    (2218) 0x469088 LDUR	X15, [X29, #456]

    (2218) 0x46908c LDR	X19, [X15]

    (2218) 0x469090 B	4690b0

      (2220) 0x469094 LDR	X15, [X20, X16,LSL #3]

      (2220) 0x469098 ADD	X15, X15, #1

      (2220) 0x46909c STR	X15, [X20, X16,LSL #3]

      (2220) 0x4690a0 LDR	X15, [X11, X28,LSL #3]

      (2220) 0x4690a4 ADD	X18, X18, #1

      (2220) 0x4690a8 CMP	X18, X15

      (2220) 0x4690ac B.GE	4690ec

      (2220) 0x4690b0 LDR	X15, [X12, X18,LSL #3]

      (2220) 0x4690b4 LDR	X16, [X13, X15,LSL #3]

      (2220) 0x4690b8 CMP	X16, #1

      (2220) 0x4690bc B.LT	4690a0

      (2220) 0x4690c0 LDR	X15, [X19, X15,LSL #3]

      (2220) 0x4690c4 CMP	X15, X5

      (2220) 0x4690c8 B.EQ	4690a0

      (2220) 0x4690cc LDR	X16, [X24, X15,LSL #3]

      (2220) 0x4690d0 SUBS	X16, X16, X30

      (2220) 0x4690d4 B.GE	469094

      (2220) 0x4690d8 STR	X2, [X24, X15,LSL #3]

      (2220) 0x4690dc SUB	X15, X2, X30

      (2220) 0x4690e0 ADD	X2, X2, #1

      (2220) 0x4690e4 STR	X3, [X20, X15,LSL #3]

      (2220) 0x4690e8 B	4690a0

    (2218) 0x4690ec LDR	X18, [X14, X27,LSL #3]

    (2218) 0x4690f0 LDR	X15, [X14, X28,LSL #3]

    (2218) 0x4690f4 CMP	X18, X15

    (2218) 0x4690f8 B.GE	469020

    (2218) 0x4690fc LDUR	X15, [X29, #464]

    (2218) 0x469100 LDR	X19, [X15]

    (2218) 0x469104 B	469124

      (2219) 0x469108 LDR	X15, [X21, X16,LSL #3]

      (2219) 0x46910c ADD	X15, X15, #1

      (2219) 0x469110 STR	X15, [X21, X16,LSL #3]

      (2219) 0x469114 LDR	X15, [X14, X28,LSL #3]

      (2219) 0x469118 ADD	X18, X18, #1

      (2219) 0x46911c CMP	X18, X15

      (2219) 0x469120 B.GE	469020

      (2219) 0x469124 LDR	X15, [X8, X18,LSL #3]

      (2219) 0x469128 LDR	X16, [X1, X15,LSL #3]

      (2219) 0x46912c CMP	X16, #1

      (2219) 0x469130 B.LT	469114

      (2219) 0x469134 LDR	X15, [X19, X15,LSL #3]

      (2219) 0x469138 LDR	X16, [X25, X15,LSL #3]

      (2219) 0x46913c SUBS	X16, X16, X7

      (2219) 0x469140 B.GE	469108

      (2219) 0x469144 STR	X4, [X25, X15,LSL #3]

      (2219) 0x469148 SUB	X15, X4, X7

      (2219) 0x46914c ADD	X4, X4, #1

      (2219) 0x469150 STR	X3, [X21, X15,LSL #3]

      (2219) 0x469154 B	469114

0x469158 HINT	#0

0x46915c HINT	#0

  (2213) 0x469160 LDUR	X8, [X29, #400]

  (2213) 0x469164 LDR	X9, [X14, X17,LSL #3]

  (2213) 0x469168 LDR	X8, [X14, X8,LSL #3]

  (2213) 0x46916c CMP	X8, X9

  (2213) 0x469170 B.GE	4692c4

  (2213) 0x469174 LDUR	X9, [X29, #464]

  (2213) 0x469178 LDR	X10, [SP, #144]

  (2213) 0x46917c LDUR	X15, [X29, #376]

  (2213) 0x469180 LDR	X9, [X9]

  (2213) 0x469184 LDR	X10, [X10]

  (2213) 0x469188 LDR	X18, [X15]

  (2213) 0x46918c B	4691b0

0x469190 HINT	#0

0x469194 HINT	#0

0x469198 HINT	#0

0x46919c HINT	#0

    (2215) 0x4691a0 LDR	X15, [X14, X17,LSL #3]

    (2215) 0x4691a4 ADD	X8, X8, #1

    (2215) 0x4691a8 CMP	X8, X15

    (2215) 0x4691ac B.GE	4692c4

    (2215) 0x4691b0 LDUR	X15, [X29, #440]

    (2215) 0x4691b4 LDR	X27, [X15, X8,LSL #3]

    (2215) 0x4691b8 LDUR	X15, [X29, #432]

    (2215) 0x4691bc LDR	X15, [X15, X27,LSL #3]

    (2215) 0x4691c0 CMP	X15, #1

    (2215) 0x4691c4 B.LT	46920c

    (2215) 0x4691c8 LDR	X15, [X9, X27,LSL #3]

    (2215) 0x4691cc LDR	X16, [X25, X15,LSL #3]

    (2215) 0x4691d0 SUBS	X16, X16, X7

    (2215) 0x4691d4 B.GE	469200

    (2215) 0x4691d8 STR	X4, [X25, X15,LSL #3]

    (2215) 0x4691dc SUB	X15, X4, X7

    (2215) 0x4691e0 MOVZ	W16, #2

    (2215) 0x4691e4 ADD	X4, X4, #1

    (2215) 0x4691e8 STR	X16, [X21, X15,LSL #3]

    (2215) 0x4691ec B	46920c

0x4691f0 HINT	#0

0x4691f4 HINT	#0

0x4691f8 HINT	#0

0x4691fc HINT	#0

    (2215) 0x469200 LDR	X15, [X21, X16,LSL #3]

    (2215) 0x469204 ADD	X15, X15, #2

    (2215) 0x469208 STR	X15, [X21, X16,LSL #3]

    (2215) 0x46920c LDR	X19, [X0, X27,LSL #3]

    (2215) 0x469210 ADD	X1, X27, #1

    (2215) 0x469214 B	469230

0x469218 HINT	#0

0x46921c HINT	#0

      (2217) 0x469220 LDR	X15, [X20, X16,LSL #3]

      (2217) 0x469224 ADD	X15, X15, #1

      (2217) 0x469228 STR	X15, [X20, X16,LSL #3]

      (2217) 0x46922c ADD	X19, X19, #1

      (2217) 0x469230 LDR	X15, [X0, X1,LSL #3]

      (2217) 0x469234 CMP	X19, X15

      (2217) 0x469238 B.GE	46926c

      (2217) 0x46923c LDR	X15, [X10, X19,LSL #3]

      (2217) 0x469240 CMP	X15, X5

      (2217) 0x469244 B.EQ	46922c

      (2217) 0x469248 LDR	X16, [X24, X15,LSL #3]

      (2217) 0x46924c SUBS	X16, X16, X30

      (2217) 0x469250 B.GE	469220

      (2217) 0x469254 STR	X2, [X24, X15,LSL #3]

      (2217) 0x469258 SUB	X15, X2, X30

      (2217) 0x46925c ADD	X2, X2, #1

      (2217) 0x469260 ADD	X19, X19, #1

      (2217) 0x469264 STR	X3, [X20, X15,LSL #3]

      (2217) 0x469268 B	469230

    (2215) 0x46926c LDR	X19, [X6, X27,LSL #3]

    (2215) 0x469270 B	469294

0x469274 HINT	#0

0x469278 HINT	#0

0x46927c HINT	#0

      (2216) 0x469280 STR	X4, [X25, X15,LSL #3]

      (2216) 0x469284 SUB	X15, X4, X7

      (2216) 0x469288 ADD	X4, X4, #1

      (2216) 0x46928c ADD	X19, X19, #1

      (2216) 0x469290 STR	X3, [X21, X15,LSL #3]

      (2216) 0x469294 LDR	X15, [X6, X1,LSL #3]

      (2216) 0x469298 CMP	X19, X15

      (2216) 0x46929c B.GE	4691a0

      (2216) 0x4692a0 LDR	X15, [X18, X19,LSL #3]

      (2216) 0x4692a4 LDR	X16, [X25, X15,LSL #3]

      (2216) 0x4692a8 SUBS	X16, X16, X7

      (2216) 0x4692ac B.LT	469280

      (2216) 0x4692b0 LDR	X15, [X21, X16,LSL #3]

      (2216) 0x4692b4 ADD	X19, X19, #1

      (2216) 0x4692b8 ADD	X15, X15, #1

      (2216) 0x4692bc STR	X15, [X21, X16,LSL #3]

      (2216) 0x4692c0 B	469294

  (2213) 0x4692c4 LDUR	X16, [X29, #448]

  (2213) 0x4692c8 LDUR	X27, [X29, #416]

  (2213) 0x4692cc CMP	X2, X30

  (2213) 0x4692d0 B.LE	469310

  (2213) 0x4692d4 SUB	W8, W2, W30

  (2213) 0x4692d8 ORR	X9, XZR, X30

  (2213) 0x4692dc TBZ	W8, #0, 469304

  (2213) 0x4692e0 LDR	X8, [X20]

  (2213) 0x4692e4 LDR	X9, [X16]

  (2213) 0x4692e8 CMP	X8, X9

  (2213) 0x4692ec B.LT	4692fc

  (2213) 0x4692f0 LDUR	X8, [X29, #480]

  (2213) 0x4692f4 ADD	X8, X8, #1

  (2213) 0x4692f8 STUR	X8, [X29, #480]

  (2213) 0x4692fc ADD	X9, X30, #1

  (2213) 0x469300 STR	XZR, [X20]

  (2213) 0x469304 ADD	X8, X30, #1

  (2213) 0x469308 CMP	X2, X8

  (2213) 0x46930c B.NE	4693c0

  (2213) 0x469310 CMP	X4, X7

  (2213) 0x469314 B.LE	468fa0

  (2213) 0x469318 SUB	W8, W4, W7

  (2213) 0x46931c ORR	X9, XZR, X7

  (2213) 0x469320 TBZ	W8, #0, 469348

  (2213) 0x469324 LDR	X8, [X21]

  (2213) 0x469328 LDR	X9, [X16]

  (2213) 0x46932c CMP	X8, X9

  (2213) 0x469330 B.LT	469340

  (2213) 0x469334 LDUR	X8, [X29, #472]

  (2213) 0x469338 ADD	X8, X8, #1

  (2213) 0x46933c STUR	X8, [X29, #472]

  (2213) 0x469340 ADD	X9, X7, #1

  (2213) 0x469344 STR	XZR, [X21]

  (2213) 0x469348 ADD	X8, X7, #1

  (2213) 0x46934c CMP	X4, X8

  (2213) 0x469350 B.EQ	468fa0

  (2213) 0x469354 LDR	X10, [SP, #64]

  (2213) 0x469358 SUB	X8, X4, X9

  (2213) 0x46935c SUB	X10, X10, X7,LSL #3

  (2213) 0x469360 ADD	X9, X10, X9,LSL #3

  (2213) 0x469364 B	469374

    (2221) 0x469368 STR	XZR, [X9], #16

    (2221) 0x46936c SUBS	X8, X8, #2

    (2221) 0x469370 B.EQ	468fa0

    (2221) 0x469374 LDUR	X10, [X9, #504]

    (2221) 0x469378 LDR	X15, [X16]

    (2221) 0x46937c CMP	X10, X15

    (2221) 0x469380 B.LT	469390

    (2221) 0x469384 LDUR	X10, [X29, #472]

    (2221) 0x469388 ADD	X10, X10, #1

    (2221) 0x46938c STUR	X10, [X29, #472]

    (2221) 0x469390 STUR	XZR, [X9, #504]

    (2221) 0x469394 LDR	X10, [X9]

    (2221) 0x469398 LDR	X15, [X16]

    (2221) 0x46939c CMP	X10, X15

    (2221) 0x4693a0 B.LT	469368

    (2221) 0x4693a4 LDUR	X10, [X29, #472]

    (2221) 0x4693a8 ADD	X10, X10, #1

    (2221) 0x4693ac STUR	X10, [X29, #472]

    (2221) 0x4693b0 B	469368

0x4693b4 HINT	#0

0x4693b8 HINT	#0

0x4693bc HINT	#0

(2214) 0x4693c0 LDR	X10, [SP, #72]

(2214) 0x4693c4 SUB	X8, X2, X9

(2214) 0x4693c8 SUB	X10, X10, X30,LSL #3

(2214) 0x4693cc ADD	X9, X10, X9,LSL #3

(2214) 0x4693d0 B	4693ec

0x4693d4 HINT	#0

0x4693d8 HINT	#0

0x4693dc HINT	#0

(2214) 0x4693e0 STR	XZR, [X9], #16

(2214) 0x4693e4 SUBS	X8, X8, #2

(2214) 0x4693e8 B.EQ	469310

(2214) 0x4693ec LDUR	X10, [X9, #504]

(2214) 0x4693f0 LDR	X15, [X16]

(2214) 0x4693f4 CMP	X10, X15

(2214) 0x4693f8 B.LT	469408

(2214) 0x4693fc LDUR	X10, [X29, #480]

(2214) 0x469400 ADD	X10, X10, #1

(2214) 0x469404 STUR	X10, [X29, #480]

(2214) 0x469408 STUR	XZR, [X9, #504]

(2214) 0x46940c LDR	X10, [X9]

(2214) 0x469410 LDR	X15, [X16]

(2214) 0x469414 CMP	X10, X15

(2214) 0x469418 B.LT	4693e0

(2214) 0x46941c LDUR	X10, [X29, #480]

(2214) 0x469420 ADD	X10, X10, #1

(2214) 0x469424 STUR	X10, [X29, #480]

(2214) 0x469428 B	4693e0

0x46942c LDP	X10, X19, [SP, #96]

0x469430 LDR	X9, [SP, #120]

0x469434 SUB	X0, X29, #32

0x469438 SUB	X2, X29, #40

0x46943c LDR	X8, [X19]

0x469440 LDR	X9, [X9]

0x469444 LDR	X4, [X10]

0x469448 LDUR	X10, [X29, #408]

0x46944c ADD	X1, X10, X8,LSL #3

0x469450 ADD	X3, X9, X8,LSL #3

0x469454 BL	4a95f0

0x469458 LDR	X8, [X19]

0x46945c CMP	X8, #1

0x469460 B.LT	469494

0x469464 MOVN	X9, #0

0x469468 ORR	X11, XZR, X19

0x46946c ORR	X8, XZR, XZR

0x469470 HINT	#0

0x469474 HINT	#0

0x469478 HINT	#0

0x46947c HINT	#0

(2212) 0x469480 STR	X9, [X24, X8,LSL #3]

(2212) 0x469484 ADD	X8, X8, #1

(2212) 0x469488 LDR	X10, [X11]

(2212) 0x46948c CMP	X8, X10

(2212) 0x469490 B.LT	469480

0x469494 LDP	X8, X9, [X29, #264]

0x469498 STUR	X8, [X29, #440]

0x46949c LDR	X8, [X27]

0x4694a0 STUR	X9, [X29, #408]

0x4694a4 CMP	X8, #1

0x4694a8 B.LT	4694d4

0x4694ac MOVN	X9, #0

0x4694b0 ORR	X8, XZR, XZR

0x4694b4 HINT	#0

0x4694b8 HINT	#0

0x4694bc HINT	#0

(2211) 0x4694c0 STR	X9, [X25, X8,LSL #3]

(2211) 0x4694c4 ADD	X8, X8, #1

(2211) 0x4694c8 LDR	X10, [X27]

(2211) 0x4694cc CMP	X8, X10

(2211) 0x4694d0 B.LT	4694c0

0x4694d4 LDR	X8, [SP, #56]

0x4694d8 ADRP	X0,

0x4694dc ADD	X0, X0, #560

0x4694e0 LDR	W27, [X8]

0x4694e4 ORR	W1, WZR, W27

0x4694e8 BL	40f440

0x4694ec ADRP	X0,

0x4694f0 ADD	X0, X0, #584

0x4694f4 ORR	W1, WZR, W27

0x4694f8 BL	40f970

0x4694fc CBZ	W0, 46955c

0x469500 LDP	X10, X8, [SP, #104]

0x469504 LDR	X9, [X8]

0x469508 LDR	X8, [X10]

0x46950c LDR	X9, [X9, X8,LSL #3]

0x469510 CBZ	X9, 46952c

0x469514 UBFM	X0, X9, #61, #60

0x469518 ORR	X19, XZR, X10

0x46951c BL	4a6c20

0x469520 LDUR	X8, [X29, #440]

0x469524 STR	X0, [X8]

0x469528 LDR	X8, [X19]

0x46952c LDR	X9, [SP, #120]

0x469530 LDR	X9, [X9]

0x469534 LDR	X8, [X9, X8,LSL #3]

0x469538 CBZ	X8, 46954c

0x46953c UBFM	X0, X8, #61, #60

0x469540 BL	4a6c20

0x469544 LDUR	X8, [X29, #408]

0x469548 STR	X0, [X8]

0x46954c ADRP	X0,

0x469550 ADD	X0, X0, #584

0x469554 ORR	W1, WZR, W27

0x469558 BL	40f8a0

0x46955c ADRP	X0,

0x469560 ADD	X0, X0, #608

0x469564 ORR	W1, WZR, W27

0x469568 BL	40f440

0x46956c LDUR	X0, [X29, #424]

0x469570 LDR	X1, [SP, #112]

0x469574 LDUR	X30, [X29, #408]

0x469578 ORR	X9, XZR, X22

0x46957c SUB	X8, X0, #1

0x469580 CMP	X22, X8

0x469584 B.GE	469618

0x469588 LDR	X9, [SP, #120]

0x46958c LDR	X13, [X1]

0x469590 MOVZ	W14, #2

0x469594 LDR	X12, [X9]

0x469598 LDP	X10, X9, [SP, #80]

0x46959c ADD	X13, X13, X22,LSL #3

0x4695a0 LDR	X11, [X10]

0x4695a4 LDR	X9, [X9]

0x4695a8 ORN	X10, XZR, X22

0x4695ac ADD	X12, X12, X22,LSL #3

0x4695b0 ADD	X10, X10, X0

0x4695b4 ADD	X11, X11, X22,LSL #3

0x4695b8 B	4695e8

0x4695bc HINT	#0

(2210) 0x4695c0 LDUR	X16, [X29, #480]

(2210) 0x4695c4 SUBS	X10, X10, #1

(2210) 0x4695c8 ADD	X11, X11, #8

(2210) 0x4695cc ADD	X15, X15, X16

(2210) 0x4695d0 STR	X15, [X13], #8

(2210) 0x4695d4 LDUR	X15, [X29, #472]

(2210) 0x4695d8 LDR	X16, [X12]

(2210) 0x4695dc ADD	X15, X16, X15

(2210) 0x4695e0 STR	X15, [X12], #8

(2210) 0x4695e4 B.EQ	469614

(2210) 0x4695e8 LDP	X15, X16, [X13]

(2210) 0x4695ec CMP	X16, X15

(2210) 0x4695f0 B.NE	4695c0

(2210) 0x4695f4 LDP	X18, X17, [X12]

(2210) 0x4695f8 ORR	X15, XZR, X16

(2210) 0x4695fc CMP	X17, X18

(2210) 0x469600 B.NE	4695c0

(2210) 0x469604 LDR	X15, [X11]

(2210) 0x469608 STR	X14, [X9, X15,LSL #3]

(2210) 0x46960c LDR	X15, [X13]

(2210) 0x469610 B	4695c0

0x469614 ORR	X9, XZR, X8

0x469618 CMP	X22, X0

0x46961c B.GE	469f28

0x469620 LDR	X11, [X1]

0x469624 LDUR	X8, [X29, #480]

0x469628 LDR	X13, [SP, #8]

0x46962c LDR	X10, [X11, X9,LSL #3]

0x469630 ADD	X8, X10, X8

0x469634 LDR	X10, [SP, #120]

0x469638 STR	X8, [X11, X9,LSL #3]

0x46963c LDUR	X8, [X29, #472]

0x469640 LDR	X10, [X10]

0x469644 LDR	X12, [X10, X9,LSL #3]

0x469648 ADD	X8, X12, X8

0x46964c UBFM	X12, X13, #60, #59

0x469650 STR	X8, [X10, X9,LSL #3]

0x469654 LDR	X10, [SP, #96]

0x469658 LDR	X11, [X11, X9,LSL #3]

0x46965c LDR	X10, [X10]

0x469660 LDR	X12, [X10, X12]

0x469664 CMP	X12, X11

0x469668 B.NE	469698

0x46966c UBFM	X11, X13, #63, #62

0x469670 ADD	X10, X10, X11,LSL #3

0x469674 LDR	X10, [X10, #8]

0x469678 CMP	X10, X8

0x46967c B.NE	469698

0x469680 LDP	X10, X8, [SP, #80]

0x469684 LDR	X10, [X10]

0x469688 LDR	X8, [X8]

0x46968c LDR	X9, [X10, X9,LSL #3]

0x469690 MOVZ	W10, #2

0x469694 STR	X10, [X8, X9,LSL #3]

0x469698 LDUR	X8, [X29, #448]

0x46969c LDR	X8, [X8]

0x4696a0 CMP	X8, #1

0x4696a4 B.NE	4699c0

0x4696a8 CMP	X22, X0

0x4696ac B.GE	469f28

0x4696b0 LDP	X8, X11, [SP, #80]

0x4696b4 LDP	X9, X10, [SP, #16]

0x4696b8 LDP	X12, X15, [SP, #32]

0x4696bc LDP	X13, X14, [X29, #896]

0x4696c0 LDR	X16, [SP, #48]

0x4696c4 LDR	X8, [X8]

0x4696c8 LDR	X9, [X9]

0x4696cc LDR	X10, [X10]

0x4696d0 LDR	X11, [X11]

0x4696d4 LDR	X12, [X12]

0x4696d8 LDR	X13, [X13]

0x4696dc LDR	X14, [X14]

0x4696e0 LDR	X15, [X15]

0x4696e4 LDR	X16, [X16]

0x4696e8 B	4696fc

  (2203) 0x4696ec LDUR	X17, [X29, #424]

  (2203) 0x4696f0 ADD	X22, X22, #1

  (2203) 0x4696f4 CMP	X22, X17

  (2203) 0x4696f8 B.EQ	469f28

  (2203) 0x4696fc LDR	X1, [X8, X22,LSL #3]

  (2203) 0x469700 LDP	X18, X17, [X29, #984]

  (2203) 0x469704 ADD	X0, X1, #1

  (2203) 0x469708 LDR	X2, [X9, X1,LSL #3]

  (2203) 0x46970c LDR	X3, [X9, X0,LSL #3]

  (2203) 0x469710 CMP	X2, X3

  (2203) 0x469714 B.GE	46988c

  (2203) 0x469718 LDUR	X3, [X29, #456]

  (2203) 0x46971c LDUR	X4, [X29, #440]

  (2203) 0x469720 LDP	X5, X6, [X29, #896]

  (2203) 0x469724 LDR	X3, [X3]

  (2203) 0x469728 LDR	X4, [X4]

  (2203) 0x46972c LDR	X5, [X5]

  (2203) 0x469730 LDR	X6, [X6]

  (2203) 0x469734 B	469750

0x469738 HINT	#0

0x46973c HINT	#0

    (2207) 0x469740 LDR	X7, [X9, X0,LSL #3]

    (2207) 0x469744 ADD	X2, X2, #1

    (2207) 0x469748 CMP	X2, X7

    (2207) 0x46974c B.GE	46988c

    (2207) 0x469750 LDR	X19, [X10, X2,LSL #3]

    (2207) 0x469754 LDR	X7, [X11, X19,LSL #3]

    (2207) 0x469758 CMP	X7, #1

    (2207) 0x46975c B.LT	469788

    (2207) 0x469760 LDR	X7, [X3, X19,LSL #3]

    (2207) 0x469764 LDR	X20, [X24, X7,LSL #3]

    (2207) 0x469768 CMP	X20, X17

    (2207) 0x46976c B.GE	469788

    (2207) 0x469770 LDUR	X20, [X29, #480]

    (2207) 0x469774 STR	X20, [X24, X7,LSL #3]

    (2207) 0x469778 STR	X7, [X4, X20,LSL #3]

    (2207) 0x46977c LDUR	X7, [X29, #480]

    (2207) 0x469780 ADD	X7, X7, #1

    (2207) 0x469784 STUR	X7, [X29, #480]

    (2207) 0x469788 ADD	X7, X19, #1

    (2207) 0x46978c LDR	X20, [X9, X19,LSL #3]

    (2207) 0x469790 LDR	X23, [X9, X7,LSL #3]

    (2207) 0x469794 CMP	X20, X23

    (2207) 0x469798 B.GE	469820

    (2207) 0x46979c LDUR	X21, [X29, #456]

    (2207) 0x4697a0 LDUR	X26, [X29, #440]

    (2207) 0x4697a4 LDR	X21, [X21]

    (2207) 0x4697a8 LDR	X26, [X26]

    (2207) 0x4697ac B	4697cc

0x4697b0 HINT	#0

0x4697b4 HINT	#0

0x4697b8 HINT	#0

0x4697bc HINT	#0

      (2209) 0x4697c0 ADD	X20, X20, #1

      (2209) 0x4697c4 CMP	X20, X23

      (2209) 0x4697c8 B.GE	469820

      (2209) 0x4697cc LDR	X27, [X10, X20,LSL #3]

      (2209) 0x4697d0 LDR	X28, [X11, X27,LSL #3]

      (2209) 0x4697d4 CMP	X28, #1

      (2209) 0x4697d8 B.LT	4697c0

      (2209) 0x4697dc LDR	X27, [X21, X27,LSL #3]

      (2209) 0x4697e0 CMP	X27, X22

      (2209) 0x4697e4 B.EQ	4697c0

      (2209) 0x4697e8 LDR	X28, [X24, X27,LSL #3]

      (2209) 0x4697ec CMP	X28, X17

      (2209) 0x4697f0 B.GE	4697c0

      (2209) 0x4697f4 LDUR	X23, [X29, #480]

      (2209) 0x4697f8 STR	X23, [X24, X27,LSL #3]

      (2209) 0x4697fc STR	X27, [X26, X23,LSL #3]

      (2209) 0x469800 LDUR	X23, [X29, #480]

      (2209) 0x469804 ADD	X23, X23, #1

      (2209) 0x469808 STUR	X23, [X29, #480]

      (2209) 0x46980c LDR	X23, [X9, X7,LSL #3]

      (2209) 0x469810 B	4697c0

0x469814 HINT	#0

0x469818 HINT	#0

0x46981c HINT	#0

    (2207) 0x469820 LDR	X19, [X12, X19,LSL #3]

    (2207) 0x469824 LDR	X21, [X12, X7,LSL #3]

    (2207) 0x469828 CMP	X19, X21

    (2207) 0x46982c B.GE	469740

    (2207) 0x469830 LDUR	X20, [X29, #464]

    (2207) 0x469834 LDR	X23, [X30]

    (2207) 0x469838 LDR	X20, [X20]

    (2207) 0x46983c B	46984c

      (2208) 0x469840 ADD	X19, X19, #1

      (2208) 0x469844 CMP	X19, X21

      (2208) 0x469848 B.GE	469740

      (2208) 0x46984c LDR	X26, [X5, X19,LSL #3]

      (2208) 0x469850 LDR	X27, [X6, X26,LSL #3]

      (2208) 0x469854 CMP	X27, #1

      (2208) 0x469858 B.LT	469840

      (2208) 0x46985c LDR	X26, [X20, X26,LSL #3]

      (2208) 0x469860 LDR	X27, [X25, X26,LSL #3]

      (2208) 0x469864 CMP	X27, X18

      (2208) 0x469868 B.GE	469840

      (2208) 0x46986c LDUR	X21, [X29, #472]

      (2208) 0x469870 STR	X21, [X25, X26,LSL #3]

      (2208) 0x469874 STR	X26, [X23, X21,LSL #3]

      (2208) 0x469878 LDUR	X21, [X29, #472]

      (2208) 0x46987c ADD	X21, X21, #1

      (2208) 0x469880 STUR	X21, [X29, #472]

      (2208) 0x469884 LDR	X21, [X12, X7,LSL #3]

      (2208) 0x469888 B	469840

  (2203) 0x46988c LDR	X1, [X12, X1,LSL #3]

  (2203) 0x469890 LDR	X2, [X12, X0,LSL #3]

  (2203) 0x469894 CMP	X1, X2

  (2203) 0x469898 B.GE	4696ec

(2204) 0x46989c LDUR	X2, [X29, #464]

(2204) 0x4698a0 LDR	X4, [SP, #144]

(2204) 0x4698a4 LDUR	X5, [X29, #376]

(2204) 0x4698a8 LDR	X3, [X30]

(2204) 0x4698ac LDR	X2, [X2]

(2204) 0x4698b0 LDR	X4, [X4]

(2204) 0x4698b4 LDR	X5, [X5]

(2204) 0x4698b8 B	4698d0

0x4698bc HINT	#0

(2204) 0x4698c0 LDR	X6, [X12, X0,LSL #3]

(2204) 0x4698c4 ADD	X1, X1, #1

(2204) 0x4698c8 CMP	X1, X6

(2204) 0x4698cc B.GE	4696ec

(2204) 0x4698d0 LDR	X7, [X13, X1,LSL #3]

(2204) 0x4698d4 LDR	X6, [X14, X7,LSL #3]

(2204) 0x4698d8 CMP	X6, #1

(2204) 0x4698dc B.LT	469908

(2204) 0x4698e0 LDR	X6, [X2, X7,LSL #3]

(2204) 0x4698e4 LDR	X19, [X25, X6,LSL #3]

(2204) 0x4698e8 CMP	X19, X18

(2204) 0x4698ec B.GE	469908

(2204) 0x4698f0 LDUR	X19, [X29, #472]

(2204) 0x4698f4 STR	X19, [X25, X6,LSL #3]

(2204) 0x4698f8 STR	X6, [X3, X19,LSL #3]

(2204) 0x4698fc LDUR	X6, [X29, #472]

(2204) 0x469900 ADD	X6, X6, #1

(2204) 0x469904 STUR	X6, [X29, #472]

(2204) 0x469908 ADD	X6, X7, #1

(2204) 0x46990c LDR	X19, [X15, X7,LSL #3]

(2204) 0x469910 LDR	X21, [X15, X6,LSL #3]

(2204) 0x469914 CMP	X19, X21

(2204) 0x469918 B.GE	46996c

(2204) 0x46991c LDUR	X20, [X29, #440]

(2204) 0x469920 LDR	X20, [X20]

(2204) 0x469924 B	469934

  (2206) 0x469928 ADD	X19, X19, #1

  (2206) 0x46992c CMP	X19, X21

  (2206) 0x469930 B.GE	46996c

  (2206) 0x469934 LDR	X23, [X4, X19,LSL #3]

  (2206) 0x469938 CMP	X23, X22

  (2206) 0x46993c B.EQ	469928

  (2206) 0x469940 LDR	X26, [X24, X23,LSL #3]

  (2206) 0x469944 CMP	X26, X17

  (2206) 0x469948 B.GE	469928

  (2206) 0x46994c LDUR	X21, [X29, #480]

  (2206) 0x469950 STR	X21, [X24, X23,LSL #3]

  (2206) 0x469954 STR	X23, [X20, X21,LSL #3]

  (2206) 0x469958 LDUR	X21, [X29, #480]

  (2206) 0x46995c ADD	X21, X21, #1

  (2206) 0x469960 STUR	X21, [X29, #480]

  (2206) 0x469964 LDR	X21, [X15, X6,LSL #3]

  (2206) 0x469968 B	469928

(2204) 0x46996c LDR	X7, [X16, X7,LSL #3]

(2204) 0x469970 LDR	X20, [X16, X6,LSL #3]

(2204) 0x469974 CMP	X7, X20

(2204) 0x469978 B.GE	4698c0

(2204) 0x46997c LDR	X19, [X30]

(2204) 0x469980 B	469990

  (2205) 0x469984 ADD	X7, X7, #1

  (2205) 0x469988 CMP	X7, X20

  (2205) 0x46998c B.GE	4698c0

  (2205) 0x469990 LDR	X21, [X5, X7,LSL #3]

  (2205) 0x469994 LDR	X23, [X25, X21,LSL #3]

  (2205) 0x469998 CMP	X23, X18

  (2205) 0x46999c B.GE	469984

  (2205) 0x4699a0 LDUR	X20, [X29, #472]

  (2205) 0x4699a4 STR	X20, [X25, X21,LSL #3]

  (2205) 0x4699a8 STR	X21, [X19, X20,LSL #3]

  (2205) 0x4699ac LDUR	X20, [X29, #472]

  (2205) 0x4699b0 ADD	X20, X20, #1

  (2205) 0x4699b4 STUR	X20, [X29, #472]

  (2205) 0x4699b8 LDR	X20, [X16, X6,LSL #3]

  (2205) 0x4699bc B	469984

0x4699c0 CMP	X22, X0

0x4699c4 B.GE	469f28

0x4699c8 LDR	X8, [SP, #80]

0x4699cc LDP	X12, X13, [X29, #984]

0x4699d0 MOVZ	W4, #1

0x4699d4 LDR	X8, [X8]

0x4699d8 STUR	X8, [X29, #400]

0x4699dc LDP	X10, X8, [SP, #16]

0x4699e0 LDR	X9, [X10]

0x4699e4 LDR	X10, [X8]

0x4699e8 LDR	X8, [SP, #88]

0x4699ec LDR	X11, [X8]

0x4699f0 LDR	X8, [SP, #32]

0x4699f4 LDR	X14, [X8]

0x4699f8 LDUR	X8, [X29, #384]

0x4699fc LDR	X8, [X8]

0x469a00 STUR	X8, [X29, #432]

0x469a04 ADD	X8, X26, #8

0x469a08 STR	X8, [SP, #136]

0x469a0c LDUR	X8, [X29, #392]

0x469a10 LDR	X17, [X8]

0x469a14 ADD	X8, X20, #8

0x469a18 STR	X8, [SP, #128]

0x469a1c ADD	X8, X23, #8

0x469a20 STR	X8, [SP, #120]

0x469a24 LDR	X8, [SP, #40]

0x469a28 LDR	X1, [X8]

0x469a2c ADD	X8, X21, #8

0x469a30 STR	X8, [SP, #112]

0x469a34 LDR	X8, [SP, #48]

0x469a38 LDR	X5, [X8]

0x469a3c B	469a50

  (2194) 0x469a40 LDUR	X8, [X29, #424]

  (2194) 0x469a44 ADD	X22, X22, #1

  (2194) 0x469a48 CMP	X22, X8

  (2194) 0x469a4c B.EQ	469f28

  (2194) 0x469a50 LDUR	X8, [X29, #400]

  (2194) 0x469a54 ORR	X6, XZR, X12

  (2194) 0x469a58 ORR	X7, XZR, X13

  (2194) 0x469a5c LDR	X8, [X8, X22,LSL #3]

  (2194) 0x469a60 ADD	X30, X8, #1

  (2194) 0x469a64 LDR	X18, [X9, X8,LSL #3]

  (2194) 0x469a68 STUR	X8, [X29, #416]

  (2194) 0x469a6c LDR	X8, [X9, X30,LSL #3]

  (2194) 0x469a70 CMP	X18, X8

  (2194) 0x469a74 B.GE	469c00

  (2194) 0x469a78 LDUR	X8, [X29, #456]

  (2194) 0x469a7c ORR	X13, XZR, X7

  (2194) 0x469a80 ORR	X12, XZR, X6

  (2194) 0x469a84 LDR	X0, [X8]

  (2194) 0x469a88 LDUR	X8, [X29, #384]

  (2194) 0x469a8c LDR	X2, [X8]

  (2194) 0x469a90 LDUR	X8, [X29, #392]

  (2194) 0x469a94 LDR	X8, [X8]

  (2194) 0x469a98 B	469ab0

0x469a9c HINT	#0

    (2199) 0x469aa0 LDR	X15, [X9, X30,LSL #3]

    (2199) 0x469aa4 ADD	X18, X18, #1

    (2199) 0x469aa8 CMP	X18, X15

    (2199) 0x469aac B.GE	469c00

    (2199) 0x469ab0 LDR	X28, [X10, X18,LSL #3]

    (2199) 0x469ab4 LDR	X15, [X11, X28,LSL #3]

    (2199) 0x469ab8 CMP	X15, #1

    (2199) 0x469abc B.LT	469af8

    (2199) 0x469ac0 LDR	X16, [X0, X28,LSL #3]

    (2199) 0x469ac4 LDR	X15, [X24, X16,LSL #3]

    (2199) 0x469ac8 SUBS	X3, X15, X7

    (2199) 0x469acc B.GE	469aec

    (2199) 0x469ad0 SUB	X15, X13, X7

    (2199) 0x469ad4 STR	X13, [X24, X16,LSL #3]

    (2199) 0x469ad8 ADD	X13, X13, #1

    (2199) 0x469adc STR	X16, [X26, X15,LSL #3]

    (2199) 0x469ae0 MOVZ	W16, #2

    (2199) 0x469ae4 STR	X16, [X20, X15,LSL #3]

    (2199) 0x469ae8 B	469af8

    (2199) 0x469aec LDR	X15, [X20, X3,LSL #3]

    (2199) 0x469af0 ADD	X15, X15, #2

    (2199) 0x469af4 STR	X15, [X20, X3,LSL #3]

    (2199) 0x469af8 ADD	X3, X28, #1

    (2199) 0x469afc LDR	X27, [X9, X28,LSL #3]

    (2199) 0x469b00 LDR	X15, [X9, X3,LSL #3]

    (2199) 0x469b04 CMP	X27, X15

    (2199) 0x469b08 B.GE	469b80

    (2199) 0x469b0c LDUR	X15, [X29, #456]

    (2199) 0x469b10 LDR	X16, [X15]

    (2199) 0x469b14 B	469b34

      (2201) 0x469b18 LDR	X19, [X20, X15,LSL #3]

      (2201) 0x469b1c ADD	X19, X19, #1

      (2201) 0x469b20 STR	X19, [X20, X15,LSL #3]

      (2201) 0x469b24 LDR	X15, [X9, X3,LSL #3]

      (2201) 0x469b28 ADD	X27, X27, #1

      (2201) 0x469b2c CMP	X27, X15

      (2201) 0x469b30 B.GE	469b80

      (2201) 0x469b34 LDR	X19, [X10, X27,LSL #3]

      (2201) 0x469b38 LDR	X15, [X11, X19,LSL #3]

      (2201) 0x469b3c CMP	X15, #1

      (2201) 0x469b40 B.LT	469b24

      (2201) 0x469b44 LDR	X19, [X16, X19,LSL #3]

      (2201) 0x469b48 CMP	X19, X22

      (2201) 0x469b4c B.EQ	469b24

      (2201) 0x469b50 LDR	X15, [X24, X19,LSL #3]

      (2201) 0x469b54 SUBS	X15, X15, X7

      (2201) 0x469b58 B.GE	469b18

      (2201) 0x469b5c SUB	X15, X13, X7

      (2201) 0x469b60 STR	X13, [X24, X19,LSL #3]

      (2201) 0x469b64 ADD	X13, X13, #1

      (2201) 0x469b68 STR	X19, [X26, X15,LSL #3]

      (2201) 0x469b6c STR	X4, [X20, X15,LSL #3]

      (2201) 0x469b70 B	469b24

0x469b74 HINT	#0

0x469b78 HINT	#0

0x469b7c HINT	#0

    (2199) 0x469b80 LDR	X27, [X14, X28,LSL #3]

    (2199) 0x469b84 LDR	X15, [X14, X3,LSL #3]

    (2199) 0x469b88 CMP	X27, X15

    (2199) 0x469b8c B.GE	469aa0

    (2199) 0x469b90 LDUR	X15, [X29, #464]

    (2199) 0x469b94 LDR	X16, [X15]

    (2199) 0x469b98 B	469bbc

0x469b9c HINT	#0

      (2200) 0x469ba0 LDR	X19, [X21, X15,LSL #3]

      (2200) 0x469ba4 ADD	X19, X19, #1

      (2200) 0x469ba8 STR	X19, [X21, X15,LSL #3]

      (2200) 0x469bac LDR	X15, [X14, X3,LSL #3]

      (2200) 0x469bb0 ADD	X27, X27, #1

      (2200) 0x469bb4 CMP	X27, X15

      (2200) 0x469bb8 B.GE	469aa0

      (2200) 0x469bbc LDR	X15, [X2, X27,LSL #3]

      (2200) 0x469bc0 LDR	X19, [X8, X15,LSL #3]

      (2200) 0x469bc4 CMP	X19, #1

      (2200) 0x469bc8 B.LT	469bac

      (2200) 0x469bcc LDR	X19, [X16, X15,LSL #3]

      (2200) 0x469bd0 LDR	X15, [X25, X19,LSL #3]

      (2200) 0x469bd4 SUBS	X15, X15, X6

      (2200) 0x469bd8 B.GE	469ba0

      (2200) 0x469bdc SUB	X15, X12, X6

      (2200) 0x469be0 STR	X12, [X25, X19,LSL #3]

      (2200) 0x469be4 ADD	X12, X12, #1

      (2200) 0x469be8 STR	X19, [X23, X15,LSL #3]

      (2200) 0x469bec STR	X4, [X21, X15,LSL #3]

      (2200) 0x469bf0 B	469bac

0x469bf4 HINT	#0

0x469bf8 HINT	#0

0x469bfc HINT	#0

  (2194) 0x469c00 LDUR	X8, [X29, #416]

  (2194) 0x469c04 LDR	X15, [X14, X30,LSL #3]

  (2194) 0x469c08 LDR	X8, [X14, X8,LSL #3]

  (2194) 0x469c0c CMP	X8, X15

  (2194) 0x469c10 B.GE	469d60

  (2194) 0x469c14 LDUR	X15, [X29, #464]

  (2194) 0x469c18 LDR	X16, [X15]

  (2194) 0x469c1c LDR	X15, [SP, #144]

  (2194) 0x469c20 LDR	X18, [X15]

  (2194) 0x469c24 LDUR	X15, [X29, #376]

  (2194) 0x469c28 LDR	X0, [X15]

  (2194) 0x469c2c B	469c50

0x469c30 HINT	#0

0x469c34 HINT	#0

0x469c38 HINT	#0

0x469c3c HINT	#0

    (2196) 0x469c40 LDR	X15, [X14, X30,LSL #3]

    (2196) 0x469c44 ADD	X8, X8, #1

    (2196) 0x469c48 CMP	X8, X15

    (2196) 0x469c4c B.GE	469d60

    (2196) 0x469c50 LDUR	X15, [X29, #432]

    (2196) 0x469c54 LDR	X3, [X15, X8,LSL #3]

    (2196) 0x469c58 LDR	X15, [X17, X3,LSL #3]

    (2196) 0x469c5c CMP	X15, #1

    (2196) 0x469c60 B.LT	469c98

    (2196) 0x469c64 LDR	X2, [X16, X3,LSL #3]

    (2196) 0x469c68 LDR	X15, [X25, X2,LSL #3]

    (2196) 0x469c6c SUBS	X15, X15, X6

    (2196) 0x469c70 B.GE	469c8c

    (2196) 0x469c74 SUB	X15, X12, X6

    (2196) 0x469c78 STR	X12, [X25, X2,LSL #3]

    (2196) 0x469c7c ADD	X12, X12, #1

    (2196) 0x469c80 STR	X2, [X23, X15,LSL #3]

    (2196) 0x469c84 MOVZ	W2, #2

    (2196) 0x469c88 B	469c94

    (2196) 0x469c8c LDR	X2, [X21, X15,LSL #3]

    (2196) 0x469c90 ADD	X2, X2, #2

    (2196) 0x469c94 STR	X2, [X21, X15,LSL #3]

    (2196) 0x469c98 LDR	X19, [X1, X3,LSL #3]

    (2196) 0x469c9c ADD	X2, X3, #1

    (2196) 0x469ca0 B	469cb4

      (2198) 0x469ca4 LDR	X27, [X20, X15,LSL #3]

      (2198) 0x469ca8 ADD	X27, X27, #1

      (2198) 0x469cac STR	X27, [X20, X15,LSL #3]

      (2198) 0x469cb0 ADD	X19, X19, #1

      (2198) 0x469cb4 LDR	X15, [X1, X2,LSL #3]

      (2198) 0x469cb8 CMP	X19, X15

      (2198) 0x469cbc B.GE	469d00

      (2198) 0x469cc0 LDR	X27, [X18, X19,LSL #3]

      (2198) 0x469cc4 CMP	X27, X22

      (2198) 0x469cc8 B.EQ	469cb0

      (2198) 0x469ccc LDR	X15, [X24, X27,LSL #3]

      (2198) 0x469cd0 SUBS	X15, X15, X7

      (2198) 0x469cd4 B.GE	469ca4

      (2198) 0x469cd8 SUB	X15, X13, X7

      (2198) 0x469cdc STR	X13, [X24, X27,LSL #3]

      (2198) 0x469ce0 ADD	X13, X13, #1

      (2198) 0x469ce4 ADD	X19, X19, #1

      (2198) 0x469ce8 STR	X27, [X26, X15,LSL #3]

      (2198) 0x469cec STR	X4, [X20, X15,LSL #3]

      (2198) 0x469cf0 B	469cb4

0x469cf4 HINT	#0

0x469cf8 HINT	#0

0x469cfc HINT	#0

    (2196) 0x469d00 LDR	X3, [X5, X3,LSL #3]

    (2196) 0x469d04 B	469d20

      (2197) 0x469d08 SUB	X15, X12, X6

      (2197) 0x469d0c STR	X12, [X25, X19,LSL #3]

      (2197) 0x469d10 ADD	X12, X12, #1

      (2197) 0x469d14 ADD	X3, X3, #1

      (2197) 0x469d18 STR	X19, [X23, X15,LSL #3]

      (2197) 0x469d1c STR	X4, [X21, X15,LSL #3]

      (2197) 0x469d20 LDR	X15, [X5, X2,LSL #3]

      (2197) 0x469d24 CMP	X3, X15

      (2197) 0x469d28 B.GE	469c40

      (2197) 0x469d2c LDR	X19, [X0, X3,LSL #3]

      (2197) 0x469d30 LDR	X15, [X25, X19,LSL #3]

      (2197) 0x469d34 SUBS	X15, X15, X6

      (2197) 0x469d38 B.LT	469d08

      (2197) 0x469d3c LDR	X19, [X21, X15,LSL #3]

      (2197) 0x469d40 ADD	X3, X3, #1

      (2197) 0x469d44 ADD	X19, X19, #1

      (2197) 0x469d48 STR	X19, [X21, X15,LSL #3]

      (2197) 0x469d4c B	469d20

0x469d50 HINT	#0

0x469d54 HINT	#0

0x469d58 HINT	#0

0x469d5c HINT	#0

  (2194) 0x469d60 LDUR	X19, [X29, #408]

  (2194) 0x469d64 CMP	X13, X7

  (2194) 0x469d68 B.LE	469dbc

  (2194) 0x469d6c LDUR	X8, [X29, #440]

  (2194) 0x469d70 SUB	W15, W13, W7

  (2194) 0x469d74 ORR	X18, XZR, X7

  (2194) 0x469d78 LDR	X8, [X8]

  (2194) 0x469d7c TBZ	W15, #0, 469db0

  (2194) 0x469d80 LDUR	X16, [X29, #448]

  (2194) 0x469d84 LDR	X15, [X20]

  (2194) 0x469d88 LDR	X16, [X16]

  (2194) 0x469d8c CMP	X15, X16

  (2194) 0x469d90 B.LT	469da8

  (2194) 0x469d94 LDUR	X16, [X29, #480]

  (2194) 0x469d98 LDR	X15, [X26]

  (2194) 0x469d9c ADD	X18, X16, #1

  (2194) 0x469da0 STUR	X18, [X29, #480]

  (2194) 0x469da4 STR	X15, [X8, X16,LSL #3]

  (2194) 0x469da8 ADD	X18, X7, #1

  (2194) 0x469dac STR	XZR, [X20]

  (2194) 0x469db0 ADD	X15, X7, #1

  (2194) 0x469db4 CMP	X13, X15

  (2194) 0x469db8 B.NE	469ea0

  (2194) 0x469dbc CMP	X12, X6

  (2194) 0x469dc0 B.LE	469a40

  (2194) 0x469dc4 LDR	X8, [X19]

  (2194) 0x469dc8 SUB	W15, W12, W6

  (2194) 0x469dcc ORR	X18, XZR, X6

  (2194) 0x469dd0 TBZ	W15, #0, 469e04

  (2194) 0x469dd4 LDUR	X16, [X29, #448]

  (2194) 0x469dd8 LDR	X15, [X21]

  (2194) 0x469ddc LDR	X16, [X16]

  (2194) 0x469de0 CMP	X15, X16

  (2194) 0x469de4 B.LT	469dfc

  (2194) 0x469de8 LDUR	X16, [X29, #472]

  (2194) 0x469dec LDR	X15, [X23]

  (2194) 0x469df0 ADD	X18, X16, #1

  (2194) 0x469df4 STUR	X18, [X29, #472]

  (2194) 0x469df8 STR	X15, [X8, X16,LSL #3]

  (2194) 0x469dfc ADD	X18, X6, #1

  (2194) 0x469e00 STR	XZR, [X21]

  (2194) 0x469e04 ADD	X15, X6, #1

  (2194) 0x469e08 CMP	X12, X15

  (2194) 0x469e0c B.EQ	469a40

  (2194) 0x469e10 SUB	X16, X12, X18

  (2194) 0x469e14 UBFM	X15, X18, #61, #60

  (2194) 0x469e18 LDP	X0, X18, [SP, #112]

  (2194) 0x469e1c SUB	X15, X15, X6,LSL #3

  (2194) 0x469e20 ADD	X18, X18, X15

  (2194) 0x469e24 ADD	X0, X0, X15

  (2194) 0x469e28 B	469e3c

    (2202) 0x469e2c STR	XZR, [X0], #16

    (2202) 0x469e30 SUBS	X16, X16, #2

    (2202) 0x469e34 ADD	X18, X18, #16

    (2202) 0x469e38 B.EQ	469a40

    (2202) 0x469e3c LDUR	X2, [X29, #448]

    (2202) 0x469e40 LDUR	X15, [X0, #504]

    (2202) 0x469e44 LDR	X2, [X2]

    (2202) 0x469e48 CMP	X15, X2

    (2202) 0x469e4c B.LT	469e64

    (2202) 0x469e50 LDUR	X2, [X29, #472]

    (2202) 0x469e54 LDUR	X15, [X18, #504]

    (2202) 0x469e58 ADD	X3, X2, #1

    (2202) 0x469e5c STUR	X3, [X29, #472]

    (2202) 0x469e60 STR	X15, [X8, X2,LSL #3]

    (2202) 0x469e64 LDUR	X2, [X29, #448]

    (2202) 0x469e68 STUR	XZR, [X0, #504]

    (2202) 0x469e6c LDR	X15, [X0]

    (2202) 0x469e70 LDR	X2, [X2]

    (2202) 0x469e74 CMP	X15, X2

    (2202) 0x469e78 B.LT	469e2c

    (2202) 0x469e7c LDUR	X2, [X29, #472]

    (2202) 0x469e80 LDR	X15, [X18]

    (2202) 0x469e84 ADD	X3, X2, #1

    (2202) 0x469e88 STUR	X3, [X29, #472]

    (2202) 0x469e8c STR	X15, [X8, X2,LSL #3]

    (2202) 0x469e90 B	469e2c

0x469e94 HINT	#0

0x469e98 HINT	#0

0x469e9c HINT	#0

(2195) 0x469ea0 SUB	X16, X13, X18

(2195) 0x469ea4 UBFM	X15, X18, #61, #60

(2195) 0x469ea8 LDP	X0, X18, [SP, #128]

(2195) 0x469eac SUB	X15, X15, X7,LSL #3

(2195) 0x469eb0 ADD	X18, X18, X15

(2195) 0x469eb4 ADD	X0, X0, X15

(2195) 0x469eb8 B	469ed0

0x469ebc HINT	#0

(2195) 0x469ec0 STR	XZR, [X0], #16

(2195) 0x469ec4 SUBS	X16, X16, #2

(2195) 0x469ec8 ADD	X18, X18, #16

(2195) 0x469ecc B.EQ	469dbc

(2195) 0x469ed0 LDUR	X2, [X29, #448]

(2195) 0x469ed4 LDUR	X15, [X0, #504]

(2195) 0x469ed8 LDR	X2, [X2]

(2195) 0x469edc CMP	X15, X2

(2195) 0x469ee0 B.LT	469ef8

(2195) 0x469ee4 LDUR	X2, [X29, #480]

(2195) 0x469ee8 LDUR	X15, [X18, #504]

(2195) 0x469eec ADD	X3, X2, #1

(2195) 0x469ef0 STUR	X3, [X29, #480]

(2195) 0x469ef4 STR	X15, [X8, X2,LSL #3]

(2195) 0x469ef8 LDUR	X2, [X29, #448]

(2195) 0x469efc STUR	XZR, [X0, #504]

(2195) 0x469f00 LDR	X15, [X0]

(2195) 0x469f04 LDR	X2, [X2]

(2195) 0x469f08 CMP	X15, X2

(2195) 0x469f0c B.LT	469ec0

(2195) 0x469f10 LDUR	X2, [X29, #480]

(2195) 0x469f14 LDR	X15, [X18]

(2195) 0x469f18 ADD	X3, X2, #1

(2195) 0x469f1c STUR	X3, [X29, #480]

(2195) 0x469f20 STR	X15, [X8, X2,LSL #3]

(2195) 0x469f24 B	469ec0

0x469f28 LDP	X20, X19, [SP, #368]

0x469f2c LDP	X22, X21, [SP, #352]

0x469f30 LDP	X24, X23, [SP, #336]

0x469f34 LDP	X26, X25, [SP, #320]

0x469f38 LDP	X28, X27, [SP, #304]

0x469f3c LDP	X29, X30, [SP, #288]

0x469f40 ADD	SP, SP, #384

0x469f44 RET

0x469f48 HINT	#0

0x469f4c HINT	#0

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libomp.so
○	hypre_prefix_sum_pair	hypre_prefix_sum.c:80	exec

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	par_strength.c:1668-2230
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1668-1697,1705-1714,1720-1797,1806,1812-2000,2006-2083,2093-2095,2101-2230.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 54% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 67.67 to 59.67 cycles (1.13x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 67.67 to 4.50 cycles (15.04x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 1460 bytes. The binary function is storing 464 bytes.

General properties

nb instructions	419
loop length	1676
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

42.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	17.50	17.50	18.42	18.42	18.33	18.33	18.25	18.25	0.00	0.00	0.00	0.00	67.67	67.67	67.67	24.00	24.00
cycles	17.50	17.50	18.42	18.42	18.33	18.33	18.25	18.25	0.00	0.00	0.00	0.00	67.67	67.67	67.67	24.00	24.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	42.38
Overall L1	67.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 67.67 cycles. At this rate:

22% of peak load performance is reached (21.58 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (6.86 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 468a40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #384	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #288	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X27, X22, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ORR X21, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X24, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X20, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X25, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X19, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X26, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X0, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a8a10 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X28, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X0, X29, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X1, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a8a30 <hypre_GetSimpleThreadPartition>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X15, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD X11, X10, X28, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
STUR X21, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 468ae4 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X13, X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X12, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X26, X12, X11,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MADD X12, X9, X28, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X23, X14, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X20, X13, X11,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X21, X8, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 468af8 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X20, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X23, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X26, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD X12, X9, X28, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR X13, [X27]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X10, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
LDR X14, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X11, X13, X11,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CSEL X24, XZR, X11, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X11, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X9, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
ADD X11, X11, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CSEL X25, XZR, X11, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X10, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 468b5c <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x11c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X27, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVN X10, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X9, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR X9, [X27]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 468b60 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X27, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X15, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X10, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X11, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X10, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X10, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X11, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X11, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X10, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X11, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X11, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X11, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X10, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X10, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X9, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 468bf4 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x1b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X10, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X9, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP XZR, XZR, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X9, X28, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X10, [X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X19, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X14, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X9, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X22, [X8, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X10, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X9, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 468f20 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x4e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X22, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 46942c <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x9ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X18, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X9, X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X9, X8, [X29, #896]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X15, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X9, X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X17, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 468c98 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x258>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
CMP X22, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 46942c <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x9ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X2, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X4, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X5, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X8, X9, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X9, X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X8, X9, [X29, #944]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X9, X20, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X8, X21, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X8, X9, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X9, X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X0, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X6, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 468fb0 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x570>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDP X10, X19, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X9, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X0, X29, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X2, X29, #40	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X10, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, X10, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, X9, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 4a95f0 <hypre_prefix_sum_pair>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 469494 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xa54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X11, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDP X8, X9, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X27]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 4694d4 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xa94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <4de4d8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #560	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR W27, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR W1, WZR, W27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 40f440 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4de4ec>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #584	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 40f970 <@plt_start@+0x580>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ W0, 46955c <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xb1c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X10, X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X9, 46952c <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xaec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X0, X9, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X19, XZR, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6c20 <hypre_MAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 46954c <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xb0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X0, X8, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 4a6c20 <hypre_MAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADRP X0, <4de54c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #584	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 40f8a0 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4de55c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #608	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 40f440 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X0, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X1, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X30, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X9, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X8, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X22, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 469618 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xbd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W14, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X12, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X10, X9, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD X13, X13, X22,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORN X10, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X12, X12, X22,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X10, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X11, X11, X22,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 4695e8 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xba8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
ORR X9, XZR, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X22, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 469f28 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x14e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X11, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X10, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X10, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [X11, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X10, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X12, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X12, X13, #60, #59	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [X10, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X10, X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X12, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 469698 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xc58>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X11, X13, #63, #62	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X10, X11,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X10, [X10, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X10, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 469698 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xc58>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X10, X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X10, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W10, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X10, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 4699c0 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xf80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X22, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 469f28 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x14e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X11, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X9, X10, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X12, X15, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X13, X14, [X29, #896]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X16, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 4696fc <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xcbc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
CMP X22, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 469f28 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x14e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X12, X13, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
MOVZ W4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X9, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X8, X26, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X8, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X8, X20, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X8, X23, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X21, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 469a50 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x1010>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDP X20, X19, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X26, X25, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X28, X27, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X29, X30, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #384	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	par_strength.c:1668-2230
Module	exec

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 67.67 to 4.50 cycles (15.04x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 1460 bytes. The binary function is storing 464 bytes.

General properties

nb instructions	419
loop length	1676
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

42.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	17.50	17.50	18.42	18.42	18.33	18.33	18.25	18.25	0.00	0.00	0.00	0.00	67.67	67.67	67.67	24.00	24.00
cycles	17.50	17.50	18.42	18.42	18.33	18.33	18.25	18.25	0.00	0.00	0.00	0.00	67.67	67.67	67.67	24.00	24.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	42.38
Overall L1	67.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 67.67 cycles. At this rate:

22% of peak load performance is reached (21.58 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (6.86 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 468a40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #384	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #288	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X27, X22, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ORR X21, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X24, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X20, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X25, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X19, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X26, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X0, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a8a10 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X28, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X0, X29, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X1, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a8a30 <hypre_GetSimpleThreadPartition>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X15, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD X11, X10, X28, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
STUR X21, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 468ae4 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X13, X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X12, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X26, X12, X11,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MADD X12, X9, X28, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X23, X14, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X20, X13, X11,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X21, X8, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 468af8 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X20, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X23, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X26, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD X12, X9, X28, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR X13, [X27]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X10, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
LDR X14, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X11, X13, X11,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CSEL X24, XZR, X11, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X11, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X9, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
ADD X11, X11, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CSEL X25, XZR, X11, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X10, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 468b5c <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x11c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X27, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVN X10, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X9, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR X9, [X27]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 468b60 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X27, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X15, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X10, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X11, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X10, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X10, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X11, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X11, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X10, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X11, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X11, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X11, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X10, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X10, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X9, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 468bf4 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x1b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X10, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X9, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP XZR, XZR, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X9, X28, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X10, [X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X19, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X14, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X9, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X22, [X8, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X10, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X9, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 468f20 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x4e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X22, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 46942c <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x9ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X18, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X9, X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X9, X8, [X29, #896]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X15, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X9, X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X17, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 468c98 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x258>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
CMP X22, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 46942c <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x9ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X2, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X4, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X5, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X8, X9, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X9, X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X8, X9, [X29, #944]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X9, X20, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X8, X21, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X8, X9, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X9, X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X0, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X6, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 468fb0 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x570>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDP X10, X19, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X9, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X0, X29, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X2, X29, #40	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X10, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, X10, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, X9, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 4a95f0 <hypre_prefix_sum_pair>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 469494 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xa54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X11, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDP X8, X9, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X27]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 4694d4 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xa94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <4de4d8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #560	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR W27, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR W1, WZR, W27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 40f440 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4de4ec>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #584	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 40f970 <@plt_start@+0x580>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ W0, 46955c <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xb1c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X10, X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X9, 46952c <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xaec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X0, X9, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X19, XZR, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6c20 <hypre_MAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 46954c <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xb0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X0, X8, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 4a6c20 <hypre_MAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADRP X0, <4de54c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #584	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 40f8a0 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4de55c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #608	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 40f440 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X0, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X1, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X30, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X9, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X8, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X22, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 469618 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xbd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W14, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X12, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X10, X9, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD X13, X13, X22,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORN X10, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X12, X12, X22,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X10, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X11, X11, X22,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 4695e8 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xba8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
ORR X9, XZR, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X22, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 469f28 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x14e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X11, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X10, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X10, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [X11, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X10, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X12, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X12, X13, #60, #59	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [X10, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X10, X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X12, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 469698 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xc58>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X11, X13, #63, #62	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X10, X11,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X10, [X10, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X10, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 469698 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xc58>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X10, X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X10, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W10, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X10, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 4699c0 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xf80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X22, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 469f28 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x14e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X11, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X9, X10, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X12, X15, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X13, X14, [X29, #896]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X16, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 4696fc <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xcbc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
CMP X22, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 469f28 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x14e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X12, X13, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
MOVZ W4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X9, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X8, X26, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X8, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X8, X20, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X8, X23, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X21, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 469a50 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x1010>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDP X20, X19, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X26, X25, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X28, X27, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X29, X30, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #384	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A

▶Scalability Runs Description

Run 1x1	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_NUM_THREADS: 1OMP_PLACES: threads
Run 1x2	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 2OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x4	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 4OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x8	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 8OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x16	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 16OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x24	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 24OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x32	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 32OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x40	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 40OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x48	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 48OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x56	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 56OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x64	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 64OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x72	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 72OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x80	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 80OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x88	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 88OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x96	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 96OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads

(1x1) Efficiency	(1x1) Potential Speed-Up (%)	(1x2) Efficiency	(1x2) Potential Speed-Up (%)	(1x4) Efficiency	(1x4) Potential Speed-Up (%)	(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x16) Efficiency	(1x16) Potential Speed-Up (%)	(1x24) Efficiency	(1x24) Potential Speed-Up (%)	(1x32) Efficiency	(1x32) Potential Speed-Up (%)	(1x40) Efficiency	(1x40) Potential Speed-Up (%)	(1x48) Efficiency	(1x48) Potential Speed-Up (%)	(1x56) Efficiency	(1x56) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)	(1x72) Efficiency	(1x72) Potential Speed-Up (%)	(1x80) Efficiency	(1x80) Potential Speed-Up (%)	(1x88) Efficiency	(1x88) Potential Speed-Up (%)	(1x96) Efficiency	(1x96) Potential Speed-Up (%)
1	0	1.93	0	3.75	0	7.13	0	13.44	0	18.97	0	25.05	0	27.3	0	32.87	0	37.7	0	39.63	0	40.84	0	44.82	0	42.14	0	43.12	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x1	1	1	1	1	15.464997291565	5.8132767677307
1x2	2	1.93	1.93	2	7.9400000572205	5.6612281799316
1x4	4	3.75	3.75	4	4.0300002098083	5.4500832557678
1x8	8	7.13	7.13	8	2.0649998188019	4.9204616546631
1x16	16	13.44	13.44	16	1.0699996948242	3.9943754673004
1x24	24	18.97	18.97	24	0.74499976634979	3.2912046909332
1x32	32	25.05	25.05	32	0.57999992370605	2.7191879749298
1x40	40	27.3	27.3	40	0.48000004887581	2.3477468490601
1x48	48	32.87	32.87	48	0.41999992728233	2.1229681968689
1x56	56	37.7	37.7	56	0.37000000476837	2.0363368988037
1x64	64	39.63	39.63	64	0.35000002384186	2.0039315223694
1x72	72	40.84	40.84	72	0.33500003814697	1.9467564821243
1x80	80	44.82	44.82	80	0.32000002264977	1.9277926683426
1x88	88	42.14	42.14	88	0.30999997258186	1.8707441091537
1x96	96	43.12	43.12	96	0.29499998688698	1.8361146450043

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGCreate2ndS.omp_outlined.16–	5.81	15.46
○Loop 2210 - par_strength.c:1978-1984 - exec	0.00	0.00
○Loop 2212 - par_strength.c:1951-1953 - exec	0.00	0.00
○Loop 2230 - par_strength.c:1691-1693 - exec	0.00	0.00
▼Loop 2223 - par_strength.c:1714-1797 - exec–	0.00	0.00
▼Loop 2222 - par_strength.c:1714-1770 - exec–	0.02	0.04
▼Loop 2225 - par_strength.c:1731-1765 - exec–	0.34	0.90
○Loop 2227 - par_strength.c:1743-1752 - exec	2.54	6.75
○Loop 2226 - par_strength.c:1756-1765 - exec	0.00	0.00
○Loop 2228 - par_strength.c:1791-1797 - exec	0.00	0.00
○Loop 2224 - par_strength.c:1782-1788 - exec	0.00	0.00
▼Loop 2204 - par_strength.c:2000-2083 - exec–	0.00	0.00
▼Loop 2203 - par_strength.c:2000-2053 - exec–	0.01	0.02
▼Loop 2207 - par_strength.c:2011-2048 - exec–	0.33	0.89
○Loop 2209 - par_strength.c:2024-2034 - exec	2.57	6.84
○Loop 2208 - par_strength.c:2038-2048 - exec	0.00	0.00
○Loop 2205 - par_strength.c:2076-2083 - exec	0.00	0.00
○Loop 2206 - par_strength.c:2066-2073 - exec	0.00	0.00
▼Loop 2214 - par_strength.c:1806-1941 - exec–	0.00	0.00
▼Loop 2213 - par_strength.c:1806-1941 - exec–	0.00	0.00
▼Loop 2218 - par_strength.c:1823-1872 - exec–	0.00	0.00
○Loop 2219 - par_strength.c:1858-1872 - exec	0.00	0.00
○Loop 2220 - par_strength.c:1840-1854 - exec	0.00	0.00
▼Loop 2215 - par_strength.c:1877-1922 - exec–	0.00	0.00
○Loop 2217 - par_strength.c:1894-1907 - exec	0.00	0.00
○Loop 2216 - par_strength.c:1911-1922 - exec	0.00	0.00
○Loop 2221 - par_strength.c:1935-1941 - exec	0.00	0.00
○Loop 2211 - par_strength.c:1955-1957 - exec	0.00	0.00
▼Loop 2195 - par_strength.c:2095-2230 - exec–	0.00	0.00
▼Loop 2194 - par_strength.c:2095-2230 - exec–	0.00	0.00
▼Loop 2196 - par_strength.c:2163-2211 - exec–	0.00	0.00
○Loop 2198 - par_strength.c:2181-2195 - exec	0.00	0.00
○Loop 2197 - par_strength.c:2199-2211 - exec	0.00	0.00
○Loop 2202 - par_strength.c:2224-2230 - exec	0.00	0.00
▼Loop 2199 - par_strength.c:2106-2158 - exec–	0.00	0.00
○Loop 2200 - par_strength.c:2143-2158 - exec	0.00	0.00
○Loop 2201 - par_strength.c:2124-2139 - exec	0.00	0.00
○Loop 2229 - par_strength.c:1695-1697 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency