OV - exec - Function hypre_BoomerAMGBuildMultipass.omp

	Function: hypre_BoomerAMGBuildMultipass.omp_outlined.20	Module: exec	Source: par_multi_interp.c:1737-1881 [...]	Coverage (incl. loops): 4.51% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1737 - 1881

--------------------------------------------------------------------------------

1737: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa,tmp_array,tmp_array_offd)

[...]

1747:              if (n_fine)

1748:              {    tmp_marker = hypre_CTAlloc(HYPRE_Int,n_fine); }

1749:              tmp_marker_offd = NULL;

1750:              if (num_cols_offd)

1751:              {    tmp_marker_offd = hypre_CTAlloc(HYPRE_Int,num_cols_offd); }

1752:              tmp_array = NULL;

1753:              if (n_coarse)

1754:              {    tmp_array = hypre_CTAlloc(HYPRE_Int,n_coarse); }

1755:              tmp_array_offd = NULL;

1756:              if (new_num_cols_offd > n_coarse_offd)

1757:              {    tmp_array_offd = hypre_CTAlloc(HYPRE_Int,new_num_cols_offd); }

1758:              else

1759:              {    tmp_array_offd = hypre_CTAlloc(HYPRE_Int,n_coarse_offd);}

1760:              for (i=0; i < n_fine; i++)

1761:              {    tmp_marker[i] = -1; }

1762:              for (i=0; i < num_cols_offd; i++)

1763:              {    tmp_marker_offd[i] = -1; }

1764:

1765:              /* Compute this thread's range of pass_length */

1766:              my_thread_num = hypre_GetThreadNum();

1767:              num_threads = hypre_NumActiveThreads();

1768:              thread_start = pass_pointer[pass] + (pass_length/num_threads)*my_thread_num;

1769:              if (my_thread_num == num_threads-1)

1770:              {  thread_stop = pass_pointer[pass] + pass_length; }

1771:              else

1772:              {  thread_stop = pass_pointer[pass] + (pass_length/num_threads)*(my_thread_num+1); }

1773:

1774:              for (i=thread_start; i < thread_stop; i++)

1775:              {

1776:                 i1 = pass_array[i];

1777:                 sum_C = 0;

1778:                 sum_N = 0;

1779:                 j_start = P_diag_start[i1];

1780:                 j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1];

1781:                 cnt = P_diag_i[i1];

1782:                 for (j=j_start; j < j_end; j++)

1783:                 {

1784:                    k1 = P_diag_pass[pass][j];

1785:                tmp_array[k1] = cnt;

1786:                P_diag_data[cnt] = 0;

1787:                P_diag_j[cnt++] = k1;

1788:                 }

1789:                 j_start = P_offd_start[i1];

1790:                 j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1];

1791:                 cnt_offd = P_offd_i[i1];

1792:                 for (j=j_start; j < j_end; j++)

1793:                 {

1794:                    k1 = P_offd_pass[pass][j];

1795:                tmp_array_offd[k1] = cnt_offd;

1796:                P_offd_data[cnt_offd] = 0;

1797:                P_offd_j[cnt_offd++] = k1;

1798:                 }

1799:                 for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

1800:                 {

1801:                j1 = S_diag_j[j];

1802:                if (assigned[j1] == pass-1)

1803:                   tmp_marker[j1] = i1;

1804:                 }

1805:                 for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

1806:                 {

1807:                j1 = S_offd_j[j];

1808:                if (assigned_offd[j1] == pass-1)

1809:                   tmp_marker_offd[j1] = i1;

1810:                 }

1811:                 for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1812:                 {

1813:                j1 = A_diag_j[j];

1814:                if (tmp_marker[j1] == i1)

1815:                {

1816:                   for (k=P_diag_i[j1]; k < P_diag_i[j1+1]; k++)

1817:                   {

1818:                  k1 = P_diag_j[k];

1819:                      alfa = A_diag_data[j]*P_diag_data[k];

1820:                      P_diag_data[tmp_array[k1]] += alfa;

1821:                      sum_C += alfa;

1822:                      sum_N += alfa;

1823:                       }

1824:                   for (k=P_offd_i[j1]; k < P_offd_i[j1+1]; k++)

1825:                   {

1826:                  k1 = P_offd_j[k];

1827:                      alfa = A_diag_data[j]*P_offd_data[k];

1828:                      P_offd_data[tmp_array_offd[k1]] += alfa;

1829:                      sum_C += alfa;

1830:                      sum_N += alfa;

1831:                       }

1832:                    }

1833:                    else

1834:                    {

1835:                       if (CF_marker[j1] != -3 &&

1836:                 (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1837:                  sum_N += A_diag_data[j];

1838:                    }

1839:                 }

1840:                 for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++)

1841:                 {

1842:                if (col_offd_S_to_A)

1843:                   j1 = map_A_to_S[A_offd_j[j]];

1844:                else

1845:                   j1 = A_offd_j[j];

1846:

1847:                if (j1 > -1 && tmp_marker_offd[j1] == i1)

1848:                {

1849:                   j_start = Pext_start[j1];

1850:                   j_end = j_start+Pext_i[j1+1];

1851:                   for (k=j_start; k < j_end; k++)

1852:                   {

1853:                  k1 = Pext_pass[pass][k];

1854:                      alfa = A_offd_data[j]*Pext_data[k];

1855:                  if (k1 < 0)

1856:                         P_diag_data[tmp_array[-k1-1]] += alfa;

1857:                  else

1858:                         P_offd_data[tmp_array_offd[k1]] += alfa;

1859:                      sum_C += alfa;

1860:                      sum_N += alfa;

1861:                       }

1862:                    }

1863:                    else

1864:                    {

1865:                       if (CF_marker_offd[j1] != -3 &&

1866:                 (num_functions == 1 || dof_func_offd[j1] == dof_func[i1]))

1867:                  sum_N += A_offd_data[j];

1868:                    }

1869:                 }

1870:                 diagonal = A_diag_data[A_diag_i[i1]];

1871:                 if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal);

1872:

1873:                 for (j=P_diag_i[i1]; j < P_diag_i[i1+1]; j++)

1874:                P_diag_data[j] *= alfa;

1875:                 for (j=P_offd_i[i1]; j < P_offd_i[i1+1]; j++)

1876:                P_offd_data[j] *= alfa;

1877:              }

1878:              hypre_TFree(tmp_marker);

1879:              hypre_TFree(tmp_marker_offd);

1880:              hypre_TFree(tmp_array);

1881:              hypre_TFree(tmp_array_offd);

0x4354f0 SUB	SP, SP, #480

0x4354f4 STP	X29, X30, [SP, #384]

0x4354f8 STP	X28, X27, [SP, #400]

0x4354fc STP	X26, X25, [SP, #416]

0x435500 STP	X24, X23, [SP, #432]

0x435504 STP	X22, X21, [SP, #448]

0x435508 STP	X20, X19, [SP, #464]

0x43550c ADD	X29, SP, #384

0x435510 LDR	X8, [X29, #376]

0x435514 STUR	X7, [X29, #424]

0x435518 LDR	X0, [X2]

0x43551c ORR	X22, XZR, X6

0x435520 ORR	X26, XZR, X5

0x435524 ORR	X21, XZR, X4

0x435528 ORR	X24, XZR, X3

0x43552c ORR	X25, XZR, X2

0x435530 STR	X8, [SP, #136]

0x435534 LDR	X8, [X29, #368]

0x435538 STR	X8, [SP, #128]

0x43553c LDR	X8, [X29, #360]

0x435540 STR	X8, [SP, #120]

0x435544 LDR	X8, [X29, #352]

0x435548 STR	X8, [SP, #112]

0x43554c LDR	X8, [X29, #344]

0x435550 STR	X8, [SP, #104]

0x435554 LDR	X8, [X29, #336]

0x435558 STR	X8, [SP, #96]

0x43555c LDR	X8, [X29, #328]

0x435560 STR	X8, [SP, #88]

0x435564 LDR	X8, [X29, #320]

0x435568 STR	X8, [SP, #80]

0x43556c LDR	X8, [X29, #312]

0x435570 STR	X8, [SP, #72]

0x435574 LDP	X8, X20, [X29, #296]

0x435578 STUR	X8, [X29, #488]

0x43557c LDP	X8, X9, [X29, #280]

0x435580 STP	X8, X9, [X29, #944]

0x435584 LDR	X8, [X29, #272]

0x435588 STR	X8, [SP, #64]

0x43558c LDR	X8, [X29, #264]

0x435590 STR	X8, [SP, #160]

0x435594 LDP	X10, X9, [X29, #248]

0x435598 STUR	X9, [X29, #496]

0x43559c LDP	X11, X9, [X29, #232]

0x4355a0 STP	X9, X10, [X29, #960]

0x4355a4 LDP	X10, X9, [X29, #216]

0x4355a8 STP	X11, X9, [X29, #856]

0x4355ac LDP	X8, X9, [X29, #200]

0x4355b0 STUR	X8, [X29, #384]

0x4355b4 LDR	X8, [X29, #192]

0x4355b8 STP	X10, X9, [X29, #872]

0x4355bc STR	X8, [SP, #152]

0x4355c0 LDP	X10, X9, [X29, #176]

0x4355c4 STUR	X9, [X29, #472]

0x4355c8 LDP	X8, X9, [X29, #160]

0x4355cc STP	X10, X8, [X29, #904]

0x4355d0 LDR	X8, [X29, #152]

0x4355d4 STUR	X9, [X29, #376]

0x4355d8 STR	X8, [SP, #144]

0x4355dc LDP	X10, X9, [X29, #136]

0x4355e0 LDP	X27, X23, [X29, #104]

0x4355e4 LDR	X28, [X29, #96]

0x4355e8 STUR	X9, [X29, #464]

0x4355ec LDP	X8, X9, [X29, #120]

0x4355f0 STUR	X9, [X29, #336]

0x4355f4 STP	X10, X8, [X29, #920]

0x4355f8 CBZ	X0, 435634

0x4355fc MOVZ	W1, #8

0x435600 BL	4a6c90

0x435604 ORR	X19, XZR, X0

0x435608 LDR	X0, [X24]

0x43560c CBZ	X0, 435618

0x435610 MOVZ	W1, #8

0x435614 BL	4a6c90

0x435618 STUR	X0, [X29, #480]

0x43561c LDR	X0, [X21]

0x435620 CBZ	X0, 435644

0x435624 MOVZ	W1, #8

0x435628 BL	4a6c90

0x43562c ORR	X21, XZR, X0

0x435630 B	435648

0x435634 ORR	X19, XZR, XZR

0x435638 LDR	X0, [X24]

0x43563c CBNZ	X0, 435610

0x435640 B	435618

0x435644 ORR	X21, XZR, XZR

0x435648 LDR	X8, [X26]

0x43564c LDR	X9, [X22]

0x435650 MOVZ	W1, #8

0x435654 CMP	X8, X9

0x435658 CSEL	X0, X8, X9, #12

0x43565c BL	4a6c90

0x435660 LDR	X8, [X25]

0x435664 ORR	X22, XZR, X0

0x435668 CMP	X8, #1

0x43566c B.LT	435694

0x435670 MOVN	X9, #0

0x435674 ORR	X8, XZR, XZR

0x435678 HINT	#0

0x43567c HINT	#0

(750) 0x435680 STR	X9, [X19, X8,LSL #3]

(750) 0x435684 ADD	X8, X8, #1

(750) 0x435688 LDR	X10, [X25]

(750) 0x43568c CMP	X8, X10

(750) 0x435690 B.LT	435680

0x435694 LDR	X8, [X24]

0x435698 LDUR	X11, [X29, #480]

0x43569c CMP	X8, #1

0x4356a0 B.LT	4356c0

0x4356a4 MOVN	X9, #0

0x4356a8 ORR	X8, XZR, XZR

(749) 0x4356ac STR	X9, [X11, X8,LSL #3]

(749) 0x4356b0 ADD	X8, X8, #1

(749) 0x4356b4 LDR	X10, [X24]

(749) 0x4356b8 CMP	X8, X10

(749) 0x4356bc B.LT	4356ac

0x4356c0 BL	4a8a10

0x4356c4 ORR	X24, XZR, X0

0x4356c8 BL	4a89f0

0x4356cc LDR	X9, [X27]

0x4356d0 SUB	X11, X0, #1

0x4356d4 CMP	X24, X11

0x4356d8 SDIV	X10, X9, X0

0x4356dc MADD	X8, X10, X24, XZR

0x4356e0 ADD	X10, X10, X8

0x4356e4 CSEL	X9, X9, X10, #0

0x4356e8 CMP	X8, X9

0x4356ec B.GE	435f38

0x4356f0 LDUR	X10, [X29, #424]

0x4356f4 LDUR	X12, [X29, #464]

0x4356f8 LDR	X11, [X28]

0x4356fc LDR	X10, [X10]

0x435700 LDR	X13, [X12]

0x435704 LDR	X12, [SP, #144]

0x435708 LDR	X15, [X12]

0x43570c LDUR	X12, [X29, #472]

0x435710 LDR	X10, [X10, X11,LSL #3]

0x435714 LDR	X11, [X23]

0x435718 LDR	X16, [X12]

0x43571c LDR	X12, [SP, #152]

0x435720 STUR	X11, [X29, #424]

0x435724 LDUR	X11, [X29, #416]

0x435728 ADD	X9, X9, X10

0x43572c LDR	X11, [X11]

0x435730 LDR	X12, [X12]

0x435734 STUR	X11, [X29, #416]

0x435738 LDUR	X11, [X29, #336]

0x43573c LDR	X14, [X11]

0x435740 LDUR	X11, [X29, #408]

0x435744 LDR	X0, [X11]

0x435748 LDUR	X11, [X29, #400]

0x43574c LDR	X11, [X11]

0x435750 STUR	X11, [X29, #400]

0x435754 LDUR	X11, [X29, #376]

0x435758 STUR	X9, [X29, #376]

0x43575c ADD	X9, X8, X10

0x435760 LDP	X8, X10, [X29, #872]

0x435764 LDR	X3, [X10]

0x435768 LDR	X4, [X8]

0x43576c LDP	X8, X10, [X29, #856]

0x435770 LDR	X17, [X11]

0x435774 LDUR	X11, [X29, #392]

0x435778 LDR	X5, [X10]

0x43577c LDR	X6, [X8]

0x435780 LDP	X10, X8, [X29, #960]

0x435784 LDR	X1, [X11]

0x435788 LDUR	X11, [X29, #384]

0x43578c LDR	X8, [X8]

0x435790 LDR	X2, [X11]

0x435794 LDR	X7, [X10]

0x435798 ADD	X10, X13, #8

0x43579c STUR	X8, [X29, #328]

0x4357a0 LDUR	X8, [X29, #496]

0x4357a4 LDR	X8, [X8]

0x4357a8 STUR	X8, [X29, #496]

0x4357ac LDUR	X8, [X29, #488]

0x4357b0 LDR	X8, [X8]

0x4357b4 STR	X8, [SP, #192]

0x4357b8 LDR	X8, [X20]

0x4357bc STUR	X8, [X29, #488]

0x4357c0 LDR	X8, [SP, #160]

0x4357c4 STP	X12, X15, [SP, #48]

0x4357c8 STR	X16, [SP, #168]

0x4357cc LDR	X8, [X8]

0x4357d0 STP	X13, X8, [SP, #176]

0x4357d4 ADD	X8, X15, #8

0x4357d8 STP	X8, X10, [SP, #32]

0x4357dc ADD	X10, X16, #8

0x4357e0 ADD	X8, X12, #8

0x4357e4 STP	X8, X10, [SP, #16]

0x4357e8 ADD	X10, X13, #16

0x4357ec ADD	X8, X16, #16

0x4357f0 STP	X8, X10, [SP]

0x4357f4 STUR	X0, [X29, #408]

0x4357f8 STP	X2, X1, [X29, #896]

0x4357fc STP	X4, X3, [X29, #872]

0x435800 STP	X6, X5, [X29, #856]

0x435804 STUR	X7, [X29, #336]

0x435808 B	435820

    (734) 0x43580c LDUR	X9, [X29, #456]

    (734) 0x435810 LDUR	X8, [X29, #376]

    (734) 0x435814 ADD	X9, X9, #1

    (734) 0x435818 CMP	X9, X8

    (734) 0x43581c B.GE	435f38

    (734) 0x435820 LDP	X8, X10, [X29, #928]

    (734) 0x435824 STUR	X9, [X29, #456]

    (734) 0x435828 LDR	X11, [X10, X9,LSL #3]

    (734) 0x43582c LDR	X9, [X8, X11,LSL #3]

    (734) 0x435830 ADD	X8, X11, #1

    (734) 0x435834 LDR	X12, [X14, X11,LSL #3]

    (734) 0x435838 LDR	X13, [X14, X8,LSL #3]

    (734) 0x43583c ADD	X10, X13, X9

    (734) 0x435840 SUB	X10, X10, X12

    (734) 0x435844 CMP	X9, X10

    (734) 0x435848 B.GE	4358e8

    (734) 0x43584c SUB	W16, W13, W12

    (734) 0x435850 ADD	X15, X12, #1

    (734) 0x435854 TBZ	W16, #0, 435880

    (734) 0x435858 LDR	X16, [X28]

    (734) 0x43585c LDR	X18, [SP, #176]

    (734) 0x435860 LDR	X16, [X0, X16,LSL #3]

    (734) 0x435864 STR	XZR, [X18, X12,LSL #3]

    (734) 0x435868 LDR	X18, [SP, #56]

    (734) 0x43586c LDR	X16, [X16, X9,LSL #3]

    (734) 0x435870 ADD	X9, X9, #1

    (734) 0x435874 STR	X12, [X21, X16,LSL #3]

    (734) 0x435878 STR	X16, [X18, X12,LSL #3]

    (734) 0x43587c ORR	X12, XZR, X15

    (734) 0x435880 CMP	X13, X15

    (734) 0x435884 B.EQ	4358e8

    (734) 0x435888 LDP	X15, X13, [SP, #32]

    (734) 0x43588c ADD	X13, X13, X12,LSL #3

    (734) 0x435890 ADD	X16, X15, X12,LSL #3

    (734) 0x435894 HINT	#0

    (734) 0x435898 HINT	#0

    (734) 0x43589c HINT	#0

      (744) 0x4358a0 LDR	X15, [X28]

      (744) 0x4358a4 ADD	X18, X12, #1

      (744) 0x4358a8 LDR	X15, [X0, X15,LSL #3]

      (744) 0x4358ac LDR	X15, [X15, X9,LSL #3]

      (744) 0x4358b0 STR	X12, [X21, X15,LSL #3]

      (744) 0x4358b4 STP	XZR, XZR, [X13, #1016]

      (744) 0x4358b8 STUR	X15, [X16, #504]

      (744) 0x4358bc ADD	X13, X13, #16

      (744) 0x4358c0 ADD	X12, X12, #2

      (744) 0x4358c4 LDR	X15, [X28]

      (744) 0x4358c8 LDR	X15, [X0, X15,LSL #3]

      (744) 0x4358cc ADD	X15, X15, X9,LSL #3

      (744) 0x4358d0 ADD	X9, X9, #2

      (744) 0x4358d4 LDR	X15, [X15, #8]

      (744) 0x4358d8 STR	X18, [X21, X15,LSL #3]

      (744) 0x4358dc STR	X15, [X16], #16

      (744) 0x4358e0 CMP	X10, X9

      (744) 0x4358e4 B.NE	4358a0

    (734) 0x4358e8 LDUR	X9, [X29, #400]

    (734) 0x4358ec LDR	X13, [X17, X8,LSL #3]

    (734) 0x4358f0 LDR	X12, [X17, X11,LSL #3]

    (734) 0x4358f4 LDR	X9, [X9, X11,LSL #3]

    (734) 0x4358f8 ADD	X10, X13, X9

    (734) 0x4358fc SUB	X10, X10, X12

    (734) 0x435900 CMP	X9, X10

    (734) 0x435904 B.GE	4359a8

    (734) 0x435908 SUB	W16, W13, W12

    (734) 0x43590c ADD	X15, X12, #1

    (734) 0x435910 TBZ	W16, #0, 43593c

    (734) 0x435914 LDR	X16, [X28]

    (734) 0x435918 LDR	X18, [SP, #168]

    (734) 0x43591c LDR	X16, [X1, X16,LSL #3]

    (734) 0x435920 STR	XZR, [X18, X12,LSL #3]

    (734) 0x435924 LDR	X18, [SP, #48]

    (734) 0x435928 LDR	X16, [X16, X9,LSL #3]

    (734) 0x43592c ADD	X9, X9, #1

    (734) 0x435930 STR	X12, [X22, X16,LSL #3]

    (734) 0x435934 STR	X16, [X18, X12,LSL #3]

    (734) 0x435938 ORR	X12, XZR, X15

    (734) 0x43593c CMP	X13, X15

    (734) 0x435940 B.EQ	4359a8

    (734) 0x435944 LDP	X15, X13, [SP, #16]

    (734) 0x435948 ADD	X13, X13, X12,LSL #3

    (734) 0x43594c ADD	X16, X15, X12,LSL #3

    (734) 0x435950 HINT	#0

    (734) 0x435954 HINT	#0

    (734) 0x435958 HINT	#0

    (734) 0x43595c HINT	#0

      (743) 0x435960 LDR	X15, [X28]

      (743) 0x435964 ADD	X18, X12, #1

      (743) 0x435968 LDR	X15, [X1, X15,LSL #3]

      (743) 0x43596c LDR	X15, [X15, X9,LSL #3]

      (743) 0x435970 STR	X12, [X22, X15,LSL #3]

      (743) 0x435974 STP	XZR, XZR, [X13, #1016]

      (743) 0x435978 STUR	X15, [X16, #504]

      (743) 0x43597c ADD	X13, X13, #16

      (743) 0x435980 ADD	X12, X12, #2

      (743) 0x435984 LDR	X15, [X28]

      (743) 0x435988 LDR	X15, [X1, X15,LSL #3]

      (743) 0x43598c ADD	X15, X15, X9,LSL #3

      (743) 0x435990 ADD	X9, X9, #2

      (743) 0x435994 LDR	X15, [X15, #8]

      (743) 0x435998 STR	X18, [X22, X15,LSL #3]

      (743) 0x43599c STR	X15, [X16], #16

      (743) 0x4359a0 CMP	X10, X9

      (743) 0x4359a4 B.NE	435960

    (734) 0x4359a8 LDR	X9, [X2, X11,LSL #3]

    (734) 0x4359ac LDR	X10, [X2, X8,LSL #3]

    (734) 0x4359b0 LDUR	X16, [X29, #480]

    (734) 0x4359b4 CMP	X9, X10

    (734) 0x4359b8 B.LT	435a0c

    (734) 0x4359bc LDR	X9, [X5, X11,LSL #3]

    (734) 0x4359c0 LDR	X10, [X5, X8,LSL #3]

    (734) 0x4359c4 B	4359cc

      (741) 0x4359c8 ADD	X9, X9, #1

      (741) 0x4359cc CMP	X9, X10

      (741) 0x4359d0 B.GE	435a40

      (741) 0x4359d4 LDR	X12, [X6, X9,LSL #3]

      (741) 0x4359d8 LDR	X15, [X28]

      (741) 0x4359dc LDR	X13, [X7, X12,LSL #3]

      (741) 0x4359e0 SUB	X15, X15, #1

      (741) 0x4359e4 CMP	X13, X15

      (741) 0x4359e8 B.NE	4359c8

      (741) 0x4359ec STR	X11, [X16, X12,LSL #3]

      (741) 0x4359f0 LDR	X10, [X5, X8,LSL #3]

      (741) 0x4359f4 B	4359c8

0x4359f8 HINT	#0

0x4359fc HINT	#0

      (742) 0x435a00 ADD	X9, X9, #1

      (742) 0x435a04 CMP	X9, X10

      (742) 0x435a08 B.GE	4359bc

      (742) 0x435a0c LDR	X12, [X3, X9,LSL #3]

      (742) 0x435a10 LDR	X15, [X28]

      (742) 0x435a14 LDR	X13, [X4, X12,LSL #3]

      (742) 0x435a18 SUB	X15, X15, #1

      (742) 0x435a1c CMP	X13, X15

      (742) 0x435a20 B.NE	435a00

      (742) 0x435a24 STR	X11, [X19, X12,LSL #3]

      (742) 0x435a28 LDR	X10, [X2, X8,LSL #3]

      (742) 0x435a2c B	435a00

0x435a30 HINT	#0

0x435a34 HINT	#0

0x435a38 HINT	#0

0x435a3c HINT	#0

    (734) 0x435a40 LDUR	X9, [X29, #328]

    (734) 0x435a44 MOVI	D2, #0

    (734) 0x435a48 LDR	X10, [X9, X11,LSL #3]

    (734) 0x435a4c LDR	X12, [X9, X8,LSL #3]

    (734) 0x435a50 ADD	X13, X10, #1

    (734) 0x435a54 STUR	X10, [X29, #448]

    (734) 0x435a58 CMP	X13, X12

    (734) 0x435a5c B.GE	435ca0

    (734) 0x435a60 LDR	X9, [SP, #64]

    (734) 0x435a64 MOVI	D1, #0

    (734) 0x435a68 LDR	X16, [X9]

    (734) 0x435a6c LDP	X10, X9, [X29, #944]

    (734) 0x435a70 LDR	X1, [X10]

    (734) 0x435a74 LDR	X10, [SP, #160]

    (734) 0x435a78 LDR	X9, [X9]

    (734) 0x435a7c LDR	X24, [X10]

    (734) 0x435a80 LDR	X10, [SP, #144]

    (734) 0x435a84 LDR	X4, [X10]

    (734) 0x435a88 LDUR	X10, [X29, #464]

    (734) 0x435a8c LDR	X23, [X10]

    (734) 0x435a90 LDR	X10, [SP, #152]

    (734) 0x435a94 ADD	X6, X4, #8

    (734) 0x435a98 LDR	X27, [X10]

    (734) 0x435a9c LDUR	X10, [X29, #472]

    (734) 0x435aa0 ADD	X7, X23, #8

    (734) 0x435aa4 LDR	X10, [X10]

    (734) 0x435aa8 ADD	X20, X27, #8

    (734) 0x435aac ADD	X25, X10, #8

    (734) 0x435ab0 B	435acc

      (738) 0x435ab4 LDR	D3, [X24, X13,LSL #3]

      (738) 0x435ab8 FADD	D1, D3, D1

      (738) 0x435abc HINT	#0

      (738) 0x435ac0 ADD	X13, X13, #1

      (738) 0x435ac4 CMP	X13, X12

      (738) 0x435ac8 B.EQ	435ca4

      (738) 0x435acc LDUR	X15, [X29, #496]

      (738) 0x435ad0 LDR	X2, [X15, X13,LSL #3]

      (738) 0x435ad4 LDR	X15, [X19, X2,LSL #3]

      (738) 0x435ad8 CMP	X15, X11

      (738) 0x435adc B.NE	435b0c

      (738) 0x435ae0 ADD	X0, X2, #1

      (738) 0x435ae4 LDR	X26, [X14, X2,LSL #3]

      (738) 0x435ae8 LDR	X3, [X14, X0,LSL #3]

      (738) 0x435aec CMP	X3, X26

      (738) 0x435af0 B.LE	435bd8

      (738) 0x435af4 SUB	W18, W3, W26

      (738) 0x435af8 ADD	X15, X26, #1

      (738) 0x435afc TBNZ	W18, #0, 435b34

      (738) 0x435b00 CMP	X3, X15

      (738) 0x435b04 B.NE	435b68

      (738) 0x435b08 B	435bd8

      (738) 0x435b0c LDR	X15, [X16, X2,LSL #3]

      (738) 0x435b10 CMN	X15, #3

      (738) 0x435b14 B.EQ	435ac0

      (738) 0x435b18 CMP	X1, #1

      (738) 0x435b1c B.EQ	435ab4

      (738) 0x435b20 LDR	X15, [X9, X11,LSL #3]

      (738) 0x435b24 LDR	X18, [X9, X2,LSL #3]

      (738) 0x435b28 CMP	X15, X18

      (738) 0x435b2c B.EQ	435ab4

      (738) 0x435b30 B	435ac0

      (738) 0x435b34 LDR	X18, [X4, X26,LSL #3]

      (738) 0x435b38 LDR	D0, [X24, X13,LSL #3]

      (738) 0x435b3c LDR	D3, [X23, X26,LSL #3]

      (738) 0x435b40 ORR	X26, XZR, X15

      (738) 0x435b44 FMUL	D0, D3, D0

      (738) 0x435b48 LDR	X18, [X21, X18,LSL #3]

      (738) 0x435b4c LDR	D3, [X23, X18,LSL #3]

      (738) 0x435b50 FADD	D2, D0, D2

      (738) 0x435b54 FADD	D1, D0, D1

      (738) 0x435b58 FADD	D3, D3, D0

      (738) 0x435b5c STR	D3, [X23, X18,LSL #3]

      (738) 0x435b60 CMP	X3, X15

      (738) 0x435b64 B.EQ	435bd8

      (738) 0x435b68 SUB	X3, X3, X26

      (738) 0x435b6c ADD	X5, X6, X26,LSL #3

      (738) 0x435b70 ADD	X26, X7, X26,LSL #3

      (738) 0x435b74 HINT	#0

      (738) 0x435b78 HINT	#0

      (738) 0x435b7c HINT	#0

        (740) 0x435b80 LDP	X15, X18, [X5, #1016]

        (740) 0x435b84 LDR	D0, [X24, X13,LSL #3]

        (740) 0x435b88 LDUR	D3, [X26, #504]

        (740) 0x435b8c SUBS	X3, X3, #2

        (740) 0x435b90 ADD	X5, X5, #16

        (740) 0x435b94 FMUL	D0, D3, D0

        (740) 0x435b98 LDR	X15, [X21, X15,LSL #3]

        (740) 0x435b9c LDR	D3, [X23, X15,LSL #3]

        (740) 0x435ba0 FADD	D2, D0, D2

        (740) 0x435ba4 FADD	D1, D0, D1

        (740) 0x435ba8 FADD	D3, D3, D0

        (740) 0x435bac STR	D3, [X23, X15,LSL #3]

        (740) 0x435bb0 LDR	X15, [X21, X18,LSL #3]

        (740) 0x435bb4 LDR	D0, [X24, X13,LSL #3]

        (740) 0x435bb8 LDR	D3, [X26], #16

        (740) 0x435bbc FMUL	D0, D3, D0

        (740) 0x435bc0 LDR	D3, [X23, X15,LSL #3]

        (740) 0x435bc4 FADD	D2, D0, D2

        (740) 0x435bc8 FADD	D1, D0, D1

        (740) 0x435bcc FADD	D3, D3, D0

        (740) 0x435bd0 STR	D3, [X23, X15,LSL #3]

        (740) 0x435bd4 B.NE	435b80

      (738) 0x435bd8 LDR	X3, [X17, X2,LSL #3]

      (738) 0x435bdc LDR	X0, [X17, X0,LSL #3]

      (738) 0x435be0 CMP	X0, X3

      (738) 0x435be4 B.LE	435ac0

      (738) 0x435be8 SUB	W18, W0, W3

      (738) 0x435bec ADD	X15, X3, #1

      (738) 0x435bf0 TBNZ	W18, #0, 435c00

      (738) 0x435bf4 CMP	X0, X15

      (738) 0x435bf8 B.EQ	435ac0

      (738) 0x435bfc B	435c34

      (738) 0x435c00 LDR	X18, [X27, X3,LSL #3]

      (738) 0x435c04 LDR	D0, [X24, X13,LSL #3]

      (738) 0x435c08 LDR	D3, [X10, X3,LSL #3]

      (738) 0x435c0c ORR	X3, XZR, X15

      (738) 0x435c10 FMUL	D0, D3, D0

      (738) 0x435c14 LDR	X18, [X22, X18,LSL #3]

      (738) 0x435c18 LDR	D3, [X10, X18,LSL #3]

      (738) 0x435c1c FADD	D2, D0, D2

      (738) 0x435c20 FADD	D1, D0, D1

      (738) 0x435c24 FADD	D3, D3, D0

      (738) 0x435c28 STR	D3, [X10, X18,LSL #3]

      (738) 0x435c2c CMP	X0, X15

      (738) 0x435c30 B.EQ	435ac0

      (738) 0x435c34 SUB	X0, X0, X3

      (738) 0x435c38 ADD	X2, X20, X3,LSL #3

      (738) 0x435c3c ADD	X3, X25, X3,LSL #3

        (739) 0x435c40 LDP	X15, X18, [X2, #1016]

        (739) 0x435c44 LDR	D0, [X24, X13,LSL #3]

        (739) 0x435c48 LDUR	D3, [X3, #504]

        (739) 0x435c4c SUBS	X0, X0, #2

        (739) 0x435c50 ADD	X2, X2, #16

        (739) 0x435c54 FMUL	D0, D3, D0

        (739) 0x435c58 LDR	X15, [X22, X15,LSL #3]

        (739) 0x435c5c LDR	D3, [X10, X15,LSL #3]

        (739) 0x435c60 FADD	D2, D0, D2

        (739) 0x435c64 FADD	D1, D0, D1

        (739) 0x435c68 FADD	D3, D3, D0

        (739) 0x435c6c STR	D3, [X10, X15,LSL #3]

        (739) 0x435c70 LDR	X15, [X22, X18,LSL #3]

        (739) 0x435c74 LDR	D0, [X24, X13,LSL #3]

        (739) 0x435c78 LDR	D3, [X3], #16

        (739) 0x435c7c FMUL	D0, D3, D0

        (739) 0x435c80 LDR	D3, [X10, X15,LSL #3]

        (739) 0x435c84 FADD	D2, D0, D2

        (739) 0x435c88 FADD	D1, D0, D1

        (739) 0x435c8c FADD	D3, D3, D0

        (739) 0x435c90 STR	D3, [X10, X15,LSL #3]

        (739) 0x435c94 B.NE	435c40

      (738) 0x435c98 B	435ac0

0x435c9c HINT	#0

    (734) 0x435ca0 MOVI	D1, #0

    (734) 0x435ca4 LDR	X10, [SP, #192]

    (734) 0x435ca8 LDR	X9, [X10, X11,LSL #3]

    (734) 0x435cac LDR	X10, [X10, X8,LSL #3]

    (734) 0x435cb0 CMP	X9, X10

    (734) 0x435cb4 B.GE	435e08

  (736) 0x435cb8 LDR	X15, [SP, #128]

  (736) 0x435cbc LDP	X12, X13, [SP, #72]

  (736) 0x435cc0 LDR	X5, [X28]

  (736) 0x435cc4 LDR	X16, [X15]

  (736) 0x435cc8 LDUR	X15, [X29, #432]

  (736) 0x435ccc LDR	X12, [X12]

  (736) 0x435cd0 LDR	X13, [X13]

  (736) 0x435cd4 LDR	X1, [X15]

  (736) 0x435cd8 LDR	X15, [SP, #136]

  (736) 0x435cdc LDR	X23, [X15]

  (736) 0x435ce0 LDUR	X15, [X29, #440]

  (736) 0x435ce4 LDR	X24, [X15]

  (736) 0x435ce8 LDR	X15, [SP, #112]

  (736) 0x435cec LDR	X2, [X15]

  (736) 0x435cf0 LDR	X15, [SP, #88]

  (736) 0x435cf4 LDR	X26, [X15]

  (736) 0x435cf8 LDR	X15, [SP, #96]

  (736) 0x435cfc LDR	X15, [X15]

  (736) 0x435d00 ADD	X27, X15, #8

  (736) 0x435d04 LDR	X15, [SP, #104]

  (736) 0x435d08 LDR	X0, [X15]

  (736) 0x435d0c LDR	X15, [SP, #120]

  (736) 0x435d10 LDR	X3, [X15]

  (736) 0x435d14 B	435d34

0x435d18 HINT	#0

0x435d1c HINT	#0

(735) 0x435d20 LDR	D3, [X2, X9,LSL #3]

(735) 0x435d24 FADD	D1, D3, D1

  (736) 0x435d28 ADD	X9, X9, #1

  (736) 0x435d2c CMP	X9, X10

  (736) 0x435d30 B.EQ	435e08

  (736) 0x435d34 LDUR	X18, [X29, #488]

  (736) 0x435d38 ADD	X15, X13, X9,LSL #3

  (736) 0x435d3c CBZ	X18, 435d48

  (736) 0x435d40 LDR	X15, [X15]

  (736) 0x435d44 ADD	X15, X12, X15,LSL #3

  (736) 0x435d48 LDR	X15, [X15]

  (736) 0x435d4c TBNZ	X15, #63, 435de0

  (736) 0x435d50 LDUR	X18, [X29, #480]

  (736) 0x435d54 LDR	X18, [X18, X15,LSL #3]

  (736) 0x435d58 CMP	X18, X11

  (736) 0x435d5c B.NE	435de0

  (736) 0x435d60 LDR	X18, [X27, X15,LSL #3]

  (736) 0x435d64 CMP	X18, #1

  (736) 0x435d68 B.LT	435d28

  (736) 0x435d6c LDR	X4, [X26, X15,LSL #3]

  (736) 0x435d70 LDR	X6, [X0, X5,LSL #3]

  (736) 0x435d74 ADD	X15, X18, X4

  (736) 0x435d78 LDUR	X18, [X29, #472]

  (736) 0x435d7c LDR	X7, [X18]

  (736) 0x435d80 LDUR	X18, [X29, #464]

  (736) 0x435d84 LDR	X18, [X18]

    (737) 0x435d88 LDR	X25, [X6, X4,LSL #3]

    (737) 0x435d8c LDR	D0, [X2, X9,LSL #3]

    (737) 0x435d90 LDR	D3, [X3, X4,LSL #3]

    (737) 0x435d94 ADD	X4, X4, #1

    (737) 0x435d98 ORN	X20, XZR, X25

    (737) 0x435d9c ADD	X30, X22, X25,LSL #3

    (737) 0x435da0 CMP	X25, #0

    (737) 0x435da4 ADD	X20, X21, X20,LSL #3

    (737) 0x435da8 CSEL	X25, X18, X7, #11

    (737) 0x435dac CSEL	X20, X20, X30, #11

    (737) 0x435db0 FMUL	D0, D3, D0

    (737) 0x435db4 LDR	X20, [X20]

    (737) 0x435db8 FADD	D2, D0, D2

    (737) 0x435dbc FADD	D1, D0, D1

    (737) 0x435dc0 LDR	D3, [X25, X20,LSL #3]

    (737) 0x435dc4 FADD	D3, D3, D0

    (737) 0x435dc8 STR	D3, [X25, X20,LSL #3]

    (737) 0x435dcc CMP	X4, X15

    (737) 0x435dd0 B.LT	435d88

  (736) 0x435dd4 B	435d28

0x435dd8 HINT	#0

0x435ddc HINT	#0

(735) 0x435de0 LDR	X18, [X16, X15,LSL #3]

(735) 0x435de4 CMN	X18, #3

(735) 0x435de8 B.EQ	435d28

(735) 0x435dec CMP	X1, #1

(735) 0x435df0 B.EQ	435d20

(735) 0x435df4 LDR	X15, [X23, X15,LSL #3]

(735) 0x435df8 LDR	X18, [X24, X11,LSL #3]

(735) 0x435dfc CMP	X15, X18

(735) 0x435e00 B.EQ	435d20

(735) 0x435e04 B	435d28

    (734) 0x435e08 LDR	X9, [SP, #184]

    (734) 0x435e0c LDUR	X10, [X29, #448]

    (734) 0x435e10 LDR	D3, [X9, X10,LSL #3]

    (734) 0x435e14 FMUL	D2, D3, D2

    (734) 0x435e18 FCMP	D2, #0

    (734) 0x435e1c B.EQ	435e28

    (734) 0x435e20 FNEG	D0, D1

    (734) 0x435e24 FDIV	D0, D0, D2

    (734) 0x435e28 LDR	X15, [X14, X11,LSL #3]

    (734) 0x435e2c LDR	X9, [X14, X8,LSL #3]

    (734) 0x435e30 LDUR	X0, [X29, #408]

    (734) 0x435e34 SUBS	X10, X9, X15

    (734) 0x435e38 LDP	X2, X1, [X29, #896]

    (734) 0x435e3c LDP	X4, X3, [X29, #872]

    (734) 0x435e40 LDP	X6, X5, [X29, #856]

    (734) 0x435e44 LDUR	X7, [X29, #336]

    (734) 0x435e48 B.LE	435eb4

    (734) 0x435e4c ORR	X12, XZR, X15

    (734) 0x435e50 CMP	X10, #4

    (734) 0x435e54 B.CC	435e90

    (734) 0x435e58 LDR	X16, [SP, #8]

    (734) 0x435e5c AND	X13, X10, #8062

    (734) 0x435e60 ADD	X12, X15, X13

    (734) 0x435e64 ADD	X15, X16, X15,LSL #3

    (734) 0x435e68 ORR	X16, XZR, X13

      (748) 0x435e6c LDP	Q1, Q2, [X15, #2032]

      (748) 0x435e70 SUBS	X16, X16, #4

      (748) 0x435e74 FMUL	V2.2D, V2.2D, V0.D[0]

      (748) 0x435e78 FMUL	V1.2D, V1.2D, V0.D[0]

      (748) 0x435e7c STP	Q1, Q2, [X15, #2032]

      (748) 0x435e80 ADD	X15, X15, #32

      (748) 0x435e84 B.NE	435e6c

    (734) 0x435e88 CMP	X10, X13

    (734) 0x435e8c B.EQ	435eb4

    (734) 0x435e90 LDR	X10, [SP, #176]

    (734) 0x435e94 SUB	X9, X9, X12

    (734) 0x435e98 ADD	X10, X10, X12,LSL #3

    (734) 0x435e9c HINT	#0

      (747) 0x435ea0 LDR	D1, [X10]

      (747) 0x435ea4 SUBS	X9, X9, #1

      (747) 0x435ea8 FMUL	D1, D1, D0

      (747) 0x435eac STR	D1, [X10], #8

      (747) 0x435eb0 B.NE	435ea0

    (734) 0x435eb4 LDR	X12, [X17, X11,LSL #3]

    (734) 0x435eb8 LDR	X8, [X17, X8,LSL #3]

    (734) 0x435ebc SUBS	X9, X8, X12

    (734) 0x435ec0 B.LE	43580c

    (734) 0x435ec4 ORR	X10, XZR, X12

    (734) 0x435ec8 CMP	X9, #4

    (734) 0x435ecc B.CC	435f08

    (734) 0x435ed0 LDR	X13, [SP]

    (734) 0x435ed4 AND	X11, X9, #8062

    (734) 0x435ed8 ADD	X10, X12, X11

    (734) 0x435edc ADD	X12, X13, X12,LSL #3

    (734) 0x435ee0 ORR	X13, XZR, X11

      (746) 0x435ee4 LDP	Q1, Q2, [X12, #2032]

      (746) 0x435ee8 SUBS	X13, X13, #4

      (746) 0x435eec FMUL	V2.2D, V2.2D, V0.D[0]

      (746) 0x435ef0 FMUL	V1.2D, V1.2D, V0.D[0]

      (746) 0x435ef4 STP	Q1, Q2, [X12, #2032]

      (746) 0x435ef8 ADD	X12, X12, #32

      (746) 0x435efc B.NE	435ee4

    (734) 0x435f00 CMP	X9, X11

    (734) 0x435f04 B.EQ	43580c

    (734) 0x435f08 LDR	X9, [SP, #168]

    (734) 0x435f0c SUB	X8, X8, X10

    (734) 0x435f10 ADD	X9, X9, X10,LSL #3

    (734) 0x435f14 HINT	#0

    (734) 0x435f18 HINT	#0

    (734) 0x435f1c HINT	#0

      (745) 0x435f20 LDR	D1, [X9]

      (745) 0x435f24 SUBS	X8, X8, #1

      (745) 0x435f28 FMUL	D1, D1, D0

      (745) 0x435f2c STR	D1, [X9], #8

      (745) 0x435f30 B.NE	435f20

    (734) 0x435f34 B	43580c

0x435f38 ORR	X0, XZR, X19

0x435f3c BL	4a6d90

0x435f40 LDUR	X0, [X29, #480]

0x435f44 BL	4a6d90

0x435f48 ORR	X0, XZR, X21

0x435f4c BL	4a6d90

0x435f50 ORR	X0, XZR, X22

0x435f54 LDP	X20, X19, [SP, #464]

0x435f58 LDP	X22, X21, [SP, #448]

0x435f5c LDP	X24, X23, [SP, #432]

0x435f60 LDP	X26, X25, [SP, #416]

0x435f64 LDP	X28, X27, [SP, #400]

0x435f68 LDP	X29, X30, [SP, #384]

0x435f6c ADD	SP, SP, #480

0x435f70 B	4a6d90

0x435f74 HINT	#0

0x435f78 HINT	#0

0x435f7c HINT	#0

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	par_multi_interp.c:1737-1881
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1737,1747-1881.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 59% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 46.17 to 37.42 cycles (1.23x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 46.17 to 4.50 cycles (10.26x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 840 bytes. The binary function is storing 584 bytes.

General properties

nb instructions	218
loop length	872
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

25.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	10.00	10.00	8.83	8.83	8.83	8.83	8.83	8.83	0.00	0.00	0.00	0.00	46.17	45.83	46.00	26.50	26.50
cycles	10.00	10.00	8.83	8.83	8.83	8.83	8.83	8.83	0.00	0.00	0.00	0.00	46.17	45.83	46.00	26.50	26.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	25.25
Overall L1	46.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 46.17 cycles. At this rate:

18% of peak load performance is reached (18.19 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.65 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4354f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #480	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #384	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X7, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X22, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X26, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X21, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X24, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X25, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #312]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X20, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X8, X9, [X29, #944]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X8, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X9, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X11, X9, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X9, X10, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X10, X9, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X11, X9, [X29, #856]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X8, X9, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X10, X9, [X29, #872]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X9, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X10, X8, [X29, #904]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X8, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X9, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X27, X23, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X28, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X10, X8, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
CBZ X0, 435634 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CBZ X0, 435618 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR X0, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CBZ X0, 435644 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x154>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 435648 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x158>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CBNZ X0, 435610 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 435618 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP X8, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X0, X8, X9, #12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X22, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 435694 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x1a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X11, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 4356c0 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x1d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a8a10 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a89f0 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X27]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB X11, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X24, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
SDIV X10, X9, X0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MADD X8, X10, X24, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X10, X10, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CSEL X9, X9, X10, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X8, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 435f38 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0xa48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X10, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X12, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X28]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X12, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X12, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X12, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X11, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X9, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X11, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X11, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X11, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X11, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X9, X8, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X8, X10, [X29, #872]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X3, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X4, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X8, X10, [X29, #856]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X17, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X11, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X6, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X10, X8, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X1, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X11, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X10, X13, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X8, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X12, X15, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X16, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X13, X8, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X8, X15, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X8, X10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X10, X16, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X8, X12, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X8, X10, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X10, X13, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X8, X16, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X8, X10, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X0, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X2, X1, [X29, #896]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X4, X3, [X29, #872]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X6, X5, [X29, #856]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X7, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 435820 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x330>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X0, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X20, X19, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X26, X25, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X28, X27, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X29, X30, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #480	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 4a6d90 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	par_multi_interp.c:1737-1881
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1737,1747-1881.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 46.17 to 4.50 cycles (10.26x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 840 bytes. The binary function is storing 584 bytes.

General properties

nb instructions	218
loop length	872
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

25.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	10.00	10.00	8.83	8.83	8.83	8.83	8.83	8.83	0.00	0.00	0.00	0.00	46.17	45.83	46.00	26.50	26.50
cycles	10.00	10.00	8.83	8.83	8.83	8.83	8.83	8.83	0.00	0.00	0.00	0.00	46.17	45.83	46.00	26.50	26.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	25.25
Overall L1	46.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 46.17 cycles. At this rate:

18% of peak load performance is reached (18.19 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.65 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4354f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #480	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #384	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X7, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X22, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X26, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X21, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X24, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X25, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #312]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X20, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X8, X9, [X29, #944]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X8, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X9, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X11, X9, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X9, X10, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X10, X9, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X11, X9, [X29, #856]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X8, X9, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X10, X9, [X29, #872]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X9, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X10, X8, [X29, #904]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X8, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X9, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X27, X23, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X28, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X10, X8, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
CBZ X0, 435634 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CBZ X0, 435618 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR X0, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CBZ X0, 435644 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x154>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 435648 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x158>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CBNZ X0, 435610 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 435618 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP X8, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X0, X8, X9, #12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X22, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 435694 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x1a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X11, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 4356c0 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x1d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a8a10 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a89f0 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X27]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB X11, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X24, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
SDIV X10, X9, X0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MADD X8, X10, X24, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X10, X10, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CSEL X9, X9, X10, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X8, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 435f38 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0xa48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X10, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X12, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X28]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X12, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X12, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X12, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X11, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X9, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X11, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X11, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X11, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X11, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X9, X8, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X8, X10, [X29, #872]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X3, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X4, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X8, X10, [X29, #856]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X17, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X11, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X6, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X10, X8, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X1, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X11, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X10, X13, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X8, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X12, X15, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X16, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X13, X8, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X8, X15, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X8, X10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X10, X16, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X8, X12, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X8, X10, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X10, X13, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X8, X16, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X8, X10, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X0, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X2, X1, [X29, #896]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X4, X3, [X29, #872]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X6, X5, [X29, #856]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X7, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 435820 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x330>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X0, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X20, X19, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X26, X25, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X28, X27, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X29, X30, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #480	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 4a6d90 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

▶Scalability Runs Description

Run 1x1	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_NUM_THREADS: 1OMP_PLACES: threads
Run 1x2	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 2OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x4	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 4OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x8	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 8OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x16	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 16OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x24	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 24OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x32	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 32OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x40	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 40OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x48	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 48OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x56	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 56OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x64	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 64OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x72	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 72OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x80	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 80OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x88	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 88OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x96	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 96OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads

(1x1) Efficiency	(1x1) Potential Speed-Up (%)	(1x2) Efficiency	(1x2) Potential Speed-Up (%)	(1x4) Efficiency	(1x4) Potential Speed-Up (%)	(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x16) Efficiency	(1x16) Potential Speed-Up (%)	(1x24) Efficiency	(1x24) Potential Speed-Up (%)	(1x32) Efficiency	(1x32) Potential Speed-Up (%)	(1x40) Efficiency	(1x40) Potential Speed-Up (%)	(1x48) Efficiency	(1x48) Potential Speed-Up (%)	(1x56) Efficiency	(1x56) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)	(1x72) Efficiency	(1x72) Potential Speed-Up (%)	(1x80) Efficiency	(1x80) Potential Speed-Up (%)	(1x88) Efficiency	(1x88) Potential Speed-Up (%)	(1x96) Efficiency	(1x96) Potential Speed-Up (%)
1	0	1.9	0	3.56	0	6.69	0	12.11	0	16.24	0	21.31	0	23.31	0	27.52	0	32.26	0	36.57	0	38.12	0	42.57	0	41.38	0	44.5	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x1	1	1	1	1	11.999996185303	4.5107865333557
1x2	2	1.9	1.9	2	6.3949966430664	4.4722971916199
1x4	4	3.56	3.56	4	3.3350005149841	4.4565353393555
1x8	8	6.69	6.69	8	1.7300001382828	4.0646634101868
1x16	16	12.11	12.11	16	0.93999963998795	3.4413440227509
1x24	24	16.24	16.24	24	0.6949999332428	2.9836599826813
1x32	32	21.31	21.31	32	0.53999990224838	2.4803297519684
1x40	40	23.31	23.31	40	0.45500010251999	2.1342580318451
1x48	48	27.52	27.52	48	0.4099999666214	1.9672654867172
1x56	56	32.26	32.26	56	0.36999994516373	1.8462716341019
1x64	64	36.57	36.57	64	0.32000005245209	1.6849211454391
1x72	72	38.12	38.12	72	0.31499999761581	1.6185266971588
1x80	80	42.57	42.57	80	0.29000002145767	1.5748391151428
1x88	88	41.38	41.38	88	0.27999994158745	1.4784095287323
1x96	96	44.5	44.5	96	0.28999999165535	1.3804439306259

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGBuildMultipass.omp_outlined.20–	4.51	12.00
○Loop 750 - par_multi_interp.c:1760-1761 - exec	0.01	0.03
○Loop 749 - par_multi_interp.c:1762-1763 - exec	0.00	0.00
▼Loop 735 - par_multi_interp.c:1774-1876 - exec–	0.00	0.00
▼Loop 736 - par_multi_interp.c:1774-1876 - exec–	0.00	0.00
▼Loop 734 - par_multi_interp.c:1774-1876 - exec–	0.68	1.81
▼Loop 738 - par_multi_interp.c:1811-1837 - exec–	2.57	6.83
○Loop 740 - par_multi_interp.c:1816-1822 - exec	0.16	0.43
○Loop 739 - par_multi_interp.c:1824-1830 - exec	0.00	0.00
○Loop 742 - par_multi_interp.c:1799-1803 - exec	1.03	2.73
○Loop 744 - par_multi_interp.c:1782-1787 - exec	0.05	0.13
○Loop 747 - par_multi_interp.c:1873-1874 - exec	0.01	0.01
○Loop 748 - par_multi_interp.c:1874-1874 - exec	0.00	0.00
○Loop 746 - par_multi_interp.c:1876-1876 - exec	0.00	0.00
○Loop 743 - par_multi_interp.c:1792-1797 - exec	0.00	0.00
○Loop 745 - par_multi_interp.c:1875-1876 - exec	0.00	0.00
○Loop 741 - par_multi_interp.c:1805-1809 - exec	0.00	0.00
○Loop 737 - par_multi_interp.c:1851-1860 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency