OV - exec - Function hypre_BoomerAMGBuildMultipass.omp

	Function: hypre_BoomerAMGBuildMultipass.omp_outlined.18	Module: exec	Source: par_multi_interp.c:1575-1663 [...]	Coverage (incl. loops): 0.83% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1575 - 1663

--------------------------------------------------------------------------------

1575: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa)

[...]

1585:            if (n_fine)

1586:            {   tmp_marker = hypre_CTAlloc(HYPRE_Int,n_fine); }

1587:            tmp_marker_offd = NULL;

1588:            if (num_cols_offd)

1589:            {   tmp_marker_offd = hypre_CTAlloc(HYPRE_Int,num_cols_offd); }

1590:            for (i=0; i < n_fine; i++)

1591:            {   tmp_marker[i] = -1; }

1592:            for (i=0; i < num_cols_offd; i++)

1593:            {   tmp_marker_offd[i] = -1; }

1594:

1595:            /* Compute this thread's range of pass_length */

1596:            my_thread_num = hypre_GetThreadNum();

1597:            num_threads = hypre_NumActiveThreads();

1598:            thread_start = pass_pointer[1] + (pass_length/num_threads)*my_thread_num;

1599:            if (my_thread_num == num_threads-1)

[...]

1605:            for (i=thread_start; i < thread_stop; i++)

1606:            {

1607:              i1 = pass_array[i];

1608:              sum_C = 0;

1609:              sum_N = 0;

1610:              j_start = P_diag_start[i1];

1611:              j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1];

1612:              for (j=j_start; j < j_end; j++)

1613:              {

1614:                 k1 = P_diag_pass[1][j];

1615:                 tmp_marker[C_array[k1]] = i1;

1616:              }

1617:              cnt = P_diag_i[i1];

1618:              for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1619:              {

1620:                 j1 = A_diag_j[j];

1621:                 if (CF_marker[j1] != -3 &&

1622:                    (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1623:                    sum_N += A_diag_data[j];

1624:                 if (j1 != -1 && tmp_marker[j1] == i1)

1625:                 {

1626:                    P_diag_data[cnt] = A_diag_data[j];

1627:                    P_diag_j[cnt++] = fine_to_coarse[j1];

1628:                    sum_C += A_diag_data[j];

1629:                 }

1630:              }

1631:              j_start = P_offd_start[i1];

1632:              j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1];

1633:              for (j=j_start; j < j_end; j++)

1634:              {

1635:                 k1 = P_offd_pass[1][j];

1636:                 tmp_marker_offd[C_array_offd[k1]] = i1;

1637:              }

1638:              cnt_offd = P_offd_i[i1];

1639:              for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++)

1640:              {

1641:                 if (col_offd_S_to_A)

1642:                     j1 = map_A_to_S[A_offd_j[j]];

1643:                 else

1644:                     j1 = A_offd_j[j];

1645:                 if (CF_marker_offd[j1] != -3 &&

1646:                   (num_functions == 1 || dof_func[i1] == dof_func_offd[j1]))

1647:                     sum_N += A_offd_data[j];

1648:                 if (j1 != -1 && tmp_marker_offd[j1] == i1)

1649:                 {

1650:                    P_offd_data[cnt_offd] = A_offd_data[j];

1651:                    P_offd_j[cnt_offd++] = map_S_to_new[j1];

1652:                    sum_C += A_offd_data[j];

1653:                 }

1654:              }

1655:              diagonal = A_diag_data[A_diag_i[i1]];

1656:              if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal);

1657:              for (j=P_diag_i[i1]; j < cnt; j++)

1658:                 P_diag_data[j] *= alfa;

1659:              for (j=P_offd_i[i1]; j < cnt_offd; j++)

1660:                 P_offd_data[j] *= alfa;

1661:           }

1662:           hypre_TFree(tmp_marker);

1663:           hypre_TFree(tmp_marker_offd);

0x434df0 SUB	SP, SP, #304

0x434df4 STP	X29, X30, [SP, #208]

0x434df8 STP	X28, X27, [SP, #224]

0x434dfc STP	X26, X25, [SP, #240]

0x434e00 STP	X24, X23, [SP, #256]

0x434e04 STP	X22, X21, [SP, #272]

0x434e08 STP	X20, X19, [SP, #288]

0x434e0c ADD	X29, SP, #208

0x434e10 LDP	X8, X9, [X29, #288]

0x434e14 STP	X7, X6, [X29, #992]

0x434e18 STUR	X4, [X29, #472]

0x434e1c LDR	X0, [X2]

0x434e20 ORR	X24, XZR, X5

0x434e24 ORR	X25, XZR, X3

0x434e28 ORR	X26, XZR, X2

0x434e2c STUR	X9, [X29, #416]

0x434e30 STR	X8, [SP, #104]

0x434e34 LDP	X8, X9, [X29, #272]

0x434e38 STUR	X9, [X29, #440]

0x434e3c STR	X8, [SP, #96]

0x434e40 LDR	X8, [X29, #264]

0x434e44 STR	X8, [SP, #88]

0x434e48 LDP	X8, X21, [X29, #248]

0x434e4c STR	X8, [SP, #80]

0x434e50 LDR	X8, [X29, #240]

0x434e54 STR	X8, [SP, #72]

0x434e58 LDP	X8, X28, [X29, #208]

0x434e5c LDP	X27, X22, [X29, #224]

0x434e60 STUR	X8, [X29, #448]

0x434e64 LDR	X8, [X29, #200]

0x434e68 STR	X8, [SP, #40]

0x434e6c LDP	X8, X9, [X29, #184]

0x434e70 STUR	X9, [X29, #456]

0x434e74 STR	X8, [SP, #64]

0x434e78 LDR	X8, [X29, #176]

0x434e7c STR	X8, [SP, #56]

0x434e80 LDP	X8, X9, [X29, #160]

0x434e84 STP	X8, X9, [X29, #936]

0x434e88 LDP	X23, X8, [X29, #144]

0x434e8c STUR	X8, [X29, #496]

0x434e90 LDR	X8, [X29, #136]

0x434e94 STR	X8, [SP, #32]

0x434e98 LDR	X8, [X29, #128]

0x434e9c STR	X8, [SP, #24]

0x434ea0 LDR	X8, [X29, #120]

0x434ea4 STR	X8, [SP, #16]

0x434ea8 LDR	X8, [X29, #112]

0x434eac STR	X8, [SP, #8]

0x434eb0 LDP	X8, X9, [X29, #96]

0x434eb4 STUR	X9, [X29, #464]

0x434eb8 STR	X8, [SP, #48]

0x434ebc CBZ	X0, 434ee4

0x434ec0 MOVZ	W1, #8

0x434ec4 BL	4a6c90

0x434ec8 ORR	X19, XZR, X0

0x434ecc LDR	X0, [X25]

0x434ed0 CBZ	X0, 434ef0

0x434ed4 MOVZ	W1, #8

0x434ed8 BL	4a6c90

0x434edc ORR	X20, XZR, X0

0x434ee0 B	434ef4

0x434ee4 ORR	X19, XZR, XZR

0x434ee8 LDR	X0, [X25]

0x434eec CBNZ	X0, 434ed4

0x434ef0 ORR	X20, XZR, XZR

0x434ef4 LDR	X8, [X26]

0x434ef8 CMP	X8, #1

0x434efc B.LT	434f1c

0x434f00 MOVN	X9, #0

0x434f04 ORR	X8, XZR, XZR

(733) 0x434f08 STR	X9, [X19, X8,LSL #3]

(733) 0x434f0c ADD	X8, X8, #1

(733) 0x434f10 LDR	X10, [X26]

(733) 0x434f14 CMP	X8, X10

(733) 0x434f18 B.LT	434f08

0x434f1c LDR	X8, [X25]

0x434f20 CMP	X8, #1

0x434f24 B.LT	434f54

0x434f28 MOVN	X9, #0

0x434f2c ORR	X8, XZR, XZR

0x434f30 HINT	#0

0x434f34 HINT	#0

0x434f38 HINT	#0

0x434f3c HINT	#0

(732) 0x434f40 STR	X9, [X20, X8,LSL #3]

(732) 0x434f44 ADD	X8, X8, #1

(732) 0x434f48 LDR	X10, [X25]

(732) 0x434f4c CMP	X8, X10

(732) 0x434f50 B.LT	434f40

0x434f54 BL	4a8a10

0x434f58 ORR	X25, XZR, X0

0x434f5c BL	4a89f0

0x434f60 LDR	X9, [X24]

0x434f64 SUB	X11, X0, #1

0x434f68 CMP	X25, X11

0x434f6c SDIV	X10, X9, X0

0x434f70 MADD	X8, X10, X25, XZR

0x434f74 ADD	X10, X10, X8

0x434f78 CSEL	X9, X9, X10, #0

0x434f7c CMP	X8, X9

0x434f80 B.GE	4354b8

0x434f84 LDP	X12, X10, [X29, #976]

0x434f88 LDR	X2, [X28]

0x434f8c LDR	X3, [X27]

0x434f90 LDR	X4, [X22]

0x434f94 LDR	X5, [X21]

0x434f98 LDR	X11, [X10]

0x434f9c LDUR	X10, [X29, #488]

0x434fa0 LDR	X12, [X12]

0x434fa4 LDR	X10, [X10]

0x434fa8 LDR	X11, [X11, #8]

0x434fac STUR	X10, [X29, #488]

0x434fb0 LDUR	X10, [X29, #480]

0x434fb4 ADD	X9, X9, X11

0x434fb8 ADD	X13, X8, X11

0x434fbc LDR	X10, [X10]

0x434fc0 STUR	X10, [X29, #480]

0x434fc4 LDR	X10, [SP, #48]

0x434fc8 STR	X12, [SP, #48]

0x434fcc STUR	X9, [X29, #464]

0x434fd0 LDP	X9, X8, [SP, #8]

0x434fd4 LDR	X10, [X10]

0x434fd8 LDR	X14, [X9]

0x434fdc LDR	X15, [X8]

0x434fe0 LDP	X9, X8, [SP, #24]

0x434fe4 LDR	X17, [X8]

0x434fe8 LDUR	X8, [X29, #456]

0x434fec LDR	X16, [X9]

0x434ff0 LDR	X8, [X8]

0x434ff4 STUR	X8, [X29, #456]

0x434ff8 LDR	X8, [SP, #40]

0x434ffc LDR	X0, [X8]

0x435000 LDUR	X8, [X29, #448]

0x435004 LDR	X8, [X8]

0x435008 STR	X8, [SP, #40]

0x43500c LDUR	X8, [X29, #424]

0x435010 LDR	X8, [X8]

0x435014 STUR	X8, [X29, #448]

0x435018 LDP	X11, X8, [X29, #944]

0x43501c LDR	X9, [X11]

0x435020 LDR	X8, [X8]

0x435024 STP	X8, X9, [SP, #24]

0x435028 ADD	X9, X9, #16

0x43502c ADD	X8, X8, #16

0x435030 STP	X8, X9, [SP, #8]

0x435034 STUR	X10, [X29, #472]

0x435038 B	435050

0x43503c HINT	#0

  (721) 0x435040 LDUR	X8, [X29, #464]

  (721) 0x435044 ADD	X13, X13, #1

  (721) 0x435048 CMP	X13, X8

  (721) 0x43504c B.GE	4354b8

  (721) 0x435050 LDP	X8, X9, [X29, #992]

  (721) 0x435054 LDR	X30, [X9, X13,LSL #3]

  (721) 0x435058 ADD	X26, X30, #1

  (721) 0x43505c LDR	X8, [X8, X30,LSL #3]

  (721) 0x435060 LDR	X25, [X10, X30,LSL #3]

  (721) 0x435064 LDR	X9, [X10, X26,LSL #3]

  (721) 0x435068 ADD	X11, X9, X8

  (721) 0x43506c SUB	X11, X11, X25

  (721) 0x435070 CMP	X8, X11

  (721) 0x435074 B.GE	435120

  (721) 0x435078 LDR	X11, [SP, #48]

  (721) 0x43507c SUB	W12, W9, W25

  (721) 0x435080 ANDS	X18, X12, #4160

  (721) 0x435084 LDR	X11, [X11, #8]

  (721) 0x435088 B.EQ	4350bc

  (721) 0x43508c ORR	X12, XZR, X8

  (721) 0x435090 HINT	#0

  (721) 0x435094 HINT	#0

  (721) 0x435098 HINT	#0

  (721) 0x43509c HINT	#0

    (727) 0x4350a0 LDR	X1, [X11, X12,LSL #3]

    (727) 0x4350a4 ADD	X12, X12, #1

    (727) 0x4350a8 SUBS	X18, X18, #1

    (727) 0x4350ac LDR	X1, [X14, X1,LSL #3]

    (727) 0x4350b0 STR	X30, [X19, X1,LSL #3]

    (727) 0x4350b4 B.NE	4350a0

  (721) 0x4350b8 B	4350c0

  (721) 0x4350bc ORR	X12, XZR, X8

  (721) 0x4350c0 SUB	X18, X25, X9

  (721) 0x4350c4 CMN	X18, #4

  (721) 0x4350c8 B.HI	43511c

  (721) 0x4350cc ADD	X8, X9, X8

  (721) 0x4350d0 ADD	X11, X11, X12,LSL #3

  (721) 0x4350d4 SUB	X8, X8, X12

  (721) 0x4350d8 ADD	X9, X11, #16

  (721) 0x4350dc SUB	X8, X8, X25

    (726) 0x4350e0 LDUR	X11, [X9, #496]

    (726) 0x4350e4 SUBS	X8, X8, #4

    (726) 0x4350e8 LDR	X11, [X14, X11,LSL #3]

    (726) 0x4350ec STR	X30, [X19, X11,LSL #3]

    (726) 0x4350f0 LDUR	X11, [X9, #504]

    (726) 0x4350f4 LDR	X11, [X14, X11,LSL #3]

    (726) 0x4350f8 STR	X30, [X19, X11,LSL #3]

    (726) 0x4350fc LDR	X11, [X9]

    (726) 0x435100 LDR	X11, [X14, X11,LSL #3]

    (726) 0x435104 STR	X30, [X19, X11,LSL #3]

    (726) 0x435108 LDR	X11, [X9, #8]

    (726) 0x43510c ADD	X9, X9, #32

    (726) 0x435110 LDR	X11, [X14, X11,LSL #3]

    (726) 0x435114 STR	X30, [X19, X11,LSL #3]

    (726) 0x435118 B.NE	4350e0

  (721) 0x43511c LDR	X25, [X10, X30,LSL #3]

  (721) 0x435120 LDR	X8, [X15, X30,LSL #3]

  (721) 0x435124 LDR	X12, [X15, X26,LSL #3]

  (721) 0x435128 MOVI	D2, #0

  (721) 0x43512c ADD	X8, X8, #1

  (721) 0x435130 CMP	X8, X12

  (721) 0x435134 B.GE	4351e0

  (721) 0x435138 LDUR	X10, [X29, #424]

  (721) 0x43513c LDUR	X9, [X29, #496]

  (721) 0x435140 MOVI	D1, #0

  (721) 0x435144 LDR	X11, [X10]

  (721) 0x435148 LDUR	X10, [X29, #432]

  (721) 0x43514c LDR	X9, [X9]

  (721) 0x435150 LDR	X1, [X10]

  (721) 0x435154 LDR	X10, [SP, #64]

  (721) 0x435158 LDR	X7, [X10]

  (721) 0x43515c LDR	X10, [SP, #56]

  (721) 0x435160 LDR	X21, [X10]

  (721) 0x435164 B	435174

    (725) 0x435168 ADD	X8, X8, #1

    (725) 0x43516c CMP	X8, X12

    (725) 0x435170 B.GE	4351e4

    (725) 0x435174 LDR	X22, [X16, X8,LSL #3]

    (725) 0x435178 LDR	X18, [X17, X22,LSL #3]

    (725) 0x43517c CMN	X18, #3

    (725) 0x435180 B.EQ	4351a8

    (725) 0x435184 LDR	X18, [X23]

    (725) 0x435188 CMP	X18, #1

    (725) 0x43518c B.EQ	4351a0

    (725) 0x435190 LDR	X18, [X9, X30,LSL #3]

    (725) 0x435194 LDR	X24, [X9, X22,LSL #3]

    (725) 0x435198 CMP	X18, X24

    (725) 0x43519c B.NE	4351a8

    (725) 0x4351a0 LDR	D3, [X11, X8,LSL #3]

    (725) 0x4351a4 FADD	D1, D3, D1

    (725) 0x4351a8 CMN	X22, #1

    (725) 0x4351ac B.EQ	435168

    (725) 0x4351b0 LDR	X18, [X19, X22,LSL #3]

    (725) 0x4351b4 CMP	X18, X30

    (725) 0x4351b8 B.NE	435168

    (725) 0x4351bc LDR	X12, [X7, X22,LSL #3]

    (725) 0x4351c0 LDR	D3, [X11, X8,LSL #3]

    (725) 0x4351c4 STR	X12, [X21, X25,LSL #3]

    (725) 0x4351c8 LDR	X12, [X15, X26,LSL #3]

    (725) 0x4351cc FADD	D2, D3, D2

    (725) 0x4351d0 STR	D3, [X1, X25,LSL #3]

    (725) 0x4351d4 ADD	X25, X25, #1

    (725) 0x4351d8 B	435168

0x4351dc HINT	#0

  (721) 0x4351e0 MOVI	D1, #0

  (721) 0x4351e4 LDUR	X8, [X29, #456]

  (721) 0x4351e8 LDR	X9, [X0, X26,LSL #3]

  (721) 0x4351ec LDR	X7, [X0, X30,LSL #3]

  (721) 0x4351f0 LDR	X8, [X8, X30,LSL #3]

  (721) 0x4351f4 ADD	X11, X9, X8

  (721) 0x4351f8 SUB	X11, X11, X7

  (721) 0x4351fc CMP	X8, X11

  (721) 0x435200 B.GE	4352a0

  (721) 0x435204 LDR	X10, [SP, #40]

  (721) 0x435208 SUB	W12, W9, W7

  (721) 0x43520c ANDS	X18, X12, #4160

  (721) 0x435210 LDR	X11, [X10, #8]

  (721) 0x435214 B.EQ	43523c

  (721) 0x435218 ORR	X12, XZR, X8

  (721) 0x43521c HINT	#0

    (724) 0x435220 LDR	X1, [X11, X12,LSL #3]

    (724) 0x435224 ADD	X12, X12, #1

    (724) 0x435228 SUBS	X18, X18, #1

    (724) 0x43522c LDR	X1, [X2, X1,LSL #3]

    (724) 0x435230 STR	X30, [X20, X1,LSL #3]

    (724) 0x435234 B.NE	435220

  (721) 0x435238 B	435240

  (721) 0x43523c ORR	X12, XZR, X8

  (721) 0x435240 SUB	X18, X7, X9

  (721) 0x435244 CMN	X18, #4

  (721) 0x435248 B.HI	43529c

  (721) 0x43524c ADD	X8, X9, X8

  (721) 0x435250 ADD	X11, X11, X12,LSL #3

  (721) 0x435254 SUB	X8, X8, X12

  (721) 0x435258 ADD	X9, X11, #16

  (721) 0x43525c SUB	X8, X8, X7

    (723) 0x435260 LDUR	X11, [X9, #496]

    (723) 0x435264 SUBS	X8, X8, #4

    (723) 0x435268 LDR	X11, [X2, X11,LSL #3]

    (723) 0x43526c STR	X30, [X20, X11,LSL #3]

    (723) 0x435270 LDUR	X11, [X9, #504]

    (723) 0x435274 LDR	X11, [X2, X11,LSL #3]

    (723) 0x435278 STR	X30, [X20, X11,LSL #3]

    (723) 0x43527c LDR	X11, [X9]

    (723) 0x435280 LDR	X11, [X2, X11,LSL #3]

    (723) 0x435284 STR	X30, [X20, X11,LSL #3]

    (723) 0x435288 LDR	X11, [X9, #8]

    (723) 0x43528c ADD	X9, X9, #32

    (723) 0x435290 LDR	X11, [X2, X11,LSL #3]

    (723) 0x435294 STR	X30, [X20, X11,LSL #3]

    (723) 0x435298 B.NE	435260

  (721) 0x43529c LDR	X7, [X0, X30,LSL #3]

  (721) 0x4352a0 LDR	X24, [X3, X30,LSL #3]

  (721) 0x4352a4 LDR	X28, [X3, X26,LSL #3]

  (721) 0x4352a8 CMP	X24, X28

  (721) 0x4352ac B.GE	435388

(722) 0x4352b0 LDP	X9, X8, [SP, #72]

(722) 0x4352b4 LDR	X12, [X8]

(722) 0x4352b8 LDUR	X8, [X29, #496]

(722) 0x4352bc LDR	X21, [X9]

(722) 0x4352c0 LDR	X27, [X8]

(722) 0x4352c4 LDP	X9, X8, [SP, #88]

(722) 0x4352c8 ADD	X12, X12, X24,LSL #3

(722) 0x4352cc LDR	X1, [X8]

(722) 0x4352d0 LDUR	X8, [X29, #440]

(722) 0x4352d4 LDR	X11, [X9]

(722) 0x4352d8 LDR	X9, [SP, #104]

(722) 0x4352dc LDR	X22, [X8]

(722) 0x4352e0 LDUR	X8, [X29, #416]

(722) 0x4352e4 LDR	X9, [X9]

(722) 0x4352e8 LDR	X8, [X8]

(722) 0x4352ec B	435310

0x4352f0 HINT	#0

0x4352f4 HINT	#0

0x4352f8 HINT	#0

0x4352fc HINT	#0

(722) 0x435300 ADD	X24, X24, #1

(722) 0x435304 ADD	X12, X12, #8

(722) 0x435308 CMP	X24, X28

(722) 0x43530c B.GE	435388

(722) 0x435310 ORR	X18, XZR, X12

(722) 0x435314 CBZ	X4, 435320

(722) 0x435318 LDR	X18, [X12]

(722) 0x43531c ADD	X18, X21, X18,LSL #3

(722) 0x435320 LDR	X18, [X18]

(722) 0x435324 LDR	X6, [X5, X18,LSL #3]

(722) 0x435328 CMN	X6, #3

(722) 0x43532c B.EQ	435354

(722) 0x435330 LDR	X6, [X23]

(722) 0x435334 CMP	X6, #1

(722) 0x435338 B.EQ	43534c

(722) 0x43533c LDR	X6, [X27, X30,LSL #3]

(722) 0x435340 LDR	X10, [X11, X18,LSL #3]

(722) 0x435344 CMP	X6, X10

(722) 0x435348 B.NE	435354

(722) 0x43534c LDR	D3, [X1, X24,LSL #3]

(722) 0x435350 FADD	D1, D3, D1

(722) 0x435354 CMN	X18, #1

(722) 0x435358 B.EQ	435300

(722) 0x43535c LDR	X10, [X20, X18,LSL #3]

(722) 0x435360 CMP	X10, X30

(722) 0x435364 B.NE	435300

(722) 0x435368 LDR	X10, [X8, X18,LSL #3]

(722) 0x43536c LDR	D3, [X1, X24,LSL #3]

(722) 0x435370 STR	X10, [X9, X7,LSL #3]

(722) 0x435374 LDR	X28, [X3, X26,LSL #3]

(722) 0x435378 FADD	D2, D3, D2

(722) 0x43537c STR	D3, [X22, X7,LSL #3]

(722) 0x435380 ADD	X7, X7, #1

(722) 0x435384 B	435300

  (721) 0x435388 LDR	X8, [X15, X30,LSL #3]

  (721) 0x43538c LDUR	X9, [X29, #448]

  (721) 0x435390 LDR	D3, [X9, X8,LSL #3]

  (721) 0x435394 FMUL	D2, D3, D2

  (721) 0x435398 FCMP	D2, #0

  (721) 0x43539c B.EQ	4353a8

  (721) 0x4353a0 FNEG	D0, D1

  (721) 0x4353a4 FDIV	D0, D0, D2

  (721) 0x4353a8 LDUR	X10, [X29, #472]

  (721) 0x4353ac LDR	X12, [X10, X30,LSL #3]

  (721) 0x4353b0 SUBS	X8, X25, X12

  (721) 0x4353b4 B.LE	435434

  (721) 0x4353b8 ORR	X9, XZR, X12

  (721) 0x4353bc CMP	X8, #4

  (721) 0x4353c0 B.CC	435404

  (721) 0x4353c4 LDR	X18, [SP, #16]

  (721) 0x4353c8 AND	X11, X8, #8062

  (721) 0x4353cc ADD	X9, X12, X11

  (721) 0x4353d0 ADD	X12, X18, X12,LSL #3

  (721) 0x4353d4 ORR	X18, XZR, X11

  (721) 0x4353d8 HINT	#0

  (721) 0x4353dc HINT	#0

    (731) 0x4353e0 LDP	Q1, Q2, [X12, #2032]

    (731) 0x4353e4 SUBS	X18, X18, #4

    (731) 0x4353e8 FMUL	V2.2D, V2.2D, V0.D[0]

    (731) 0x4353ec FMUL	V1.2D, V1.2D, V0.D[0]

    (731) 0x4353f0 STP	Q1, Q2, [X12, #2032]

    (731) 0x4353f4 ADD	X12, X12, #32

    (731) 0x4353f8 B.NE	4353e0

  (721) 0x4353fc CMP	X8, X11

  (721) 0x435400 B.EQ	435434

  (721) 0x435404 LDR	X8, [SP, #32]

  (721) 0x435408 ADD	X8, X8, X9,LSL #3

  (721) 0x43540c SUB	X9, X25, X9

  (721) 0x435410 HINT	#0

  (721) 0x435414 HINT	#0

  (721) 0x435418 HINT	#0

  (721) 0x43541c HINT	#0

    (730) 0x435420 LDR	D1, [X8]

    (730) 0x435424 SUBS	X9, X9, #1

    (730) 0x435428 FMUL	D1, D1, D0

    (730) 0x43542c STR	D1, [X8], #8

    (730) 0x435430 B.NE	435420

  (721) 0x435434 LDR	X12, [X0, X30,LSL #3]

  (721) 0x435438 SUBS	X8, X7, X12

  (721) 0x43543c B.LE	435040

  (721) 0x435440 ORR	X9, XZR, X12

  (721) 0x435444 CMP	X8, #4

  (721) 0x435448 B.CC	435484

  (721) 0x43544c LDR	X18, [SP, #8]

  (721) 0x435450 AND	X11, X8, #8062

  (721) 0x435454 ADD	X9, X12, X11

  (721) 0x435458 ADD	X12, X18, X12,LSL #3

  (721) 0x43545c ORR	X18, XZR, X11

    (729) 0x435460 LDP	Q1, Q2, [X12, #2032]

    (729) 0x435464 SUBS	X18, X18, #4

    (729) 0x435468 FMUL	V2.2D, V2.2D, V0.D[0]

    (729) 0x43546c FMUL	V1.2D, V1.2D, V0.D[0]

    (729) 0x435470 STP	Q1, Q2, [X12, #2032]

    (729) 0x435474 ADD	X12, X12, #32

    (729) 0x435478 B.NE	435460

  (721) 0x43547c CMP	X8, X11

  (721) 0x435480 B.EQ	435040

  (721) 0x435484 LDR	X8, [SP, #24]

  (721) 0x435488 ADD	X8, X8, X9,LSL #3

  (721) 0x43548c SUB	X9, X7, X9

  (721) 0x435490 HINT	#0

  (721) 0x435494 HINT	#0

  (721) 0x435498 HINT	#0

  (721) 0x43549c HINT	#0

    (728) 0x4354a0 LDR	D1, [X8]

    (728) 0x4354a4 SUBS	X9, X9, #1

    (728) 0x4354a8 FMUL	D1, D1, D0

    (728) 0x4354ac STR	D1, [X8], #8

    (728) 0x4354b0 B.NE	4354a0

  (721) 0x4354b4 B	435040

0x4354b8 ORR	X0, XZR, X19

0x4354bc BL	4a6d90

0x4354c0 ORR	X0, XZR, X20

0x4354c4 LDP	X20, X19, [SP, #288]

0x4354c8 LDP	X22, X21, [SP, #272]

0x4354cc LDP	X24, X23, [SP, #256]

0x4354d0 LDP	X26, X25, [SP, #240]

0x4354d4 LDP	X28, X27, [SP, #224]

0x4354d8 LDP	X29, X30, [SP, #208]

0x4354dc ADD	SP, SP, #304

0x4354e0 B	4a6d90

0x4354e4 HINT	#0

0x4354e8 HINT	#0

0x4354ec HINT	#0

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	par_multi_interp.c:1575-1663
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1575,1585-1599,1605-1663.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 57% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 32.67 to 26.17 cycles (1.25x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 32.67 to 2.50 cycles (13.07x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 632 bytes. The binary function is storing 384 bytes.

General properties

nb instructions	157
loop length	628
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

18.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	7.00	7.00	6.25	6.25	6.17	6.17	6.08	6.08	0.00	0.00	0.00	0.00	32.67	32.67	32.67	19.00	19.00
cycles	7.00	7.00	6.25	6.25	6.17	6.17	6.08	6.08	0.00	0.00	0.00	0.00	32.67	32.67	32.67	19.00	19.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	18.00
Overall L1	32.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 32.67 cycles. At this rate:

20% of peak load performance is reached (19.35 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
24% of peak store performance is reached (11.76 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 434df0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #304	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #208	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X8, X9, [X29, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X7, X6, [X29, #992]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X4, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X24, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X25, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X26, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X9, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X21, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X28, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X27, X22, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X8, X9, [X29, #936]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X23, X8, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBZ X0, 434ee4 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CBZ X0, 434ef0 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x100>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 434ef4 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x104>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CBNZ X0, 434ed4 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0xe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 434f1c <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x12c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 434f54 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
BL 4a8a10 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X25, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a89f0 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X11, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X25, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
SDIV X10, X9, X0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MADD X8, X10, X25, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X10, X10, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CSEL X9, X9, X10, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X8, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4354b8 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x6c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X12, X10, [X29, #976]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X2, [X28]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X27]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X4, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X5, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X10, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X10, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X10, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X9, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X13, X8, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X10, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X12, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X9, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X9, X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X15, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X9, X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X17, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X11, X8, [X29, #944]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X9, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X8, X9, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X9, X9, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X8, X8, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X8, X9, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X10, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 435050 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x260>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X20, X19, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X22, X21, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X26, X25, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X28, X27, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X29, X30, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #304	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 4a6d90 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	par_multi_interp.c:1575-1663
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1575,1585-1599,1605-1663.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 32.67 to 2.50 cycles (13.07x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 632 bytes. The binary function is storing 384 bytes.

General properties

nb instructions	157
loop length	628
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

18.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	7.00	7.00	6.25	6.25	6.17	6.17	6.08	6.08	0.00	0.00	0.00	0.00	32.67	32.67	32.67	19.00	19.00
cycles	7.00	7.00	6.25	6.25	6.17	6.17	6.08	6.08	0.00	0.00	0.00	0.00	32.67	32.67	32.67	19.00	19.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	18.00
Overall L1	32.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 32.67 cycles. At this rate:

20% of peak load performance is reached (19.35 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
24% of peak store performance is reached (11.76 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 434df0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #304	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #208	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X8, X9, [X29, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X7, X6, [X29, #992]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X4, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X24, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X25, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X26, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X9, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X21, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X28, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X27, X22, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X8, X9, [X29, #936]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X23, X8, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBZ X0, 434ee4 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CBZ X0, 434ef0 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x100>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 434ef4 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x104>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CBNZ X0, 434ed4 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0xe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 434f1c <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x12c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 434f54 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
BL 4a8a10 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X25, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a89f0 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X11, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X25, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
SDIV X10, X9, X0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MADD X8, X10, X25, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X10, X10, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CSEL X9, X9, X10, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X8, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4354b8 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x6c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X12, X10, [X29, #976]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X2, [X28]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X27]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X4, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X5, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X10, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X10, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X10, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X9, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X13, X8, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X10, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X12, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X9, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X9, X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X15, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X9, X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X17, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X11, X8, [X29, #944]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X9, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X8, X9, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X9, X9, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X8, X8, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X8, X9, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X10, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 435050 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x260>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X20, X19, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X22, X21, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X26, X25, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X28, X27, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X29, X30, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #304	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 4a6d90 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

▶Scalability Runs Description

Run 1x1	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_NUM_THREADS: 1OMP_PLACES: threads
Run 1x2	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 2OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x4	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 4OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x8	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 8OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x16	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 16OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x24	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 24OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x32	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 32OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x40	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 40OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x48	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 48OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x56	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 56OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x64	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 64OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x72	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 72OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x80	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 80OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x88	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 88OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x96	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 96OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads

(1x1) Efficiency	(1x1) Potential Speed-Up (%)	(1x2) Efficiency	(1x2) Potential Speed-Up (%)	(1x4) Efficiency	(1x4) Potential Speed-Up (%)	(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x16) Efficiency	(1x16) Potential Speed-Up (%)	(1x24) Efficiency	(1x24) Potential Speed-Up (%)	(1x32) Efficiency	(1x32) Potential Speed-Up (%)	(1x40) Efficiency	(1x40) Potential Speed-Up (%)	(1x48) Efficiency	(1x48) Potential Speed-Up (%)	(1x56) Efficiency	(1x56) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)	(1x72) Efficiency	(1x72) Potential Speed-Up (%)	(1x80) Efficiency	(1x80) Potential Speed-Up (%)	(1x88) Efficiency	(1x88) Potential Speed-Up (%)	(1x96) Efficiency	(1x96) Potential Speed-Up (%)
1	0	1.87	0	3.53	0	6.21	0	9.96	0	12.48	0	16.32	0	18.26	0	19.15	0	24.96	0	25.9	0	25.01	0	28	0	26.39	0	27.37	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x1	1	1	1	1	2.2049994468689	0.82885706424713
1x2	2	1.87	1.87	2	1.1699997186661	0.83242863416672
1x4	4	3.53	3.53	4	0.6200003027916	0.827108502388
1x8	8	6.21	6.21	8	0.35499992966652	0.80483937263489
1x16	16	9.96	9.96	16	0.22000001370907	0.76855915784836
1x24	24	12.48	12.48	24	0.17499999701977	0.71350449323654
1x32	32	16.32	16.32	32	0.15499998629093	0.59524887800217
1x40	40	18.26	18.26	40	0.12500001490116	0.50065952539444
1x48	48	19.15	19.15	48	0.11999998986721	0.51956123113632
1x56	56	24.96	24.96	56	0.12000001221895	0.4385721385479
1x64	64	25.9	25.9	64	0.10500000417233	0.43711021542549
1x72	72	25.01	25.01	72	0.10499998927116	0.45328986644745
1x80	80	28	28	80	0.1000000089407	0.44000527262688
1x88	88	26.39	26.39	88	0.1000000089407	0.42602548003197
1x96	96	27.37	27.37	96	0.099999994039536	0.41235342621803

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGBuildMultipass.omp_outlined.18–	0.83	2.20
○Loop 733 - par_multi_interp.c:1590-1591 - exec	0.00	0.01
▼Loop 722 - par_multi_interp.c:1605-1660 - exec–	0.00	0.00
▼Loop 721 - par_multi_interp.c:1605-1660 - exec–	0.14	0.38
○Loop 725 - par_multi_interp.c:1618-1628 - exec	0.67	1.78
○Loop 727 - par_multi_interp.c:1612-1615 - exec	0.01	0.02
○Loop 730 - par_multi_interp.c:1657-1658 - exec	0.00	0.00
○Loop 728 - par_multi_interp.c:1659-1660 - exec	0.00	0.00
○Loop 723 - par_multi_interp.c:1633-1636 - exec	0.00	0.00
○Loop 726 - par_multi_interp.c:1612-1615 - exec	0.00	0.00
○Loop 731 - par_multi_interp.c:1658-1658 - exec	0.00	0.00
○Loop 729 - par_multi_interp.c:1660-1660 - exec	0.00	0.00
○Loop 724 - par_multi_interp.c:1633-1636 - exec	0.00	0.00
○Loop 732 - par_multi_interp.c:1592-1593 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency