OV - exec - Function hypre_BoomerAMGInterpTruncation.omp

	Function: hypre_BoomerAMGInterpTruncation.omp_outlined	Module: exec	Source: par_interp.c:2726-3155 [...]	Coverage (incl. loops): 0.02% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_interp.c: 2726 - 3155

--------------------------------------------------------------------------------

2726: #pragma omp parallel private(i,my_thread_num,num_threads,max_coef,j,start_j,row_sum,scale,num_lost,now_checking,next_open,num_lost_offd,now_checking_offd,next_open_offd,start,stop,cnt_diag,cnt_offd,num_elmts,cnt)

2727: #endif

2728:    {

2729:        my_thread_num = hypre_GetThreadNum();

2730:        num_threads = hypre_NumActiveThreads();

[...]

2740:        start = (n_fine/num_threads)*my_thread_num;

2741:        if (my_thread_num == num_threads-1)

[...]

2750:        if (trunc_factor > 0)

2751:        {

2752:           num_lost = 0;

2753:           num_lost_offd = 0;

2754:

2755:           next_open = P_diag_i[start];

2756:           now_checking = P_diag_i[start];

2757:           next_open_offd = P_offd_i[start];;

2758:           now_checking_offd = P_offd_i[start];;

2759:

2760:           for (i = start; i < stop; i++)

2761:           {

2762:             max_coef = 0;

2763:             for (j = P_diag_i[i]; j < P_diag_i[i+1]; j++)

2764:                max_coef = (max_coef < fabs(P_diag_data[j])) ?

2765:                       fabs(P_diag_data[j]) : max_coef;

2766:             for (j = P_offd_i[i]; j < P_offd_i[i+1]; j++)

2767:                max_coef = (max_coef < fabs(P_offd_data[j])) ?

2768:                       fabs(P_offd_data[j]) : max_coef;

2769:             max_coef *= trunc_factor;

2770:

2771:             start_j = P_diag_i[i];

2772:             if (num_lost) P_diag_i[i] -= num_lost;

2773:             row_sum = 0;

2774:             scale = 0;

2775:             for (j = start_j; j < P_diag_i[i+1]; j++)

2776:             {

2777:                row_sum += P_diag_data[now_checking];

2778:                if (fabs(P_diag_data[now_checking]) < max_coef)

2779:                {

2780:                   num_lost++;

2781:                   now_checking++;

2782:                }

2783:                else

2784:                {

2785:                   scale += P_diag_data[now_checking];

2786:                   P_diag_data[next_open] = P_diag_data[now_checking];

2787:                   P_diag_j[next_open] = P_diag_j[now_checking];

2788:                   now_checking++;

2789:                   next_open++;

2790:                }

2791:             }

2792:

2793:             start_j = P_offd_i[i];

2794:             if (num_lost_offd) P_offd_i[i] -= num_lost_offd;

2795:             for (j = start_j; j < P_offd_i[i+1]; j++)

2796:             {

2797:                row_sum += P_offd_data[now_checking_offd];

2798:                if (fabs(P_offd_data[now_checking_offd]) < max_coef)

2799:                {

2800:                   num_lost_offd++;

2801:                   now_checking_offd++;

2802:                }

2803:                else

2804:                {

2805:                   scale += P_offd_data[now_checking_offd];

2806:                   P_offd_data[next_open_offd] = P_offd_data[now_checking_offd];

2807:                   P_offd_j[next_open_offd] = P_offd_j[now_checking_offd];

2808:                   now_checking_offd++;

2809:                   next_open_offd++;

2810:                }

2811:             }

2812:             /* normalize row of P */

2813:

2814:             if (scale != 0.)

2815:             {

2816:                if (scale != row_sum)

2817:                {

2818:                    scale = row_sum/scale;

2819:                    for (j = P_diag_i[i]; j < (P_diag_i[i+1]-num_lost); j++)

2820:                           P_diag_data[j] *= scale;

2821:                    for (j = P_offd_i[i]; j < (P_offd_i[i+1]-num_lost_offd); j++)

2822:                           P_offd_data[j] *= scale;

[...]

2828:           if(my_thread_num == 0)

2829:           {   max_num_threads[0] = num_threads; }

2830:           num_lost_per_thread[my_thread_num] = num_lost;

2831:           num_lost_offd_per_thread[my_thread_num] = num_lost_offd;

[...]

2840:        if (max_elmts > 0)

[...]

2848:            for (i=start; i<stop; i++)

2849:            {

2850:               /* Note P_diag_i[stop] is the starting point for the next thread

2851:                * in j and data, not the stop point for this thread */

2852:               last_index = P_diag_i[i+1];

2853:               last_index_offd = P_offd_i[i+1];

2854:               if(i == stop-1)

2855:               {

2856:                   last_index -= num_lost_per_thread[my_thread_num];

2857:                   last_index_offd -= num_lost_offd_per_thread[my_thread_num];

2858:               }

2859:               cnt1 = last_index-P_diag_i[i] + last_index_offd-P_offd_i[i];

2860:               if (cnt1 > P_mxnum) P_mxnum = cnt1;

2861:            }

2862:

2863:            /* Some rows exceed max_elmts, and require truncation.  Essentially,

2864:             * each thread truncates and compresses its range of rows locally. */

2865:            if (P_mxnum > max_elmts)

[...]

2872:                P_aux_j = hypre_CTAlloc(HYPRE_Int, P_mxnum);

2873:                P_aux_data = hypre_CTAlloc(HYPRE_Real, P_mxnum);

2874:                cnt_diag = P_diag_i[start];

2875:                cnt_offd = P_offd_i[start];

2876:

2877:                for (i = start; i < stop; i++)

2878:                {

2879:                 /* Note P_diag_i[stop] is the starting point for the next thread

2880:                  * in j and data, not the stop point for this thread */

2881:                 last_index = P_diag_i[i+1];

2882:                 last_index_offd = P_offd_i[i+1];

2883:                 if(i == stop-1)

2884:                 {

2885:                     last_index -= num_lost_per_thread[my_thread_num];

2886:                     last_index_offd -= num_lost_offd_per_thread[my_thread_num];

2887:                 }

2888:

2889:                 row_sum = 0;

2890:                 num_elmts = last_index-P_diag_i[i] + last_index_offd-P_offd_i[i];

2891:                 if (max_elmts < num_elmts)

2892:                 {

2893:                   /* copy both diagonal and off-diag parts of row i to _aux_ arrays */

2894:                   cnt = 0;

2895:                   for (j = P_diag_i[i]; j < last_index; j++)

2896:                   {

2897:                      P_aux_j[cnt] = P_diag_j[j];

2898:                      P_aux_data[cnt++] = P_diag_data[j];

2899:                      row_sum += P_diag_data[j];

2900:                   }

2901:                   num_lost += cnt;

2902:                   cnt1 = cnt;

2903:                   for (j = P_offd_i[i]; j < last_index_offd; j++)

2904:                   {

2905:                      P_aux_j[cnt] = P_offd_j[j]+num_cols;

2906:                      P_aux_data[cnt++] = P_offd_data[j];

2907:                      row_sum += P_offd_data[j];

2908:                   }

2909:                   num_lost_offd += cnt-cnt1;

2910:

2911:                   /* sort data */

2912:                   hypre_qsort2abs(P_aux_j,P_aux_data,0,cnt-1);

2913:                   scale = 0;

2914:                   if (i > start)

2915:                   {

2916:                      P_diag_i[i] = cnt_diag;

2917:                      P_offd_i[i] = cnt_offd;

2918:                   }

2919:                   for (j = 0; j < max_elmts; j++)

2920:                   {

2921:                      scale += P_aux_data[j];

2922:                      if (P_aux_j[j] < num_cols)

2923:                      {

2924:                         P_diag_j[cnt_diag] = P_aux_j[j];

2925:                         P_diag_data[cnt_diag++] = P_aux_data[j];

2926:                      }

2927:                      else

2928:                      {

2929:                         P_offd_j[cnt_offd] = P_aux_j[j]-num_cols;

2930:                         P_offd_data[cnt_offd++] = P_aux_data[j];

2931:                      }

2932:                   }

2933:                   num_lost -= cnt_diag-P_diag_i[i];

2934:                   num_lost_offd -= cnt_offd-P_offd_i[i];

2935:

2936:                   /* normalize row of P */

2937:                   if (scale != 0.)

2938:                   {

2939:                      if (scale != row_sum)

2940:                      {

2941:                         scale = row_sum/scale;

2942:                         for (j = P_diag_i[i]; j < cnt_diag; j++)

2943:                                P_diag_data[j] *= scale;

2944:                         for (j = P_offd_i[i]; j < cnt_offd; j++)

2945:                                P_offd_data[j] *= scale;

[...]

2955:                   if (P_diag_i[i] != cnt_diag)

2956:                   {

2957:                      start_j = P_diag_i[i];

2958:                      P_diag_i[i] = cnt_diag;

2959:                      for (j = start_j; j < last_index; j++)

2960:                      {

2961:                         P_diag_j[cnt_diag] = P_diag_j[j];

2962:                         P_diag_data[cnt_diag++] = P_diag_data[j];

2963:                      }

2964:                   }

2965:                   else

2966:                      cnt_diag += last_index-P_diag_i[i];

2967:

2968:                   if (P_offd_i[i] != cnt_offd)

2969:                   {

2970:                      start_j = P_offd_i[i];

2971:                      P_offd_i[i] = cnt_offd;

2972:                      for (j = start_j; j < last_index_offd; j++)

2973:                      {

2974:                         P_offd_j[cnt_offd] = P_offd_j[j];

2975:                         P_offd_data[cnt_offd++] = P_offd_data[j];

[...]

2983:                num_lost_per_thread[my_thread_num] += num_lost;

2984:                num_lost_offd_per_thread[my_thread_num] += num_lost_offd;

2985:                hypre_TFree(P_aux_j);

2986:                hypre_TFree(P_aux_data);

[...]

2994: #pragma omp barrier

2995: #endif

2996:        if(my_thread_num == 0)

2997:        {

2998:            num_lost_global = 0;

2999:            num_lost_global_offd = 0;

3000:            for(i = 0; i < max_num_threads[0]; i++)

3001:            {

3002:                num_lost_global += num_lost_per_thread[i];

3003:                num_lost_global_offd += num_lost_offd_per_thread[i];

3004:            }

3005:        }

3006: #ifdef HYPRE_USING_OPENMP

3007: #pragma omp barrier

[...]

3013:        if (num_lost_global)

[...]

3023:           if(my_thread_num == 0)

3024:           {

3025:               P_diag_size = P_diag_i[n_fine];

3026:

3027:               for(i = 0; i < max_num_threads[0]; i++)

3028:               {

3029:                   P_diag_size -= num_lost_per_thread[i];

3030:                   if(i > 0)

3031:                   {   cum_lost_per_thread[i] = num_lost_per_thread[i] + cum_lost_per_thread[i-1]; }

3032:                   else

3033:                   {   cum_lost_per_thread[i] = num_lost_per_thread[i]; }

3034:               }

3035:

3036:               P_diag_j_new = hypre_CTAlloc(HYPRE_Int,P_diag_size);

3037:               P_diag_data_new = hypre_CTAlloc(HYPRE_Real,P_diag_size);

3038:           }

3039: #ifdef HYPRE_USING_OPENMP

3040: #pragma omp barrier

3041: #endif

3042:

3043:           /* points to next open spot in new data structures for this thread */

3044:           if(my_thread_num == 0)

[...]

3050:               next_open = P_diag_i[start] - cum_lost_per_thread[my_thread_num-1];

3051:           }

3052:           /* copy the j and data arrays over */

3053:           for(i = P_diag_i[start]; i < P_diag_i[stop] - num_lost_per_thread[my_thread_num]; i++)

3054:           {

3055:               P_diag_j_new[next_open] = P_diag_j[i];

3056:               P_diag_data_new[next_open] = P_diag_data[i];

3057:               next_open += 1;

3058:           }

3059:

3060: #ifdef HYPRE_USING_OPENMP

3061: #pragma omp barrier

3062: #endif

3063:           /* update P_diag_i with number of dropped entries by all lower ranked

3064:            * threads */

3065:           if(my_thread_num > 0)

3066:           {

3067:               for(i=start; i<stop; i++)

3068:               {

3069:                   P_diag_i[i] -= cum_lost_per_thread[my_thread_num-1];

3070:               }

3071:           }

3072:

3073:           if(my_thread_num == 0)

3074:           {

3075:               /* Set last entry */

3076:               P_diag_i[n_fine] = P_diag_size ;

3077:

3078:               hypre_TFree(P_diag_j);

3079:               hypre_TFree(P_diag_data);

3080:               hypre_CSRMatrixJ(P_diag) = P_diag_j_new;

3081:               hypre_CSRMatrixData(P_diag) = P_diag_data_new;

3082:               hypre_CSRMatrixNumNonzeros(P_diag) = P_diag_size;

[...]

3091: #pragma omp barrier

3092: #endif

3093:        if (num_lost_global_offd)

3094:        {

3095:           /* Repeat process for off-diagonal */

3096:           if(my_thread_num == 0)

3097:           {

3098:               P_offd_size = P_offd_i[n_fine];

3099:               for(i = 0; i < max_num_threads[0]; i++)

3100:               {

3101:                   P_offd_size -= num_lost_offd_per_thread[i];

3102:                   if(i > 0)

3103:                   {   cum_lost_per_thread[i] = num_lost_offd_per_thread[i] + cum_lost_per_thread[i-1]; }

3104:                   else

3105:                   {   cum_lost_per_thread[i] = num_lost_offd_per_thread[i]; }

3106:               }

3107:

3108:               P_offd_j_new = hypre_CTAlloc(HYPRE_Int,P_offd_size);

3109:               P_offd_data_new = hypre_CTAlloc(HYPRE_Real,P_offd_size);

3110:           }

3111: #ifdef HYPRE_USING_OPENMP

3112: #pragma omp barrier

3113: #endif

3114:

3115:           /* points to next open spot in new data structures for this thread */

3116:           if(my_thread_num == 0)

[...]

3122:               next_open = P_offd_i[start] - cum_lost_per_thread[my_thread_num-1];

3123:           }

3124:

3125:           /* copy the j and data arrays over */

3126:           for(i = P_offd_i[start]; i < P_offd_i[stop] - num_lost_offd_per_thread[my_thread_num]; i++)

3127:           {

3128:               P_offd_j_new[next_open] = P_offd_j[i];

3129:               P_offd_data_new[next_open] = P_offd_data[i];

3130:               next_open += 1;

3131:           }

3132:

3133: #ifdef HYPRE_USING_OPENMP

3134: #pragma omp barrier

3135: #endif

3136:           /* update P_offd_i with number of dropped entries by all lower ranked

3137:            * threads */

3138:           if(my_thread_num > 0)

3139:           {

3140:               for(i=start; i<stop; i++)

3141:               {

3142:                   P_offd_i[i] -= cum_lost_per_thread[my_thread_num-1];

3143:               }

3144:           }

3145:

3146:           if(my_thread_num == 0)

3147:           {

3148:               /* Set last entry */

3149:               P_offd_i[n_fine] = P_offd_size ;

3150:

3151:               hypre_TFree(P_offd_j);

3152:               hypre_TFree(P_offd_data);

3153:               hypre_CSRMatrixJ(P_offd) = P_offd_j_new;

3154:               hypre_CSRMatrixData(P_offd) = P_offd_data_new;

3155:               hypre_CSRMatrixNumNonzeros(P_offd) = P_offd_size;

0x42c260 SUB	SP, SP, #320

0x42c264 STP	X29, X30, [SP, #224]

0x42c268 STP	X28, X27, [SP, #240]

0x42c26c STP	X26, X25, [SP, #256]

0x42c270 STP	X24, X23, [SP, #272]

0x42c274 STP	X22, X21, [SP, #288]

0x42c278 STP	X20, X19, [SP, #304]

0x42c27c ADD	X29, SP, #224

0x42c280 LDR	X8, [X29, #136]

0x42c284 LDP	X24, X28, [X29, #96]

0x42c288 STP	X6, X7, [X29, #976]

0x42c28c ORR	X26, XZR, X3

0x42c290 ORR	X19, XZR, X2

0x42c294 ORR	X20, XZR, X0

0x42c298 STP	X4, X5, [X29, #1000]

0x42c29c STR	X8, [SP, #112]

0x42c2a0 LDP	X8, X9, [X29, #120]

0x42c2a4 STP	X8, X9, [X29, #960]

0x42c2a8 LDR	X8, [X29, #112]

0x42c2ac STR	X8, [SP, #72]

0x42c2b0 BL	4a8a10

0x42c2b4 ORR	X23, XZR, X0

0x42c2b8 BL	4a89f0

0x42c2bc LDR	X8, [X19]

0x42c2c0 LDR	D0, [X26]

0x42c2c4 SUB	X9, X0, #1

0x42c2c8 CMP	X23, X9

0x42c2cc SDIV	X10, X8, X0

0x42c2d0 MADD	X27, X10, X23, XZR

0x42c2d4 STP	X10, X19, [SP, #56]

0x42c2d8 ADD	X10, X10, X27

0x42c2dc CSEL	X30, X8, X10, #0

0x42c2e0 FCMP	D0, #0

0x42c2e4 B.LE	42c694

0x42c2e8 STR	X20, [SP, #48]

0x42c2ec CMP	X30, X27

0x42c2f0 B.LE	42c660

0x42c2f4 LDP	X10, X11, [X29, #1000]

0x42c2f8 LDP	X13, X14, [X29, #976]

0x42c2fc ORR	X8, XZR, XZR

0x42c300 ORR	X9, XZR, XZR

0x42c304 ORR	X1, XZR, X27

0x42c308 LDR	X10, [X10]

0x42c30c LDR	X11, [X11]

0x42c310 LDR	X13, [X13]

0x42c314 LDR	X14, [X14]

0x42c318 LDR	X4, [X11, X27,LSL #3]

0x42c31c LDR	X12, [X10, X27,LSL #3]

0x42c320 ADD	X15, X13, #16

0x42c324 ADD	X16, X14, #16

0x42c328 ORR	X17, XZR, X4

0x42c32c ORR	X18, XZR, X4

0x42c330 ORR	X2, XZR, X12

0x42c334 B	42c348

0x42c338 HINT	#0

0x42c33c HINT	#0

(525) 0x42c340 CMP	X1, X30

(525) 0x42c344 B.EQ	42c668

(525) 0x42c348 ORR	X3, XZR, X1

(525) 0x42c34c LDR	X5, [X10, X1,LSL #3]

(525) 0x42c350 ADD	X1, X1, #1

(525) 0x42c354 MOVI	D0, #0

(525) 0x42c358 LDR	X6, [X10, X1,LSL #3]

(525) 0x42c35c SUBS	X7, X6, X5

(525) 0x42c360 B.LE	42c3d8

(525) 0x42c364 MOVI	D0, #0

(525) 0x42c368 ORR	X19, XZR, X5

(525) 0x42c36c CMP	X7, #4

(525) 0x42c370 B.CC	42c3bc

(525) 0x42c374 AND	X20, X7, #8062

(525) 0x42c378 ADD	X21, X15, X5,LSL #3

(525) 0x42c37c MOVI	V0.2D, #0

(525) 0x42c380 MOVI	V1.2D, #0

(525) 0x42c384 ADD	X19, X5, X20

(525) 0x42c388 ORR	X22, XZR, X20

  (531) 0x42c38c LDP	Q2, Q3, [X21, #2032]

  (531) 0x42c390 ADD	X21, X21, #32

  (531) 0x42c394 SUBS	X22, X22, #4

  (531) 0x42c398 FABS	V3.2D, V3.2D

  (531) 0x42c39c FABS	V2.2D, V2.2D

  (531) 0x42c3a0 FMAXNM	V1.2D, V1.2D, V3.2D

  (531) 0x42c3a4 FMAXNM	V0.2D, V0.2D, V2.2D

  (531) 0x42c3a8 B.NE	42c38c

(525) 0x42c3ac FMAXNM	V0.2D, V0.2D, V1.2D

(525) 0x42c3b0 FMAXNMP	D0, V0.2D

(525) 0x42c3b4 CMP	X7, X20

(525) 0x42c3b8 B.EQ	42c3d8

(525) 0x42c3bc ADD	X7, X13, X19,LSL #3

(525) 0x42c3c0 SUB	X19, X6, X19

  (530) 0x42c3c4 LDR	D1, [X7], #8

  (530) 0x42c3c8 SUBS	X19, X19, #1

  (530) 0x42c3cc FABS	D1, D1

  (530) 0x42c3d0 FMAXNM	D0, D0, D1

  (530) 0x42c3d4 B.NE	42c3c4

(525) 0x42c3d8 LDR	X7, [X11, X1,LSL #3]

(525) 0x42c3dc SUBS	X20, X7, X4

(525) 0x42c3e0 B.LE	42c474

(525) 0x42c3e4 CMP	X20, #4

(525) 0x42c3e8 B.CS	42c400

(525) 0x42c3ec ORR	X19, XZR, X4

(525) 0x42c3f0 B	42c450

0x42c3f4 HINT	#0

0x42c3f8 HINT	#0

0x42c3fc HINT	#0

(525) 0x42c400 DUP	V0.2D, V0.D[0]

(525) 0x42c404 AND	X21, X20, #8062

(525) 0x42c408 ADD	X19, X4, X21

(525) 0x42c40c ADD	X4, X16, X4,LSL #3

(525) 0x42c410 ORR	X22, XZR, X21

(525) 0x42c414 ORR	V1.16B, V0.16B, V0.16B

(525) 0x42c418 HINT	#0

(525) 0x42c41c HINT	#0

  (528) 0x42c420 LDP	Q2, Q3, [X4, #2032]

  (528) 0x42c424 ADD	X4, X4, #32

  (528) 0x42c428 SUBS	X22, X22, #4

  (528) 0x42c42c FABS	V3.2D, V3.2D

  (528) 0x42c430 FABS	V2.2D, V2.2D

  (528) 0x42c434 FMAXNM	V1.2D, V1.2D, V3.2D

  (528) 0x42c438 FMAXNM	V0.2D, V0.2D, V2.2D

  (528) 0x42c43c B.NE	42c420

(525) 0x42c440 FMAXNM	V0.2D, V0.2D, V1.2D

(525) 0x42c444 FMAXNMP	D0, V0.2D

(525) 0x42c448 CMP	X20, X21

(525) 0x42c44c B.EQ	42c474

(525) 0x42c450 ADD	X4, X14, X19,LSL #3

(525) 0x42c454 SUB	X7, X7, X19

(525) 0x42c458 HINT	#0

(525) 0x42c45c HINT	#0

  (529) 0x42c460 LDR	D1, [X4], #8

  (529) 0x42c464 SUBS	X7, X7, #1

  (529) 0x42c468 FABS	D1, D1

  (529) 0x42c46c FMAXNM	D0, D0, D1

  (529) 0x42c470 B.NE	42c460

(525) 0x42c474 LDR	D1, [X26]

(525) 0x42c478 CBZ	X9, 42c484

(525) 0x42c47c SUB	X4, X5, X9

(525) 0x42c480 STR	X4, [X10, X3,LSL #3]

(525) 0x42c484 FMUL	D2, D1, D0

(525) 0x42c488 MOVI	D1, #0

(525) 0x42c48c CMP	X6, X5

(525) 0x42c490 B.LE	42c4e4

(525) 0x42c494 LDR	X4, [X24]

(525) 0x42c498 MOVI	D0, #0

(525) 0x42c49c B	42c4cc

  (527) 0x42c4a0 LDR	X6, [X4, X2,LSL #3]

  (527) 0x42c4a4 FADD	D0, D3, D0

  (527) 0x42c4a8 STR	D3, [X13, X12,LSL #3]

  (527) 0x42c4ac STR	X6, [X4, X12,LSL #3]

  (527) 0x42c4b0 ADD	X12, X12, #1

  (527) 0x42c4b4 LDR	X6, [X10, X1,LSL #3]

  (527) 0x42c4b8 FADD	D1, D3, D1

  (527) 0x42c4bc ADD	X2, X2, #1

  (527) 0x42c4c0 ADD	X5, X5, #1

  (527) 0x42c4c4 CMP	X5, X6

  (527) 0x42c4c8 B.GE	42c4e8

  (527) 0x42c4cc LDR	D3, [X13, X2,LSL #3]

  (527) 0x42c4d0 FABS	D4, D3

  (527) 0x42c4d4 FCMP	D4, D2

  (527) 0x42c4d8 B.GE	42c4a0

  (527) 0x42c4dc ADD	X9, X9, #1

  (527) 0x42c4e0 B	42c4b8

(525) 0x42c4e4 MOVI	D0, #0

(525) 0x42c4e8 LDR	X5, [X11, X3,LSL #3]

(525) 0x42c4ec CBZ	X8, 42c4f8

(525) 0x42c4f0 SUB	X4, X5, X8

(525) 0x42c4f4 STR	X4, [X11, X3,LSL #3]

(525) 0x42c4f8 LDR	X4, [X11, X1,LSL #3]

(525) 0x42c4fc CMP	X5, X4

(525) 0x42c500 B.GE	42c560

(525) 0x42c504 LDR	X6, [X28]

(525) 0x42c508 B	42c524

  (526) 0x42c50c ADD	X8, X8, #1

  (526) 0x42c510 FADD	D1, D3, D1

  (526) 0x42c514 ADD	X18, X18, #1

  (526) 0x42c518 ADD	X5, X5, #1

  (526) 0x42c51c CMP	X5, X4

  (526) 0x42c520 B.GE	42c560

  (526) 0x42c524 LDR	D3, [X14, X18,LSL #3]

  (526) 0x42c528 FABS	D4, D3

  (526) 0x42c52c FCMP	D4, D2

  (526) 0x42c530 B.LT	42c50c

  (526) 0x42c534 LDR	X4, [X6, X18,LSL #3]

  (526) 0x42c538 FADD	D0, D3, D0

  (526) 0x42c53c STR	D3, [X14, X17,LSL #3]

  (526) 0x42c540 STR	X4, [X6, X17,LSL #3]

  (526) 0x42c544 ADD	X17, X17, #1

  (526) 0x42c548 LDR	X4, [X11, X1,LSL #3]

  (526) 0x42c54c B	42c510

0x42c550 HINT	#0

0x42c554 HINT	#0

0x42c558 HINT	#0

0x42c55c HINT	#0

(525) 0x42c560 FCMP	D0, #0

(525) 0x42c564 FCCMP	D0, D1, #4, #1

(525) 0x42c568 B.EQ	42c340

(525) 0x42c56c FDIV	D0, D1, D0

(525) 0x42c570 LDR	X6, [X10, X1,LSL #3]

(525) 0x42c574 LDR	X20, [X10, X3,LSL #3]

(525) 0x42c578 SUB	X5, X6, X9

(525) 0x42c57c CMP	X20, X5

(525) 0x42c580 B.GE	42c5e4

(525) 0x42c584 ADD	X7, X9, X20

(525) 0x42c588 SUB	X7, X6, X7

(525) 0x42c58c ORR	X6, XZR, X20

(525) 0x42c590 CMP	X7, #4

(525) 0x42c594 B.CC	42c5cc

(525) 0x42c598 AND	X19, X7, #8062

(525) 0x42c59c ADD	X6, X20, X19

(525) 0x42c5a0 ADD	X20, X15, X20,LSL #3

(525) 0x42c5a4 ORR	X21, XZR, X19

  (535) 0x42c5a8 LDP	Q1, Q2, [X20, #2032]

  (535) 0x42c5ac SUBS	X21, X21, #4

  (535) 0x42c5b0 FMUL	V2.2D, V2.2D, V0.D[0]

  (535) 0x42c5b4 FMUL	V1.2D, V1.2D, V0.D[0]

  (535) 0x42c5b8 STP	Q1, Q2, [X20, #2032]

  (535) 0x42c5bc ADD	X20, X20, #32

  (535) 0x42c5c0 B.NE	42c5a8

(525) 0x42c5c4 CMP	X7, X19

(525) 0x42c5c8 B.EQ	42c5e4

  (534) 0x42c5cc LDR	D1, [X13, X6,LSL #3]

  (534) 0x42c5d0 FMUL	D1, D1, D0

  (534) 0x42c5d4 STR	D1, [X13, X6,LSL #3]

  (534) 0x42c5d8 ADD	X6, X6, #1

  (534) 0x42c5dc CMP	X6, X5

  (534) 0x42c5e0 B.LT	42c5cc

(525) 0x42c5e4 LDR	X19, [X11, X3,LSL #3]

(525) 0x42c5e8 SUB	X3, X4, X8

(525) 0x42c5ec CMP	X19, X3

(525) 0x42c5f0 B.GE	42c340

(525) 0x42c5f4 ADD	X5, X8, X19

(525) 0x42c5f8 SUB	X6, X4, X5

(525) 0x42c5fc ORR	X5, XZR, X19

(525) 0x42c600 CMP	X6, #4

(525) 0x42c604 B.CC	42c644

(525) 0x42c608 AND	X7, X6, #8062

(525) 0x42c60c ADD	X5, X19, X7

(525) 0x42c610 ADD	X19, X16, X19,LSL #3

(525) 0x42c614 ORR	X20, XZR, X7

(525) 0x42c618 HINT	#0

(525) 0x42c61c HINT	#0

  (533) 0x42c620 LDP	Q1, Q2, [X19, #2032]

  (533) 0x42c624 SUBS	X20, X20, #4

  (533) 0x42c628 FMUL	V2.2D, V2.2D, V0.D[0]

  (533) 0x42c62c FMUL	V1.2D, V1.2D, V0.D[0]

  (533) 0x42c630 STP	Q1, Q2, [X19, #2032]

  (533) 0x42c634 ADD	X19, X19, #32

  (533) 0x42c638 B.NE	42c620

(525) 0x42c63c CMP	X6, X7

(525) 0x42c640 B.EQ	42c340

  (532) 0x42c644 LDR	D1, [X14, X5,LSL #3]

  (532) 0x42c648 FMUL	D1, D1, D0

  (532) 0x42c64c STR	D1, [X14, X5,LSL #3]

  (532) 0x42c650 ADD	X5, X5, #1

  (532) 0x42c654 CMP	X5, X3

  (532) 0x42c658 B.LT	42c644

(525) 0x42c65c B	42c340

0x42c660 ORR	X9, XZR, XZR

0x42c664 ORR	X8, XZR, XZR

0x42c668 CBNZ	X23, 42c678

0x42c66c LDR	X10, [SP, #72]

0x42c670 LDR	X10, [X10]

0x42c674 STR	X0, [X10]

0x42c678 LDUR	X10, [X29, #448]

0x42c67c LDR	X20, [SP, #48]

0x42c680 LDR	X10, [X10]

0x42c684 STR	X9, [X10, X23,LSL #3]

0x42c688 LDUR	X9, [X29, #456]

0x42c68c LDR	X9, [X9]

0x42c690 STR	X8, [X9, X23,LSL #3]

0x42c694 LDR	X8, [SP, #112]

0x42c698 LDP	X21, X26, [X29, #152]

0x42c69c STUR	X27, [X29, #440]

0x42c6a0 STUR	X30, [X29, #480]

0x42c6a4 LDR	X8, [X8]

0x42c6a8 CMP	X8, #1

0x42c6ac B.LT	42d158

0x42c6b0 LDUR	X9, [X29, #440]

0x42c6b4 ORR	X27, XZR, XZR

0x42c6b8 SUBS	X9, X30, X9

0x42c6bc B.LE	42c750

0x42c6c0 LDP	X11, X10, [X29, #1000]

0x42c6c4 LDR	X14, [SP, #56]

0x42c6c8 LDR	X13, [X11]

0x42c6cc LDR	X12, [X10]

0x42c6d0 LDP	X10, X11, [X29, #960]

0x42c6d4 MADD	X14, X23, X14, XZR

0x42c6d8 UBFM	X14, X14, #61, #60

0x42c6dc ADD	X14, X14, #8

0x42c6e0 LDR	X10, [X10]

0x42c6e4 LDR	X11, [X11]

0x42c6e8 ADD	X12, X12, X14

0x42c6ec ADD	X13, X13, X14

0x42c6f0 B	42c72c

0x42c6f4 HINT	#0

0x42c6f8 HINT	#0

0x42c6fc HINT	#0

(524) 0x42c700 LDUR	X16, [X13, #504]

(524) 0x42c704 LDUR	X17, [X12, #504]

(524) 0x42c708 ADD	X14, X15, X14

(524) 0x42c70c ADD	X12, X12, #8

(524) 0x42c710 ADD	X13, X13, #8

(524) 0x42c714 ADD	X15, X16, X17

(524) 0x42c718 SUB	X14, X14, X15

(524) 0x42c71c CMP	X14, X27

(524) 0x42c720 CSEL	X27, X14, X27, #12

(524) 0x42c724 SUBS	X9, X9, #1

(524) 0x42c728 B.EQ	42c750

(524) 0x42c72c LDR	X14, [X13]

(524) 0x42c730 LDR	X15, [X12]

(524) 0x42c734 CMP	X9, #1

(524) 0x42c738 B.NE	42c700

(524) 0x42c73c LDR	X16, [X10, X23,LSL #3]

(524) 0x42c740 SUB	X14, X14, X16

(524) 0x42c744 LDR	X16, [X11, X23,LSL #3]

(524) 0x42c748 SUB	X15, X15, X16

(524) 0x42c74c B	42c700

0x42c750 CMP	X27, X8

0x42c754 B.LE	42d158

0x42c758 MOVZ	W1, #8

0x42c75c STR	X21, [SP, #8]

0x42c760 STR	X26, [SP, #24]

0x42c764 ORR	X0, XZR, X27

0x42c768 STR	X20, [SP, #48]

0x42c76c STP	X23, X24, [SP, #88]

0x42c770 STR	X28, [SP, #104]

0x42c774 BL	4a6c90

0x42c778 MOVZ	W1, #8

0x42c77c ORR	X26, XZR, X0

0x42c780 ORR	X0, XZR, X27

0x42c784 BL	4a6c90

0x42c788 LDUR	X4, [X29, #480]

0x42c78c LDUR	X28, [X29, #440]

0x42c790 ORR	X27, XZR, X0

0x42c794 CMP	X4, X28

0x42c798 B.LE	42d104

0x42c79c LDP	X9, X8, [X29, #1000]

0x42c7a0 LDR	X21, [X29, #144]

0x42c7a4 LDR	X30, [SP, #112]

0x42c7a8 SUB	X7, X4, #1

0x42c7ac ADD	X11, X26, #16

0x42c7b0 ORR	X5, XZR, XZR

0x42c7b4 ORR	X6, XZR, XZR

0x42c7b8 STR	X7, [SP, #80]

0x42c7bc LDR	X8, [X8]

0x42c7c0 LDR	X10, [X9]

0x42c7c4 ADD	X9, X21, #8

0x42c7c8 STR	X9, [SP, #16]

0x42c7cc ADD	X9, X27, #16

0x42c7d0 STP	X9, X11, [SP, #32]

0x42c7d4 LDR	X20, [X8, X28,LSL #3]

0x42c7d8 LDR	X24, [X10, X28,LSL #3]

0x42c7dc B	42c7fc

    (512) 0x42c7e0 ORR	X13, XZR, X24

      (505) 0x42c7e4 ORR	X9, XZR, X20

        (504) 0x42c7e8 ORR	X28, XZR, X25

        (504) 0x42c7ec ORR	X20, XZR, X9

        (504) 0x42c7f0 ORR	X24, XZR, X13

        (504) 0x42c7f4 CMP	X25, X4

        (504) 0x42c7f8 B.EQ	42d10c

        (504) 0x42c7fc ADD	X25, X28, #1

        (504) 0x42c800 LDR	X11, [X10, X25,LSL #3]

        (504) 0x42c804 LDR	X9, [X8, X25,LSL #3]

        (504) 0x42c808 CMP	X28, X7

        (504) 0x42c80c B.NE	42c834

        (504) 0x42c810 LDUR	X12, [X29, #448]

        (504) 0x42c814 LDR	X13, [SP, #88]

        (504) 0x42c818 LDR	X12, [X12]

        (504) 0x42c81c LDR	X12, [X12, X13,LSL #3]

        (504) 0x42c820 SUB	X11, X11, X12

        (504) 0x42c824 LDUR	X12, [X29, #456]

        (504) 0x42c828 LDR	X12, [X12]

        (504) 0x42c82c LDR	X12, [X12, X13,LSL #3]

        (504) 0x42c830 SUB	X9, X9, X12

        (504) 0x42c834 LDR	X12, [X10, X28,LSL #3]

        (504) 0x42c838 LDR	X13, [X8, X28,LSL #3]

        (504) 0x42c83c LDR	X15, [X30]

        (504) 0x42c840 SUB	X19, X11, X12

        (504) 0x42c844 ADD	X14, X19, X9

        (504) 0x42c848 SUB	X14, X14, X13

        (504) 0x42c84c CMP	X15, X14

        (504) 0x42c850 B.GE	42c8cc

    (512) 0x42c854 CMP	X11, X12

    (512) 0x42c858 B.LE	42c8e0

    (512) 0x42c85c LDR	X10, [SP, #96]

    (512) 0x42c860 MOVI	D2, #0

    (512) 0x42c864 LDR	X13, [X10]

    (512) 0x42c868 LDUR	X10, [X29, #464]

    (512) 0x42c86c LDR	X10, [X10]

    (512) 0x42c870 CMP	X19, #4

    (512) 0x42c874 B.CS	42c974

    (512) 0x42c878 ORR	X14, XZR, XZR

    (512) 0x42c87c ORR	X15, XZR, X12

    (512) 0x42c880 SUB	W16, W11, W12

    (512) 0x42c884 ANDS	X16, X16, #4160

    (512) 0x42c888 B.EQ	42ca68

    (512) 0x42c88c ADD	X18, X27, X14,LSL #3

    (512) 0x42c890 ADD	X0, X26, X14,LSL #3

    (512) 0x42c894 ADD	X1, X10, X15,LSL #3

    (512) 0x42c898 ADD	X2, X13, X15,LSL #3

    (512) 0x42c89c ORR	X17, XZR, XZR

      (518) 0x42c8a0 LDR	D0, [X1, X17,LSL #3]

      (518) 0x42c8a4 LDR	X3, [X2, X17,LSL #3]

      (518) 0x42c8a8 STR	X3, [X0, X17,LSL #3]

      (518) 0x42c8ac FADD	D2, D0, D2

      (518) 0x42c8b0 STR	D0, [X18, X17,LSL #3]

      (518) 0x42c8b4 ADD	X17, X17, #1

      (518) 0x42c8b8 CMP	X16, X17

      (518) 0x42c8bc B.NE	42c8a0

    (512) 0x42c8c0 ADD	X16, X14, X17

    (512) 0x42c8c4 ADD	X15, X15, X17

    (512) 0x42c8c8 B	42ca6c

        (504) 0x42c8cc SUBS	X13, X24, X12

        (504) 0x42c8d0 B.NE	42c8ec

        (504) 0x42c8d4 ADD	X13, X19, X24

        (504) 0x42c8d8 B	42cf80

0x42c8dc HINT	#0

    (512) 0x42c8e0 ORR	X19, XZR, XZR

    (512) 0x42c8e4 MOVI	D2, #0

    (512) 0x42c8e8 B	42cb0c

        (504) 0x42c8ec STR	X24, [X10, X28,LSL #3]

        (504) 0x42c8f0 CMP	X11, X12

        (504) 0x42c8f4 B.LE	42ca0c

        (504) 0x42c8f8 LDR	X14, [SP, #96]

        (504) 0x42c8fc LDR	X15, [X14]

        (504) 0x42c900 LDUR	X14, [X29, #464]

        (504) 0x42c904 LDR	X14, [X14]

        (504) 0x42c908 CMP	X19, #4

        (504) 0x42c90c B.CC	42ca14

        (504) 0x42c910 ANDS	XZR, X13, #7870

        (504) 0x42c914 B.EQ	42ca14

        (504) 0x42c918 AND	X17, X19, #8062

        (504) 0x42c91c ADD	X2, X14, #16

        (504) 0x42c920 ADD	X1, X15, #16

        (504) 0x42c924 ADD	X13, X24, X17

        (504) 0x42c928 ADD	X16, X12, X17

        (504) 0x42c92c ADD	X18, X2, X24,LSL #3

        (504) 0x42c930 ADD	X0, X1, X12,LSL #3

        (504) 0x42c934 ADD	X1, X1, X24,LSL #3

        (504) 0x42c938 ADD	X12, X2, X12,LSL #3

        (504) 0x42c93c ORR	X2, XZR, X17

          (511) 0x42c940 LDP	Q0, Q1, [X0, #2032]

          (511) 0x42c944 SUBS	X2, X2, #4

          (511) 0x42c948 ADD	X0, X0, #32

          (511) 0x42c94c STP	Q0, Q1, [X1, #2032]

          (511) 0x42c950 LDP	Q0, Q1, [X12, #2032]

          (511) 0x42c954 ADD	X1, X1, #32

          (511) 0x42c958 ADD	X12, X12, #32

          (511) 0x42c95c STP	Q0, Q1, [X18, #2032]

          (511) 0x42c960 ADD	X18, X18, #32

          (511) 0x42c964 B.NE	42c940

        (504) 0x42c968 CMP	X19, X17

        (504) 0x42c96c B.NE	42ca1c

        (504) 0x42c970 B	42cf80

    (512) 0x42c974 ADD	X15, X13, X12,LSL #3

    (512) 0x42c978 ORR	X14, XZR, XZR

    (512) 0x42c97c SUB	X15, X26, X15

    (512) 0x42c980 CMP	X15, #32

    (512) 0x42c984 B.CC	42c87c

    (512) 0x42c988 ADD	X15, X10, X12,LSL #3

    (512) 0x42c98c SUB	X16, X27, X15

    (512) 0x42c990 ORR	X15, XZR, X12

    (512) 0x42c994 CMP	X16, #32

    (512) 0x42c998 B.CC	42c880

    (512) 0x42c99c LDP	X0, X1, [SP, #32]

    (512) 0x42c9a0 UBFM	X17, X12, #61, #60

    (512) 0x42c9a4 AND	X14, X19, #8062

    (512) 0x42c9a8 MOVI	V0.2D, #0

    (512) 0x42c9ac MOVI	V1.2D, #0

    (512) 0x42c9b0 ADD	X16, X10, X17

    (512) 0x42c9b4 ADD	X17, X13, X17

    (512) 0x42c9b8 ADD	X15, X12, X14

    (512) 0x42c9bc ORR	X18, XZR, X14

    (512) 0x42c9c0 ADD	X16, X16, #16

    (512) 0x42c9c4 ADD	X17, X17, #16

      (519) 0x42c9c8 LDP	Q2, Q3, [X17, #2032]

      (519) 0x42c9cc ADD	X17, X17, #32

      (519) 0x42c9d0 SUBS	X18, X18, #4

      (519) 0x42c9d4 STP	Q2, Q3, [X1, #2032]

      (519) 0x42c9d8 LDP	Q2, Q3, [X16, #2032]

      (519) 0x42c9dc ADD	X16, X16, #32

      (519) 0x42c9e0 ADD	X1, X1, #32

      (519) 0x42c9e4 FADD	V1.2D, V3.2D, V1.2D

      (519) 0x42c9e8 FADD	V0.2D, V2.2D, V0.2D

      (519) 0x42c9ec STP	Q2, Q3, [X0, #2032]

      (519) 0x42c9f0 ADD	X0, X0, #32

      (519) 0x42c9f4 B.NE	42c9c8

    (512) 0x42c9f8 FADD	V0.2D, V1.2D, V0.2D

    (512) 0x42c9fc FADDP	D2, V0.2D

    (512) 0x42ca00 CMP	X19, X14

    (512) 0x42ca04 B.NE	42c880

    (512) 0x42ca08 B	42cb08

        (504) 0x42ca0c ORR	X13, XZR, X24

        (504) 0x42ca10 B	42cf80

        (504) 0x42ca14 ORR	X13, XZR, X24

        (504) 0x42ca18 ORR	X16, XZR, X12

        (504) 0x42ca1c SUB	W12, W11, W16

        (504) 0x42ca20 ANDS	X17, X12, #4160

        (504) 0x42ca24 B.EQ	42cef4

        (504) 0x42ca28 ADD	X18, X14, X13,LSL #3

        (504) 0x42ca2c ADD	X0, X15, X13,LSL #3

        (504) 0x42ca30 ADD	X1, X14, X16,LSL #3

        (504) 0x42ca34 ADD	X2, X15, X16,LSL #3

        (504) 0x42ca38 ORR	X12, XZR, XZR

        (504) 0x42ca3c HINT	#0

          (510) 0x42ca40 LDR	D0, [X1, X12,LSL #3]

          (510) 0x42ca44 LDR	X3, [X2, X12,LSL #3]

          (510) 0x42ca48 STR	X3, [X0, X12,LSL #3]

          (510) 0x42ca4c STR	D0, [X18, X12,LSL #3]

          (510) 0x42ca50 ADD	X12, X12, #1

          (510) 0x42ca54 CMP	X17, X12

          (510) 0x42ca58 B.NE	42ca40

        (504) 0x42ca5c ADD	X13, X13, X12

        (504) 0x42ca60 ADD	X17, X16, X12

        (504) 0x42ca64 B	42cef8

    (512) 0x42ca68 ORR	X16, XZR, X14

    (512) 0x42ca6c SUB	X14, X14, X11

    (512) 0x42ca70 ADD	X14, X14, X12

    (512) 0x42ca74 CMN	X14, #4

    (512) 0x42ca78 B.HI	42cb08

    (512) 0x42ca7c ADD	X13, X13, X15,LSL #3

    (512) 0x42ca80 ADD	X10, X10, X15,LSL #3

    (512) 0x42ca84 LDP	X15, X17, [SP, #32]

    (512) 0x42ca88 ADD	X14, X16, X12

    (512) 0x42ca8c SUB	X14, X14, X11

    (512) 0x42ca90 ADD	X13, X13, #16

    (512) 0x42ca94 ADD	X10, X10, #16

    (512) 0x42ca98 ADD	X15, X15, X16,LSL #3

    (512) 0x42ca9c ADD	X16, X17, X16,LSL #3

      (517) 0x42caa0 LDUR	D0, [X10, #496]

      (517) 0x42caa4 LDUR	X17, [X13, #496]

      (517) 0x42caa8 ADDS	X14, X14, #4

      (517) 0x42caac STUR	X17, [X16, #496]

      (517) 0x42cab0 LDUR	X17, [X13, #504]

      (517) 0x42cab4 STUR	D0, [X15, #496]

      (517) 0x42cab8 FADD	D0, D0, D2

      (517) 0x42cabc LDUR	D1, [X10, #504]

      (517) 0x42cac0 STUR	X17, [X16, #504]

      (517) 0x42cac4 LDR	X17, [X13]

      (517) 0x42cac8 STUR	D1, [X15, #504]

      (517) 0x42cacc LDR	D2, [X10]

      (517) 0x42cad0 STR	X17, [X16]

      (517) 0x42cad4 LDR	X17, [X13, #8]

      (517) 0x42cad8 ADD	X13, X13, #32

      (517) 0x42cadc STR	X17, [X16, #8]

      (517) 0x42cae0 ADD	X16, X16, #32

      (517) 0x42cae4 FADD	D1, D2, D1

      (517) 0x42cae8 STR	D2, [X15]

      (517) 0x42caec FADD	D0, D1, D0

      (517) 0x42caf0 LDR	D1, [X10, #8]

      (517) 0x42caf4 ADD	X10, X10, #32

      (517) 0x42caf8 FADD	D2, D1, D0

      (517) 0x42cafc STR	D1, [X15, #8]

      (517) 0x42cb00 ADD	X15, X15, #32

      (517) 0x42cb04 B.NE	42caa0

    (512) 0x42cb08 LDR	X13, [X8, X28,LSL #3]

    (512) 0x42cb0c SUBS	X14, X9, X13

    (512) 0x42cb10 STUR	X19, [X29, #408]

    (512) 0x42cb14 B.LE	42cba0

    (512) 0x42cb18 LDR	X8, [SP, #104]

    (512) 0x42cb1c ADD	X15, X9, X19

    (512) 0x42cb20 SUB	X7, X15, X13

    (512) 0x42cb24 LDR	X10, [X8]

    (512) 0x42cb28 LDUR	X8, [X29, #472]

    (512) 0x42cb2c LDR	X8, [X8]

    (512) 0x42cb30 CMP	X14, #8

    (512) 0x42cb34 B.CS	42cde0

    (512) 0x42cb38 ORR	X15, XZR, X19

    (512) 0x42cb3c ORR	X16, XZR, X13

    (512) 0x42cb40 ADD	X13, X15, X13

    (512) 0x42cb44 CMP	X11, X12

    (512) 0x42cb48 ADD	X14, X26, X15,LSL #3

    (512) 0x42cb4c ADD	X10, X10, X16,LSL #3

    (512) 0x42cb50 ADD	X8, X8, X16,LSL #3

    (512) 0x42cb54 ADD	X13, X13, X12

    (512) 0x42cb58 CSEL	X11, X11, X12, #12

    (512) 0x42cb5c SUB	X9, X13, X9

    (512) 0x42cb60 SUB	X9, X9, X11

    (512) 0x42cb64 ADD	X11, X27, X15,LSL #3

      (515) 0x42cb68 LDR	D0, [X8], #8

      (515) 0x42cb6c LDR	X12, [X10], #8

      (515) 0x42cb70 LDR	X13, [X21]

      (515) 0x42cb74 ADDS	X9, X9, #1

      (515) 0x42cb78 ADD	X12, X13, X12

      (515) 0x42cb7c STR	X12, [X14], #8

      (515) 0x42cb80 FADD	D2, D0, D2

      (515) 0x42cb84 STR	D0, [X11], #8

      (515) 0x42cb88 B.CC	42cb68

    (512) 0x42cb8c STUR	Q2, [X29, #416]

    (512) 0x42cb90 ORR	X22, XZR, X6

    (512) 0x42cb94 ORR	X23, XZR, X5

    (512) 0x42cb98 B	42cbb0

0x42cb9c HINT	#0

    (512) 0x42cba0 STUR	Q2, [X29, #416]

    (512) 0x42cba4 ORR	X22, XZR, X6

    (512) 0x42cba8 ORR	X23, XZR, X5

    (512) 0x42cbac ORR	X7, XZR, X19

    (512) 0x42cbb0 SUB	X3, X7, #1

    (512) 0x42cbb4 ORR	X19, XZR, X7

    (512) 0x42cbb8 ORR	X0, XZR, X26

    (512) 0x42cbbc ORR	X1, XZR, X27

    (512) 0x42cbc0 ORR	X2, XZR, XZR

    (512) 0x42cbc4 BL	42c170

    (512) 0x42cbc8 LDUR	X8, [X29, #440]

    (512) 0x42cbcc CMP	X28, X8

    (512) 0x42cbd0 B.LE	42cbec

    (512) 0x42cbd4 LDUR	X8, [X29, #488]

    (512) 0x42cbd8 LDR	X8, [X8]

    (512) 0x42cbdc STR	X24, [X8, X28,LSL #3]

    (512) 0x42cbe0 LDUR	X8, [X29, #496]

    (512) 0x42cbe4 LDR	X8, [X8]

    (512) 0x42cbe8 STR	X20, [X8, X28,LSL #3]

    (512) 0x42cbec LDR	X30, [SP, #112]

    (512) 0x42cbf0 LDUR	Q2, [X29, #416]

    (512) 0x42cbf4 LDUR	X4, [X29, #480]

    (512) 0x42cbf8 ORR	X16, XZR, X22

    (512) 0x42cbfc LDR	X7, [SP, #80]

    (512) 0x42cc00 LDR	X8, [X30]

    (512) 0x42cc04 CMP	X8, #1

    (512) 0x42cc08 B.LT	42cc90

  (514) 0x42cc0c LDP	X11, X9, [SP, #96]

  (514) 0x42cc10 LDP	X12, X10, [X29, #976]

  (514) 0x42cc14 MOVI	D0, #0

  (514) 0x42cc18 ORR	X8, XZR, XZR

  (514) 0x42cc1c LDR	X9, [X9]

  (514) 0x42cc20 LDR	X10, [X10]

  (514) 0x42cc24 LDR	X11, [X11]

  (514) 0x42cc28 LDR	X12, [X12]

  (514) 0x42cc2c B	42cc68

0x42cc30 HINT	#0

0x42cc34 HINT	#0

0x42cc38 HINT	#0

0x42cc3c HINT	#0

(513) 0x42cc40 UBFM	X13, X20, #61, #60

(513) 0x42cc44 STR	X14, [X9, X13]

(513) 0x42cc48 ADD	X13, X10, X20,LSL #3

(513) 0x42cc4c ADD	X20, X20, #1

  (514) 0x42cc50 STR	D1, [X13]

  (514) 0x42cc54 LDR	X13, [X30]

  (514) 0x42cc58 FADD	D0, D1, D0

  (514) 0x42cc5c ADD	X8, X8, #1

  (514) 0x42cc60 CMP	X8, X13

  (514) 0x42cc64 B.GE	42cc94

  (514) 0x42cc68 LDR	D1, [X27, X8,LSL #3]

  (514) 0x42cc6c LDR	X13, [X26, X8,LSL #3]

  (514) 0x42cc70 LDR	X14, [X21]

  (514) 0x42cc74 SUBS	X14, X13, X14

  (514) 0x42cc78 B.GE	42cc40

  (514) 0x42cc7c UBFM	X14, X24, #61, #60

  (514) 0x42cc80 STR	X13, [X11, X14]

  (514) 0x42cc84 ADD	X13, X12, X24,LSL #3

  (514) 0x42cc88 ADD	X24, X24, #1

  (514) 0x42cc8c B	42cc50

    (512) 0x42cc90 MOVI	D0, #0

    (512) 0x42cc94 LDUR	X9, [X29, #488]

    (512) 0x42cc98 LDUR	X12, [X29, #408]

    (512) 0x42cc9c FCMP	D0, #0

    (512) 0x42cca0 LDR	X10, [X9]

    (512) 0x42cca4 ADD	X8, X12, X16

    (512) 0x42cca8 SUB	X12, X23, X12

    (512) 0x42ccac FCCMP	D0, D2, #4, #1

    (512) 0x42ccb0 ADD	X12, X12, X19

    (512) 0x42ccb4 LDR	X13, [X10, X28,LSL #3]

    (512) 0x42ccb8 SUB	X9, X13, X24

    (512) 0x42ccbc ADD	X6, X8, X9

    (512) 0x42ccc0 LDUR	X8, [X29, #496]

    (512) 0x42ccc4 LDR	X8, [X8]

    (512) 0x42ccc8 LDR	X9, [X8, X28,LSL #3]

    (512) 0x42cccc SUB	X11, X9, X20

    (512) 0x42ccd0 ADD	X5, X12, X11

    (512) 0x42ccd4 B.EQ	42c7e0

    (512) 0x42ccd8 FDIV	D0, D2, D0

    (512) 0x42ccdc CMP	X13, X24

    (512) 0x42cce0 B.GE	42cd60

    (512) 0x42cce4 LDUR	X11, [X29, #464]

    (512) 0x42cce8 SUB	X14, X24, X13

    (512) 0x42ccec ORR	X12, XZR, X13

    (512) 0x42ccf0 LDR	X11, [X11]

    (512) 0x42ccf4 CMP	X14, #3

    (512) 0x42ccf8 B.LS	42cd44

    (512) 0x42ccfc AND	X15, X14, #8062

    (512) 0x42cd00 ADD	X12, X13, X15

    (512) 0x42cd04 ADD	X13, X11, X13,LSL #3

    (512) 0x42cd08 ORR	X16, XZR, X15

    (512) 0x42cd0c ADD	X13, X13, #16

    (512) 0x42cd10 HINT	#0

    (512) 0x42cd14 HINT	#0

    (512) 0x42cd18 HINT	#0

    (512) 0x42cd1c HINT	#0

      (523) 0x42cd20 LDP	Q1, Q2, [X13, #2032]

      (523) 0x42cd24 SUBS	X16, X16, #4

      (523) 0x42cd28 FMUL	V2.2D, V2.2D, V0.D[0]

      (523) 0x42cd2c FMUL	V1.2D, V1.2D, V0.D[0]

      (523) 0x42cd30 STP	Q1, Q2, [X13, #2032]

      (523) 0x42cd34 ADD	X13, X13, #32

      (523) 0x42cd38 B.NE	42cd20

    (512) 0x42cd3c CMP	X14, X15

    (512) 0x42cd40 B.EQ	42cd60

    (512) 0x42cd44 ADD	X11, X11, X12,LSL #3

    (512) 0x42cd48 SUB	X12, X24, X12

      (522) 0x42cd4c LDR	D1, [X11]

      (522) 0x42cd50 SUBS	X12, X12, #1

      (522) 0x42cd54 FMUL	D1, D1, D0

      (522) 0x42cd58 STR	D1, [X11], #8

      (522) 0x42cd5c B.NE	42cd4c

    (512) 0x42cd60 CMP	X9, X20

    (512) 0x42cd64 B.GE	42c7e0

    (512) 0x42cd68 LDUR	X11, [X29, #472]

    (512) 0x42cd6c SUB	X13, X20, X9

    (512) 0x42cd70 ORR	X12, XZR, X9

    (512) 0x42cd74 LDR	X11, [X11]

    (512) 0x42cd78 CMP	X13, #3

    (512) 0x42cd7c B.LS	42cdc4

    (512) 0x42cd80 AND	X14, X13, #8062

    (512) 0x42cd84 ADD	X12, X9, X14

    (512) 0x42cd88 ADD	X9, X11, X9,LSL #3

    (512) 0x42cd8c ORR	X15, XZR, X14

    (512) 0x42cd90 ADD	X9, X9, #16

    (512) 0x42cd94 HINT	#0

    (512) 0x42cd98 HINT	#0

    (512) 0x42cd9c HINT	#0

      (521) 0x42cda0 LDP	Q1, Q2, [X9, #2032]

      (521) 0x42cda4 SUBS	X15, X15, #4

      (521) 0x42cda8 FMUL	V2.2D, V2.2D, V0.D[0]

      (521) 0x42cdac FMUL	V1.2D, V1.2D, V0.D[0]

      (521) 0x42cdb0 STP	Q1, Q2, [X9, #2032]

      (521) 0x42cdb4 ADD	X9, X9, #32

      (521) 0x42cdb8 B.NE	42cda0

    (512) 0x42cdbc CMP	X13, X14

    (512) 0x42cdc0 B.EQ	42c7e0

      (520) 0x42cdc4 LDR	D1, [X11, X12,LSL #3]

      (520) 0x42cdc8 FMUL	D1, D1, D0

      (520) 0x42cdcc STR	D1, [X11, X12,LSL #3]

      (520) 0x42cdd0 ADD	X12, X12, #1

      (520) 0x42cdd4 CMP	X20, X12

      (520) 0x42cdd8 B.NE	42cdc4

    (512) 0x42cddc B	42c7e0

    (512) 0x42cde0 CMP	X11, X12

    (512) 0x42cde4 ADD	X18, X13, X12

    (512) 0x42cde8 ADD	X4, X8, X9,LSL #3

    (512) 0x42cdec ADD	X3, X8, X13,LSL #3

    (512) 0x42cdf0 ADD	X0, X10, X13,LSL #3

    (512) 0x42cdf4 ADD	X1, X10, X9,LSL #3

    (512) 0x42cdf8 CSEL	X15, X11, X12, #12

    (512) 0x42cdfc SUB	X16, X15, X12

    (512) 0x42ce00 ADD	X15, X9, X15

    (512) 0x42ce04 SUB	X15, X15, X18

    (512) 0x42ce08 ADD	X17, X26, X16,LSL #3

    (512) 0x42ce0c ADD	X16, X27, X16,LSL #3

    (512) 0x42ce10 ADD	X18, X26, X15,LSL #3

    (512) 0x42ce14 ADD	X2, X27, X15,LSL #3

    (512) 0x42ce18 LDR	X15, [SP, #16]

    (512) 0x42ce1c CMP	X17, X15

    (512) 0x42ce20 CCMP	X18, X21, #0, #3

    (512) 0x42ce24 CSINC	W15, WZR, WZR, #9

    (512) 0x42ce28 CMP	X16, X4

    (512) 0x42ce2c CCMP	X3, X2, #2, #3

    (512) 0x42ce30 CSINC	W16, WZR, WZR, #2

    (512) 0x42ce34 CMP	X0, X18

    (512) 0x42ce38 CCMP	X17, X1, #2, #3

    (512) 0x42ce3c B.CC	42cb38

    (512) 0x42ce40 TBNZ	W15, #0, 42cb38

    (512) 0x42ce44 TBNZ	W16, #0, 42cb38

    (512) 0x42ce48 CMP	X11, X12

    (512) 0x42ce4c AND	X17, X14, #8062

    (512) 0x42ce50 MOVI	V1.2D, #0

    (512) 0x42ce54 MOV	V1.D[0], V2.D[0]

    (512) 0x42ce58 ADD	X0, X10, X13,LSL #3

    (512) 0x42ce5c MOVI	V0.2D, #0

    (512) 0x42ce60 CSEL	X18, X11, X12, #12

    (512) 0x42ce64 ADD	X15, X19, X17

    (512) 0x42ce68 ADD	X16, X13, X17

    (512) 0x42ce6c ADD	X0, X0, #16

    (512) 0x42ce70 ORR	X3, XZR, X17

    (512) 0x42ce74 UBFM	X18, X18, #61, #60

    (512) 0x42ce78 SUB	X1, X18, X12,LSL #3

    (512) 0x42ce7c LDP	X18, X2, [SP, #32]

    (512) 0x42ce80 ADD	X18, X18, X1

    (512) 0x42ce84 ADD	X1, X2, X1

    (512) 0x42ce88 ADD	X2, X8, X13,LSL #3

    (512) 0x42ce8c ADD	X2, X2, #16

    (512) 0x42ce90 HINT	#0

    (512) 0x42ce94 HINT	#0

    (512) 0x42ce98 HINT	#0

    (512) 0x42ce9c HINT	#0

      (516) 0x42cea0 LDR	D2, [X21]

      (516) 0x42cea4 LDP	Q3, Q4, [X0, #2032]

      (516) 0x42cea8 SUBS	X3, X3, #4

      (516) 0x42ceac ADD	X0, X0, #32

      (516) 0x42ceb0 DUP	V2.2D, V2.D[0]

      (516) 0x42ceb4 ADD	V3.2D, V2.2D, V3.2D

      (516) 0x42ceb8 ADD	V2.2D, V2.2D, V4.2D

      (516) 0x42cebc STP	Q3, Q2, [X1, #2032]

      (516) 0x42cec0 LDP	Q2, Q3, [X2, #2032]

      (516) 0x42cec4 ADD	X1, X1, #32

      (516) 0x42cec8 ADD	X2, X2, #32

      (516) 0x42cecc FADD	V0.2D, V3.2D, V0.2D

      (516) 0x42ced0 FADD	V1.2D, V2.2D, V1.2D

      (516) 0x42ced4 STP	Q2, Q3, [X18, #2032]

      (516) 0x42ced8 ADD	X18, X18, #32

      (516) 0x42cedc B.NE	42cea0

    (512) 0x42cee0 FADD	V0.2D, V0.2D, V1.2D

    (512) 0x42cee4 FADDP	D2, V0.2D

    (512) 0x42cee8 CMP	X14, X17

    (512) 0x42ceec B.NE	42cb40

    (512) 0x42cef0 B	42cb8c

        (504) 0x42cef4 ORR	X17, XZR, X16

        (504) 0x42cef8 SUB	X12, X16, X11

        (504) 0x42cefc CMN	X12, #4

        (504) 0x42cf00 B.HI	42cf80

        (504) 0x42cf04 ADD	X16, X15, #16

        (504) 0x42cf08 ADD	X15, X14, #16

        (504) 0x42cf0c SUB	X11, X11, X17

        (504) 0x42cf10 ADD	X12, X16, X17,LSL #3

        (504) 0x42cf14 ADD	X14, X15, X17,LSL #3

        (504) 0x42cf18 ADD	X15, X15, X13,LSL #3

        (504) 0x42cf1c ADD	X16, X16, X13,LSL #3

          (509) 0x42cf20 LDUR	D0, [X14, #496]

          (509) 0x42cf24 LDUR	X17, [X12, #496]

          (509) 0x42cf28 ADD	X13, X13, #4

          (509) 0x42cf2c SUBS	X11, X11, #4

          (509) 0x42cf30 STUR	X17, [X16, #496]

          (509) 0x42cf34 LDUR	X17, [X12, #504]

          (509) 0x42cf38 STUR	D0, [X15, #496]

          (509) 0x42cf3c LDUR	D0, [X14, #504]

          (509) 0x42cf40 STUR	X17, [X16, #504]

          (509) 0x42cf44 LDR	X17, [X12]

          (509) 0x42cf48 STUR	D0, [X15, #504]

          (509) 0x42cf4c LDR	D0, [X14]

          (509) 0x42cf50 STR	X17, [X16]

          (509) 0x42cf54 LDR	X17, [X12, #8]

          (509) 0x42cf58 ADD	X12, X12, #32

          (509) 0x42cf5c STR	X17, [X16, #8]

          (509) 0x42cf60 ADD	X16, X16, #32

          (509) 0x42cf64 STR	D0, [X15]

          (509) 0x42cf68 LDR	D0, [X14, #8]

          (509) 0x42cf6c ADD	X14, X14, #32

          (509) 0x42cf70 STR	D0, [X15, #8]

          (509) 0x42cf74 ADD	X15, X15, #32

          (509) 0x42cf78 B.NE	42cf20

        (504) 0x42cf7c HINT	#0

        (504) 0x42cf80 LDR	X2, [X8, X28,LSL #3]

        (504) 0x42cf84 SUBS	X11, X20, X2

        (504) 0x42cf88 B.EQ	42c7e8

        (504) 0x42cf8c SUBS	X16, X9, X2

        (504) 0x42cf90 STR	X20, [X8, X28,LSL #3]

        (504) 0x42cf94 B.LE	42c7e4

        (504) 0x42cf98 LDR	X12, [SP, #104]

        (504) 0x42cf9c LDR	X14, [X12]

        (504) 0x42cfa0 LDUR	X12, [X29, #472]

        (504) 0x42cfa4 LDR	X12, [X12]

        (504) 0x42cfa8 CMP	X16, #4

        (504) 0x42cfac B.CC	42d014

        (504) 0x42cfb0 ANDS	XZR, X11, #7870

        (504) 0x42cfb4 B.EQ	42d014

        (504) 0x42cfb8 AND	X17, X16, #8062

        (504) 0x42cfbc ADD	X3, X12, #16

        (504) 0x42cfc0 ADD	X1, X14, #16

        (504) 0x42cfc4 ADD	X11, X20, X17

        (504) 0x42cfc8 ADD	X15, X2, X17

        (504) 0x42cfcc ADD	X18, X3, X20,LSL #3

        (504) 0x42cfd0 ADD	X0, X1, X2,LSL #3

        (504) 0x42cfd4 ADD	X1, X1, X20,LSL #3

        (504) 0x42cfd8 ADD	X2, X3, X2,LSL #3

        (504) 0x42cfdc ORR	X3, XZR, X17

          (508) 0x42cfe0 LDP	Q0, Q1, [X0, #2032]

          (508) 0x42cfe4 SUBS	X3, X3, #4

          (508) 0x42cfe8 ADD	X0, X0, #32

          (508) 0x42cfec STP	Q0, Q1, [X1, #2032]

          (508) 0x42cff0 LDP	Q0, Q1, [X2, #2032]

          (508) 0x42cff4 ADD	X1, X1, #32

          (508) 0x42cff8 ADD	X2, X2, #32

          (508) 0x42cffc STP	Q0, Q1, [X18, #2032]

          (508) 0x42d000 ADD	X18, X18, #32

          (508) 0x42d004 B.NE	42cfe0

        (504) 0x42d008 CMP	X16, X17

        (504) 0x42d00c B.NE	42d01c

        (504) 0x42d010 B	42d0fc

        (504) 0x42d014 ORR	X11, XZR, X20

        (504) 0x42d018 ORR	X15, XZR, X2

        (504) 0x42d01c SUB	W16, W9, W15

        (504) 0x42d020 ANDS	X17, X16, #4160

        (504) 0x42d024 B.EQ	42d068

        (504) 0x42d028 ADD	X18, X12, X11,LSL #3

        (504) 0x42d02c ADD	X0, X14, X11,LSL #3

        (504) 0x42d030 ADD	X1, X12, X15,LSL #3

        (504) 0x42d034 ADD	X2, X14, X15,LSL #3

        (504) 0x42d038 ORR	X16, XZR, XZR

        (504) 0x42d03c HINT	#0

          (507) 0x42d040 LDR	D0, [X1, X16,LSL #3]

          (507) 0x42d044 LDR	X3, [X2, X16,LSL #3]

          (507) 0x42d048 STR	X3, [X0, X16,LSL #3]

          (507) 0x42d04c STR	D0, [X18, X16,LSL #3]

          (507) 0x42d050 ADD	X16, X16, #1

          (507) 0x42d054 CMP	X17, X16

          (507) 0x42d058 B.NE	42d040

        (504) 0x42d05c ADD	X11, X11, X16

        (504) 0x42d060 ADD	X16, X15, X16

        (504) 0x42d064 B	42d06c

        (504) 0x42d068 ORR	X16, XZR, X15

        (504) 0x42d06c SUB	X15, X15, X9

        (504) 0x42d070 CMN	X15, #4

        (504) 0x42d074 B.HI	42d0fc

        (504) 0x42d078 ADD	X17, X14, #16

        (504) 0x42d07c ADD	X15, X12, #16

        (504) 0x42d080 SUB	X9, X9, X16

        (504) 0x42d084 ADD	X14, X17, X16,LSL #3

        (504) 0x42d088 ADD	X12, X15, X16,LSL #3

        (504) 0x42d08c ADD	X15, X15, X11,LSL #3

        (504) 0x42d090 ADD	X16, X17, X11,LSL #3

        (504) 0x42d094 HINT	#0

        (504) 0x42d098 HINT	#0

        (504) 0x42d09c HINT	#0

          (506) 0x42d0a0 LDUR	D0, [X12, #496]

          (506) 0x42d0a4 LDUR	X17, [X14, #496]

          (506) 0x42d0a8 ADD	X11, X11, #4

          (506) 0x42d0ac SUBS	X9, X9, #4

          (506) 0x42d0b0 STUR	X17, [X16, #496]

          (506) 0x42d0b4 LDUR	X17, [X14, #504]

          (506) 0x42d0b8 STUR	D0, [X15, #496]

          (506) 0x42d0bc LDUR	D0, [X12, #504]

          (506) 0x42d0c0 STUR	X17, [X16, #504]

          (506) 0x42d0c4 LDR	X17, [X14]

          (506) 0x42d0c8 STUR	D0, [X15, #504]

          (506) 0x42d0cc LDR	D0, [X12]

          (506) 0x42d0d0 STR	X17, [X16]

          (506) 0x42d0d4 LDR	X17, [X14, #8]

          (506) 0x42d0d8 ADD	X14, X14, #32

          (506) 0x42d0dc STR	X17, [X16, #8]

          (506) 0x42d0e0 ADD	X16, X16, #32

          (506) 0x42d0e4 STR	D0, [X15]

          (506) 0x42d0e8 LDR	D0, [X12, #8]

          (506) 0x42d0ec ADD	X12, X12, #32

          (506) 0x42d0f0 STR	D0, [X15, #8]

          (506) 0x42d0f4 ADD	X15, X15, #32

          (506) 0x42d0f8 B.NE	42d0a0

        (504) 0x42d0fc ORR	X9, XZR, X11

        (504) 0x42d100 B	42c7e8

0x42d104 ORR	X6, XZR, XZR

0x42d108 ORR	X5, XZR, XZR

0x42d10c LDUR	X8, [X29, #448]

0x42d110 LDR	X23, [SP, #88]

0x42d114 ORR	X0, XZR, X26

0x42d118 LDR	X8, [X8]

0x42d11c LDR	X9, [X8, X23,LSL #3]

0x42d120 ADD	X9, X9, X6

0x42d124 STR	X9, [X8, X23,LSL #3]

0x42d128 LDUR	X8, [X29, #456]

0x42d12c LDR	X8, [X8]

0x42d130 LDR	X9, [X8, X23,LSL #3]

0x42d134 ADD	X9, X9, X5

0x42d138 STR	X9, [X8, X23,LSL #3]

0x42d13c BL	4a6d90

0x42d140 ORR	X0, XZR, X27

0x42d144 BL	4a6d90

0x42d148 LDP	X24, X28, [SP, #96]

0x42d14c LDR	X20, [SP, #48]

0x42d150 LDR	X26, [SP, #24]

0x42d154 LDR	X21, [SP, #8]

0x42d158 LDR	W25, [X20]

0x42d15c LDR	X19, [X29, #176]

0x42d160 ADRP	X0,

0x42d164 ADD	X0, X0, #3536

0x42d168 ORR	W1, WZR, W25

0x42d16c BL	40f440

0x42d170 CBNZ	X23, 42d1d0

0x42d174 LDR	X8, [SP, #72]

0x42d178 STR	XZR, [X21]

0x42d17c STR	XZR, [X26]

0x42d180 LDR	X8, [X8]

0x42d184 LDR	X9, [X8]

0x42d188 CMP	X9, #1

0x42d18c B.LT	42d1d0

0x42d190 LDP	X10, X11, [X29, #960]

0x42d194 ORR	X9, XZR, XZR

0x42d198 LDR	X10, [X10]

0x42d19c LDR	X11, [X11]

(503) 0x42d1a0 LDR	X12, [X10, X9,LSL #3]

(503) 0x42d1a4 LDR	X13, [X21]

(503) 0x42d1a8 ADD	X12, X13, X12

(503) 0x42d1ac STR	X12, [X21]

(503) 0x42d1b0 LDR	X12, [X11, X9,LSL #3]

(503) 0x42d1b4 LDR	X13, [X26]

(503) 0x42d1b8 ADD	X9, X9, #1

(503) 0x42d1bc ADD	X12, X13, X12

(503) 0x42d1c0 STR	X12, [X26]

(503) 0x42d1c4 LDR	X12, [X8]

(503) 0x42d1c8 CMP	X9, X12

(503) 0x42d1cc B.LT	42d1a0

0x42d1d0 ADRP	X0,

0x42d1d4 ADD	X0, X0, #3560

0x42d1d8 ORR	W1, WZR, W25

0x42d1dc BL	40f440

0x42d1e0 LDR	X8, [X21]

0x42d1e4 LDUR	X27, [X29, #440]

0x42d1e8 CBZ	X8, 42d4b4

0x42d1ec LDP	X22, X21, [X29, #184]

0x42d1f0 LDR	X20, [X29, #168]

0x42d1f4 CBNZ	X23, 42d2b0

0x42d1f8 LDUR	X8, [X29, #488]

0x42d1fc LDR	X9, [SP, #64]

0x42d200 LDR	X8, [X8]

0x42d204 LDR	X9, [X9]

0x42d208 LDR	X0, [X8, X9,LSL #3]

0x42d20c LDR	X8, [SP, #72]

0x42d210 LDR	X8, [X8]

0x42d214 STR	X0, [X20]

0x42d218 LDR	X9, [X8]

0x42d21c CMP	X9, #1

0x42d220 B.LT	42d294

0x42d224 LDUR	X9, [X29, #448]

0x42d228 LDR	X10, [X19]

0x42d22c LDR	X9, [X9]

0x42d230 LDR	X11, [X9]

0x42d234 SUB	X11, X0, X11

0x42d238 STR	X11, [X20]

0x42d23c LDR	X11, [X9]

0x42d240 STR	X11, [X10]

0x42d244 LDR	X11, [X8]

0x42d248 CMP	X11, #2

0x42d24c B.LT	42d290

0x42d250 ADD	X9, X9, #8

0x42d254 ADD	X10, X10, #8

0x42d258 MOVZ	W11, #1

0x42d25c HINT	#0

(502) 0x42d260 LDR	X12, [X9]

(502) 0x42d264 LDR	X13, [X20]

(502) 0x42d268 ADD	X11, X11, #1

(502) 0x42d26c SUB	X12, X13, X12

(502) 0x42d270 STR	X12, [X20]

(502) 0x42d274 LDR	X12, [X9], #8

(502) 0x42d278 LDUR	X13, [X10, #504]

(502) 0x42d27c ADD	X12, X13, X12

(502) 0x42d280 STR	X12, [X10], #8

(502) 0x42d284 LDR	X12, [X8]

(502) 0x42d288 CMP	X11, X12

(502) 0x42d28c B.LT	42d260

0x42d290 LDR	X0, [X20]

0x42d294 MOVZ	W1, #8

0x42d298 BL	4a6c90

0x42d29c STR	X0, [X22]

0x42d2a0 LDR	X0, [X20]

0x42d2a4 MOVZ	W1, #8

0x42d2a8 BL	4a6c90

0x42d2ac STR	X0, [X21]

0x42d2b0 ADRP	X0,

0x42d2b4 ADD	X0, X0, #3584

0x42d2b8 ORR	W1, WZR, W25

0x42d2bc BL	40f440

0x42d2c0 LDUR	X8, [X29, #488]

0x42d2c4 LDR	X8, [X8]

0x42d2c8 LDR	X9, [X8, X27,LSL #3]

0x42d2cc CBZ	X23, 42d2e4

0x42d2d0 LDR	X10, [X19]

0x42d2d4 ADD	X10, X10, X23,LSL #3

0x42d2d8 LDUR	X10, [X10, #504]

0x42d2dc SUB	X14, X9, X10

0x42d2e0 B	42d2e8

0x42d2e4 ORR	X14, XZR, XZR

0x42d2e8 LDUR	X10, [X29, #448]

0x42d2ec LDUR	X17, [X29, #480]

0x42d2f0 LDR	X10, [X10]

0x42d2f4 LDR	X11, [X8, X17,LSL #3]

0x42d2f8 LDR	X12, [X10, X23,LSL #3]

0x42d2fc SUB	X11, X11, X12

0x42d300 CMP	X9, X11

0x42d304 B.GE	42d34c

0x42d308 LDUR	X12, [X29, #464]

0x42d30c LDR	X13, [X22]

0x42d310 LDR	X15, [X21]

0x42d314 ADD	X13, X13, X14,LSL #3

0x42d318 LDR	X11, [X24]

0x42d31c LDR	X12, [X12]

0x42d320 ADD	X14, X15, X14,LSL #3

(501) 0x42d324 LDR	X15, [X11, X9,LSL #3]

(501) 0x42d328 LDR	D0, [X12, X9,LSL #3]

(501) 0x42d32c ADD	X9, X9, #1

(501) 0x42d330 STR	X15, [X13], #8

(501) 0x42d334 LDR	X15, [X8, X17,LSL #3]

(501) 0x42d338 LDR	X16, [X10, X23,LSL #3]

(501) 0x42d33c STR	D0, [X14], #8

(501) 0x42d340 SUB	X15, X15, X16

(501) 0x42d344 CMP	X9, X15

(501) 0x42d348 B.LT	42d324

0x42d34c ADRP	X0,

0x42d350 ADD	X0, X0, #3608

0x42d354 ORR	W1, WZR, W25

0x42d358 BL	40f440

0x42d35c LDUR	X15, [X29, #480]

0x42d360 CMP	X23, #1

0x42d364 B.LT	42d444

0x42d368 SUBS	X11, X15, X27

0x42d36c B.LE	42d444

0x42d370 LDUR	X9, [X29, #488]

0x42d374 LDR	X8, [X19]

0x42d378 ORR	X10, XZR, X27

0x42d37c LDR	X9, [X9]

0x42d380 ADD	X12, X8, X23,LSL #3

0x42d384 SUB	X8, X12, #8

0x42d388 CMP	X11, #8

0x42d38c B.CC	42d3ec

0x42d390 LDR	X10, [SP, #56]

0x42d394 MADD	X10, X23, X10, XZR

0x42d398 ADD	X13, X9, X10,LSL #3

0x42d39c CMP	X13, X12

0x42d3a0 B.CS	42d3b4

0x42d3a4 ADD	X12, X9, X15,LSL #3

0x42d3a8 ORR	X10, XZR, X27

0x42d3ac CMP	X8, X12

0x42d3b0 B.CC	42d3ec

0x42d3b4 LD1R	{V0.2D}, [X8]

0x42d3b8 AND	X12, X11, #8062

0x42d3bc ADD	X13, X13, #16

0x42d3c0 ADD	X10, X27, X12

0x42d3c4 ORR	X14, XZR, X12

(500) 0x42d3c8 LDP	Q1, Q2, [X13, #2032]

(500) 0x42d3cc SUBS	X14, X14, #4

(500) 0x42d3d0 SUB	V2.2D, V2.2D, V0.2D

(500) 0x42d3d4 SUB	V1.2D, V1.2D, V0.2D

(500) 0x42d3d8 STP	Q1, Q2, [X13, #2032]

(500) 0x42d3dc ADD	X13, X13, #32

(500) 0x42d3e0 B.NE	42d3c8

0x42d3e4 CMP	X11, X12

0x42d3e8 B.EQ	42d444

0x42d3ec SUB	W12, W15, W10

0x42d3f0 ADD	X11, X10, #1

0x42d3f4 TBZ	W12, #0, 42d40c

0x42d3f8 LDR	X12, [X8]

0x42d3fc LDR	X13, [X9, X10,LSL #3]

0x42d400 SUB	X12, X13, X12

0x42d404 STR	X12, [X9, X10,LSL #3]

0x42d408 ORR	X10, XZR, X11

0x42d40c CMP	X15, X11

0x42d410 B.EQ	42d444

0x42d414 ADD	X9, X9, X10,LSL #3

0x42d418 SUB	X10, X15, X10

0x42d41c ADD	X9, X9, #8

(499) 0x42d420 LDR	X11, [X8]

(499) 0x42d424 LDP	X12, X13, [X9, #1016]

(499) 0x42d428 SUBS	X10, X10, #2

(499) 0x42d42c SUB	X11, X12, X11

(499) 0x42d430 STUR	X11, [X9, #504]

(499) 0x42d434 LDR	X11, [X8]

(499) 0x42d438 SUB	X11, X13, X11

(499) 0x42d43c STR	X11, [X9], #16

(499) 0x42d440 B.NE	42d420

0x42d444 CBNZ	X23, 42d4b4

0x42d448 LDUR	X9, [X29, #488]

0x42d44c LDR	X10, [SP, #64]

0x42d450 LDR	X8, [X20]

0x42d454 LDR	X0, [X24]

0x42d458 STR	X26, [SP, #24]

0x42d45c ORR	X26, XZR, X23

0x42d460 LDR	X23, [X29, #200]

0x42d464 LDR	X9, [X9]

0x42d468 LDR	X10, [X10]

0x42d46c STR	X8, [X9, X10,LSL #3]

0x42d470 BL	4a6d90

0x42d474 STR	XZR, [X24]

0x42d478 LDUR	X24, [X29, #464]

0x42d47c LDR	X0, [X24]

0x42d480 BL	4a6d90

0x42d484 STR	XZR, [X24]

0x42d488 LDR	X8, [X22]

0x42d48c LDR	X9, [X23]

0x42d490 STR	X8, [X9, #8]

0x42d494 LDR	X8, [X21]

0x42d498 LDR	X9, [X23]

0x42d49c STR	X8, [X9, #48]

0x42d4a0 LDR	X8, [X20]

0x42d4a4 LDR	X9, [X23]

0x42d4a8 ORR	X23, XZR, X26

0x42d4ac LDR	X26, [SP, #24]

0x42d4b0 STR	X8, [X9, #32]

0x42d4b4 ADRP	X0,

0x42d4b8 ADD	X0, X0, #3632

0x42d4bc ORR	W1, WZR, W25

0x42d4c0 BL	40f440

0x42d4c4 LDR	X8, [X26]

0x42d4c8 CBZ	X8, 42d784

0x42d4cc LDP	X22, X21, [X29, #216]

0x42d4d0 LDR	X20, [X29, #208]

0x42d4d4 CBNZ	X23, 42d590

0x42d4d8 LDUR	X8, [X29, #496]

0x42d4dc LDR	X9, [SP, #64]

0x42d4e0 LDR	X8, [X8]

0x42d4e4 LDR	X9, [X9]

0x42d4e8 LDR	X0, [X8, X9,LSL #3]

0x42d4ec LDR	X8, [SP, #72]

0x42d4f0 LDR	X8, [X8]

0x42d4f4 STR	X0, [X20]

0x42d4f8 LDR	X9, [X8]

0x42d4fc CMP	X9, #1

0x42d500 B.LT	42d574

0x42d504 LDUR	X9, [X29, #456]

0x42d508 LDR	X10, [X19]

0x42d50c LDR	X9, [X9]

0x42d510 LDR	X11, [X9]

0x42d514 SUB	X11, X0, X11

0x42d518 STR	X11, [X20]

0x42d51c LDR	X11, [X9]

0x42d520 STR	X11, [X10]

0x42d524 LDR	X11, [X8]

0x42d528 CMP	X11, #2

0x42d52c B.LT	42d570

0x42d530 ADD	X9, X9, #8

0x42d534 ADD	X10, X10, #8

0x42d538 MOVZ	W11, #1

0x42d53c HINT	#0

(498) 0x42d540 LDR	X12, [X9]

(498) 0x42d544 LDR	X13, [X20]

(498) 0x42d548 ADD	X11, X11, #1

(498) 0x42d54c SUB	X12, X13, X12

(498) 0x42d550 STR	X12, [X20]

(498) 0x42d554 LDR	X12, [X9], #8

(498) 0x42d558 LDUR	X13, [X10, #504]

(498) 0x42d55c ADD	X12, X13, X12

(498) 0x42d560 STR	X12, [X10], #8

(498) 0x42d564 LDR	X12, [X8]

(498) 0x42d568 CMP	X11, X12

(498) 0x42d56c B.LT	42d540

0x42d570 LDR	X0, [X20]

0x42d574 MOVZ	W1, #8

0x42d578 BL	4a6c90

0x42d57c STR	X0, [X22]

0x42d580 LDR	X0, [X20]

0x42d584 MOVZ	W1, #8

0x42d588 BL	4a6c90

0x42d58c STR	X0, [X21]

0x42d590 ADRP	X0,

0x42d594 ADD	X0, X0, #3656

0x42d598 ORR	W1, WZR, W25

0x42d59c BL	40f440

0x42d5a0 LDUR	X8, [X29, #496]

0x42d5a4 LDR	X8, [X8]

0x42d5a8 LDR	X9, [X8, X27,LSL #3]

0x42d5ac CBZ	X23, 42d5c4

0x42d5b0 LDR	X10, [X19]

0x42d5b4 ADD	X10, X10, X23,LSL #3

0x42d5b8 LDUR	X10, [X10, #504]

0x42d5bc SUB	X14, X9, X10

0x42d5c0 B	42d5c8

0x42d5c4 ORR	X14, XZR, XZR

0x42d5c8 LDUR	X10, [X29, #456]

0x42d5cc LDUR	X17, [X29, #480]

0x42d5d0 LDR	X10, [X10]

0x42d5d4 LDR	X11, [X8, X17,LSL #3]

0x42d5d8 LDR	X12, [X10, X23,LSL #3]

0x42d5dc SUB	X11, X11, X12

0x42d5e0 CMP	X9, X11

0x42d5e4 B.GE	42d62c

0x42d5e8 LDUR	X12, [X29, #472]

0x42d5ec LDR	X13, [X22]

0x42d5f0 LDR	X15, [X21]

0x42d5f4 ADD	X13, X13, X14,LSL #3

0x42d5f8 LDR	X11, [X28]

0x42d5fc LDR	X12, [X12]

0x42d600 ADD	X14, X15, X14,LSL #3

(497) 0x42d604 LDR	X15, [X11, X9,LSL #3]

(497) 0x42d608 LDR	D0, [X12, X9,LSL #3]

(497) 0x42d60c ADD	X9, X9, #1

(497) 0x42d610 STR	X15, [X13], #8

(497) 0x42d614 LDR	X15, [X8, X17,LSL #3]

(497) 0x42d618 LDR	X16, [X10, X23,LSL #3]

(497) 0x42d61c STR	D0, [X14], #8

(497) 0x42d620 SUB	X15, X15, X16

(497) 0x42d624 CMP	X9, X15

(497) 0x42d628 B.LT	42d604

0x42d62c ADRP	X0,

0x42d630 ADD	X0, X0, #3680

0x42d634 ORR	W1, WZR, W25

0x42d638 BL	40f440

0x42d63c LDUR	X14, [X29, #480]

0x42d640 CMP	X23, #1

0x42d644 B.LT	42d724

0x42d648 SUBS	X10, X14, X27

0x42d64c B.LE	42d724

0x42d650 LDUR	X9, [X29, #496]

0x42d654 LDR	X8, [X19]

0x42d658 LDR	X9, [X9]

0x42d65c ADD	X11, X8, X23,LSL #3

0x42d660 SUB	X8, X11, #8

0x42d664 CMP	X10, #8

0x42d668 B.CC	42d6c4

0x42d66c LDR	X12, [SP, #56]

0x42d670 MADD	X12, X23, X12, XZR

0x42d674 ADD	X12, X9, X12,LSL #3

0x42d678 CMP	X12, X11

0x42d67c B.CS	42d68c

0x42d680 ADD	X11, X9, X14,LSL #3

0x42d684 CMP	X8, X11

0x42d688 B.CC	42d6c4

0x42d68c LD1R	{V0.2D}, [X8]

0x42d690 AND	X11, X10, #8062

0x42d694 ADD	X12, X12, #16

0x42d698 ADD	X27, X27, X11

0x42d69c ORR	X13, XZR, X11

(496) 0x42d6a0 LDP	Q1, Q2, [X12, #2032]

(496) 0x42d6a4 SUBS	X13, X13, #4

(496) 0x42d6a8 SUB	V2.2D, V2.2D, V0.2D

(496) 0x42d6ac SUB	V1.2D, V1.2D, V0.2D

(496) 0x42d6b0 STP	Q1, Q2, [X12, #2032]

(496) 0x42d6b4 ADD	X12, X12, #32

(496) 0x42d6b8 B.NE	42d6a0

0x42d6bc CMP	X10, X11

0x42d6c0 B.EQ	42d724

0x42d6c4 SUB	W11, W14, W27

0x42d6c8 ADD	X10, X27, #1

0x42d6cc TBZ	W11, #0, 42d6e4

0x42d6d0 LDR	X11, [X8]

0x42d6d4 LDR	X12, [X9, X27,LSL #3]

0x42d6d8 SUB	X11, X12, X11

0x42d6dc STR	X11, [X9, X27,LSL #3]

0x42d6e0 ORR	X27, XZR, X10

0x42d6e4 CMP	X14, X10

0x42d6e8 B.EQ	42d724

0x42d6ec ADD	X9, X9, X27,LSL #3

0x42d6f0 SUB	X10, X14, X27

0x42d6f4 ADD	X9, X9, #8

0x42d6f8 HINT	#0

0x42d6fc HINT	#0

(495) 0x42d700 LDR	X11, [X8]

(495) 0x42d704 LDP	X12, X13, [X9, #1016]

(495) 0x42d708 SUBS	X10, X10, #2

(495) 0x42d70c SUB	X11, X12, X11

(495) 0x42d710 STUR	X11, [X9, #504]

(495) 0x42d714 LDR	X11, [X8]

(495) 0x42d718 SUB	X11, X13, X11

(495) 0x42d71c STR	X11, [X9], #16

(495) 0x42d720 B.NE	42d700

0x42d724 CBNZ	X23, 42d784

0x42d728 LDUR	X9, [X29, #496]

0x42d72c LDR	X10, [SP, #64]

0x42d730 LDR	X8, [X20]

0x42d734 LDR	X0, [X28]

0x42d738 LDR	X19, [X29, #232]

0x42d73c LDR	X9, [X9]

0x42d740 LDR	X10, [X10]

0x42d744 STR	X8, [X9, X10,LSL #3]

0x42d748 BL	4a6d90

0x42d74c LDUR	X23, [X29, #472]

0x42d750 STR	XZR, [X28]

0x42d754 LDR	X0, [X23]

0x42d758 BL	4a6d90

0x42d75c STR	XZR, [X23]

0x42d760 LDR	X8, [X22]

0x42d764 LDR	X9, [X19]

0x42d768 STR	X8, [X9, #8]

0x42d76c LDR	X8, [X21]

0x42d770 LDR	X9, [X19]

0x42d774 STR	X8, [X9, #48]

0x42d778 LDR	X8, [X20]

0x42d77c LDR	X9, [X19]

0x42d780 STR	X8, [X9, #32]

0x42d784 LDP	X20, X19, [SP, #304]

0x42d788 LDP	X22, X21, [SP, #288]

0x42d78c LDP	X24, X23, [SP, #272]

0x42d790 LDP	X26, X25, [SP, #256]

0x42d794 LDP	X28, X27, [SP, #240]

0x42d798 LDP	X29, X30, [SP, #224]

0x42d79c ADD	SP, SP, #320

0x42d7a0 RET

0x42d7a4 HINT	#0

0x42d7a8 HINT	#0

0x42d7ac HINT	#0

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	par_interp.c:2726-3155
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_interp.c:2726-2730,2740-2741,2750-2822,2828-2831,2840,2848-2865,2872-2945,2955-2975,2983-2986,2994-3007,3013,3023-3044,3050-3082,3091-3116,3122-3155.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 79.17 to 6.00 cycles (13.19x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 51% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 79.17 to 68.42 cycles (1.16x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 79.17 to 10.50 cycles (7.54x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 1596 bytes. The binary function is storing 536 bytes.

General properties

nb instructions	484
loop length	1936
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

57.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	33.00	33.00	29.33	29.33	29.33	29.33	29.33	29.33	1.00	0.75	0.75	0.50	79.17	78.83	79.00	27.50	27.50
cycles	33.00	33.00	29.33	29.33	29.33	29.33	29.33	29.33	1.00	0.75	0.75	0.50	79.17	78.83	79.00	27.50	27.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	57.38
Overall L1	79.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 79.17 cycles. At this rate:

21% of peak load performance is reached (20.16 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (6.77 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42c260

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #320	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #224	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X24, X28, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X6, X7, [X29, #976]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X26, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X19, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X4, X5, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X8, X9, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X8, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a8a10 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X23, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a89f0 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D0, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
SUB X9, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X23, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
SDIV X10, X8, X0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MADD X27, X10, X23, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
STP X10, X19, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X10, X10, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CSEL X30, X8, X10, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
FCMP D0, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.LE 42c694 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x434>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X20, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X30, X27	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 42c660 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x400>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X10, X11, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X13, X14, [X29, #976]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X9, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X1, XZR, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X11, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X12, [X10, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X15, X13, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X16, X14, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X17, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X18, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X2, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 42c348 <hypre_BoomerAMGInterpTruncation.omp_outlined+0xe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ORR X9, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CBNZ X23, 42c678 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x418>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X10, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X20, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X9, [X10, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [X9, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X21, X26, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X27, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X30, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 42d158 <hypre_BoomerAMGInterpTruncation.omp_outlined+0xef8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X27, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUBS X9, X30, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 42c750 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x4f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X11, X10, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X14, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X10, X11, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
MADD X14, X23, X14, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
UBFM X14, X14, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X14, X14, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X12, X12, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X13, X13, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 42c72c <hypre_BoomerAMGInterpTruncation.omp_outlined+0x4cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
CMP X27, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 42d158 <hypre_BoomerAMGInterpTruncation.omp_outlined+0xef8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR X21, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X26, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X0, XZR, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X20, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X28, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X26, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X0, XZR, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X4, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X28, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X27, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X4, X28	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 42d104 <hypre_BoomerAMGInterpTruncation.omp_outlined+0xea4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X9, X8, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X21, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X30, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB X7, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X11, X26, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X5, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X6, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X7, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X21, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X9, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X9, X27, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X9, X11, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X20, [X8, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X24, [X10, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 42c7fc <hypre_BoomerAMGInterpTruncation.omp_outlined+0x59c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ORR X6, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X5, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X23, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X0, XZR, X26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X8, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X9, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X9, [X8, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X8, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X9, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X9, [X8, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X24, X28, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X20, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X26, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X21, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W25, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X19, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <4db160>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #3536	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f440 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBNZ X23, 42d1d0 <hypre_BoomerAMGInterpTruncation.omp_outlined+0xf70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X9, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 42d1d0 <hypre_BoomerAMGInterpTruncation.omp_outlined+0xf70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X10, X11, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ORR X9, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <4db1d0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #3560	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f440 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X27, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 42d4b4 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x1254>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X22, X21, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X20, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X23, 42d2b0 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x1050>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X9, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 42d294 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x1034>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X11, X0, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X11, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X11, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X11, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 42d290 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x1030>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X9, X9, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X10, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W11, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
LDR X0, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADRP X0, <4db2b0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #3584	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f440 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X8, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X23, 42d2e4 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x1084>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X10, X10, X23,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR X10, [X10, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X14, X9, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 42d2e8 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x1088>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X14, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR X10, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X17, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X8, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X10, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X11, X11, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X9, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 42d34c <hypre_BoomerAMGInterpTruncation.omp_outlined+0x10ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X12, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X13, X13, X14,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X11, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X14, X15, X14,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <4db34c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #3608	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f440 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X15, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X23, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 42d444 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x11e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUBS X11, X15, X27	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 42d444 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x11e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X10, XZR, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X12, X8, X23,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X8, X12, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X11, #8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CC 42d3ec <hypre_BoomerAMGInterpTruncation.omp_outlined+0x118c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MADD X10, X23, X10, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X13, X9, X10,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X13, X12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 42d3b4 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x1154>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X12, X9, X15,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X10, XZR, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X8, X12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CC 42d3ec <hypre_BoomerAMGInterpTruncation.omp_outlined+0x118c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LD1R {V0.2D}, [X8]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (50.0%)
AND X12, X11, #8062	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X13, X13, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X27, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X14, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X11, X12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 42d444 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x11e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W12, W15, W10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X11, X10, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TBZ W12, #0, 42d40c <hypre_BoomerAMGInterpTruncation.omp_outlined+0x11ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X9, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X12, X13, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X12, [X9, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X10, XZR, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X15, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 42d444 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x11e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X9, X9, X10,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X10, X15, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X9, X9, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CBNZ X23, 42d4b4 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x1254>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X26, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X26, XZR, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X23, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [X9, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X24, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [X9, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [X9, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X23, XZR, X26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X26, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [X9, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADRP X0, <4db4b4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #3632	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f440 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 42d784 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x1524>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X22, X21, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X20, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X23, 42d590 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x1330>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X9, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 42d574 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x1314>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X11, X0, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X11, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X11, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X11, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 42d570 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x1310>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X9, X9, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X10, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W11, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
LDR X0, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADRP X0, <4db590>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #3656	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f440 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X8, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X23, 42d5c4 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x1364>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X10, X10, X23,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR X10, [X10, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X14, X9, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 42d5c8 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x1368>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X14, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR X10, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X17, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X8, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X10, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X11, X11, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X9, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 42d62c <hypre_BoomerAMGInterpTruncation.omp_outlined+0x13cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X12, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X13, X13, X14,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X11, [X28]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X14, X15, X14,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <4db62c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #3680	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f440 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X14, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X23, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 42d724 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x14c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUBS X10, X14, X27	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 42d724 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x14c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X11, X8, X23,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X8, X11, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X10, #8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CC 42d6c4 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x1464>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MADD X12, X23, X12, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X12, X9, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X12, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 42d68c <hypre_BoomerAMGInterpTruncation.omp_outlined+0x142c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X11, X9, X14,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X8, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CC 42d6c4 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x1464>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LD1R {V0.2D}, [X8]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (50.0%)
AND X11, X10, #8062	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X12, X12, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X27, X27, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X13, XZR, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X10, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 42d724 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x14c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W11, W14, W27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X27, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TBZ W11, #0, 42d6e4 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x1484>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X9, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X11, X12, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X11, [X9, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X27, XZR, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X14, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 42d724 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x14c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X9, X9, X27,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X10, X14, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X9, X9, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
CBNZ X23, 42d784 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x1524>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X28]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X19, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [X9, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X23, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X28]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [X9, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [X9, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [X9, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X20, X19, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X26, X25, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X28, X27, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X29, X30, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #320	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	par_interp.c:2726-3155
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 79.17 to 10.50 cycles (7.54x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 1596 bytes. The binary function is storing 536 bytes.

General properties

nb instructions	484
loop length	1936
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

57.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	33.00	33.00	29.33	29.33	29.33	29.33	29.33	29.33	1.00	0.75	0.75	0.50	79.17	78.83	79.00	27.50	27.50
cycles	33.00	33.00	29.33	29.33	29.33	29.33	29.33	29.33	1.00	0.75	0.75	0.50	79.17	78.83	79.00	27.50	27.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	57.38
Overall L1	79.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 79.17 cycles. At this rate:

21% of peak load performance is reached (20.16 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (6.77 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42c260

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #320	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #224	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X24, X28, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X6, X7, [X29, #976]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X26, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X19, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X4, X5, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X8, X9, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X8, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a8a10 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X23, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a89f0 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D0, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
SUB X9, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X23, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
SDIV X10, X8, X0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MADD X27, X10, X23, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
STP X10, X19, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X10, X10, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CSEL X30, X8, X10, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
FCMP D0, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.LE 42c694 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x434>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X20, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X30, X27	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 42c660 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x400>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X10, X11, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X13, X14, [X29, #976]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X9, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X1, XZR, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X11, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X12, [X10, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X15, X13, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X16, X14, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X17, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X18, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X2, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 42c348 <hypre_BoomerAMGInterpTruncation.omp_outlined+0xe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ORR X9, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CBNZ X23, 42c678 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x418>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X10, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X20, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X9, [X10, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [X9, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X21, X26, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X27, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X30, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 42d158 <hypre_BoomerAMGInterpTruncation.omp_outlined+0xef8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X27, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUBS X9, X30, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 42c750 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x4f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X11, X10, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X14, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X10, X11, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
MADD X14, X23, X14, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
UBFM X14, X14, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X14, X14, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X12, X12, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X13, X13, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 42c72c <hypre_BoomerAMGInterpTruncation.omp_outlined+0x4cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
CMP X27, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 42d158 <hypre_BoomerAMGInterpTruncation.omp_outlined+0xef8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR X21, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X26, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X0, XZR, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X20, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X28, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X26, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X0, XZR, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X4, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X28, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X27, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X4, X28	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 42d104 <hypre_BoomerAMGInterpTruncation.omp_outlined+0xea4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X9, X8, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X21, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X30, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB X7, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X11, X26, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X5, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X6, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X7, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X21, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X9, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X9, X27, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X9, X11, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X20, [X8, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X24, [X10, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 42c7fc <hypre_BoomerAMGInterpTruncation.omp_outlined+0x59c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ORR X6, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X5, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X23, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X0, XZR, X26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X8, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X9, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X9, [X8, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X8, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X9, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X9, [X8, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X24, X28, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X20, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X26, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X21, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W25, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X19, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <4db160>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #3536	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f440 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBNZ X23, 42d1d0 <hypre_BoomerAMGInterpTruncation.omp_outlined+0xf70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X9, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 42d1d0 <hypre_BoomerAMGInterpTruncation.omp_outlined+0xf70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X10, X11, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ORR X9, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <4db1d0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #3560	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f440 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X27, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 42d4b4 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x1254>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X22, X21, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X20, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X23, 42d2b0 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x1050>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X9, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 42d294 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x1034>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X11, X0, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X11, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X11, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X11, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 42d290 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x1030>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X9, X9, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X10, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W11, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
LDR X0, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADRP X0, <4db2b0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #3584	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f440 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X8, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X23, 42d2e4 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x1084>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X10, X10, X23,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR X10, [X10, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X14, X9, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 42d2e8 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x1088>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X14, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR X10, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X17, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X8, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X10, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X11, X11, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X9, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 42d34c <hypre_BoomerAMGInterpTruncation.omp_outlined+0x10ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X12, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X13, X13, X14,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X11, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X14, X15, X14,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <4db34c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #3608	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f440 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X15, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X23, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 42d444 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x11e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUBS X11, X15, X27	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 42d444 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x11e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X10, XZR, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X12, X8, X23,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X8, X12, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X11, #8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CC 42d3ec <hypre_BoomerAMGInterpTruncation.omp_outlined+0x118c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MADD X10, X23, X10, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X13, X9, X10,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X13, X12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 42d3b4 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x1154>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X12, X9, X15,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X10, XZR, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X8, X12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CC 42d3ec <hypre_BoomerAMGInterpTruncation.omp_outlined+0x118c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LD1R {V0.2D}, [X8]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (50.0%)
AND X12, X11, #8062	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X13, X13, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X27, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X14, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X11, X12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 42d444 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x11e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W12, W15, W10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X11, X10, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TBZ W12, #0, 42d40c <hypre_BoomerAMGInterpTruncation.omp_outlined+0x11ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X9, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X12, X13, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X12, [X9, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X10, XZR, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X15, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 42d444 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x11e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X9, X9, X10,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X10, X15, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X9, X9, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CBNZ X23, 42d4b4 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x1254>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X26, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X26, XZR, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X23, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [X9, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X24, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [X9, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [X9, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X23, XZR, X26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X26, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [X9, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADRP X0, <4db4b4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #3632	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f440 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 42d784 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x1524>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X22, X21, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X20, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X23, 42d590 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x1330>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X9, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 42d574 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x1314>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X11, X0, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X11, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X11, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X11, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 42d570 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x1310>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X9, X9, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X10, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W11, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
LDR X0, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADRP X0, <4db590>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #3656	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f440 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X8, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X23, 42d5c4 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x1364>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X10, X10, X23,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR X10, [X10, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X14, X9, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 42d5c8 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x1368>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X14, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR X10, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X17, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X8, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X10, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X11, X11, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X9, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 42d62c <hypre_BoomerAMGInterpTruncation.omp_outlined+0x13cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X12, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X13, X13, X14,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X11, [X28]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X14, X15, X14,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <4db62c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #3680	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f440 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X14, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X23, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 42d724 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x14c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUBS X10, X14, X27	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 42d724 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x14c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X11, X8, X23,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X8, X11, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X10, #8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CC 42d6c4 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x1464>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MADD X12, X23, X12, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X12, X9, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X12, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 42d68c <hypre_BoomerAMGInterpTruncation.omp_outlined+0x142c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X11, X9, X14,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X8, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CC 42d6c4 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x1464>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LD1R {V0.2D}, [X8]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (50.0%)
AND X11, X10, #8062	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X12, X12, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X27, X27, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X13, XZR, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X10, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 42d724 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x14c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W11, W14, W27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X27, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TBZ W11, #0, 42d6e4 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x1484>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X9, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X11, X12, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X11, [X9, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X27, XZR, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X14, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 42d724 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x14c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X9, X9, X27,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X10, X14, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X9, X9, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
CBNZ X23, 42d784 <hypre_BoomerAMGInterpTruncation.omp_outlined+0x1524>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X28]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X19, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [X9, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X23, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X28]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [X9, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [X9, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [X9, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X20, X19, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X26, X25, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X28, X27, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X29, X30, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #320	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

▶Scalability Runs Description

Run 1x1	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_NUM_THREADS: 1OMP_PLACES: threads
Run 1x2	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 2OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x4	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 4OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x8	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 8OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x16	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 16OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x24	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 24OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x32	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 32OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x40	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 40OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x48	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 48OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x56	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 56OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x64	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 64OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x72	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 72OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x80	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 80OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x88	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 88OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x96	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 96OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads

(1x1) Efficiency	(1x1) Potential Speed-Up (%)	(1x2) Efficiency	(1x2) Potential Speed-Up (%)	(1x4) Efficiency	(1x4) Potential Speed-Up (%)	(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x16) Efficiency	(1x16) Potential Speed-Up (%)	(1x24) Efficiency	(1x24) Potential Speed-Up (%)	(1x32) Efficiency	(1x32) Potential Speed-Up (%)	(1x40) Efficiency	(1x40) Potential Speed-Up (%)	(1x48) Efficiency	(1x48) Potential Speed-Up (%)	(1x56) Efficiency	(1x56) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)	(1x72) Efficiency	(1x72) Potential Speed-Up (%)	(1x80) Efficiency	(1x80) Potential Speed-Up (%)	(1x88) Efficiency	(1x88) Potential Speed-Up (%)	(1x96) Efficiency	(1x96) Potential Speed-Up (%)
1	0	4.46	0	8.76	0	11.34	0	18.85	0	38.4	0	26.14	0	42.31	0	73.54	0	109.89	0	61.39	0	135.51	0	158.84	0	158.32	0	85.75	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x1	1	1	1	1	0.044999998062849	0.016915453597903
1x2	2	4.46	4.46	2	0.014999999664724	0.0071300105191767
1x4	3	8.76	8.76	4	0.00999999884516	0.0067934966646135
1x8	5	11.34	11.34	8	0.0099999997764826	0.0089926198124886
1x16	6	18.85	18.85	16	0.00999999884516	0.0082895439118147
1x24	5	38.4	38.4	24	0.00499999942258	0.0047314614057541
1x32	9	26.14	26.14	32	0.0099999997764826	0.0075827888213098
1x40	7	42.31	42.31	40	0.0050000003539026	0.0044083222746849
1x48	5	73.54	73.54	48	0.00499999942258	0.0027606869116426
1x56	4	109.89	109.89	56	0.0049999998882413	0.0020327793899924
1x64	8	61.39	61.39	64	0.0050000003539026	0.0037641352973878
1x72	4	135.51	135.51	72	0.0049999998882413	0.0017073064809665
1x80	4	158.84	158.84	80	0.0049999998882413	0.0015827527968213
1x88	4	158.32	158.32	88	0.0049999998882413	0.0014490660978481
1x96	8	85.75	85.75	96	0.0049999998882413	0.0026863417588174

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGInterpTruncation.omp_outlined–	0.02	0.04
○Loop 501 - par_interp.c:3053-3056 - exec	0.00	0.01
○Loop 524 - par_interp.c:2848-2860 - exec	0.00	0.00
○Loop 498 - par_interp.c:3099-3103 - exec	0.00	0.00
○Loop 495 - par_interp.c:3140-3142 - exec	0.00	0.00
○Loop 500 - par_interp.c:3067-3069 - exec	0.00	0.00
○Loop 499 - par_interp.c:3067-3069 - exec	0.00	0.00
○Loop 497 - par_interp.c:3126-3129 - exec	0.00	0.00
○Loop 502 - par_interp.c:3027-3031 - exec	0.00	0.00
▼Loop 525 - par_interp.c:2760-2822 - exec–	0.00	0.00
○Loop 532 - par_interp.c:2821-2822 - exec	0.00	0.00
○Loop 527 - par_interp.c:2775-2789 - exec	0.00	0.00
○Loop 526 - par_interp.c:2795-2809 - exec	0.00	0.00
○Loop 534 - par_interp.c:2819-2820 - exec	0.00	0.00
○Loop 529 - par_interp.c:2766-2767 - exec	0.00	0.00
○Loop 528 - par_interp.c:2767-2767 - exec	0.00	0.00
○Loop 531 - par_interp.c:2764-2764 - exec	0.00	0.00
○Loop 533 - par_interp.c:2822-2822 - exec	0.00	0.00
○Loop 535 - par_interp.c:2820-2820 - exec	0.00	0.00
○Loop 530 - par_interp.c:2763-2764 - exec	0.00	0.00
○Loop 496 - par_interp.c:3140-3142 - exec	0.00	0.00
▼Loop 513 - par_interp.c:2874-2975 - exec–	0.00	0.00
▼Loop 514 - par_interp.c:2874-2975 - exec–	0.01	0.01
▼Loop 512 - par_interp.c:2874-2975 - exec–	0.00	0.00
○Loop 519 - par_interp.c:2897-2899 - exec	0.00	0.00
○Loop 516 - par_interp.c:2903-2907 - exec	0.00	0.00
○Loop 523 - par_interp.c:2943-2943 - exec	0.00	0.00
○Loop 518 - par_interp.c:2895-2899 - exec	0.00	0.00
○Loop 521 - par_interp.c:2945-2945 - exec	0.00	0.00
○Loop 517 - par_interp.c:2895-2899 - exec	0.00	0.00
○Loop 522 - par_interp.c:2942-2943 - exec	0.00	0.00
▼Loop 505 - par_interp.c:2874-2975 - exec–	0.00	0.00
▼Loop 504 - par_interp.c:2874-2975 - exec–	0.00	0.01
○Loop 510 - par_interp.c:2959-2962 - exec	0.00	0.00
○Loop 508 - par_interp.c:2974-2975 - exec	0.00	0.00
○Loop 511 - par_interp.c:2961-2962 - exec	0.00	0.00
○Loop 509 - par_interp.c:2959-2962 - exec	0.00	0.00
○Loop 506 - par_interp.c:2972-2975 - exec	0.00	0.00
○Loop 507 - par_interp.c:2972-2975 - exec	0.00	0.00
○Loop 520 - par_interp.c:2944-2945 - exec	0.00	0.00
○Loop 515 - par_interp.c:2903-2907 - exec	0.00	0.00
○Loop 503 - par_interp.c:3000-3003 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency