OV - exec - Function hypre_BoomerAMGCoarsenPMIS

	Function: hypre_BoomerAMGCoarsenPMIS	Module: exec	Source: par_coarsen.c:1980-2624 [...]	Coverage (incl. loops): 0.04% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c: 1980 - 2624

--------------------------------------------------------------------------------

1980: {

1981: #ifdef HYPRE_PROFILE

1982:    hypre_profile_times[HYPRE_TIMER_ID_PMIS] -= hypre_MPI_Wtime();

1983: #endif

1984:

1985:    MPI_Comm 	       comm            = hypre_ParCSRMatrixComm(S);

1986:    hypre_ParCSRCommPkg      *comm_pkg        = hypre_ParCSRMatrixCommPkg(S);

1987:    hypre_ParCSRCommHandle   *comm_handle;

1988:

1989:    hypre_CSRMatrix    *S_diag          = hypre_ParCSRMatrixDiag(S);

1990:    HYPRE_Int                *S_diag_i        = hypre_CSRMatrixI(S_diag);

1991:    HYPRE_Int                *S_diag_j        = hypre_CSRMatrixJ(S_diag);

1992:

1993:    hypre_CSRMatrix    *S_offd          = hypre_ParCSRMatrixOffd(S);

1994:    HYPRE_Int                *S_offd_i        = hypre_CSRMatrixI(S_offd);

1995:    HYPRE_Int                *S_offd_j;

1996:

1997:    HYPRE_Int                 num_variables   = hypre_CSRMatrixNumRows(S_diag);

[...]

2058:    if (debug_flag == 3) wall_time = time_getWallclockSeconds();

2059:    hypre_MPI_Comm_size(comm,&num_procs);

2060:    hypre_MPI_Comm_rank(comm,&my_id);

2061:

2062:    if (!comm_pkg)

2063:    {

2064:         comm_pkg = hypre_ParCSRMatrixCommPkg(A);

2065:    }

2066:

2067:    if (!comm_pkg)

2068:    {

2069:         hypre_MatvecCommPkgCreate(A);

2070:         comm_pkg = hypre_ParCSRMatrixCommPkg(A);

2071:    }

2072:

2073:    num_sends = hypre_ParCSRCommPkgNumSends(comm_pkg);

2074:

2075:    int_buf_data = hypre_CTAlloc(HYPRE_Int, hypre_ParCSRCommPkgSendMapStart(comm_pkg,

2076:                                                 num_sends));

2077:    buf_data = hypre_CTAlloc(HYPRE_Real, hypre_ParCSRCommPkgSendMapStart(comm_pkg,

2078:                                                 num_sends));

2079:

2080:    num_cols_offd = hypre_CSRMatrixNumCols(S_offd);

2081:

2082:    S_diag_j = hypre_CSRMatrixJ(S_diag);

2083:

2084:    if (num_cols_offd)

2085:    {

2086:       S_offd_j = hypre_CSRMatrixJ(S_offd);

[...]

2100:    measure_array = hypre_CTAlloc(HYPRE_Real, num_variables+num_cols_offd);

2101:

2102:    /* first calculate the local part of the sums for the external nodes */

2103: #ifdef HYPRE_USING_OPENMP

2104:    HYPRE_Int *measure_array_temp = hypre_CTAlloc(HYPRE_Int, num_variables+num_cols_offd);

2105:

2106: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

[...]

2113: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

[...]

2126:    if (num_procs > 1)

2127:    comm_handle = hypre_ParCSRCommHandleCreate(2, comm_pkg,

2128:                         &measure_array[num_variables], buf_data);

2129:

2130:    /* calculate the local part for the local nodes */

2131: #ifdef HYPRE_USING_OPENMP

2132: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

[...]

2139: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

[...]

2145:    hypre_TFree(measure_array_temp);

[...]

2154:    if (num_procs > 1)

2155:    hypre_ParCSRCommHandleDestroy(comm_handle);

2156:

2157:    /* now add the externally calculated part of the local nodes to the local nodes */

2158:    index = 0;

2159:    for (i=0; i < num_sends; i++)

2160:    {

2161:       start = hypre_ParCSRCommPkgSendMapStart(comm_pkg, i);

2162:       for (j=start; j < hypre_ParCSRCommPkgSendMapStart(comm_pkg, i+1); j++)

2163:             measure_array[hypre_ParCSRCommPkgSendMapElmt(comm_pkg,j)]

2164:                         += buf_data[index++];

2165:    }

2166:

2167:    /* set the measures of the external nodes to zero */

2168:    for (i=num_variables; i < num_variables+num_cols_offd; i++)

2169:    {

2170:       measure_array[i] = 0;

[...]

2176:    if (CF_init == 2 || CF_init == 4)

2177:       hypre_BoomerAMGIndepSetInit(S, measure_array, 1);

2178:    else

2179:       hypre_BoomerAMGIndepSetInit(S, measure_array, 0);

[...]

2186:    if (num_cols_offd)

2187:       graph_array_offd = hypre_CTAlloc(HYPRE_Int, num_cols_offd);

2188:    else

2189:       graph_array_offd = NULL;

2190:

2191:    for (ig = 0; ig < num_cols_offd; ig++)

2192:       graph_array_offd[ig] = ig;

2193:

2194:    graph_offd_size = num_cols_offd;

2195:

2196:    /* now the local part of the graph array, and the local CF_marker array */

2197:    graph_array = hypre_CTAlloc(HYPRE_Int, num_variables);

2198:

2199:    if (CF_init==1)

2200:    {

2201:       CF_marker = *CF_marker_ptr;

2202:       cnt = 0;

2203:       for (i=0; i < num_variables; i++)

2204:       {

2205:          if ( (S_offd_i[i+1]-S_offd_i[i]) > 0 || CF_marker[i] == -1)

2206: 	 {

2207: 	   CF_marker[i] = 0;

2208: 	 }

2209:          if ( CF_marker[i] == Z_PT)

2210:          {

2211:             if (measure_array[i] >= 1.0 ||

2212:                 (S_diag_i[i+1]-S_diag_i[i]) > 0)

[...]

2219:                CF_marker[i] = F_PT;

2220:             }

2221:          }

2222:          else if (CF_marker[i] == SF_PT)

2223:             measure_array[i] = 0;

[...]

2230:       CF_marker = hypre_CTAlloc(HYPRE_Int, num_variables);

2231:       cnt = 0;

2232:       for (i=0; i < num_variables; i++)

2233:       {

2234:          CF_marker[i] = 0;

2235:          if ( (S_diag_i[i+1]-S_diag_i[i]) == 0

2236:                 && (S_offd_i[i+1]-S_offd_i[i]) == 0)

2237:          {

2238:             CF_marker[i] = SF_PT; /* an isolated fine grid */

2239:             if (CF_init == 3 || CF_init == 4) CF_marker[i] = C_PT;

2240:             measure_array[i] = 0;

2241:          }

2242:          else

2243:             graph_array[cnt++] = i;

2244:       }

2245:    }

2246:    graph_size = cnt;

2247:

2248:    /* now the off-diagonal part of CF_marker */

2249:    if (num_cols_offd)

2250:      CF_marker_offd = hypre_CTAlloc(HYPRE_Int, num_cols_offd);

2251:    else

2252:      CF_marker_offd = NULL;

2253:

2254:    for (i=0; i < num_cols_offd; i++)

2255: 	CF_marker_offd[i] = 0;

[...]

2262:    for (i = 0; i < num_sends; i++)

2263:      {

2264:        start = hypre_ParCSRCommPkgSendMapStart(comm_pkg, i);

2265:        for (j = start; j < hypre_ParCSRCommPkgSendMapStart(comm_pkg, i+1); j++)

2266: 	 {

2267: 	   jrow = hypre_ParCSRCommPkgSendMapElmt(comm_pkg,j);

2268: 	   buf_data[index++] = measure_array[jrow];

2269:          }

2270:      }

2271:

2272:    if (num_procs > 1)

2273:      {

2274:        comm_handle = hypre_ParCSRCommHandleCreate(1, comm_pkg, buf_data,

2275: 						  &measure_array[num_variables]);

2276:

2277:        hypre_ParCSRCommHandleDestroy(comm_handle);

2278:

2279:      }

2280:

2281:    if (debug_flag == 3)

2282:    {

2283:       wall_time = time_getWallclockSeconds() - wall_time;

2284:       hypre_printf("Proc = %d    Initialize CLJP phase = %f\n",

2285:                      my_id, wall_time);

2286:    }

2287:

2288:    HYPRE_Int                *graph_array2 = hypre_CTAlloc(HYPRE_Int, num_variables);

2289:    HYPRE_Int *graph_array_offd2 = NULL;

2290:    if (num_cols_offd)

2291:      graph_array_offd2 = hypre_CTAlloc(HYPRE_Int, num_cols_offd);

[...]

2305:      hypre_MPI_Allreduce(&graph_size,&global_graph_size,1,HYPRE_MPI_INT,hypre_MPI_SUM,comm);

2306:

2307:      if (global_graph_size == 0)

[...]

2320:       if (!CF_init || iter)

[...]

2327: #pragma omp parallel for private(ig, i) HYPRE_SMP_SCHEDULE

[...]

2338: #pragma omp parallel for private(ig, i) HYPRE_SMP_SCHEDULE

[...]

2354: #pragma omp parallel for private(ig, i, jS, j, jj) HYPRE_SMP_SCHEDULE

[...]

2393:       if (num_procs > 1)

2394:       {

2395:          comm_handle = hypre_ParCSRCommHandleCreate(12, comm_pkg,

2396: 		CF_marker_offd, int_buf_data);

2397:

2398:          hypre_ParCSRCommHandleDestroy(comm_handle);

2399:       }

2400:

2401:       index = 0;

2402:       for (i = 0; i < num_sends; i++)

2403:       {

2404:          start = hypre_ParCSRCommPkgSendMapStart(comm_pkg, i);

2405:          for (j=start; j < hypre_ParCSRCommPkgSendMapStart(comm_pkg, i+1); j++)

2406:          {

2407:             elmt = hypre_ParCSRCommPkgSendMapElmt(comm_pkg,j);

2408:             if (!int_buf_data[index] && CF_marker[elmt] > 0)

2409:             {

2410:                CF_marker[elmt] = 0;

2411:                index++;

2412:             }

2413:             else

2414:             {

2415:                int_buf_data[index++] = CF_marker[elmt];

2416:             }

2417:          }

2418:       }

2419:

2420:       if (num_procs > 1)

2421:       {

2422:          comm_handle = hypre_ParCSRCommHandleCreate(11, comm_pkg, int_buf_data,

2423:         	CF_marker_offd);

2424:

2425:          hypre_ParCSRCommHandleDestroy(comm_handle);

[...]

2435: #pragma omp parallel for private(ig, i, jS, j) HYPRE_SMP_SCHEDULE

[...]

2492:       for (i = 0; i < num_sends; i++)

2493:       {

2494:         start = hypre_ParCSRCommPkgSendMapStart(comm_pkg, i);

2495:         for (j = start; j < hypre_ParCSRCommPkgSendMapStart(comm_pkg, i+1); j++)

2496:                 int_buf_data[index++]

2497:                  = CF_marker[hypre_ParCSRCommPkgSendMapElmt(comm_pkg,j)];

2498:       }

2499:

2500:       if (num_procs > 1)

2501:       {

2502:       comm_handle = hypre_ParCSRCommHandleCreate(11, comm_pkg, int_buf_data,

2503:         CF_marker_offd);

2504:

2505:       hypre_ParCSRCommHandleDestroy(comm_handle);

[...]

2513:     prefix_sum_workspace = hypre_TAlloc(HYPRE_Int, 2*(hypre_NumThreads() + 1));

2514:

2515: #ifdef HYPRE_USING_OPENMP

2516: #pragma omp parallel private(ig,i)

[...]

2581:      HYPRE_Int *temp = graph_array;

2582:      graph_array = graph_array2;

2583:      graph_array2 = temp;

[...]

2589:      hypre_TFree(prefix_sum_workspace);

[...]

2608:    hypre_TFree(measure_array);

2609:    hypre_TFree(graph_array);

2610:    hypre_TFree(graph_array2);

2611:    hypre_TFree(graph_array_offd2);

2612:    if (num_cols_offd) hypre_TFree(graph_array_offd);

2613:    hypre_TFree(buf_data);

2614:    hypre_TFree(int_buf_data);

2615:    hypre_TFree(CF_marker_offd);

2616:    /*if (num_procs > 1) hypre_CSRMatrixDestroy(S_ext);*/

2617:

2618:    *CF_marker_ptr   = CF_marker;

[...]

2624:    return (ierr);

0x41f3b0 SUB	SP, SP, #352

0x41f3b4 STR	D8, [SP, #240]

0x41f3b8 STP	X29, X30, [SP, #256]

0x41f3bc STP	X28, X27, [SP, #272]

0x41f3c0 STP	X26, X25, [SP, #288]

0x41f3c4 STP	X24, X23, [SP, #304]

0x41f3c8 STP	X22, X21, [SP, #320]

0x41f3cc STP	X20, X19, [SP, #336]

0x41f3d0 ADD	X29, SP, #256

0x41f3d4 LDR	X8, [X0]

0x41f3d8 LDP	X26, X27, [X0, #56]

0x41f3dc LDR	X22, [X0, #112]

0x41f3e0 ORR	X28, XZR, X4

0x41f3e4 ORR	X25, XZR, X3

0x41f3e8 ORR	X20, XZR, X1

0x41f3ec ORR	X19, XZR, X0

0x41f3f0 STP	X2, X8, [SP, #64]

0x41f3f4 LDP	X8, X9, [X26]

0x41f3f8 STUR	X8, [X29, #504]

0x41f3fc STUR	X9, [X29, #480]

0x41f400 LDR	X8, [X27]

0x41f404 STUR	X8, [X29, #472]

0x41f408 LDR	X8, [X26, #16]

0x41f40c STP	XZR, X8, [X29, #960]

0x41f410 CMP	X3, #3

0x41f414 B.NE	41f420

0x41f418 BL	4a8aa0

0x41f41c FMOV	D8, D0

0x41f420 LDR	X21, [SP, #72]

0x41f424 ADD	X1, SP, #112

0x41f428 ORR	X0, XZR, X21

0x41f42c BL	4a7e70

0x41f430 ADD	X1, SP, #120

0x41f434 ORR	X0, XZR, X21

0x41f438 BL	4a7ea0

0x41f43c CBNZ	X22, 41f454

0x41f440 LDR	X22, [X20, #112]

0x41f444 CBNZ	X22, 41f454

0x41f448 ORR	X0, XZR, X20

0x41f44c BL	481820

0x41f450 LDR	X22, [X20, #112]

0x41f454 LDR	X21, [X22, #8]

0x41f458 LDR	X8, [X22, #24]

0x41f45c MOVZ	W1, #8

0x41f460 LDR	X0, [X8, X21,LSL #3]

0x41f464 BL	4a6c90

0x41f468 LDR	X8, [X22, #24]

0x41f46c ORR	X23, XZR, X0

0x41f470 MOVZ	W1, #8

0x41f474 LDR	X0, [X8, X21,LSL #3]

0x41f478 BL	4a6c90

0x41f47c LDR	X8, [X27, #24]

0x41f480 LDR	X9, [X26, #8]

0x41f484 ORR	X24, XZR, X0

0x41f488 STUR	X8, [X29, #448]

0x41f48c STUR	X9, [X29, #480]

0x41f490 CBZ	X8, 41f49c

0x41f494 LDR	X9, [X27, #8]

0x41f498 STUR	X9, [X29, #464]

0x41f49c LDUR	X9, [X29, #456]

0x41f4a0 MOVZ	W1, #8

0x41f4a4 ADD	X0, X9, X8

0x41f4a8 BL	4a6c90

0x41f4ac LDP	X9, X8, [X29, #960]

0x41f4b0 STUR	X0, [X29, #424]

0x41f4b4 MOVZ	W1, #8

0x41f4b8 ADD	X0, X9, X8

0x41f4bc BL	4a6c90

0x41f4c0 STR	X0, [SP, #96]

0x41f4c4 ADRP	X0,

0x41f4c8 ADD	X0, X0, #416

0x41f4cc ADRP	X2, 41f4cc

0x41f4d0 ADD	X2, X2, #3872

0x41f4d4 SUB	X3, X29, #40

0x41f4d8 SUB	X4, X29, #56

0x41f4dc ADD	X5, SP, #96

0x41f4e0 SUB	X6, X29, #48

0x41f4e4 MOVZ	W1, #4

0x41f4e8 BL	40f600

0x41f4ec ADRP	X0,

0x41f4f0 ADD	X0, X0, #488

0x41f4f4 ADRP	X2, 4204f4

0x41f4f8 ADD	X2, X2, #112

0x41f4fc SUB	X3, X29, #64

0x41f500 SUB	X4, X29, #88

0x41f504 SUB	X5, X29, #56

0x41f508 ADD	X6, SP, #96

0x41f50c MOVZ	W1, #4

0x41f510 BL	40f600

0x41f514 LDR	X8, [SP, #112]

0x41f518 CMP	X8, #2

0x41f51c B.LT	41f540

0x41f520 LDUR	X8, [X29, #424]

0x41f524 LDUR	X9, [X29, #456]

0x41f528 MOVZ	W0, #2

0x41f52c ORR	X1, XZR, X22

0x41f530 ORR	X3, XZR, X24

0x41f534 ADD	X2, X8, X9,LSL #3

0x41f538 BL	480c50

0x41f53c ORR	X20, XZR, X0

0x41f540 ADRP	X0,

0x41f544 ADD	X0, X0, #560

0x41f548 ADRP	X2, 420548

0x41f54c ADD	X2, X2, #448

0x41f550 SUB	X3, X29, #8

0x41f554 SUB	X4, X29, #56

0x41f558 ADD	X5, SP, #96

0x41f55c SUB	X6, X29, #32

0x41f560 MOVZ	W1, #4

0x41f564 BL	40f600

0x41f568 ADRP	X0,

0x41f56c ADD	X0, X0, #632

0x41f570 ADRP	X2, 420570

0x41f574 ADD	X2, X2, #752

0x41f578 SUB	X3, X29, #56

0x41f57c SUB	X4, X29, #88

0x41f580 ADD	X5, SP, #96

0x41f584 MOVZ	W1, #3

0x41f588 BL	40f600

0x41f58c LDR	X0, [SP, #96]

0x41f590 BL	4a6d90

0x41f594 LDR	X8, [SP, #112]

0x41f598 STR	XZR, [SP, #96]

0x41f59c CMP	X8, #1

0x41f5a0 B.LE	41f5ac

0x41f5a4 ORR	X0, XZR, X20

0x41f5a8 BL	481040

0x41f5ac LDR	X20, [SP, #64]

0x41f5b0 CMP	X21, #1

0x41f5b4 B.LT	41f6d8

0x41f5b8 LDR	X9, [X22, #24]

0x41f5bc LDUR	X10, [X29, #424]

0x41f5c0 ORR	X13, XZR, XZR

0x41f5c4 ORR	X8, XZR, XZR

0x41f5c8 ADD	X11, X24, #16

0x41f5cc LDR	X12, [X9]

0x41f5d0 B	41f5ec

0x41f5d4 HINT	#0

0x41f5d8 HINT	#0

0x41f5dc HINT	#0

(219) 0x41f5e0 ORR	X13, XZR, X14

  (218) 0x41f5e4 CMP	X8, X21

  (218) 0x41f5e8 B.EQ	41f6d8

  (218) 0x41f5ec ADD	X8, X8, #1

  (218) 0x41f5f0 ORR	X15, XZR, X12

  (218) 0x41f5f4 LDR	X12, [X9, X8,LSL #3]

  (218) 0x41f5f8 SUBS	X16, X15, X12

  (218) 0x41f5fc B.GE	41f5e4

(219) 0x41f600 LDR	X17, [X22, #32]

(219) 0x41f604 SUB	W14, W12, W15

(219) 0x41f608 ORR	X18, XZR, X13

(219) 0x41f60c ORR	X0, XZR, X15

(219) 0x41f610 ANDS	X14, X14, #4160

(219) 0x41f614 B.EQ	41f648

(219) 0x41f618 ORR	X1, XZR, X13

(219) 0x41f61c ORR	X0, XZR, X15

  (221) 0x41f620 ADD	X18, X1, #1

  (221) 0x41f624 LDR	D0, [X24, X1,LSL #3]

  (221) 0x41f628 LDR	X1, [X17, X0,LSL #3]

  (221) 0x41f62c ADD	X0, X0, #1

  (221) 0x41f630 SUBS	X14, X14, #1

  (221) 0x41f634 LDR	D1, [X10, X1,LSL #3]

  (221) 0x41f638 FADD	D0, D1, D0

  (221) 0x41f63c STR	D0, [X10, X1,LSL #3]

  (221) 0x41f640 ORR	X1, XZR, X18

  (221) 0x41f644 B.NE	41f620

(219) 0x41f648 ADD	X14, X13, X12

(219) 0x41f64c SUB	X14, X14, X15

(219) 0x41f650 CMN	X16, #4

(219) 0x41f654 B.HI	41f5e0

(219) 0x41f658 ADD	X13, X13, X12

(219) 0x41f65c ADD	X16, X17, X0,LSL #3

(219) 0x41f660 ADD	X17, X11, X18,LSL #3

(219) 0x41f664 SUB	X13, X13, X18

(219) 0x41f668 ADD	X16, X16, #16

(219) 0x41f66c SUB	X13, X13, X15

(219) 0x41f670 HINT	#0

(219) 0x41f674 HINT	#0

(219) 0x41f678 HINT	#0

(219) 0x41f67c HINT	#0

  (220) 0x41f680 LDP	X15, X18, [X16, #1008]

  (220) 0x41f684 LDUR	D0, [X17, #496]

  (220) 0x41f688 SUBS	X13, X13, #4

  (220) 0x41f68c LDR	D1, [X10, X15,LSL #3]

  (220) 0x41f690 FADD	D0, D1, D0

  (220) 0x41f694 STR	D0, [X10, X15,LSL #3]

  (220) 0x41f698 LDUR	D0, [X17, #504]

  (220) 0x41f69c LDR	D1, [X10, X18,LSL #3]

  (220) 0x41f6a0 FADD	D0, D1, D0

  (220) 0x41f6a4 STR	D0, [X10, X18,LSL #3]

  (220) 0x41f6a8 LDP	X15, X18, [X16], #32

  (220) 0x41f6ac LDR	D0, [X17]

  (220) 0x41f6b0 LDR	D1, [X10, X15,LSL #3]

  (220) 0x41f6b4 FADD	D0, D1, D0

  (220) 0x41f6b8 STR	D0, [X10, X15,LSL #3]

  (220) 0x41f6bc LDR	D0, [X17, #8]

  (220) 0x41f6c0 LDR	D1, [X10, X18,LSL #3]

  (220) 0x41f6c4 ADD	X17, X17, #32

  (220) 0x41f6c8 FADD	D0, D1, D0

  (220) 0x41f6cc STR	D0, [X10, X18,LSL #3]

  (220) 0x41f6d0 B.NE	41f680

(219) 0x41f6d4 B	41f5e0

0x41f6d8 LDUR	X8, [X29, #448]

0x41f6dc CMP	X8, #1

0x41f6e0 B.LT	41f710

0x41f6e4 LDUR	X9, [X29, #456]

0x41f6e8 LDUR	X10, [X29, #424]

0x41f6ec ORR	W1, WZR, WZR

0x41f6f0 ADD	X8, X8, X9

0x41f6f4 ADD	X11, X9, #1

0x41f6f8 ADD	X0, X10, X9,LSL #3

0x41f6fc CMP	X8, X11

0x41f700 CSINC	X8, X8, X9, #12

0x41f704 SUB	X8, X8, X9

0x41f708 UBFM	X2, X8, #61, #60

0x41f70c BL	40f750

0x41f710 CMP	X20, #4

0x41f714 B.EQ	41f720

0x41f718 CMP	X20, #2

0x41f71c B.NE	41f730

0x41f720 LDUR	X1, [X29, #424]

0x41f724 ORR	X0, XZR, X19

0x41f728 MOVZ	W2, #1

0x41f72c B	41f73c

0x41f730 LDUR	X1, [X29, #424]

0x41f734 ORR	X0, XZR, X19

0x41f738 ORR	X2, XZR, XZR

0x41f73c BL	425da0

0x41f740 LDUR	X0, [X29, #448]

0x41f744 CBZ	X0, 41f77c

0x41f748 MOVZ	W1, #8

0x41f74c BL	4a6c90

0x41f750 LDUR	X8, [X29, #448]

0x41f754 STUR	X0, [X29, #408]

0x41f758 CMP	X8, #1

0x41f75c B.LT	41f784

0x41f760 ORR	X9, XZR, XZR

(217) 0x41f764 STR	X9, [X0, X9,LSL #3]

(217) 0x41f768 ADD	X9, X9, #1

(217) 0x41f76c LDUR	X8, [X29, #448]

(217) 0x41f770 CMP	X9, X8

(217) 0x41f774 B.LT	41f764

0x41f778 B	41f784

0x41f77c ORR	X8, XZR, XZR

0x41f780 STUR	XZR, [X29, #408]

0x41f784 LDUR	X0, [X29, #456]

0x41f788 MOVZ	W1, #8

0x41f78c STUR	X8, [X29, #392]

0x41f790 BL	4a6c90

0x41f794 STUR	X0, [X29, #416]

0x41f798 CMP	X20, #1

0x41f79c B.NE	41f858

0x41f7a0 LDR	X9, [X28]

0x41f7a4 LDUR	X8, [X29, #456]

0x41f7a8 STUR	X9, [X29, #440]

0x41f7ac CMP	X8, #1

0x41f7b0 B.LT	41f8fc

0x41f7b4 LDUR	X11, [X29, #472]

0x41f7b8 LDUR	X12, [X29, #424]

0x41f7bc LDUR	X13, [X29, #504]

0x41f7c0 FMOV	D0, #1.0000000

0x41f7c4 MOVN	X14, #0

0x41f7c8 ORR	X8, XZR, XZR

0x41f7cc ORR	X10, XZR, XZR

0x41f7d0 B	41f7f0

(216) 0x41f7d4 STR	XZR, [X12, X10,LSL #3]

(216) 0x41f7d8 HINT	#0

(216) 0x41f7dc HINT	#0

(216) 0x41f7e0 LDUR	X15, [X29, #456]

(216) 0x41f7e4 ADD	X10, X10, #1

(216) 0x41f7e8 CMP	X10, X15

(216) 0x41f7ec B.GE	41f900

(216) 0x41f7f0 ADD	X15, X11, X10,LSL #3

(216) 0x41f7f4 LDP	X15, X16, [X15]

(216) 0x41f7f8 CMP	X16, X15

(216) 0x41f7fc B.GT	41f840

(216) 0x41f800 LDR	X15, [X9, X10,LSL #3]

(216) 0x41f804 CMN	X15, #1

(216) 0x41f808 B.EQ	41f840

(216) 0x41f80c CMN	X15, #3

(216) 0x41f810 B.EQ	41f7d4

(216) 0x41f814 CMN	X15, #2

(216) 0x41f818 B.NE	41f844

(216) 0x41f81c LDR	D1, [X12, X10,LSL #3]

(216) 0x41f820 FCMP	D1, D0

(216) 0x41f824 B.GE	41f840

(216) 0x41f828 ADD	X15, X13, X10,LSL #3

(216) 0x41f82c LDP	X15, X16, [X15]

(216) 0x41f830 CMP	X16, X15

(216) 0x41f834 B.LE	41f850

(216) 0x41f838 HINT	#0

(216) 0x41f83c HINT	#0

(216) 0x41f840 STR	XZR, [X9, X10,LSL #3]

(216) 0x41f844 STR	X10, [X0, X8,LSL #3]

(216) 0x41f848 ADD	X8, X8, #1

(216) 0x41f84c B	41f7e0

(216) 0x41f850 STR	X14, [X9, X10,LSL #3]

(216) 0x41f854 B	41f7e0

0x41f858 LDUR	X0, [X29, #456]

0x41f85c MOVZ	W1, #8

0x41f860 BL	4a6c90

0x41f864 LDUR	X8, [X29, #456]

0x41f868 STUR	X0, [X29, #440]

0x41f86c CMP	X8, #1

0x41f870 B.LT	41f8fc

0x41f874 SUB	X10, X20, #3

0x41f878 ORR	X8, XZR, XZR

0x41f87c ORR	X9, XZR, XZR

0x41f880 CMP	X10, #2

0x41f884 MOVN	X10, #2

0x41f888 CSINC	X10, X10, XZR, #2

0x41f88c B	41f8bc

0x41f890 HINT	#0

0x41f894 HINT	#0

0x41f898 HINT	#0

0x41f89c HINT	#0

(214) 0x41f8a0 LDUR	X11, [X29, #416]

(214) 0x41f8a4 STR	X9, [X11, X8,LSL #3]

(214) 0x41f8a8 ADD	X8, X8, #1

  (215) 0x41f8ac LDUR	X11, [X29, #456]

  (215) 0x41f8b0 ADD	X9, X9, #1

  (215) 0x41f8b4 CMP	X9, X11

  (215) 0x41f8b8 B.GE	41f900

  (215) 0x41f8bc UBFM	X11, X9, #61, #60

  (215) 0x41f8c0 STR	XZR, [X0, X11]

  (215) 0x41f8c4 LDUR	X11, [X29, #504]

  (215) 0x41f8c8 ADD	X11, X11, X9,LSL #3

  (215) 0x41f8cc LDP	X11, X12, [X11]

  (215) 0x41f8d0 CMP	X12, X11

  (215) 0x41f8d4 B.NE	41f8a0

  (215) 0x41f8d8 LDUR	X11, [X29, #472]

  (215) 0x41f8dc ADD	X11, X11, X9,LSL #3

  (215) 0x41f8e0 LDP	X11, X12, [X11]

  (215) 0x41f8e4 CMP	X12, X11

  (215) 0x41f8e8 B.NE	41f8a0

  (215) 0x41f8ec STR	X10, [X0, X9,LSL #3]

  (215) 0x41f8f0 LDUR	X11, [X29, #424]

  (215) 0x41f8f4 STR	XZR, [X11, X9,LSL #3]

  (215) 0x41f8f8 B	41f8ac

0x41f8fc ORR	X8, XZR, XZR

0x41f900 LDUR	X0, [X29, #448]

0x41f904 STUR	X8, [X29, #400]

0x41f908 CBZ	X0, 41f948

0x41f90c MOVZ	W1, #8

0x41f910 BL	4a6c90

0x41f914 LDUR	X8, [X29, #448]

0x41f918 STUR	X0, [X29, #432]

0x41f91c CMP	X8, #1

0x41f920 B.LT	41f93c

0x41f924 ORR	X8, XZR, XZR

(213) 0x41f928 STR	XZR, [X0, X8,LSL #3]

(213) 0x41f92c ADD	X8, X8, #1

(213) 0x41f930 LDUR	X9, [X29, #448]

(213) 0x41f934 CMP	X8, X9

(213) 0x41f938 B.LT	41f928

0x41f93c CMP	X21, #1

0x41f940 B.GE	41f954

0x41f944 B	41fa40

0x41f948 STUR	XZR, [X29, #432]

0x41f94c CMP	X21, #1

0x41f950 B.LT	41fa40

0x41f954 LDR	X9, [X22, #24]

0x41f958 LDUR	X10, [X29, #424]

0x41f95c ORR	X13, XZR, XZR

0x41f960 ORR	X8, XZR, XZR

0x41f964 ADD	X11, X24, #16

0x41f968 LDR	X12, [X9]

0x41f96c B	41f98c

0x41f970 HINT	#0

0x41f974 HINT	#0

0x41f978 HINT	#0

0x41f97c HINT	#0

(210) 0x41f980 ORR	X13, XZR, X15

  (209) 0x41f984 CMP	X8, X21

  (209) 0x41f988 B.EQ	41fa40

  (209) 0x41f98c ADD	X8, X8, #1

  (209) 0x41f990 ORR	X14, XZR, X12

  (209) 0x41f994 LDR	X12, [X9, X8,LSL #3]

  (209) 0x41f998 SUBS	X16, X14, X12

  (209) 0x41f99c B.GE	41f984

(210) 0x41f9a0 LDR	X17, [X22, #32]

(210) 0x41f9a4 SUB	W15, W12, W14

(210) 0x41f9a8 ORR	X18, XZR, X13

(210) 0x41f9ac ORR	X0, XZR, X14

(210) 0x41f9b0 ANDS	X15, X15, #4160

(210) 0x41f9b4 B.EQ	41f9e0

(210) 0x41f9b8 ORR	X1, XZR, X13

(210) 0x41f9bc ORR	X0, XZR, X14

  (212) 0x41f9c0 LDR	X18, [X17, X0,LSL #3]

  (212) 0x41f9c4 ADD	X0, X0, #1

  (212) 0x41f9c8 SUBS	X15, X15, #1

  (212) 0x41f9cc LDR	D0, [X10, X18,LSL #3]

  (212) 0x41f9d0 ADD	X18, X1, #1

  (212) 0x41f9d4 STR	D0, [X24, X1,LSL #3]

  (212) 0x41f9d8 ORR	X1, XZR, X18

  (212) 0x41f9dc B.NE	41f9c0

(210) 0x41f9e0 ADD	X15, X13, X12

(210) 0x41f9e4 SUB	X15, X15, X14

(210) 0x41f9e8 CMN	X16, #4

(210) 0x41f9ec B.HI	41f980

(210) 0x41f9f0 ADD	X13, X13, X12

(210) 0x41f9f4 ADD	X16, X17, X0,LSL #3

(210) 0x41f9f8 ADD	X17, X11, X18,LSL #3

(210) 0x41f9fc SUB	X13, X13, X18

(210) 0x41fa00 ADD	X16, X16, #16

(210) 0x41fa04 SUB	X13, X13, X14

  (211) 0x41fa08 LDP	X14, X18, [X16, #1008]

  (211) 0x41fa0c SUBS	X13, X13, #4

  (211) 0x41fa10 LDR	D0, [X10, X14,LSL #3]

  (211) 0x41fa14 STUR	D0, [X17, #496]

  (211) 0x41fa18 LDR	D0, [X10, X18,LSL #3]

  (211) 0x41fa1c LDP	X14, X18, [X16], #32

  (211) 0x41fa20 STUR	D0, [X17, #504]

  (211) 0x41fa24 LDR	D0, [X10, X14,LSL #3]

  (211) 0x41fa28 STR	D0, [X17]

  (211) 0x41fa2c LDR	D0, [X10, X18,LSL #3]

  (211) 0x41fa30 STR	D0, [X17, #8]

  (211) 0x41fa34 ADD	X17, X17, #32

  (211) 0x41fa38 B.NE	41fa08

(210) 0x41fa3c B	41f980

0x41fa40 LDR	X8, [SP, #112]

0x41fa44 CMP	X8, #1

0x41fa48 B.LE	41fa6c

0x41fa4c LDUR	X8, [X29, #424]

0x41fa50 LDUR	X9, [X29, #456]

0x41fa54 MOVZ	W0, #1

0x41fa58 ORR	X1, XZR, X22

0x41fa5c ORR	X2, XZR, X24

0x41fa60 ADD	X3, X8, X9,LSL #3

0x41fa64 BL	480c50

0x41fa68 BL	481040

0x41fa6c CMP	X25, #3

0x41fa70 B.NE	41fa8c

0x41fa74 BL	4a8aa0

0x41fa78 LDR	X1, [SP, #120]

0x41fa7c FSUB	D0, D0, S8

0x41fa80 ADRP	X0,

0x41fa84 ADD	X0, X0, #750

0x41fa88 BL	4a6ee0

0x41fa8c LDUR	X0, [X29, #456]

0x41fa90 MOVZ	W1, #8

0x41fa94 STR	X28, [SP, #56]

0x41fa98 BL	4a6c90

0x41fa9c STP	XZR, X0, [SP, #80]

0x41faa0 LDUR	X0, [X29, #448]

0x41faa4 CBZ	X0, 41fab4

0x41faa8 MOVZ	W1, #8

0x41faac BL	4a6c90

0x41fab0 STR	X0, [SP, #80]

0x41fab4 ADRP	X3,

0x41fab8 ADRP	X4,

0x41fabc SUB	X0, X29, #112

0x41fac0 ADD	X1, SP, #128

0x41fac4 MOVZ	W2, #1

0x41fac8 LDR	X3, [X3, #4000]

0x41facc LDR	X4, [X4, #4032]

0x41fad0 LDR	X5, [SP, #72]

0x41fad4 BL	4a86a0

0x41fad8 LDR	X8, [SP, #128]

0x41fadc CBZ	X8, 41fe84

0x41fae0 AND	X27, X21, #8063

0x41fae4 SUB	X28, X29, #56

0x41fae8 SUB	X19, X29, #80

0x41faec SUB	X25, X29, #48

0x41faf0 SUB	X20, X29, #40

0x41faf4 ORR	X26, XZR, XZR

0x41faf8 B	41fbac

0x41fafc HINT	#0

    (201) 0x41fb00 ADD	X26, X26, #1

    (201) 0x41fb04 BL	4a89d0

    (201) 0x41fb08 UBFM	X8, X0, #60, #59

    (201) 0x41fb0c ADD	X0, X8, #16

    (201) 0x41fb10 BL	4a6c20

    (201) 0x41fb14 ADD	X8, SP, #80

    (201) 0x41fb18 STR	X0, [SP, #104]

    (201) 0x41fb1c SUB	X3, X29, #112

    (201) 0x41fb20 SUB	X4, X29, #120

    (201) 0x41fb24 SUB	X5, X29, #96

    (201) 0x41fb28 SUB	X6, X29, #72

    (201) 0x41fb2c SUB	X7, X29, #88

    (201) 0x41fb30 STR	X8, [SP, #40]

    (201) 0x41fb34 ADD	X8, SP, #88

    (201) 0x41fb38 ADRP	X0,

    (201) 0x41fb3c ADD	X0, X0, #944

    (201) 0x41fb40 MOVZ	W1, #11

    (201) 0x41fb44 ADRP	X2, 420b44

    (201) 0x41fb48 ADD	X2, X2, #2608

    (201) 0x41fb4c STR	X8, [SP, #32]

    (201) 0x41fb50 ADD	X8, SP, #104

    (201) 0x41fb54 STP	X28, X8, [SP, #16]

    (201) 0x41fb58 SUB	X8, X29, #104

    (201) 0x41fb5c STP	X8, X19, [SP]

    (201) 0x41fb60 BL	40f600

    (201) 0x41fb64 LDP	X8, X10, [X29, #920]

    (201) 0x41fb68 LDP	X9, X11, [SP, #80]

    (201) 0x41fb6c LDR	X0, [SP, #104]

    (201) 0x41fb70 STP	X9, X11, [X29, #920]

    (201) 0x41fb74 STP	X8, X10, [SP, #80]

    (201) 0x41fb78 BL	4a6d90

    (201) 0x41fb7c STR	XZR, [SP, #104]

    (201) 0x41fb80 ADRP	X3,

    (201) 0x41fb84 ADRP	X4,

    (201) 0x41fb88 SUB	X0, X29, #112

    (201) 0x41fb8c ADD	X1, SP, #128

    (201) 0x41fb90 MOVZ	W2, #1

    (201) 0x41fb94 LDR	X3, [X3, #4000]

    (201) 0x41fb98 LDR	X4, [X4, #4032]

    (201) 0x41fb9c LDR	X5, [SP, #72]

    (201) 0x41fba0 BL	4a86a0

    (201) 0x41fba4 LDR	X8, [SP, #128]

    (201) 0x41fba8 CBZ	X8, 41fe84

    (201) 0x41fbac LDR	X8, [SP, #64]

    (201) 0x41fbb0 CBZ	X8, 41fbb8

    (201) 0x41fbb4 CBZ	X26, 41fd24

    (201) 0x41fbb8 SUB	X3, X29, #112

    (201) 0x41fbbc SUB	X4, X29, #96

    (201) 0x41fbc0 SUB	X5, X29, #88

    (201) 0x41fbc4 SUB	X6, X29, #72

    (201) 0x41fbc8 ADRP	X0,

    (201) 0x41fbcc ADD	X0, X0, #704

    (201) 0x41fbd0 MOVZ	W1, #4

    (201) 0x41fbd4 ADRP	X2, 420bd4

    (201) 0x41fbd8 ADD	X2, X2, #1056

    (201) 0x41fbdc BL	40f600

    (201) 0x41fbe0 SUB	X3, X29, #120

    (201) 0x41fbe4 SUB	X4, X29, #104

    (201) 0x41fbe8 SUB	X5, X29, #88

    (201) 0x41fbec SUB	X6, X29, #56

    (201) 0x41fbf0 SUB	X7, X29, #80

    (201) 0x41fbf4 ADRP	X0,

    (201) 0x41fbf8 ADD	X0, X0, #776

    (201) 0x41fbfc MOVZ	W1, #5

    (201) 0x41fc00 ADRP	X2, 420c00

    (201) 0x41fc04 ADD	X2, X2, #1408

    (201) 0x41fc08 BL	40f600

    (201) 0x41fc0c SUB	X3, X29, #112

    (201) 0x41fc10 SUB	X4, X29, #96

    (201) 0x41fc14 SUB	X5, X29, #88

    (201) 0x41fc18 SUB	X6, X29, #8

    (201) 0x41fc1c SUB	X7, X29, #32

    (201) 0x41fc20 SUB	X8, X29, #72

    (201) 0x41fc24 STP	X28, X19, [SP, #24]

    (201) 0x41fc28 STP	X20, X25, [SP, #8]

    (201) 0x41fc2c STR	X8, [SP]

    (201) 0x41fc30 ADRP	X0,

    (201) 0x41fc34 ADD	X0, X0, #848

    (201) 0x41fc38 MOVZ	W1, #10

    (201) 0x41fc3c ADRP	X2, 420c3c

    (201) 0x41fc40 ADD	X2, X2, #1680

    (201) 0x41fc44 BL	40f600

    (201) 0x41fc48 LDR	X8, [SP, #112]

    (201) 0x41fc4c CMP	X8, #1

    (201) 0x41fc50 B.LE	41fc6c

    (201) 0x41fc54 LDUR	X2, [X29, #432]

    (201) 0x41fc58 MOVZ	W0, #12

    (201) 0x41fc5c ORR	X1, XZR, X22

    (201) 0x41fc60 ORR	X3, XZR, X23

    (201) 0x41fc64 BL	480c50

    (201) 0x41fc68 BL	481040

    (201) 0x41fc6c CMP	X21, #1

    (201) 0x41fc70 B.LT	41fd00

    (201) 0x41fc74 LDR	X10, [X22, #24]

    (201) 0x41fc78 ORR	X8, XZR, XZR

    (201) 0x41fc7c ORR	X9, XZR, XZR

    (201) 0x41fc80 LDR	X11, [X10]

    (201) 0x41fc84 B	41fc94

      (206) 0x41fc88 ORR	X11, XZR, X14

      (206) 0x41fc8c CMP	X9, X21

      (206) 0x41fc90 B.EQ	41fd00

      (206) 0x41fc94 ADD	X9, X9, #1

      (206) 0x41fc98 LDR	X14, [X10, X9,LSL #3]

      (206) 0x41fc9c CMP	X11, X14

      (206) 0x41fca0 B.GE	41fc88

      (206) 0x41fca4 LDR	X12, [X22, #32]

      (206) 0x41fca8 LDUR	X13, [X29, #440]

      (206) 0x41fcac B	41fcd8

0x41fcb0 HINT	#0

0x41fcb4 HINT	#0

0x41fcb8 HINT	#0

0x41fcbc HINT	#0

        (207) 0x41fcc0 STR	X15, [X23, X8,LSL #3]

        (207) 0x41fcc4 LDR	X14, [X10, X9,LSL #3]

        (207) 0x41fcc8 ADD	X8, X8, #1

        (207) 0x41fccc ADD	X11, X11, #1

        (207) 0x41fcd0 CMP	X11, X14

        (207) 0x41fcd4 B.GE	41fc88

        (207) 0x41fcd8 LDR	X14, [X12, X11,LSL #3]

        (207) 0x41fcdc LDR	X16, [X23, X8,LSL #3]

        (207) 0x41fce0 LDR	X15, [X13, X14,LSL #3]

        (207) 0x41fce4 CMP	X16, #0

        (207) 0x41fce8 CCMP	X15, #1, #8, #0

        (207) 0x41fcec B.LT	41fcc0

        (207) 0x41fcf0 STR	XZR, [X13, X14,LSL #3]

        (207) 0x41fcf4 B	41fcc4

0x41fcf8 HINT	#0

0x41fcfc HINT	#0

    (201) 0x41fd00 LDR	X8, [SP, #112]

    (201) 0x41fd04 CMP	X8, #1

    (201) 0x41fd08 B.LE	41fd24

    (201) 0x41fd0c LDUR	X3, [X29, #432]

    (201) 0x41fd10 MOVZ	W0, #11

    (201) 0x41fd14 ORR	X1, XZR, X22

    (201) 0x41fd18 ORR	X2, XZR, X23

    (201) 0x41fd1c BL	480c50

    (201) 0x41fd20 BL	481040

    (201) 0x41fd24 SUB	X3, X29, #112

    (201) 0x41fd28 SUB	X4, X29, #96

    (201) 0x41fd2c SUB	X5, X29, #88

    (201) 0x41fd30 SUB	X6, X29, #72

    (201) 0x41fd34 SUB	X7, X29, #8

    (201) 0x41fd38 SUB	X8, X29, #32

    (201) 0x41fd3c STP	X25, X19, [SP, #16]

    (201) 0x41fd40 STP	X8, X20, [SP]

    (201) 0x41fd44 ADRP	X0,

    (201) 0x41fd48 ADD	X0, X0, #920

    (201) 0x41fd4c MOVZ	W1, #9

    (201) 0x41fd50 ADRP	X2, 420d50

    (201) 0x41fd54 ADD	X2, X2, #2160

    (201) 0x41fd58 BL	40f600

    (201) 0x41fd5c CMP	X21, #1

    (201) 0x41fd60 B.LT	41fdc0

  (205) 0x41fd64 LDR	X9, [X22, #24]

  (205) 0x41fd68 LDUR	X8, [X29, #440]

  (205) 0x41fd6c LDR	X10, [X9]

  (205) 0x41fd70 CMP	X21, #1

  (205) 0x41fd74 B.NE	41fde8

  (205) 0x41fd78 ORR	X12, XZR, XZR

  (205) 0x41fd7c ORR	X11, XZR, XZR

  (205) 0x41fd80 TBZ	W21, #0, 41fdc0

  (205) 0x41fd84 ADD	X9, X9, X11,LSL #3

  (205) 0x41fd88 LDR	X11, [X9, #8]

  (205) 0x41fd8c CMP	X10, X11

  (205) 0x41fd90 B.GE	41fdc0

  (205) 0x41fd94 LDR	X11, [X22, #32]

  (205) 0x41fd98 ADD	X12, X23, X12,LSL #3

  (205) 0x41fd9c HINT	#0

    (208) 0x41fda0 LDR	X13, [X11, X10,LSL #3]

    (208) 0x41fda4 ADD	X10, X10, #1

    (208) 0x41fda8 LDR	X13, [X8, X13,LSL #3]

    (208) 0x41fdac STR	X13, [X12], #8

    (208) 0x41fdb0 LDR	X13, [X9, #8]

    (208) 0x41fdb4 CMP	X10, X13

    (208) 0x41fdb8 B.LT	41fda0

  (205) 0x41fdbc HINT	#0

    (201) 0x41fdc0 LDR	X8, [SP, #112]

    (201) 0x41fdc4 CMP	X8, #1

    (201) 0x41fdc8 B.LE	41fb00

    (201) 0x41fdcc LDUR	X3, [X29, #432]

    (201) 0x41fdd0 MOVZ	W0, #11

    (201) 0x41fdd4 ORR	X1, XZR, X22

    (201) 0x41fdd8 ORR	X2, XZR, X23

    (201) 0x41fddc BL	480c50

    (201) 0x41fde0 BL	481040

    (201) 0x41fde4 B	41fb00

(202) 0x41fde8 ORR	X12, XZR, XZR

(202) 0x41fdec ORR	X11, XZR, XZR

(202) 0x41fdf0 B	41fe08

0x41fdf4 HINT	#0

0x41fdf8 HINT	#0

0x41fdfc HINT	#0

(202) 0x41fe00 CMP	X11, X27

(202) 0x41fe04 B.EQ	41fd80

(202) 0x41fe08 ORR	X14, X11, #4096

(202) 0x41fe0c LDR	X13, [X9, X14,LSL #3]

(202) 0x41fe10 CMP	X10, X13

(202) 0x41fe14 B.GE	41fe40

(202) 0x41fe18 LDR	X15, [X22, #32]

(202) 0x41fe1c HINT	#0

  (204) 0x41fe20 LDR	X13, [X15, X10,LSL #3]

  (204) 0x41fe24 ADD	X10, X10, #1

  (204) 0x41fe28 LDR	X13, [X8, X13,LSL #3]

  (204) 0x41fe2c STR	X13, [X23, X12,LSL #3]

  (204) 0x41fe30 ADD	X12, X12, #1

  (204) 0x41fe34 LDR	X13, [X9, X14,LSL #3]

  (204) 0x41fe38 CMP	X10, X13

  (204) 0x41fe3c B.LT	41fe20

(202) 0x41fe40 ADD	X11, X11, #2

(202) 0x41fe44 LDR	X10, [X9, X11,LSL #3]

(202) 0x41fe48 CMP	X13, X10

(202) 0x41fe4c B.GE	41fe00

(202) 0x41fe50 LDR	X14, [X22, #32]

(202) 0x41fe54 HINT	#0

(202) 0x41fe58 HINT	#0

(202) 0x41fe5c HINT	#0

  (203) 0x41fe60 LDR	X10, [X14, X13,LSL #3]

  (203) 0x41fe64 ADD	X13, X13, #1

  (203) 0x41fe68 LDR	X10, [X8, X10,LSL #3]

  (203) 0x41fe6c STR	X10, [X23, X12,LSL #3]

  (203) 0x41fe70 ADD	X12, X12, #1

  (203) 0x41fe74 LDR	X10, [X9, X11,LSL #3]

  (203) 0x41fe78 CMP	X13, X10

  (203) 0x41fe7c B.LT	41fe60

(202) 0x41fe80 B	41fe00

0x41fe84 LDUR	X0, [X29, #424]

0x41fe88 BL	4a6d90

0x41fe8c LDUR	X0, [X29, #416]

0x41fe90 STUR	XZR, [X29, #424]

0x41fe94 BL	4a6d90

0x41fe98 LDR	X0, [SP, #88]

0x41fe9c STUR	XZR, [X29, #416]

0x41fea0 BL	4a6d90

0x41fea4 LDR	X0, [SP, #80]

0x41fea8 STR	XZR, [SP, #88]

0x41feac BL	4a6d90

0x41feb0 LDUR	X8, [X29, #448]

0x41feb4 STR	XZR, [SP, #80]

0x41feb8 CBZ	X8, 41fec8

0x41febc LDUR	X0, [X29, #408]

0x41fec0 BL	4a6d90

0x41fec4 STUR	XZR, [X29, #408]

0x41fec8 ORR	X0, XZR, X24

0x41fecc BL	4a6d90

0x41fed0 ORR	X0, XZR, X23

0x41fed4 BL	4a6d90

0x41fed8 LDUR	X0, [X29, #432]

0x41fedc BL	4a6d90

0x41fee0 LDUR	X8, [X29, #440]

0x41fee4 LDR	X9, [SP, #56]

0x41fee8 STR	X8, [X9]

0x41feec ORR	X0, XZR, XZR

0x41fef0 LDR	D8, [SP, #240]

0x41fef4 LDP	X20, X19, [SP, #336]

0x41fef8 LDP	X22, X21, [SP, #320]

0x41fefc LDP	X24, X23, [SP, #304]

0x41ff00 LDP	X26, X25, [SP, #288]

0x41ff04 LDP	X28, X27, [SP, #272]

0x41ff08 LDP	X29, X30, [SP, #256]

0x41ff0c ADD	SP, SP, #352

0x41ff10 RET

0x41ff14 HINT	#0

0x41ff18 HINT	#0

0x41ff1c HINT	#0

Coverage (%)	Name	Source Location	Module
►100.00+	hypre_BoomerAMGSetup	par_amg_setup.c:601	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

Coverage (%)	Name	Source Location	Module
►100.00+	hypre_BoomerAMGSetup	par_amg_setup.c:601	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

Coverage (%)	Name	Source Location	Module
►100.00+	hypre_BoomerAMGSetup	par_amg_setup.c:601	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

Coverage (%)	Name	Source Location	Module
►94.12+	hypre_BoomerAMGSetup	par_amg_setup.c:601	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►5.88+	hypre_BoomerAMGSetup	par_amg_setup.c:638	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

Coverage (%)	Name	Source Location	Module
►90.00+	hypre_BoomerAMGSetup	par_amg_setup.c:601	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►10.00+	hypre_BoomerAMGSetup	par_amg_setup.c:638	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

Coverage (%)	Name	Source Location	Module
►82.35+	hypre_BoomerAMGSetup	par_amg_setup.c:601	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►17.65+	hypre_BoomerAMGSetup	par_amg_setup.c:638	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

Coverage (%)	Name	Source Location	Module
►86.96+	hypre_BoomerAMGSetup	par_amg_setup.c:601	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►13.04+	hypre_BoomerAMGSetup	par_amg_setup.c:638	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

Coverage (%)	Name	Source Location	Module
►94.12+	hypre_BoomerAMGSetup	par_amg_setup.c:601	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►5.88+	hypre_BoomerAMGSetup	par_amg_setup.c:638	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	par_coarsen.c:1980-2624
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:1980-1997,2058-2086,2100-2106,2113,2126-2132,2139,2145,2154-2170,2176-2179,2186-2212,2219-2223,2230-2255,2262-2291,2305-2307,2320,2327,2338,2354,2393-2425,2435,2492-2505,2513-2516,2581-2583,2589,2608-2618,2624.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 39.50 to 4.00 cycles (9.87x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 50% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 39.50 to 34.50 cycles (1.14x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 39.50 to 18.00 cycles (2.19x speedup).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary function is loading 664 bytes. The binary function is storing 360 bytes.

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	340
loop length	1360
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

39.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	34.50	34.50	28.33	28.33	28.33	28.33	28.33	28.33	1.00	1.00	1.00	1.00	36.67	36.67	36.67	17.50	17.50
cycles	34.50	34.50	28.33	28.33	28.33	28.33	28.33	28.33	1.00	1.00	1.00	1.00	36.67	36.67	36.67	17.50	17.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	39.50
Overall L1	39.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 39.50 cycles. At this rate:

17% of peak load performance is reached (16.81 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
18% of peak store performance is reached (9.11 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41f3b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #352	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR D8, [SP, #240]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
STP X29, X30, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #256	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X26, X27, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X22, [X0, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X28, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X25, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X20, XZR, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X2, X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X8, X9, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X9, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X27]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X26, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP XZR, X8, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
CMP X3, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 41f420 <hypre_BoomerAMGCoarsenPMIS+0x70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 4a8aa0 <time_getWallclockSeconds>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D8, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LDR X21, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, SP, #112	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X0, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a7e70 <hypre_MPI_Comm_size>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X1, SP, #120	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X0, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a7ea0 <hypre_MPI_Comm_rank>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBNZ X22, 41f454 <hypre_BoomerAMGCoarsenPMIS+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X22, [X20, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X22, 41f454 <hypre_BoomerAMGCoarsenPMIS+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 481820 <hypre_MatvecCommPkgCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X22, [X20, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X21, [X22, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X22, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR X0, [X8, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X22, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X23, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR X0, [X8, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X27, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X26, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X24, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X9, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBZ X8, 41f49c <hypre_BoomerAMGCoarsenPMIS+0xec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X27, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X0, X9, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X9, X8, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X0, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X0, X9, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADRP X0, <4db4c4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #416	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X2, 41f4cc <hypre_BoomerAMGCoarsenPMIS+0x11c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X2, X2, #3872	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X3, X29, #40	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #56	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, SP, #96	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X6, X29, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W1, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f600 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4db4ec>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #488	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X2, 4204f4 <hypre_BoomerAMGCoarsenPMIS.omp_outlined.15+0xd4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X2, X2, #112	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X3, X29, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #88	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X5, X29, #56	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X6, SP, #96	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W1, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f600 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 41f540 <hypre_BoomerAMGCoarsenPMIS+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W0, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X1, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X3, XZR, X24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X2, X8, X9,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 480c50 <hypre_ParCSRCommHandleCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <4db540>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #560	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X2, 420548 <hypre_BoomerAMGCoarsenPMIS.omp_outlined.15+0x128>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X2, X2, #448	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X3, X29, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #56	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, SP, #96	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X6, X29, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W1, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f600 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4db568>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #632	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X2, 420570 <hypre_BoomerAMGCoarsenPMIS.omp_outlined.15+0x150>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X2, X2, #752	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X3, X29, #56	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #88	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, SP, #96	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W1, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f600 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 41f5ac <hypre_BoomerAMGCoarsenPMIS+0x1fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 481040 <hypre_ParCSRCommHandleDestroy>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X20, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X21, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 41f6d8 <hypre_BoomerAMGCoarsenPMIS+0x328>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X22, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X10, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X13, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X11, X24, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X12, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 41f5ec <hypre_BoomerAMGCoarsenPMIS+0x23c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 41f710 <hypre_BoomerAMGCoarsenPMIS+0x360>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X10, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR W1, WZR, WZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X8, X8, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X11, X9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, X10, X9,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X8, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSINC X8, X8, X9, #12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X8, X8, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X2, X8, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 40f750 <@plt_start@+0x360>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 41f720 <hypre_BoomerAMGCoarsenPMIS+0x370>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 41f730 <hypre_BoomerAMGCoarsenPMIS+0x380>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X1, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
B 41f73c <hypre_BoomerAMGCoarsenPMIS+0x38c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X1, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X2, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 425da0 <hypre_BoomerAMGIndepSetInit>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X0, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X0, 41f77c <hypre_BoomerAMGCoarsenPMIS+0x3cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X0, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 41f784 <hypre_BoomerAMGCoarsenPMIS+0x3d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X9, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 41f784 <hypre_BoomerAMGCoarsenPMIS+0x3d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR XZR, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X0, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STUR X8, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR X0, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X20, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 41f858 <hypre_BoomerAMGCoarsenPMIS+0x4a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X28]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 41f8fc <hypre_BoomerAMGCoarsenPMIS+0x54c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X11, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X12, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X13, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
FMOV D0, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MOVN X14, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X10, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 41f7f0 <hypre_BoomerAMGCoarsenPMIS+0x440>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X0, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X0, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 41f8fc <hypre_BoomerAMGCoarsenPMIS+0x54c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X10, X20, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X9, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X10, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
MOVN X10, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CSINC X10, X10, XZR, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 41f8bc <hypre_BoomerAMGCoarsenPMIS+0x50c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR X0, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBZ X0, 41f948 <hypre_BoomerAMGCoarsenPMIS+0x598>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X0, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 41f93c <hypre_BoomerAMGCoarsenPMIS+0x58c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X21, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 41f954 <hypre_BoomerAMGCoarsenPMIS+0x5a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 41fa40 <hypre_BoomerAMGCoarsenPMIS+0x690>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR XZR, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X21, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 41fa40 <hypre_BoomerAMGCoarsenPMIS+0x690>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X22, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X10, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X13, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X11, X24, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X12, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 41f98c <hypre_BoomerAMGCoarsenPMIS+0x5dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 41fa6c <hypre_BoomerAMGCoarsenPMIS+0x6bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X1, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X2, XZR, X24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X3, X8, X9,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 480c50 <hypre_ParCSRCommHandleCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 481040 <hypre_ParCSRCommHandleDestroy>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 41fa8c <hypre_BoomerAMGCoarsenPMIS+0x6dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 4a8aa0 <time_getWallclockSeconds>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
FSUB D0, D0, S8	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADRP X0, <4aca80>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #750	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6ee0 <hypre_printf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X0, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR X28, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP XZR, X0, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDUR X0, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X0, 41fab4 <hypre_BoomerAMGCoarsenPMIS+0x704>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADRP X3, <4dfab4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X4, <4dfab8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X0, X29, #112	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, SP, #128	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR X3, [X3, #4000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X4, #4032]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 4a86a0 <hypre_MPI_Allreduce>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 41fe84 <hypre_BoomerAMGCoarsenPMIS+0xad4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X27, X21, #8063	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X28, X29, #56	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X19, X29, #80	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X25, X29, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X20, X29, #40	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X26, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 41fbac <hypre_BoomerAMGCoarsenPMIS+0x7fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDUR X0, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X0, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR XZR, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR XZR, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBZ X8, 41fec8 <hypre_BoomerAMGCoarsenPMIS+0xb18>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X0, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR XZR, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X0, XZR, X24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X0, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X0, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D8, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP X20, X19, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X26, X25, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X28, X27, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X29, X30, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #352	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	par_coarsen.c:1980-2624
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 39.50 to 4.00 cycles (9.87x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 39.50 to 18.00 cycles (2.19x speedup).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary function is loading 664 bytes. The binary function is storing 360 bytes.

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	340
loop length	1360
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

39.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	34.50	34.50	28.33	28.33	28.33	28.33	28.33	28.33	1.00	1.00	1.00	1.00	36.67	36.67	36.67	17.50	17.50
cycles	34.50	34.50	28.33	28.33	28.33	28.33	28.33	28.33	1.00	1.00	1.00	1.00	36.67	36.67	36.67	17.50	17.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	39.50
Overall L1	39.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 39.50 cycles. At this rate:

17% of peak load performance is reached (16.81 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
18% of peak store performance is reached (9.11 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41f3b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #352	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR D8, [SP, #240]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
STP X29, X30, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #256	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X26, X27, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X22, [X0, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X28, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X25, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X20, XZR, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X2, X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X8, X9, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X9, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X27]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X26, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP XZR, X8, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
CMP X3, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 41f420 <hypre_BoomerAMGCoarsenPMIS+0x70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 4a8aa0 <time_getWallclockSeconds>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D8, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LDR X21, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, SP, #112	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X0, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a7e70 <hypre_MPI_Comm_size>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X1, SP, #120	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X0, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a7ea0 <hypre_MPI_Comm_rank>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBNZ X22, 41f454 <hypre_BoomerAMGCoarsenPMIS+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X22, [X20, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X22, 41f454 <hypre_BoomerAMGCoarsenPMIS+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 481820 <hypre_MatvecCommPkgCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X22, [X20, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X21, [X22, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X22, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR X0, [X8, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X22, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X23, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR X0, [X8, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X27, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X26, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X24, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X9, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBZ X8, 41f49c <hypre_BoomerAMGCoarsenPMIS+0xec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X27, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X0, X9, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X9, X8, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X0, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X0, X9, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADRP X0, <4db4c4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #416	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X2, 41f4cc <hypre_BoomerAMGCoarsenPMIS+0x11c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X2, X2, #3872	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X3, X29, #40	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #56	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, SP, #96	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X6, X29, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W1, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f600 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4db4ec>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #488	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X2, 4204f4 <hypre_BoomerAMGCoarsenPMIS.omp_outlined.15+0xd4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X2, X2, #112	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X3, X29, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #88	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X5, X29, #56	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X6, SP, #96	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W1, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f600 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 41f540 <hypre_BoomerAMGCoarsenPMIS+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W0, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X1, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X3, XZR, X24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X2, X8, X9,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 480c50 <hypre_ParCSRCommHandleCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <4db540>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #560	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X2, 420548 <hypre_BoomerAMGCoarsenPMIS.omp_outlined.15+0x128>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X2, X2, #448	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X3, X29, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #56	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, SP, #96	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X6, X29, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W1, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f600 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4db568>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #632	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X2, 420570 <hypre_BoomerAMGCoarsenPMIS.omp_outlined.15+0x150>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X2, X2, #752	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X3, X29, #56	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #88	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, SP, #96	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W1, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f600 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 41f5ac <hypre_BoomerAMGCoarsenPMIS+0x1fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 481040 <hypre_ParCSRCommHandleDestroy>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X20, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X21, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 41f6d8 <hypre_BoomerAMGCoarsenPMIS+0x328>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X22, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X10, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X13, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X11, X24, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X12, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 41f5ec <hypre_BoomerAMGCoarsenPMIS+0x23c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 41f710 <hypre_BoomerAMGCoarsenPMIS+0x360>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X10, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR W1, WZR, WZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X8, X8, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X11, X9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, X10, X9,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X8, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSINC X8, X8, X9, #12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X8, X8, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X2, X8, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 40f750 <@plt_start@+0x360>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 41f720 <hypre_BoomerAMGCoarsenPMIS+0x370>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 41f730 <hypre_BoomerAMGCoarsenPMIS+0x380>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X1, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
B 41f73c <hypre_BoomerAMGCoarsenPMIS+0x38c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X1, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X2, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 425da0 <hypre_BoomerAMGIndepSetInit>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X0, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X0, 41f77c <hypre_BoomerAMGCoarsenPMIS+0x3cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X0, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 41f784 <hypre_BoomerAMGCoarsenPMIS+0x3d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X9, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 41f784 <hypre_BoomerAMGCoarsenPMIS+0x3d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR XZR, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X0, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STUR X8, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR X0, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X20, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 41f858 <hypre_BoomerAMGCoarsenPMIS+0x4a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X28]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 41f8fc <hypre_BoomerAMGCoarsenPMIS+0x54c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X11, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X12, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X13, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
FMOV D0, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MOVN X14, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X10, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 41f7f0 <hypre_BoomerAMGCoarsenPMIS+0x440>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X0, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X0, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 41f8fc <hypre_BoomerAMGCoarsenPMIS+0x54c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X10, X20, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X9, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X10, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
MOVN X10, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CSINC X10, X10, XZR, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 41f8bc <hypre_BoomerAMGCoarsenPMIS+0x50c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR X0, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBZ X0, 41f948 <hypre_BoomerAMGCoarsenPMIS+0x598>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X0, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 41f93c <hypre_BoomerAMGCoarsenPMIS+0x58c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X21, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 41f954 <hypre_BoomerAMGCoarsenPMIS+0x5a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 41fa40 <hypre_BoomerAMGCoarsenPMIS+0x690>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR XZR, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X21, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 41fa40 <hypre_BoomerAMGCoarsenPMIS+0x690>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X22, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X10, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X13, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X11, X24, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X12, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 41f98c <hypre_BoomerAMGCoarsenPMIS+0x5dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 41fa6c <hypre_BoomerAMGCoarsenPMIS+0x6bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X1, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X2, XZR, X24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X3, X8, X9,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 480c50 <hypre_ParCSRCommHandleCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 481040 <hypre_ParCSRCommHandleDestroy>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 41fa8c <hypre_BoomerAMGCoarsenPMIS+0x6dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 4a8aa0 <time_getWallclockSeconds>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
FSUB D0, D0, S8	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADRP X0, <4aca80>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #750	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6ee0 <hypre_printf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X0, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR X28, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP XZR, X0, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDUR X0, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X0, 41fab4 <hypre_BoomerAMGCoarsenPMIS+0x704>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADRP X3, <4dfab4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X4, <4dfab8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X0, X29, #112	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, SP, #128	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR X3, [X3, #4000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X4, #4032]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 4a86a0 <hypre_MPI_Allreduce>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 41fe84 <hypre_BoomerAMGCoarsenPMIS+0xad4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X27, X21, #8063	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X28, X29, #56	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X19, X29, #80	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X25, X29, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X20, X29, #40	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X26, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 41fbac <hypre_BoomerAMGCoarsenPMIS+0x7fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDUR X0, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X0, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR XZR, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR XZR, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBZ X8, 41fec8 <hypre_BoomerAMGCoarsenPMIS+0xb18>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X0, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR XZR, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X0, XZR, X24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X0, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X0, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D8, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP X20, X19, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X26, X25, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X28, X27, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X29, X30, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #352	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

▶Scalability Runs Description

Run 1x1	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_NUM_THREADS: 1OMP_PLACES: threads
Run 1x2	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 2OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x4	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 4OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x8	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 8OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x16	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 16OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x24	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 24OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x32	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 32OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x40	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 40OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x48	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 48OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x56	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 56OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x64	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 64OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x72	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 72OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x80	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 80OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x88	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 88OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x96	Number processes: 1Number nodes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/run/oneview_runs/multicore/armclang_5/oneview_run_1741633338OMP_NUM_THREADS: 96OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads

(1x1) Efficiency	(1x1) Potential Speed-Up (%)	(1x2) Efficiency	(1x2) Potential Speed-Up (%)	(1x4) Efficiency	(1x4) Potential Speed-Up (%)	(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x16) Efficiency	(1x16) Potential Speed-Up (%)	(1x24) Efficiency	(1x24) Potential Speed-Up (%)	(1x32) Efficiency	(1x32) Potential Speed-Up (%)	(1x40) Efficiency	(1x40) Potential Speed-Up (%)	(1x48) Efficiency	(1x48) Potential Speed-Up (%)	(1x56) Efficiency	(1x56) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)	(1x72) Efficiency	(1x72) Potential Speed-Up (%)	(1x80) Efficiency	(1x80) Potential Speed-Up (%)	(1x88) Efficiency	(1x88) Potential Speed-Up (%)	(1x96) Efficiency	(1x96) Potential Speed-Up (%)
1	0	4.16	0	4.54	0	9.34	0	15.39	0	26.36	0	26.52	0	40.65	0	61.28	0	113.96	0	81.85	0	63.24	0	92.65	0	98.51	0	94.16	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x1	1	1	1	1	0.10499999672174	0.03946939483285
1x2	1	4.16	4.16	2	0.049999993294477	0.017825026065111
1x4	1	4.54	4.54	4	0.089999988675117	0.030570732429624
1x8	1	9.34	9.34	8	0.08500000089407	0.025479091331363
1x16	1	15.39	15.39	16	0.099999986588955	0.023684410378337
1x24	1	26.36	26.36	24	0.084999985992908	0.016086971387267
1x32	1	26.52	26.52	32	0.11499999463558	0.017440414056182
1x40	1	40.65	40.65	40	0.08500000834465	0.010705926455557
1x48	1	61.28	61.28	48	0.069999985396862	0.0077299228869379
1x56	1	113.96	113.96	56	0.045000001788139	0.0045737535692751
1x64	1	81.85	81.85	64	0.070000000298023	0.0065872366540134
1x72	1	63.24	63.24	72	0.099999994039536	0.0085365325212479
1x80	1	92.65	92.65	80	0.080000005662441	0.0063310111872852
1x88	1	98.51	98.51	88	0.075000010430813	0.0054339985363185
1x96	1	94.16	94.16	96	0.084999993443489	0.0057084760628641

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGCoarsenPMIS–	0.04	0.10
▼Loop 214 - par_coarsen.c:2232-2243 - exec–	0.01	0.02
○Loop 215 - par_coarsen.c:2232-2241 - exec	0.03	0.08
▼Loop 210 - par_coarsen.c:2262-2268 - exec–	0.00	0.00
○Loop 209 - par_coarsen.c:2262-2265 - exec	0.00	0.00
○Loop 211 - par_coarsen.c:2265-2268 - exec	0.00	0.00
○Loop 212 - par_coarsen.c:2265-2268 - exec	0.00	0.00
○Loop 217 - par_coarsen.c:2191-2192 - exec	0.00	0.00
○Loop 213 - par_coarsen.c:2254-2255 - exec	0.00	0.00
○Loop 216 - par_coarsen.c:2203-2223 - exec	0.00	0.00
▼Loop 202 - par_coarsen.c:2305-2589 - exec–	0.00	0.00
▼Loop 205 - par_coarsen.c:2305-2589 - exec–	0.00	0.00
○Loop 208 - par_coarsen.c:2495-2497 - exec	0.00	0.00
▼Loop 201 - par_coarsen.c:2305-2589 - exec–	0.00	0.00
▼Loop 206 - par_coarsen.c:2402-2415 - exec–	0.00	0.00
○Loop 207 - par_coarsen.c:2405-2415 - exec	0.00	0.00
○Loop 204 - par_coarsen.c:2495-2497 - exec	0.00	0.00
○Loop 203 - par_coarsen.c:2495-2497 - exec	0.00	0.00
▼Loop 219 - par_coarsen.c:2159-2164 - exec–	0.00	0.00
○Loop 221 - par_coarsen.c:2162-2164 - exec	0.00	0.00
○Loop 220 - par_coarsen.c:2162-2164 - exec	0.00	0.00
○Loop 218 - par_coarsen.c:2159-2162 - exec	0.00	0.00

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