OV - exec - Loop 985

	Loop Id: 985	Module: exec	Source: par_lr_interp.c:1624-1628	Coverage: 0.06%

0x46478c ADD	X5, X3, #32

0x464790 LD1D	{Z27.D}, P7/Z, [X3, #1, MUL VL]    [2]

0x464794 SUB	X1, X3, X8

0x464798 LD1D	{Z28.D}, P7/Z, [X3, #3, MUL VL]    [2]

0x46479c LD1D	{Z30.D}, P7/Z, [X3, MUL VL]    [2]

0x4647a0 SUB	X0, X5, X8

0x4647a4 LD1D	{Z4.D}, P7/Z, [X3, #2, MUL VL]    [2]

0x4647a8 LD1D	{Z31.D}, P7/Z, [X19, Z27.D,LSL #3]    [6]

0x4647ac CMPEQ	P4.D, P7/Z, Z28.D, Z7.D

0x4647b0 CMPEQ	P8.D, P7/Z, Z27.D, Z7.D

0x4647b4 ADD	X5, X7, X0

0x4647b8 LD1D	{Z29.D}, P7/Z, [X19, Z28.D,LSL #3]    [6]

0x4647bc CMPGE	P13.D, P7/Z, Z31.D, Z16.D

0x4647c0 CMPGE	P12.D, P7/Z, Z29.D, Z16.D

0x4647c4 LD1D	{Z5.D}, P7/Z, [X19, Z30.D,LSL #3]    [6]

0x4647c8 ORR	P5.B, P7/Z, P4.B, P12.B

0x4647cc CMPEQ	P9.D, P7/Z, Z30.D, Z7.D

0x4647d0 CMPGE	P10.D, P7/Z, Z5.D, Z16.D

0x4647d4 LD1D	{Z18.D}, P7/Z, [X19, Z4.D,LSL #3]    [6]

0x4647d8 CMPEQ	P11.D, P7/Z, Z4.D, Z7.D

0x4647dc CMPGE	P14.D, P7/Z, Z18.D, Z16.D

0x4647e0 ADD	X3, X3, #64

0x4647e4 LD1D	{Z19.D}, P5/Z, [X5, MUL VL]    [4]

0x4647e8 ORR	P6.B, P7/Z, P8.B, P13.B

0x4647ec ADD	X5, X7, X1

0x4647f0 ORR	P1.B, P7/Z, P9.B, P10.B

0x4647f4 LD1D	{Z21.D}, P6/Z, [X5, MUL VL]    [3]

0x4647f8 ORR	P4.B, P7/Z, P11.B, P14.B

0x4647fc ADD	X0, X11, X0

0x464800 ADD	X1, X11, X1

0x464804 LD1D	{Z0.D}, P4/Z, [X0, MUL VL]    [1]

0x464808 LD1D	{Z23.D}, P1/Z, [X1, MUL VL]    [5]

0x46480c FMUL	Z20.D, Z19.D, Z17.D

0x464810 FMUL	Z22.D, Z21.D, Z17.D

0x464814 FCMLT	P0.D, P5/Z, Z20.D, #0

0x464818 FCMLT	P2.D, P6/Z, Z22.D, #0

0x46481c FMUL	Z1.D, Z23.D, Z17.D

0x464820 FADD	Z6.D, P2/M, Z6.D, Z21.D

0x464824 FCMLT	P3.D, P1/Z, Z1.D, #0

0x464828 FMUL	Z27.D, Z0.D, Z17.D

0x46482c FADD	Z26.D, P3/M, Z26.D, Z23.D

0x464830 FCMLT	P5.D, P4/Z, Z27.D, #0

0x464834 FADD	Z6.D, P0/M, Z6.D, Z19.D

0x464838 FADD	Z26.D, P5/M, Z26.D, Z0.D

0x46483c CMP	X3, X25

0x464840 B.NE	46478c

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c: 1624 - 1628

--------------------------------------------------------------------------------

1624:                for(jj1 = A_diag_i[i1]+1; jj1 < A_diag_i[i1+1]; jj1++)

1625:                {

1626:                  i2 = A_diag_j[jj1];

1627:                  if((P_marker[i2] >= jj_begin_row || i2 == i) && (sgn*A_diag_data[jj1]) < 0)

1628:                    sum += A_diag_data[jj1];

Coverage (%)	Name	Source Location	Module
►100.00+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.09
Bottlenecks	P6, P8,
Function	hypre_BoomerAMGBuildExtPIInterp._omp_fn.0
Source	par_lr_interp.c:1624-1628
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.00
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	12.00
CQA cycles if fully vectorized	12.00
Front-end cycles	5.75
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.83
P3 cycles	1.75
P4 cycles	1.83
P5 cycles	1.83
P6 cycles	12.00
P7 cycles	1.75
P8 cycles	12.00
P9 cycles	2.75
P10 cycles	2.75
P11 cycles	2.50
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	4.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	46.00
Nb uops	46.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	1.33
Nb FLOP add-sub	8.00
Nb FLOP mul	8.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.00
Bytes prefetched	0.00
Bytes loaded	192.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	1.00
Stride unknown	4.00
Stride indirect	1.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	90.28
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	78.13

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.09
Bottlenecks	P6, P8,
Function	hypre_BoomerAMGBuildExtPIInterp._omp_fn.0
Source	par_lr_interp.c:1624-1628
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.00
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	12.00
CQA cycles if fully vectorized	12.00
Front-end cycles	5.75
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.83
P3 cycles	1.75
P4 cycles	1.83
P5 cycles	1.83
P6 cycles	12.00
P7 cycles	1.75
P8 cycles	12.00
P9 cycles	2.75
P10 cycles	2.75
P11 cycles	2.50
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	4.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	46.00
Nb uops	46.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	1.33
Nb FLOP add-sub	8.00
Nb FLOP mul	8.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.00
Bytes prefetched	0.00
Bytes loaded	192.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	1.00
Stride unknown	4.00
Stride indirect	1.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	90.28
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	78.13

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildExtPIInterp._omp_fn.0
Source file and lines	par_lr_interp.c:1624-1628
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1624-1628.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using 90% register length (average across all VPU instructions).

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

8: addition or subtraction
8: multiply

The binary loop is loading 192 bytes.

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	46
loop length	184
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	1.83	1.75	1.83	1.83	12.00	1.75	12.00	2.75	2.75	2.50	4.00	4.00	4.00	0.00	0.00
cycles	0.50	0.50	1.83	1.75	1.83	1.83	12.00	1.75	12.00	2.75	2.75	2.50	4.00	4.00	4.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	5.75
Data deps.	4.00
Overall L1	12.00

Vectorization ratios

INT

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.00 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 46478c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADD X5, X3, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z27.D}, P7/Z, [X3, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
SUB X1, X3, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z28.D}, P7/Z, [X3, #3, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z30.D}, P7/Z, [X3, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
SUB X0, X5, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z4.D}, P7/Z, [X3, #2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z31.D}, P7/Z, [X19, Z27.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
CMPEQ P4.D, P7/Z, Z28.D, Z7.D	1	0	0	0	0	0	0	1	0	1	0	0	0	0	0	0	4	1	vect (100.0%)
CMPEQ P8.D, P7/Z, Z27.D, Z7.D	1	0	0	0	0	0	0	1	0	1	0	0	0	0	0	0	4	1	vect (100.0%)
ADD X5, X7, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z29.D}, P7/Z, [X19, Z28.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
CMPGE P13.D, P7/Z, Z31.D, Z16.D	1	0	0	0	0	0	0	1	0	1	0	0	0	0	0	0	4	1	vect (100.0%)
CMPGE P12.D, P7/Z, Z29.D, Z16.D	1	0	0	0	0	0	0	1	0	1	0	0	0	0	0	0	4	1	vect (100.0%)
LD1D {Z5.D}, P7/Z, [X19, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ORR P5.B, P7/Z, P4.B, P12.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
CMPEQ P9.D, P7/Z, Z30.D, Z7.D	1	0	0	0	0	0	0	1	0	1	0	0	0	0	0	0	4	1	vect (100.0%)
CMPGE P10.D, P7/Z, Z5.D, Z16.D	1	0	0	0	0	0	0	1	0	1	0	0	0	0	0	0	4	1	vect (100.0%)
LD1D {Z18.D}, P7/Z, [X19, Z4.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
CMPEQ P11.D, P7/Z, Z4.D, Z7.D	1	0	0	0	0	0	0	1	0	1	0	0	0	0	0	0	4	1	vect (100.0%)
CMPGE P14.D, P7/Z, Z18.D, Z16.D	1	0	0	0	0	0	0	1	0	1	0	0	0	0	0	0	4	1	vect (100.0%)
ADD X3, X3, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z19.D}, P5/Z, [X5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ORR P6.B, P7/Z, P8.B, P13.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
ADD X5, X7, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ORR P1.B, P7/Z, P9.B, P10.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
LD1D {Z21.D}, P6/Z, [X5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ORR P4.B, P7/Z, P11.B, P14.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
ADD X0, X11, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, X11, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z0.D}, P4/Z, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z23.D}, P1/Z, [X1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMUL Z20.D, Z19.D, Z17.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL Z22.D, Z21.D, Z17.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FCMLT P0.D, P5/Z, Z20.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
FCMLT P2.D, P6/Z, Z22.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
FMUL Z1.D, Z23.D, Z17.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FADD Z6.D, P2/M, Z6.D, Z21.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FCMLT P3.D, P1/Z, Z1.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
FMUL Z27.D, Z0.D, Z17.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FADD Z26.D, P3/M, Z26.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FCMLT P5.D, P4/Z, Z27.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
FADD Z6.D, P0/M, Z6.D, Z19.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FADD Z26.D, P5/M, Z26.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
CMP X3, X25	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 46478c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1220>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_BoomerAMGBuildExtPIInterp._omp_fn.0
Source file and lines	par_lr_interp.c:1624-1628
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using 90% register length (average across all VPU instructions).

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

8: addition or subtraction
8: multiply

The binary loop is loading 192 bytes.

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	46
loop length	184
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	1.83	1.75	1.83	1.83	12.00	1.75	12.00	2.75	2.75	2.50	4.00	4.00	4.00	0.00	0.00
cycles	0.50	0.50	1.83	1.75	1.83	1.83	12.00	1.75	12.00	2.75	2.75	2.50	4.00	4.00	4.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	5.75
Data deps.	4.00
Overall L1	12.00

Vectorization ratios

INT

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.00 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 46478c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADD X5, X3, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z27.D}, P7/Z, [X3, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
SUB X1, X3, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z28.D}, P7/Z, [X3, #3, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z30.D}, P7/Z, [X3, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
SUB X0, X5, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z4.D}, P7/Z, [X3, #2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z31.D}, P7/Z, [X19, Z27.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
CMPEQ P4.D, P7/Z, Z28.D, Z7.D	1	0	0	0	0	0	0	1	0	1	0	0	0	0	0	0	4	1	vect (100.0%)
CMPEQ P8.D, P7/Z, Z27.D, Z7.D	1	0	0	0	0	0	0	1	0	1	0	0	0	0	0	0	4	1	vect (100.0%)
ADD X5, X7, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z29.D}, P7/Z, [X19, Z28.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
CMPGE P13.D, P7/Z, Z31.D, Z16.D	1	0	0	0	0	0	0	1	0	1	0	0	0	0	0	0	4	1	vect (100.0%)
CMPGE P12.D, P7/Z, Z29.D, Z16.D	1	0	0	0	0	0	0	1	0	1	0	0	0	0	0	0	4	1	vect (100.0%)
LD1D {Z5.D}, P7/Z, [X19, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ORR P5.B, P7/Z, P4.B, P12.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
CMPEQ P9.D, P7/Z, Z30.D, Z7.D	1	0	0	0	0	0	0	1	0	1	0	0	0	0	0	0	4	1	vect (100.0%)
CMPGE P10.D, P7/Z, Z5.D, Z16.D	1	0	0	0	0	0	0	1	0	1	0	0	0	0	0	0	4	1	vect (100.0%)
LD1D {Z18.D}, P7/Z, [X19, Z4.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
CMPEQ P11.D, P7/Z, Z4.D, Z7.D	1	0	0	0	0	0	0	1	0	1	0	0	0	0	0	0	4	1	vect (100.0%)
CMPGE P14.D, P7/Z, Z18.D, Z16.D	1	0	0	0	0	0	0	1	0	1	0	0	0	0	0	0	4	1	vect (100.0%)
ADD X3, X3, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z19.D}, P5/Z, [X5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ORR P6.B, P7/Z, P8.B, P13.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
ADD X5, X7, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ORR P1.B, P7/Z, P9.B, P10.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
LD1D {Z21.D}, P6/Z, [X5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ORR P4.B, P7/Z, P11.B, P14.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
ADD X0, X11, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, X11, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z0.D}, P4/Z, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z23.D}, P1/Z, [X1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMUL Z20.D, Z19.D, Z17.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL Z22.D, Z21.D, Z17.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FCMLT P0.D, P5/Z, Z20.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
FCMLT P2.D, P6/Z, Z22.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
FMUL Z1.D, Z23.D, Z17.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FADD Z6.D, P2/M, Z6.D, Z21.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FCMLT P3.D, P1/Z, Z1.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
FMUL Z27.D, Z0.D, Z17.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FADD Z26.D, P3/M, Z26.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FCMLT P5.D, P4/Z, Z27.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
FADD Z6.D, P0/M, Z6.D, Z19.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FADD Z26.D, P5/M, Z26.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
CMP X3, X25	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 46478c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1220>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code