OV - exec - Loop 983

	Loop Id: 983	Module: exec	Source: par_lr_interp.c:1644-1651	Coverage: 0.05%

0x465efc LDR	D1, [X26, X3,LSL #3]    [2]

0x465f00 FMUL	D0, D1, D24

0x465f04 FCMPE	D0, #0

0x465f08 B.MI	4662bc

0x465f0c ADD	X8, X3, #1

0x465f10 LDR	X3, [X12, X8,LSL #3]    [1]

0x465f14 LDR	X25, [X19, X3,LSL #3]    [4]

0x465f18 CMP	X2, X25

0x465f1c B.GT	4661cc

0x465f20 LDR	D21, [X26, X8,LSL #3]    [2]

0x465f24 FMUL	D6, D21, D24

0x465f28 FCMPE	D6, #0

0x465f2c B.MI	4661bc

0x465f30 ADD	X11, X8, #1

0x465f34 LDR	X5, [X12, X11,LSL #3]    [1]

0x465f38 LDR	X1, [X19, X5,LSL #3]    [4]

0x465f3c CMP	X2, X1

0x465f40 B.GT	46619c

0x465f44 LDR	D19, [X26, X11,LSL #3]    [2]

0x465f48 FMUL	D30, D19, D24

0x465f4c FCMPE	D30, #0

0x465f50 B.MI	46618c

0x465f54 ADD	X0, X8, #2

0x465f58 LDR	X7, [X12, X0,LSL #3]    [1]

0x465f5c LDR	X3, [X19, X7,LSL #3]    [4]

0x465f60 CMP	X2, X3

0x465f64 B.GT	46616c

0x465f68 LDR	D27, [X26, X0,LSL #3]    [2]

0x465f6c FMUL	D7, D27, D24

0x465f70 FCMPE	D7, #0

0x465f74 B.MI	46615c

0x465f78 ADD	X3, X8, #3

0x465f7c CMP	X4, X3

0x465f80 B.LE	465bb8

0x465f84 LDR	X9, [X12, X3,LSL #3]    [1]

0x465f88 LDR	X0, [X19, X9,LSL #3]    [4]

0x465f8c CMP	X2, X0

0x465f90 B.LE	465efc

0x465f94 CMP	X22, X9

0x465f98 B.NE	465f0c

0x465f9c LDR	D16, [X26, X3,LSL #3]    [2]

0x465fa0 FMUL	D5, D16, D24

0x465fa4 FMADD	D18, D26, D16, D25

0x465fa8 FCMPE	D5, #0

0x465fac FCSEL	D25, D18, D25, #4

0x465fb0 B	465f0c

0x46615c UBFM	X25, X3, #61, #60

0x466160 LDR	D16, [X28, X25]    [3]

0x466164 FMADD	D5, D26, D27, D16

0x466168 STR	D5, [X28, X25]    [3]

0x46616c CMP	X22, X7

0x466170 B.NE	465f78

0x466174 LDR	D18, [X26, X0,LSL #3]    [2]

0x466178 FMUL	D21, D18, D24

0x46617c FMADD	D6, D26, D18, D25

0x466180 FCMPE	D21, #0

0x466184 FCSEL	D25, D6, D25, #4

0x466188 B	465f78

0x46618c UBFM	X9, X1, #61, #60

0x466190 LDR	D20, [X28, X9]    [3]

0x466194 FMADD	D22, D26, D19, D20

0x466198 STR	D22, [X28, X9]    [3]

0x46619c CMP	X22, X5

0x4661a0 B.NE	465f54

0x4661a4 LDR	D23, [X26, X11,LSL #3]    [2]

0x4661a8 FMUL	D1, D23, D24

0x4661ac FMADD	D0, D26, D23, D25

0x4661b0 FCMPE	D1, #0

0x4661b4 FCSEL	D25, D0, D25, #4

0x4661b8 B	465f54

0x4661bc UBFM	X10, X25, #61, #60

0x4661c0 LDR	D17, [X28, X10]    [3]

0x4661c4 FMADD	D4, D26, D21, D17

0x4661c8 STR	D4, [X28, X10]    [3]

0x4661cc CMP	X22, X3

0x4661d0 B.NE	465f30

0x4661d4 LDR	D31, [X26, X8,LSL #3]    [2]

0x4661d8 FMUL	D28, D31, D24

0x4661dc FMADD	D29, D26, D31, D25

0x4661e0 FCMPE	D28, #0

0x4661e4 FCSEL	D25, D29, D25, #4

0x4661e8 B	465f30

0x4662bc UBFM	X7, X0, #61, #60

0x4662c0 LDR	D27, [X28, X7]    [3]

0x4662c4 FMADD	D7, D26, D1, D27

0x4662c8 STR	D7, [X28, X7]    [3]

0x4662cc B	465f94

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c: 1644 - 1651

--------------------------------------------------------------------------------

1644:                  for(jj1 = A_diag_i[i1]+1; jj1 < A_diag_i[i1+1]; jj1++)

1645:                  {

1646:                    i2 = A_diag_j[jj1];

1647:                    if(P_marker[i2] >= jj_begin_row && (sgn*A_diag_data[jj1]) < 0)

1648:                       P_diag_data[P_marker[i2]] +=

1649:                       distribute*A_diag_data[jj1];

1650:                        if(i2 == i && (sgn*A_diag_data[jj1]) < 0)

1651:                          diagonal += distribute*A_diag_data[jj1];

Coverage (%)	Name	Source Location	Module
►99.08+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.04
CQA speedup if FP arith vectorized	1.36
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.21
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildExtPIInterp._omp_fn.0
Source	par_lr_interp.c:1644-1651
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.88
CQA cycles if no scalar integer	5.33
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	5.44
Front-end cycles	10.88
P0 cycles	9.00
P1 cycles	9.00
P2 cycles	2.92
P3 cycles	2.92
P4 cycles	2.83
P5 cycles	2.83
P6 cycles	2.75
P7 cycles	2.75
P8 cycles	8.00
P9 cycles	8.00
P10 cycles	8.00
P11 cycles	8.00
P12 cycles	8.00
P13 cycles	8.00
P14 cycles	8.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	87.00
Nb uops	87.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	2.21
Nb FLOP add-sub	0.00
Nb FLOP mul	8.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.66
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	2.04
CQA speedup if FP arith vectorized	1.36
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.21
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildExtPIInterp._omp_fn.0
Source	par_lr_interp.c:1644-1651
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.88
CQA cycles if no scalar integer	5.33
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	5.44
Front-end cycles	10.88
P0 cycles	9.00
P1 cycles	9.00
P2 cycles	2.92
P3 cycles	2.92
P4 cycles	2.83
P5 cycles	2.83
P6 cycles	2.75
P7 cycles	2.75
P8 cycles	8.00
P9 cycles	8.00
P10 cycles	8.00
P11 cycles	8.00
P12 cycles	8.00
P13 cycles	8.00
P14 cycles	8.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	87.00
Nb uops	87.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	2.21
Nb FLOP add-sub	0.00
Nb FLOP mul	8.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.66
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildExtPIInterp._omp_fn.0
Source file and lines	par_lr_interp.c:1644-1651
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1644-1651.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 625 paths individually, rerun with max-paths=625
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 625 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.88 to 5.33 cycles (2.04x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 10.88 to 5.44 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 8 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 24 FP arithmetical operations:

8: addition or subtraction (all inside FMA instructions)
16: multiply (8 inside FMA instructions)

The binary loop is loading 160 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

General properties

nb instructions	87
loop length	348
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

10.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	9.00	9.00	2.92	2.92	2.83	2.83	2.75	2.75	8.00	8.00	8.00	8.00	8.00	8.00	8.00	0.00	0.00
cycles	9.00	9.00	2.92	2.92	2.83	2.83	2.75	2.75	8.00	8.00	8.00	8.00	8.00	8.00	8.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.88
Overall L1	10.88

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.88 cycles. At this rate:

15% of peak load performance is reached (14.71 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (2.94 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 465f84

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR D1, [X26, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL D0, D1, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FCMPE D0, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
B.MI 4662bc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2d50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X3, [X12, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X25, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X2, X25	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 4661cc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2c60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D21, [X26, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL D6, D21, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FCMPE D6, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
B.MI 4661bc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2c50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X11, X8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X5, [X12, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X1, [X19, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
CMP X2, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 46619c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2c30>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D19, [X26, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL D30, D19, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FCMPE D30, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
B.MI 46618c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2c20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X8, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X7, [X12, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X3, [X19, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X2, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 46616c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2c00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D27, [X26, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL D7, D27, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FCMPE D7, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
B.MI 46615c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2bf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X3, X8, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP X4, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 465bb8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x264c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X12, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X0, [X19, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X2, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 465efc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2990>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X22, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 465f0c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x29a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D16, [X26, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL D5, D16, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMADD D18, D26, D16, D25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FCMPE D5, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D25, D18, D25, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.25	scal (50.0%)
B 465f0c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x29a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X25, X3, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D16, [X28, X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D5, D26, D27, D16	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D5, [X28, X25]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
CMP X22, X7	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 465f78 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2a0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D18, [X26, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL D21, D18, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMADD D6, D26, D18, D25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FCMPE D21, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D25, D6, D25, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.25	scal (50.0%)
B 465f78 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2a0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X9, X1, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D20, [X28, X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D22, D26, D19, D20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D22, [X28, X9]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
CMP X22, X5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 465f54 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x29e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D23, [X26, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL D1, D23, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMADD D0, D26, D23, D25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FCMPE D1, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D25, D0, D25, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.25	scal (50.0%)
B 465f54 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x29e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X10, X25, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D17, [X28, X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D4, D26, D21, D17	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D4, [X28, X10]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
CMP X22, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 465f30 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x29c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D31, [X26, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL D28, D31, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMADD D29, D26, D31, D25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FCMPE D28, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D25, D29, D25, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.25	scal (50.0%)
B 465f30 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x29c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X7, X0, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D27, [X28, X7]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D7, D26, D1, D27	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D7, [X28, X7]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
B 465f94 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2a28>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_BoomerAMGBuildExtPIInterp._omp_fn.0
Source file and lines	par_lr_interp.c:1644-1651
Module	exec

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 625 paths individually, rerun with max-paths=625
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.88 to 5.33 cycles (2.04x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 8 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 24 FP arithmetical operations:

8: addition or subtraction (all inside FMA instructions)
16: multiply (8 inside FMA instructions)

The binary loop is loading 160 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

General properties

nb instructions	87
loop length	348
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

10.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	9.00	9.00	2.92	2.92	2.83	2.83	2.75	2.75	8.00	8.00	8.00	8.00	8.00	8.00	8.00	0.00	0.00
cycles	9.00	9.00	2.92	2.92	2.83	2.83	2.75	2.75	8.00	8.00	8.00	8.00	8.00	8.00	8.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.88
Overall L1	10.88

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.88 cycles. At this rate:

15% of peak load performance is reached (14.71 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (2.94 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 465f84

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR D1, [X26, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL D0, D1, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FCMPE D0, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
B.MI 4662bc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2d50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X3, [X12, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X25, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X2, X25	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 4661cc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2c60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D21, [X26, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL D6, D21, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FCMPE D6, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
B.MI 4661bc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2c50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X11, X8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X5, [X12, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X1, [X19, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
CMP X2, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 46619c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2c30>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D19, [X26, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL D30, D19, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FCMPE D30, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
B.MI 46618c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2c20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X8, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X7, [X12, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X3, [X19, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X2, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 46616c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2c00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D27, [X26, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL D7, D27, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FCMPE D7, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
B.MI 46615c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2bf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X3, X8, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP X4, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 465bb8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x264c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X12, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X0, [X19, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X2, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 465efc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2990>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X22, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 465f0c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x29a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D16, [X26, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL D5, D16, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMADD D18, D26, D16, D25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FCMPE D5, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D25, D18, D25, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.25	scal (50.0%)
B 465f0c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x29a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X25, X3, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D16, [X28, X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D5, D26, D27, D16	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D5, [X28, X25]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
CMP X22, X7	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 465f78 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2a0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D18, [X26, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL D21, D18, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMADD D6, D26, D18, D25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FCMPE D21, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D25, D6, D25, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.25	scal (50.0%)
B 465f78 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2a0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X9, X1, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D20, [X28, X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D22, D26, D19, D20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D22, [X28, X9]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
CMP X22, X5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 465f54 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x29e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D23, [X26, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL D1, D23, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMADD D0, D26, D23, D25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FCMPE D1, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D25, D0, D25, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.25	scal (50.0%)
B 465f54 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x29e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X10, X25, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D17, [X28, X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D4, D26, D21, D17	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D4, [X28, X10]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
CMP X22, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 465f30 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x29c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D31, [X26, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL D28, D31, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMADD D29, D26, D31, D25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FCMPE D28, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D25, D29, D25, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.25	scal (50.0%)
B 465f30 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x29c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X7, X0, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D27, [X28, X7]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D7, D26, D1, D27	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D7, [X28, X7]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
B 465f94 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2a28>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code