OV - exec - Loop 964

	Loop Id: 964	Module: exec	Source: par_lr_interp.c:1196-1756 [...]	Coverage: 0.02%

  (965) 0x463f30 LDR	X2, [X25, X22,LSL #3]

  (965) 0x463f34 UBFM	X1, X10, #61, #60

  (965) 0x463f38 STR	X2, [X16, X1]

  (965) 0x463f3c STR	D14, [X28, X1]

  (965) 0x463f40 SUB	X30, X30, #1

  (965) 0x463f44 ADD	X9, X9, #8

  (965) 0x463f48 ORR	X22, XZR, X13

  (965) 0x463f4c CMP	X14, X13

  (965) 0x463f50 B.EQ	46467c

  (965) 0x463f54 ADD	X13, X13, #1

  (965) 0x463f58 LDR	X10, [X11, X22,LSL #3]

  (965) 0x463f5c LDR	X27, [X20, X22,LSL #3]

  (965) 0x463f60 STR	X10, [SP, #128]

  (965) 0x463f64 TBZ	X27, #63, 463f30

  (965) 0x463f68 CMN	X27, #3

  (965) 0x463f6c B.EQ	463f40

  (966) 0x463f70 LDR	X4, [SP, #288]

  (966) 0x463f74 SUB	X30, X30, #1

  (966) 0x463f78 LDR	X0, [SP, #128]

  (966) 0x463f7c LDR	X1, [X15, X22,LSL #3]

  (966) 0x463f80 LDR	X27, [X4, X22,LSL #3]

  (966) 0x463f84 STR	X0, [SP, #144]

  (966) 0x463f88 LDR	X2, [X15, X9]

  (966) 0x463f8c ORR	X4, XZR, X27

  (966) 0x463f90 CMP	X1, X2

  (966) 0x463f94 B.GE	464098

  (966) 0x463f98 ORR	X3, XZR, X0

  (966) 0x463f9c LDR	X0, [SP, #144]

  (966) 0x463fa0 ORR	X18, XZR, X14

  (966) 0x463fa4 STR	X11, [SP, #120]

  (966) 0x463fa8 STR	X12, [SP, #192]

  (966) 0x463fac LDP	X12, X10, [SP, #208]

  (966) 0x463fb0 B	463fe8

    (973) 0x463fb4 LDR	X14, [X19, X6]

    (973) 0x463fb8 CMP	X3, X14

    (973) 0x463fbc B.LE	463fdc

    (973) 0x463fc0 STR	X0, [X19, X6]

    (973) 0x463fc4 UBFM	X11, X0, #61, #60

    (973) 0x463fc8 ADD	X0, X0, #1

    (973) 0x463fcc LDR	X6, [X25, X6]

    (973) 0x463fd0 STR	X6, [X16, X11]

    (973) 0x463fd4 LDR	X2, [X15, X9]

    (973) 0x463fd8 STR	D15, [X28, X11]

    (973) 0x463fdc ADD	X1, X1, #1

    (973) 0x463fe0 CMP	X1, X2

    (973) 0x463fe4 B.GE	464088

    (973) 0x463fe8 LDR	X11, [X21, X1,LSL #3]

    (973) 0x463fec UBFM	X6, X11, #61, #60

    (973) 0x463ff0 LDR	X14, [X20, X6]

    (973) 0x463ff4 TBZ	X14, #63, 463fb4

    (973) 0x463ff8 CMN	X14, #3

    (973) 0x463ffc B.EQ	463fdc

    (973) 0x464000 ADD	X7, X6, #8

    (973) 0x464004 STR	X30, [X19, X6]

    (973) 0x464008 LDR	X5, [X15, X6]

    (973) 0x46400c ADD	X24, X15, X7

    (973) 0x464010 LDR	X8, [X15, X7]

    (973) 0x464014 CMP	X5, X8

    (973) 0x464018 B.GE	464068

    (973) 0x46401c STR	X1, [SP, #112]

      (976) 0x464020 LDR	X1, [X21, X5,LSL #3]

      (976) 0x464024 ADD	X5, X5, #1

      (976) 0x464028 UBFM	X2, X1, #61, #60

      (976) 0x46402c LDR	X11, [X20, X2]

      (976) 0x464030 TBNZ	X11, #63, 46405c

      (976) 0x464034 LDR	X1, [X19, X2]

      (976) 0x464038 UBFM	X14, X0, #61, #60

      (976) 0x46403c CMP	X3, X1

      (976) 0x464040 B.LE	46405c

      (976) 0x464044 STR	X0, [X19, X2]

      (976) 0x464048 ADD	X0, X0, #1

      (976) 0x46404c LDR	X8, [X25, X2]

      (976) 0x464050 STR	X8, [X16, X14]

      (976) 0x464054 LDR	X8, [X24]

      (976) 0x464058 STR	D15, [X28, X14]

      (976) 0x46405c CMP	X5, X8

      (976) 0x464060 B.LT	464020

    (973) 0x464064 LDR	X1, [SP, #112]

    (973) 0x464068 LDR	X24, [SP, #168]

    (973) 0x46406c LDR	X5, [X24]

    (973) 0x464070 CMP	X5, #1

    (973) 0x464074 B.GT	4645e0

    (973) 0x464078 LDR	X2, [X15, X9]

    (973) 0x46407c ADD	X1, X1, #1

    (973) 0x464080 CMP	X1, X2

    (973) 0x464084 B.LT	463fe8

  (966) 0x464088 LDR	X11, [SP, #120]

  (966) 0x46408c ORR	X14, XZR, X18

  (966) 0x464090 STR	X0, [SP, #144]

  (966) 0x464094 LDR	X12, [SP, #192]

  (966) 0x464098 LDR	X1, [SP, #168]

  (966) 0x46409c LDR	X7, [X1]

  (966) 0x4640a0 STR	X7, [SP, #192]

  (966) 0x4640a4 CMP	X7, #1

  (966) 0x4640a8 B.GT	465110

  (966) 0x4640ac LDR	X18, [SP, #224]

  (966) 0x4640b0 LDR	X0, [X18, X22,LSL #3]

  (966) 0x4640b4 LDR	X18, [X18, X9]

  (966) 0x4640b8 ADD	X3, X0, #1

  (966) 0x4640bc LDR	D25, [X26, X0,LSL #3]

  (966) 0x4640c0 CMP	X3, X18

  (966) 0x4640c4 B.GE	464194

  (968) 0x4640c8 LDR	X2, [SP, #128]

  (968) 0x4640cc ORR	X24, XZR, X4

  (968) 0x4640d0 STR	X3, [SP, #112]

  (968) 0x4640d4 LDR	X6, [SP, #232]

  (968) 0x4640d8 STP	X14, X25, [SP, #248]

  (968) 0x4640dc ORR	X14, XZR, X11

  (968) 0x4640e0 STR	X9, [SP, #264]

  (968) 0x4640e4 B	464114

  (967) 0x4640e8 LDR	X8, [SP, #112]

  (967) 0x4640ec UBFM	X3, X7, #61, #60

  (967) 0x4640f0 LDR	D24, [X28, X3]

  (967) 0x4640f4 LDR	D26, [X26, X8,LSL #3]

  (967) 0x4640f8 FADD	D28, D24, D26

  (967) 0x4640fc STR	D28, [X28, X3]

  (967) 0x464100 LDR	X10, [SP, #112]

  (967) 0x464104 ADD	X4, X10, #1

  (967) 0x464108 STR	X4, [SP, #112]

  (967) 0x46410c CMP	X4, X18

  (967) 0x464110 B.EQ	464184

    (969) 0x464114 LDR	X25, [SP, #112]

    (969) 0x464118 LDR	X4, [X12, X25,LSL #3]

    (969) 0x46411c UBFM	X9, X4, #61, #60

    (969) 0x464120 LDR	X7, [X19, X9]

    (969) 0x464124 STR	X9, [SP, #120]

    (969) 0x464128 CMP	X2, X7

    (969) 0x46412c B.LE	4640e8

    (969) 0x464130 CMP	X7, X30

    (969) 0x464134 B.EQ	4646b4

    (969) 0x464138 LDR	X8, [X20, X9]

    (969) 0x46413c CMN	X8, #3

    (969) 0x464140 B.EQ	464100

    (969) 0x464144 LDR	X11, [SP, #152]

    (969) 0x464148 CMP	X11, #1

    (969) 0x46414c B.EQ	464164

    (969) 0x464150 LDR	X10, [SP, #120]

    (969) 0x464154 LDR	X1, [X6, X22,LSL #3]

    (969) 0x464158 LDR	X5, [X6, X10]

    (969) 0x46415c CMP	X1, X5

    (969) 0x464160 B.NE	464100

    (969) 0x464164 LDR	X0, [SP, #112]

    (969) 0x464168 LDR	X10, [SP, #112]

    (969) 0x46416c LDR	D4, [X26, X0,LSL #3]

    (969) 0x464170 ADD	X4, X10, #1

    (969) 0x464174 STR	X4, [SP, #112]

    (969) 0x464178 FADD	D25, D25, D4

    (969) 0x46417c CMP	X4, X18

    (969) 0x464180 B.NE	464114

    (970) 0x464184 LDR	X9, [SP, #264]

    (970) 0x464188 ORR	X11, XZR, X14

    (970) 0x46418c ORR	X4, XZR, X24

    (970) 0x464190 LDP	X14, X25, [SP, #248]

  (966) 0x464194 LDR	X2, [SP, #192]

  (966) 0x464198 CMP	X2, #1

  (966) 0x46419c B.GT	465008

0x4641a0 FCMP	D25, #0

0x4641a4 B.EQ	463f40

0x4641a8 LDR	X22, [SP, #128]

0x4641ac LDR	X2, [SP, #144]

0x4641b0 CMP	X2, X22

0x4641b4 B.LE	464324

0x4641b8 LDR	X6, [SP, #128]

0x4641bc FMOV	D19, #1.0000000

0x4641c0 FDIV	D20, D19, D25

0x4641c4 SUB	X8, X2, X6

0x4641c8 SUB	X7, X8, #1

0x4641cc CMP	X7, #2

0x4641d0 B.LS	46680c

0x4641d4 UBFM	X24, X8, #2, #63

0x4641d8 ADD	X1, X28, X6,LSL #3

0x4641dc UBFM	X18, X6, #61, #60

0x4641e0 DUP	V30.2D, V20.D[0]

0x4641e4 UBFM	X0, X24, #59, #58

0x4641e8 SUB	X3, X0, #32

0x4641ec ADD	X22, X1, X24,LSL #5

0x4641f0 UBFM	X2, X3, #5, #63

0x4641f4 ADD	X5, X2, #1

0x4641f8 ANDS	X6, X5, #4160

0x4641fc B.EQ	46426c

0x464200 CMP	X6, #1

0x464204 B.EQ	46424c

0x464208 CMP	X6, #2

0x46420c B.EQ	464234

0x464210 LDR	Q22, [X28, X18]

0x464214 ADD	X1, X1, #32

0x464218 LDUR	Q0, [X1, #496]

0x46421c FMUL	V23.2D, V22.2D, V30.2D

0x464220 FMUL	V27.2D, V0.2D, V30.2D

0x464224 FNEG	V1.2D, V23.2D

0x464228 FNEG	V7.2D, V27.2D

0x46422c STR	Q1, [X28, X18]

0x464230 STUR	Q7, [X1, #496]

0x464234 LDP	Q5, Q18, [X1]

0x464238 FMUL	V21.2D, V5.2D, V30.2D

0x46423c FMUL	V6.2D, V18.2D, V30.2D

0x464240 FNEG	V17.2D, V21.2D

0x464244 FNEG	V4.2D, V6.2D

0x464248 STP	Q17, Q4, [X1], #32

0x46424c LDP	Q31, Q24, [X1]

0x464250 FMUL	V26.2D, V31.2D, V30.2D

0x464254 FMUL	V16.2D, V24.2D, V30.2D

0x464258 FNEG	V28.2D, V26.2D

0x46425c FNEG	V29.2D, V16.2D

0x464260 STP	Q28, Q29, [X1], #32

0x464264 CMP	X22, X1

0x464268 B.EQ	4642e0

  (978) 0x46426c LDP	Q19, Q22, [X1]

  (978) 0x464270 ORR	X7, XZR, X1

  (978) 0x464274 LDP	Q7, Q5, [X1, #32]

  (978) 0x464278 LDP	Q4, Q31, [X1, #64]

  (978) 0x46427c FMUL	V23.2D, V19.2D, V30.2D

  (978) 0x464280 LDP	Q29, Q19, [X1, #96]

  (978) 0x464284 ADD	X1, X1, #128

  (978) 0x464288 FMUL	V1.2D, V22.2D, V30.2D

  (978) 0x46428c FMUL	V18.2D, V7.2D, V30.2D

  (978) 0x464290 FMUL	V6.2D, V5.2D, V30.2D

  (978) 0x464294 FMUL	V24.2D, V4.2D, V30.2D

  (978) 0x464298 FMUL	V16.2D, V31.2D, V30.2D

  (978) 0x46429c FNEG	V0.2D, V23.2D

  (978) 0x4642a0 FNEG	V27.2D, V1.2D

  (978) 0x4642a4 FNEG	V21.2D, V18.2D

  (978) 0x4642a8 FNEG	V17.2D, V6.2D

  (978) 0x4642ac FMUL	V22.2D, V29.2D, V30.2D

  (978) 0x4642b0 FMUL	V23.2D, V19.2D, V30.2D

  (978) 0x4642b4 FNEG	V26.2D, V24.2D

  (978) 0x4642b8 FNEG	V28.2D, V16.2D

  (978) 0x4642bc STP	Q0, Q27, [X1, #1920]

  (978) 0x4642c0 FNEG	V1.2D, V22.2D

  (978) 0x4642c4 FNEG	V0.2D, V23.2D

  (978) 0x4642c8 STP	Q21, Q17, [X1, #1952]

  (978) 0x4642cc STP	Q26, Q28, [X1, #1984]

  (978) 0x4642d0 STUR	Q1, [X1, #480]

  (978) 0x4642d4 STR	Q0, [X7, #112]

  (978) 0x4642d8 CMP	X22, X1

  (978) 0x4642dc B.NE	46426c

0x4642e0 AND	X10, X8, #8062

0x4642e4 ANDS	XZR, X8, #4160

0x4642e8 B.EQ	464324

0x4642ec LDR	X18, [SP, #128]

0x4642f0 SUB	X8, X8, X10

0x4642f4 DUP	Z20.D, Z20.D[0]

0x4642f8 WHILELO	P4.D, XZR, X8

0x4642fc PTRUE	P7.B, VL16

0x464300 MOVZ	X24, #2

0x464304 WHILELO	P5.D, X24, X8

0x464308 ADD	X0, X18, X10

0x46430c LD1D	{Z30.D}, P4/Z, [X28, X0,LSL #3]

0x464310 FMUL	Z27.D, Z20.D, Z30.D

0x464314 FNEG	Z27.D, P7/M, Z27.D

0x464318 ADD	X10, X28, X0,LSL #3

0x46431c ST1D	{Z27.D}, P4, [X10, MUL VL]

0x464320 B.NE	4660c8

0x464324 CMP	X4, X27

0x464328 B.LE	463f40

0x46432c SUB	X22, X4, X27

0x464330 LDR	X4, [SP, #176]

0x464334 FMOV	D18, #1.0000000

0x464338 SUB	X3, X22, #1

0x46433c FDIV	D25, D18, D25

0x464340 LDR	X6, [X4, #200]

0x464344 CMP	X3, #2

0x464348 B.LS	4667f8

0x46434c UBFM	X2, X22, #2, #63

0x464350 ADD	X0, X6, X27,LSL #3

0x464354 DUP	V21.2D, V25.D[0]

0x464358 UBFM	X1, X27, #61, #60

0x46435c UBFM	X7, X2, #59, #58

0x464360 SUB	X24, X7, #32

0x464364 ADD	X18, X0, X2,LSL #5

0x464368 UBFM	X8, X24, #5, #63

0x46436c ADD	X10, X8, #1

0x464370 ANDS	X4, X10, #4160

0x464374 B.EQ	4643e4

0x464378 CMP	X4, #1

0x46437c B.EQ	4643c4

0x464380 CMP	X4, #2

0x464384 B.EQ	4643ac

0x464388 LDR	Q6, [X6, X1]

0x46438c ADD	X0, X0, #32

0x464390 LDUR	Q31, [X0, #496]

0x464394 FMUL	V17.2D, V6.2D, V21.2D

0x464398 FMUL	V24.2D, V31.2D, V21.2D

0x46439c FNEG	V4.2D, V17.2D

0x4643a0 FNEG	V26.2D, V24.2D

0x4643a4 STR	Q4, [X6, X1]

0x4643a8 STUR	Q26, [X0, #496]

0x4643ac LDP	Q16, Q28, [X0]

0x4643b0 FMUL	V19.2D, V16.2D, V21.2D

0x4643b4 FMUL	V29.2D, V28.2D, V21.2D

0x4643b8 FNEG	V22.2D, V19.2D

0x4643bc FNEG	V23.2D, V29.2D

0x4643c0 STP	Q22, Q23, [X0], #32

0x4643c4 LDP	Q1, Q0, [X0]

0x4643c8 FMUL	V20.2D, V1.2D, V21.2D

0x4643cc FMUL	V30.2D, V0.2D, V21.2D

0x4643d0 FNEG	V27.2D, V20.2D

0x4643d4 FNEG	V7.2D, V30.2D

0x4643d8 STP	Q27, Q7, [X0], #32

0x4643dc CMP	X18, X0

0x4643e0 B.EQ	464458

  (977) 0x4643e4 LDP	Q5, Q18, [X0]

  (977) 0x4643e8 ORR	X3, XZR, X0

  (977) 0x4643ec LDP	Q24, Q26, [X0, #32]

  (977) 0x4643f0 LDP	Q22, Q23, [X0, #64]

  (977) 0x4643f4 LDP	Q27, Q7, [X0, #96]

  (977) 0x4643f8 ADD	X0, X0, #128

  (977) 0x4643fc FMUL	V6.2D, V5.2D, V21.2D

  (977) 0x464400 FMUL	V17.2D, V18.2D, V21.2D

  (977) 0x464404 FMUL	V16.2D, V24.2D, V21.2D

  (977) 0x464408 FMUL	V19.2D, V26.2D, V21.2D

  (977) 0x46440c FMUL	V1.2D, V22.2D, V21.2D

  (977) 0x464410 FMUL	V20.2D, V23.2D, V21.2D

  (977) 0x464414 FMUL	V5.2D, V27.2D, V21.2D

  (977) 0x464418 FMUL	V18.2D, V7.2D, V21.2D

  (977) 0x46441c FNEG	V4.2D, V6.2D

  (977) 0x464420 FNEG	V31.2D, V17.2D

  (977) 0x464424 FNEG	V28.2D, V16.2D

  (977) 0x464428 FNEG	V29.2D, V19.2D

  (977) 0x46442c FNEG	V0.2D, V1.2D

  (977) 0x464430 FNEG	V30.2D, V20.2D

  (977) 0x464434 FNEG	V6.2D, V5.2D

  (977) 0x464438 FNEG	V17.2D, V18.2D

  (977) 0x46443c STP	Q4, Q31, [X0, #1920]

  (977) 0x464440 STP	Q28, Q29, [X0, #1952]

  (977) 0x464444 STP	Q0, Q30, [X0, #1984]

  (977) 0x464448 STUR	Q6, [X0, #480]

  (977) 0x46444c STR	Q17, [X3, #112]

  (977) 0x464450 CMP	X18, X0

  (977) 0x464454 B.NE	4643e4

0x464458 AND	X5, X22, #8062

0x46445c ANDS	XZR, X22, #4160

0x464460 B.EQ	463f40

0x464464 ADD	X27, X27, X5

0x464468 SUB	X22, X22, X5

0x46446c DUP	Z25.D, Z25.D[0]

0x464470 WHILELO	P0.D, XZR, X22

0x464474 PTRUE	P1.B, VL16

0x464478 LD1D	{Z21.D}, P0/Z, [X6, X27,LSL #3]

0x46447c ADD	X6, X6, X27,LSL #3

0x464480 FMUL	Z4.D, Z21.D, Z25.D

0x464484 FNEG	Z4.D, P1/M, Z4.D

0x464488 ST1D	{Z4.D}, P0, [X6, MUL VL]

0x46448c MOVZ	X5, #2

0x464490 WHILELO	P6.D, X5, X22

0x464494 B.EQ	463f40

0x464498 LD1D	{Z31.D}, P6/Z, [X6, #1, MUL VL]

0x46449c FMUL	Z24.D, Z31.D, Z25.D

0x4644a0 FNEG	Z24.D, P1/M, Z24.D

0x4644a4 ST1D	{Z24.D}, P6, [X6, #1, MUL VL]

0x4644a8 B	463f40

    (973) 0x4645e0 LDR	X14, [SP, #160]

    (973) 0x4645e4 LDR	X2, [X14, X6]

    (973) 0x4645e8 ADD	X6, X14, X7

    (973) 0x4645ec LDR	X7, [X14, X7]

    (973) 0x4645f0 CMP	X2, X7

    (973) 0x4645f4 B.GE	464078

    (973) 0x4645f8 LDR	X11, [SP, #176]

    (973) 0x4645fc LDR	X8, [X11, #200]

    (973) 0x464600 LDR	X24, [X11, #240]

    (973) 0x464604 LDR	X14, [X11, #216]

    (973) 0x464608 STR	X8, [SP, #112]

    (973) 0x46460c LDR	X11, [X24]

    (973) 0x464610 CBZ	X10, 4659d8

    (973) 0x464614 STR	X19, [SP, #144]

    (973) 0x464618 ORR	X19, XZR, X18

    (973) 0x46461c STR	X0, [SP, #248]

      (975) 0x464620 LDR	X18, [X12, X2,LSL #3]

      (975) 0x464624 ADD	X2, X2, #1

      (975) 0x464628 LDR	X8, [X10, X18,LSL #3]

      (975) 0x46462c UBFM	X5, X8, #61, #60

      (975) 0x464630 LDR	X0, [X11, X5]

      (975) 0x464634 TBNZ	X0, #63, 464660

      (975) 0x464638 LDR	X18, [X23, X5]

      (975) 0x46463c UBFM	X24, X4, #61, #60

      (975) 0x464640 CMP	X27, X18

      (975) 0x464644 B.LE	464660

      (975) 0x464648 STR	X4, [X23, X5]

      (975) 0x46464c ADD	X4, X4, #1

      (975) 0x464650 STR	X8, [X14, X24]

      (975) 0x464654 LDR	X8, [SP, #112]

      (975) 0x464658 LDR	X7, [X6]

      (975) 0x46465c STR	D15, [X8, X24]

      (975) 0x464660 CMP	X7, X2

      (975) 0x464664 B.GT	464620

    (973) 0x464668 LDR	X2, [X15, X9]

    (973) 0x46466c ORR	X18, XZR, X19

    (973) 0x464670 LDR	X19, [SP, #144]

    (973) 0x464674 LDR	X0, [SP, #248]

    (973) 0x464678 B	46407c

0x46467c LDR	X27, [SP, #176]

0x464680 LDR	X20, [SP, #136]

0x464684 CBNZ	X20, 4653e4

0x464688 LDR	X13, [X27, #304]

0x46468c LDR	X16, [X13]

0x464690 CBNZ	X16, 4653a0

0x464694 LDP	D14, D15, [SP, #96]

0x464698 LDP	X19, X20, [SP, #16]

0x46469c LDP	X21, X22, [SP, #32]

0x4646a0 LDP	X23, X24, [SP, #48]

0x4646a4 LDP	X25, X26, [SP, #64]

0x4646a8 LDP	X27, X28, [SP, #80]

0x4646ac LDP	X29, X30, [SP], #384

0x4646b0 RET

  (968) 0x4646b4 LDR	X25, [SP, #224]

  (968) 0x4646b8 ADD	X11, X9, #8

  (968) 0x4646bc STR	X11, [SP, #312]

  (968) 0x4646c0 LDR	X8, [X25, X9]

  (968) 0x4646c4 LDR	X4, [X25, X11]

  (968) 0x4646c8 UBFM	X7, X8, #61, #60

  (968) 0x4646cc ADD	X9, X8, #1

  (968) 0x4646d0 LDR	D5, [X26, X7]

  (968) 0x4646d4 FCMPE	D5, #0

  (968) 0x4646d8 FCSEL	D24, D2, D3, #4

  (968) 0x4646dc CMP	X9, X4

  (968) 0x4646e0 B.GE	46628c

0x4646e4 SUB	X5, X4, X8

0x4646e8 SUB	X0, X5, #2

0x4646ec SUB	X10, X5, #1

0x4646f0 CMP	X0, #7

0x4646f4 B.LS	4662b0

0x4646f8 ADD	X25, X7, #8

0x4646fc UBFM	X1, X10, #2, #63

0x464700 DUP	Z6.D, #0

0x464704 DUP	Z7.D, X22

0x464708 ORR	Z26.D, Z6.D, Z6.D

0x46470c ADD	X7, X26, X7

0x464710 ADD	X8, X12, X25

0x464714 DUP	Z16.D, X2

0x464718 DUP	Z17.D, Z24.D[0]

0x46471c PTRUE	P7.B, VL16

0x464720 ADD	X11, X7, #8

0x464724 ADD	X25, X8, X1,LSL #5

0x464728 ORR	X3, XZR, X8

0x46472c ADD	X7, X7, #24

0x464730 TBZ	W1, #0, 46478c

0x464734 LD1D	{Z18.D}, P7/Z, [X8, MUL VL]

0x464738 LD1D	{Z19.D}, P7/Z, [X8, #1, MUL VL]

0x46473c LD1D	{Z20.D}, P7/Z, [X19, Z18.D,LSL #3]

0x464740 CMPEQ	P5.D, P7/Z, Z18.D, Z7.D

0x464744 CMPGE	P14.D, P7/Z, Z20.D, Z16.D

0x464748 LD1D	{Z21.D}, P7/Z, [X19, Z19.D,LSL #3]

0x46474c CMPEQ	P6.D, P7/Z, Z19.D, Z7.D

0x464750 CMPGE	P15.D, P7/Z, Z21.D, Z16.D

0x464754 ADD	X3, X8, #32

0x464758 ORR	P0.B, P7/Z, P5.B, P14.B

0x46475c ORR	P1.B, P7/Z, P6.B, P15.B

0x464760 LD1D	{Z22.D}, P0/Z, [X11, MUL VL]

0x464764 LD1D	{Z23.D}, P1/Z, [X7, MUL VL]

0x464768 FMUL	Z1.D, Z22.D, Z17.D

0x46476c FMUL	Z0.D, Z23.D, Z17.D

0x464770 FCMLT	P2.D, P0/Z, Z1.D, #0

0x464774 FCMLT	P3.D, P1/Z, Z0.D, #0

0x464778 MOVPRFX	Z26, Z6

0x46477c FADD	Z26.D, P2/M, Z26.D, Z22.D

0x464780 FADD	Z6.D, P3/M, Z6.D, Z23.D

0x464784 CMP	X3, X25

0x464788 B.EQ	464844

  (985) 0x46478c ADD	X5, X3, #32

  (985) 0x464790 LD1D	{Z27.D}, P7/Z, [X3, #1, MUL VL]

  (985) 0x464794 SUB	X1, X3, X8

  (985) 0x464798 LD1D	{Z28.D}, P7/Z, [X3, #3, MUL VL]

  (985) 0x46479c LD1D	{Z30.D}, P7/Z, [X3, MUL VL]

  (985) 0x4647a0 SUB	X0, X5, X8

  (985) 0x4647a4 LD1D	{Z4.D}, P7/Z, [X3, #2, MUL VL]

  (985) 0x4647a8 LD1D	{Z31.D}, P7/Z, [X19, Z27.D,LSL #3]

  (985) 0x4647ac CMPEQ	P4.D, P7/Z, Z28.D, Z7.D

  (985) 0x4647b0 CMPEQ	P8.D, P7/Z, Z27.D, Z7.D

  (985) 0x4647b4 ADD	X5, X7, X0

  (985) 0x4647b8 LD1D	{Z29.D}, P7/Z, [X19, Z28.D,LSL #3]

  (985) 0x4647bc CMPGE	P13.D, P7/Z, Z31.D, Z16.D

  (985) 0x4647c0 CMPGE	P12.D, P7/Z, Z29.D, Z16.D

  (985) 0x4647c4 LD1D	{Z5.D}, P7/Z, [X19, Z30.D,LSL #3]

  (985) 0x4647c8 ORR	P5.B, P7/Z, P4.B, P12.B

  (985) 0x4647cc CMPEQ	P9.D, P7/Z, Z30.D, Z7.D

  (985) 0x4647d0 CMPGE	P10.D, P7/Z, Z5.D, Z16.D

  (985) 0x4647d4 LD1D	{Z18.D}, P7/Z, [X19, Z4.D,LSL #3]

  (985) 0x4647d8 CMPEQ	P11.D, P7/Z, Z4.D, Z7.D

  (985) 0x4647dc CMPGE	P14.D, P7/Z, Z18.D, Z16.D

  (985) 0x4647e0 ADD	X3, X3, #64

  (985) 0x4647e4 LD1D	{Z19.D}, P5/Z, [X5, MUL VL]

  (985) 0x4647e8 ORR	P6.B, P7/Z, P8.B, P13.B

  (985) 0x4647ec ADD	X5, X7, X1

  (985) 0x4647f0 ORR	P1.B, P7/Z, P9.B, P10.B

  (985) 0x4647f4 LD1D	{Z21.D}, P6/Z, [X5, MUL VL]

  (985) 0x4647f8 ORR	P4.B, P7/Z, P11.B, P14.B

  (985) 0x4647fc ADD	X0, X11, X0

  (985) 0x464800 ADD	X1, X11, X1

  (985) 0x464804 LD1D	{Z0.D}, P4/Z, [X0, MUL VL]

  (985) 0x464808 LD1D	{Z23.D}, P1/Z, [X1, MUL VL]

  (985) 0x46480c FMUL	Z20.D, Z19.D, Z17.D

  (985) 0x464810 FMUL	Z22.D, Z21.D, Z17.D

  (985) 0x464814 FCMLT	P0.D, P5/Z, Z20.D, #0

  (985) 0x464818 FCMLT	P2.D, P6/Z, Z22.D, #0

  (985) 0x46481c FMUL	Z1.D, Z23.D, Z17.D

  (985) 0x464820 FADD	Z6.D, P2/M, Z6.D, Z21.D

  (985) 0x464824 FCMLT	P3.D, P1/Z, Z1.D, #0

  (985) 0x464828 FMUL	Z27.D, Z0.D, Z17.D

  (985) 0x46482c FADD	Z26.D, P3/M, Z26.D, Z23.D

  (985) 0x464830 FCMLT	P5.D, P4/Z, Z27.D, #0

  (985) 0x464834 FADD	Z6.D, P0/M, Z6.D, Z19.D

  (985) 0x464838 FADD	Z26.D, P5/M, Z26.D, Z0.D

  (985) 0x46483c CMP	X3, X25

  (985) 0x464840 B.NE	46478c

0x464844 AND	X8, X10, #8062

0x464848 FADD	Z6.D, Z26.D, Z6.D

0x46484c FADDV	D7, P7, Z6.D

0x464850 FADD	D31, D15, D7

0x464854 ADD	X3, X8, X9

0x464858 ANDS	XZR, X10, #4160

0x46485c B.EQ	464a14

0x464860 UBFM	X25, X3, #61, #60

0x464864 LDR	X10, [X12, X25]

0x464868 LDR	X11, [X19, X10,LSL #3]

0x46486c CMP	X2, X11

0x464870 CCMP	X10, X22, #4, #12

0x464874 B.NE	46488c

0x464878 LDR	D16, [X26, X25]

0x46487c FMUL	D17, D16, D24

0x464880 FADD	D26, D31, D16

0x464884 FCMPE	D17, #0

0x464888 FCSEL	D31, D26, D31, #4

0x46488c ADD	X7, X3, #1

0x464890 CMP	X7, X4

0x464894 B.GE	464a14

0x464898 ADD	X0, X25, #8

0x46489c LDR	X5, [X12, X0]

0x4648a0 LDR	X1, [X19, X5,LSL #3]

0x4648a4 CMP	X2, X1

0x4648a8 CCMP	X22, X5, #4, #12

0x4648ac B.NE	4648c4

0x4648b0 LDR	D28, [X26, X0]

0x4648b4 FMUL	D29, D28, D24

0x4648b8 FADD	D30, D31, D28

0x4648bc FCMPE	D29, #0

0x4648c0 FCSEL	D31, D30, D31, #4

0x4648c4 ADD	X8, X3, #2

0x4648c8 CMP	X4, X8

0x4648cc B.LE	464a14

0x4648d0 ADD	X11, X25, #16

0x4648d4 LDR	X7, [X12, X11]

0x4648d8 LDR	X10, [X19, X7,LSL #3]

0x4648dc CMP	X2, X10

0x4648e0 CCMP	X7, X22, #4, #12

0x4648e4 B.NE	4648fc

0x4648e8 LDR	D4, [X26, X11]

0x4648ec FMUL	D5, D4, D24

0x4648f0 FADD	D18, D31, D4

0x4648f4 FCMPE	D5, #0

0x4648f8 FCSEL	D31, D18, D31, #4

0x4648fc ADD	X0, X3, #3

0x464900 CMP	X4, X0

0x464904 B.LE	464a14

0x464908 ADD	X5, X25, #24

0x46490c LDR	X1, [X12, X5]

0x464910 LDR	X8, [X19, X1,LSL #3]

0x464914 CMP	X2, X8

0x464918 CCMP	X22, X1, #4, #12

0x46491c B.NE	464934

0x464920 LDR	D19, [X26, X5]

0x464924 FMUL	D20, D19, D24

0x464928 FADD	D21, D31, D19

0x46492c FCMPE	D20, #0

0x464930 FCSEL	D31, D21, D31, #4

0x464934 ADD	X11, X3, #4

0x464938 CMP	X4, X11

0x46493c B.LE	464a14

0x464940 ADD	X0, X25, #32

0x464944 LDR	X7, [X12, X0]

0x464948 LDR	X10, [X19, X7,LSL #3]

0x46494c CMP	X2, X10

0x464950 CCMP	X22, X7, #4, #12

0x464954 B.NE	46496c

0x464958 LDR	D22, [X26, X0]

0x46495c FMUL	D23, D22, D24

0x464960 FADD	D1, D31, D22

0x464964 FCMPE	D23, #0

0x464968 FCSEL	D31, D1, D31, #4

0x46496c ADD	X5, X3, #5

0x464970 CMP	X4, X5

0x464974 B.LE	464a14

0x464978 ADD	X1, X25, #40

0x46497c LDR	X8, [X12, X1]

0x464980 LDR	X11, [X19, X8,LSL #3]

0x464984 CMP	X2, X11

0x464988 CCMP	X22, X8, #4, #12

0x46498c B.NE	4649a4

0x464990 LDR	D0, [X26, X1]

0x464994 FMUL	D27, D0, D24

0x464998 FADD	D6, D31, D0

0x46499c FCMPE	D27, #0

0x4649a0 FCSEL	D31, D6, D31, #4

0x4649a4 ADD	X0, X3, #6

0x4649a8 CMP	X4, X0

0x4649ac B.LE	464a14

0x4649b0 ADD	X5, X25, #48

0x4649b4 LDR	X7, [X12, X5]

0x4649b8 LDR	X10, [X19, X7,LSL #3]

0x4649bc CMP	X2, X10

0x4649c0 CCMP	X22, X7, #4, #12

0x4649c4 B.NE	4649dc

0x4649c8 LDR	D7, [X26, X5]

0x4649cc FMUL	D16, D7, D24

0x4649d0 FADD	D17, D31, D7

0x4649d4 FCMPE	D16, #0

0x4649d8 FCSEL	D31, D17, D31, #4

0x4649dc ADD	X3, X3, #7

0x4649e0 CMP	X4, X3

0x4649e4 B.LE	464a14

0x4649e8 ADD	X25, X25, #56

0x4649ec LDR	X1, [X12, X25]

0x4649f0 LDR	X8, [X19, X1,LSL #3]

0x4649f4 CMP	X2, X8

0x4649f8 CCMP	X22, X1, #4, #12

0x4649fc B.NE	464a14

0x464a00 LDR	D26, [X26, X25]

0x464a04 FMUL	D28, D24, D26

0x464a08 FADD	D29, D31, D26

0x464a0c FCMPE	D28, #0

0x464a10 FCSEL	D31, D29, D31, #4

0x464a14 LDR	X11, [SP, #112]

0x464a18 LDR	X0, [SP, #192]

0x464a1c LDR	D4, [X26, X11,LSL #3]

0x464a20 CMP	X0, #1

0x464a24 B.GT	4656a0

0x464a28 FCMP	D31, #0

0x464a2c B.NE	465adc

0x464a30 FADD	D25, D25, D4

0x464a34 B	464100

0x465008 LDR	X6, [SP, #320]

0x46500c LDR	X18, [X6, X22,LSL #3]

0x465010 LDR	X5, [X6, X9]

0x465014 CMP	X5, X18

0x465018 B.LE	4641a0

0x46501c LDR	X0, [SP, #176]

0x465020 ORR	X24, XZR, X11

0x465024 STR	X25, [SP, #192]

0x465028 ORR	X25, XZR, X4

0x46502c LDR	X10, [SP, #240]

0x465030 LDR	X11, [SP, #280]

0x465034 LDR	X3, [X0, #256]

0x465038 LDR	X7, [X0, #200]

0x46503c LDR	X1, [X0, #240]

0x465040 LDR	X0, [X3]

0x465044 LDR	X2, [SP, #296]

0x465048 LDR	X6, [X1]

0x46504c STP	X18, X14, [SP, #112]

0x465050 LDP	X8, X14, [SP, #336]

0x465054 STP	X12, X9, [SP, #248]

0x465058 ORR	X12, XZR, X0

0x46505c B	46508c

  (979) 0x465060 LDR	X9, [SP, #112]

  (979) 0x465064 UBFM	X18, X1, #61, #60

  (979) 0x465068 LDR	D16, [X7, X18]

  (979) 0x46506c LDR	D28, [X11, X9,LSL #3]

  (979) 0x465070 FADD	D29, D16, D28

  (979) 0x465074 STR	D29, [X7, X18]

  (979) 0x465078 LDR	X0, [SP, #112]

  (979) 0x46507c ADD	X3, X0, #1

  (979) 0x465080 STR	X3, [SP, #112]

  (979) 0x465084 CMP	X5, X3

  (979) 0x465088 B.EQ	4650f8

  (979) 0x46508c LDR	X9, [SP, #112]

  (979) 0x465090 LDR	X4, [X17, X9,LSL #3]

  (979) 0x465094 UBFM	X18, X4, #61, #60

  (979) 0x465098 LDR	X1, [X23, X18]

  (979) 0x46509c CMP	X27, X1

  (979) 0x4650a0 B.LE	465060

  (979) 0x4650a4 CMP	X1, X30

  (979) 0x4650a8 B.EQ	4653f0

  (979) 0x4650ac LDR	X3, [X6, X18]

  (979) 0x4650b0 CMN	X3, #3

  (979) 0x4650b4 B.EQ	465078

  (979) 0x4650b8 LDR	X0, [SP, #152]

  (979) 0x4650bc CMP	X0, #1

  (979) 0x4650c0 B.EQ	4650d8

  (979) 0x4650c4 LDR	X4, [SP, #232]

  (979) 0x4650c8 LDR	X9, [X12, X18]

  (979) 0x4650cc LDR	X18, [X4, X22,LSL #3]

  (979) 0x4650d0 CMP	X18, X9

  (979) 0x4650d4 B.NE	465078

  (979) 0x4650d8 LDR	X18, [SP, #112]

  (979) 0x4650dc LDR	X0, [SP, #112]

  (979) 0x4650e0 LDR	D27, [X11, X18,LSL #3]

  (979) 0x4650e4 ADD	X3, X0, #1

  (979) 0x4650e8 STR	X3, [SP, #112]

  (979) 0x4650ec FADD	D25, D25, D27

  (979) 0x4650f0 CMP	X5, X3

  (979) 0x4650f4 B.NE	46508c

0x4650f8 LDR	X14, [SP, #120]

0x4650fc ORR	X4, XZR, X25

0x465100 ORR	X11, XZR, X24

0x465104 LDP	X12, X9, [SP, #248]

0x465108 LDR	X25, [SP, #192]

0x46510c B	4641a0

  (966) 0x465110 LDR	X24, [SP, #160]

  (966) 0x465114 LDR	X5, [X24, X22,LSL #3]

  (966) 0x465118 LDR	X18, [X24, X9]

  (966) 0x46511c CMP	X5, X18

  (966) 0x465120 B.GE	4640ac

  (966) 0x465124 LDR	X8, [SP, #176]

  (966) 0x465128 ORR	X10, XZR, X24

  (966) 0x46512c ORR	X7, XZR, X12

  (966) 0x465130 STR	X5, [SP, #112]

  (966) 0x465134 LDR	X24, [SP, #200]

  (966) 0x465138 STR	X14, [SP, #192]

  (966) 0x46513c LDR	X14, [SP, #144]

  (966) 0x465140 STR	X15, [SP, #264]

  (966) 0x465144 LDR	X2, [X8, #240]

  (966) 0x465148 STR	X17, [SP, #304]

  (966) 0x46514c LDR	X3, [X8, #200]

  (966) 0x465150 LDR	X17, [SP, #208]

  (966) 0x465154 LDR	X0, [X8, #216]

  (966) 0x465158 LDR	X8, [X2]

  (966) 0x46515c STP	X11, X21, [SP, #248]

  (966) 0x465160 LDR	X21, [SP, #128]

  (966) 0x465164 LDR	X6, [SP, #216]

  (966) 0x465168 LDR	X15, [SP, #240]

  (966) 0x46516c LDR	X11, [SP, #296]

  (966) 0x465170 B	4651b0

    (971) 0x465174 LDR	X5, [X23, X2]

    (971) 0x465178 CMP	X27, X5

    (971) 0x46517c B.LE	46519c

    (971) 0x465180 UBFM	X18, X4, #61, #60

    (971) 0x465184 STR	X4, [X23, X2]

    (971) 0x465188 ADD	X4, X4, #1

    (971) 0x46518c ORR	X12, XZR, X18

    (971) 0x465190 STR	X1, [X0, X18]

    (971) 0x465194 LDR	X18, [X10, X9]

    (971) 0x465198 STR	D15, [X3, X12]

    (971) 0x46519c LDR	X1, [SP, #112]

    (971) 0x4651a0 ADD	X2, X1, #1

    (971) 0x4651a4 STR	X2, [SP, #112]

    (971) 0x4651a8 CMP	X18, X2

    (971) 0x4651ac B.LE	4652a4

    (971) 0x4651b0 LDR	X12, [SP, #112]

    (971) 0x4651b4 LDR	X1, [X17, X12,LSL #3]

    (971) 0x4651b8 CBZ	X6, 4651c0

    (971) 0x4651bc LDR	X1, [X6, X1,LSL #3]

    (971) 0x4651c0 UBFM	X2, X1, #61, #60

    (971) 0x4651c4 LDR	X5, [X8, X2]

    (971) 0x4651c8 TBZ	X5, #63, 465174

    (971) 0x4651cc CMN	X5, #3

    (971) 0x4651d0 B.EQ	46519c

    (971) 0x4651d4 LDR	X1, [SP, #272]

    (971) 0x4651d8 ADD	X12, X2, #8

    (971) 0x4651dc STR	X30, [X23, X2]

    (971) 0x4651e0 LDR	X2, [X1, X2]

    (971) 0x4651e4 ADD	X18, X1, X12

    (971) 0x4651e8 LDR	X12, [X1, X12]

    (971) 0x4651ec CMP	X2, X12

    (971) 0x4651f0 B.GE	46528c

    (971) 0x4651f4 STR	X17, [SP, #120]

    (971) 0x4651f8 STR	X10, [SP, #144]

    (971) 0x4651fc B	465230

      (972) 0x465200 LDR	X5, [X23, X17]

      (972) 0x465204 UBFM	X1, X4, #61, #60

      (972) 0x465208 CMP	X27, X5

      (972) 0x46520c B.LE	465224

      (972) 0x465210 STR	X4, [X23, X17]

      (972) 0x465214 ADD	X4, X4, #1

      (972) 0x465218 STR	X10, [X0, X1]

      (972) 0x46521c LDR	X12, [X18]

      (972) 0x465220 STR	D15, [X3, X1]

      (972) 0x465224 ADD	X2, X2, #1

      (972) 0x465228 CMP	X2, X12

      (972) 0x46522c B.GE	465284

      (972) 0x465230 LDR	X1, [X24, X2,LSL #3]

      (972) 0x465234 CMP	X15, X1

      (972) 0x465238 ORN	X10, XZR, X1

      (972) 0x46523c SUB	X5, X1, X11

      (972) 0x465240 CCMP	X11, X1, #0, #12

      (972) 0x465244 UBFM	X17, X10, #61, #60

      (972) 0x465248 UBFM	X5, X5, #61, #60

      (972) 0x46524c B.GT	465200

      (972) 0x465250 LDR	X10, [X19, X5]

      (972) 0x465254 UBFM	X17, X14, #61, #60

      (972) 0x465258 CMP	X21, X10

      (972) 0x46525c B.LE	465224

      (972) 0x465260 STR	X14, [X19, X5]

      (972) 0x465264 ADD	X2, X2, #1

      (972) 0x465268 ADD	X14, X14, #1

      (972) 0x46526c LDR	X12, [X25, X5]

      (972) 0x465270 STR	X12, [X16, X17]

      (972) 0x465274 LDR	X12, [X18]

      (972) 0x465278 STR	D15, [X28, X17]

      (972) 0x46527c CMP	X2, X12

      (972) 0x465280 B.LT	465230

    (971) 0x465284 LDR	X17, [SP, #120]

    (971) 0x465288 LDR	X10, [SP, #144]

    (971) 0x46528c LDR	X1, [SP, #112]

    (971) 0x465290 LDR	X18, [X10, X9]

    (971) 0x465294 ADD	X2, X1, #1

    (971) 0x465298 STR	X2, [SP, #112]

    (971) 0x46529c CMP	X18, X2

    (971) 0x4652a0 B.GT	4651b0

  (966) 0x4652a4 LDR	X10, [SP, #168]

  (966) 0x4652a8 ORR	X12, XZR, X7

  (966) 0x4652ac LDP	X11, X21, [SP, #248]

  (966) 0x4652b0 STR	X14, [SP, #144]

  (966) 0x4652b4 LDR	X5, [X10]

  (966) 0x4652b8 LDR	X14, [SP, #192]

  (966) 0x4652bc LDR	X15, [SP, #264]

  (966) 0x4652c0 STR	X5, [SP, #192]

  (966) 0x4652c4 LDR	X17, [SP, #304]

  (966) 0x4652c8 B	4640ac

0x4653e4 ORR	X0, XZR, X19

0x4653e8 BL	546e20

0x4653ec B	464688

  (979) 0x4653f0 LDR	X1, [SP, #352]

  (979) 0x4653f4 FMOV	D0, D15

  (979) 0x4653f8 ADD	X3, X1, X18

  (979) 0x4653fc LDR	X4, [X1, X18]

  (979) 0x465400 LDR	X18, [X3, #8]

  (979) 0x465404 ORR	X0, XZR, X4

  (979) 0x465408 CMP	X4, X18

  (979) 0x46540c B.GE	4667ec

  (979) 0x465410 SUB	X9, X18, X4

  (979) 0x465414 ANDS	X1, X9, #4160

  (979) 0x465418 B.EQ	4654c8

  (979) 0x46541c CMP	X1, #1

  (979) 0x465420 B.EQ	465494

  (979) 0x465424 CMP	X1, #2

  (979) 0x465428 B.EQ	465460

  (979) 0x46542c LDR	X0, [X8, X4,LSL #3]

  (979) 0x465430 CMP	X10, X0

  (979) 0x465434 CCMP	X2, X0, #0, #12

  (979) 0x465438 B.GT	466674

  (979) 0x46543c SUB	X0, X0, X2

  (979) 0x465440 LDR	X1, [SP, #128]

  (979) 0x465444 LDR	X3, [X19, X0,LSL #3]

  (979) 0x465448 CMP	X1, X3

  (979) 0x46544c CCMP	X22, X0, #4, #12

  (979) 0x465450 B.NE	46545c

  (979) 0x465454 LDR	D29, [X14, X4,LSL #3]

  (979) 0x465458 FADD	D0, D15, D29

  (979) 0x46545c ADD	X0, X4, #1

  (979) 0x465460 LDR	X9, [X8, X0,LSL #3]

  (979) 0x465464 CMP	X10, X9

  (979) 0x465468 CCMP	X2, X9, #0, #12

  (979) 0x46546c B.GT	4662d0

  (979) 0x465470 SUB	X3, X9, X2

  (979) 0x465474 LDR	X9, [SP, #128]

  (979) 0x465478 LDR	X1, [X19, X3,LSL #3]

  (979) 0x46547c CMP	X9, X1

  (979) 0x465480 CCMP	X22, X3, #4, #12

  (979) 0x465484 B.NE	465490

  (979) 0x465488 LDR	D19, [X14, X0,LSL #3]

  (979) 0x46548c FADD	D0, D0, D19

  (979) 0x465490 ADD	X0, X0, #1

  (979) 0x465494 LDR	X3, [X8, X0,LSL #3]

  (979) 0x465498 CMP	X10, X3

  (979) 0x46549c CCMP	X2, X3, #0, #12

  (979) 0x4654a0 B.LE	46603c

  (979) 0x4654a4 ORN	X1, XZR, X3

  (979) 0x4654a8 LDR	X9, [X23, X1,LSL #3]

  (979) 0x4654ac CMP	X27, X9

  (979) 0x4654b0 B.GT	4654bc

  (979) 0x4654b4 LDR	D20, [X14, X0,LSL #3]

  (979) 0x4654b8 FADD	D0, D0, D20

  (979) 0x4654bc ADD	X0, X0, #1

  (979) 0x4654c0 CMP	X18, X0

  (979) 0x4654c4 B.EQ	465590

  (979) 0x4654c8 LDR	X9, [SP, #128]

  (979) 0x4654cc STR	X4, [SP, #264]

    (980) 0x4654d0 LDR	X4, [X8, X0,LSL #3]

    (980) 0x4654d4 CMP	X10, X4

    (980) 0x4654d8 CCMP	X2, X4, #0, #12

    (980) 0x4654dc B.LE	46594c

    (980) 0x4654e0 ORN	X3, XZR, X4

    (980) 0x4654e4 LDR	X1, [X23, X3,LSL #3]

    (980) 0x4654e8 CMP	X27, X1

    (980) 0x4654ec B.LE	465960

    (980) 0x4654f0 ADD	X0, X0, #1

    (980) 0x4654f4 LDR	X1, [X8, X0,LSL #3]

    (980) 0x4654f8 CMP	X10, X1

    (980) 0x4654fc CCMP	X2, X1, #0, #12

    (980) 0x465500 B.GT	46597c

    (980) 0x465504 SUB	X1, X1, X2

    (980) 0x465508 LDR	X4, [X19, X1,LSL #3]

    (980) 0x46550c CMP	X9, X4

    (980) 0x465510 CCMP	X22, X1, #4, #12

    (980) 0x465514 B.NE	465520

    (980) 0x465518 LDR	D22, [X14, X0,LSL #3]

    (980) 0x46551c FADD	D0, D0, D22

    (980) 0x465520 ADD	X3, X0, #1

    (980) 0x465524 LDR	X1, [X8, X3,LSL #3]

    (980) 0x465528 CMP	X10, X1

    (980) 0x46552c CCMP	X2, X1, #0, #12

    (980) 0x465530 B.GT	4659a0

    (980) 0x465534 SUB	X1, X1, X2

    (980) 0x465538 LDR	X4, [X19, X1,LSL #3]

    (980) 0x46553c CMP	X9, X4

    (980) 0x465540 CCMP	X22, X1, #4, #12

    (980) 0x465544 B.NE	465550

    (980) 0x465548 LDR	D23, [X14, X3,LSL #3]

    (980) 0x46554c FADD	D0, D0, D23

    (980) 0x465550 ADD	X3, X0, #2

    (980) 0x465554 LDR	X1, [X8, X3,LSL #3]

    (980) 0x465558 CMP	X10, X1

    (980) 0x46555c CCMP	X2, X1, #0, #12

    (980) 0x465560 B.GT	4659c4

    (980) 0x465564 SUB	X1, X1, X2

    (980) 0x465568 LDR	X4, [X19, X1,LSL #3]

    (980) 0x46556c CMP	X9, X4

    (980) 0x465570 CCMP	X22, X1, #4, #12

    (980) 0x465574 B.NE	465580

    (980) 0x465578 LDR	D1, [X14, X3,LSL #3]

    (980) 0x46557c FADD	D0, D0, D1

    (980) 0x465580 ADD	X0, X0, #3

    (980) 0x465584 CMP	X18, X0

    (980) 0x465588 B.NE	4654d0

  (979) 0x46558c LDR	X4, [SP, #264]

  (979) 0x465590 FCMP	D0, #0

  (979) 0x465594 B.EQ	4650d8

  (979) 0x465598 LDR	X9, [SP, #112]

  (979) 0x46559c SUB	X3, X18, X4

  (979) 0x4655a0 ANDS	X1, X3, #4160

  (979) 0x4655a4 LDR	D7, [X11, X9,LSL #3]

  (979) 0x4655a8 FDIV	D16, D7, D0

  (979) 0x4655ac B.EQ	466314

  (979) 0x4655b0 CMP	X1, #1

  (979) 0x4655b4 B.EQ	465648

  (979) 0x4655b8 CMP	X1, #2

  (979) 0x4655bc B.EQ	465604

  (979) 0x4655c0 LDR	X0, [X8, X4,LSL #3]

  (979) 0x4655c4 CMP	X10, X0

  (979) 0x4655c8 CCMP	X2, X0, #0, #12

  (979) 0x4655cc B.GT	466868

  (979) 0x4655d0 SUB	X9, X0, X2

  (979) 0x4655d4 LDR	X3, [SP, #128]

  (979) 0x4655d8 LDR	X0, [X19, X9,LSL #3]

  (979) 0x4655dc CMP	X3, X0

  (979) 0x4655e0 B.GT	4655f8

  (979) 0x4655e4 UBFM	X1, X0, #61, #60

  (979) 0x4655e8 LDR	D6, [X14, X4,LSL #3]

  (979) 0x4655ec LDR	D17, [X28, X1]

  (979) 0x4655f0 FMADD	D4, D16, D6, D17

  (979) 0x4655f4 STR	D4, [X28, X1]

  (979) 0x4655f8 CMP	X22, X9

  (979) 0x4655fc B.EQ	4667b4

  (979) 0x465600 ADD	X4, X4, #1

  (979) 0x465604 LDR	X9, [X8, X4,LSL #3]

  (979) 0x465608 CMP	X10, X9

  (979) 0x46560c CCMP	X2, X9, #0, #12

  (979) 0x465610 B.GT	466824

  (979) 0x465614 SUB	X9, X9, X2

  (979) 0x465618 LDR	X3, [SP, #128]

  (979) 0x46561c LDR	X0, [X19, X9,LSL #3]

  (979) 0x465620 CMP	X3, X0

  (979) 0x465624 B.GT	46563c

  (979) 0x465628 UBFM	X1, X0, #61, #60

  (979) 0x46562c LDR	D29, [X14, X4,LSL #3]

  (979) 0x465630 LDR	D19, [X28, X1]

  (979) 0x465634 FMADD	D20, D16, D29, D19

  (979) 0x465638 STR	D20, [X28, X1]

  (979) 0x46563c CMP	X22, X9

  (979) 0x465640 B.EQ	466750

  (979) 0x465644 ADD	X4, X4, #1

  (979) 0x465648 LDR	X9, [X8, X4,LSL #3]

  (979) 0x46564c CMP	X10, X9

  (979) 0x465650 CCMP	X2, X9, #0, #12

  (979) 0x465654 B.GT	4662e4

  (979) 0x465658 SUB	X9, X9, X2

  (979) 0x46565c LDR	X3, [SP, #128]

  (979) 0x465660 LDR	X0, [X19, X9,LSL #3]

  (979) 0x465664 CMP	X3, X0

  (979) 0x465668 B.GT	465680

  (979) 0x46566c UBFM	X1, X0, #61, #60

  (979) 0x465670 LDR	D0, [X14, X4,LSL #3]

  (979) 0x465674 LDR	D27, [X28, X1]

  (979) 0x465678 FMADD	D7, D16, D0, D27

  (979) 0x46567c STR	D7, [X28, X1]

  (979) 0x465680 CMP	X22, X9

  (979) 0x465684 B.NE	466308

  (979) 0x465688 LDR	D5, [X14, X4,LSL #3]

  (979) 0x46568c FMADD	D25, D16, D5, D25

  (979) 0x465690 B	466308

0x465694 FMOV	D31, D15

0x465698 HINT	#0

0x46569c HINT	#0

0x4656a0 LDR	X10, [SP, #312]

0x4656a4 LDR	X7, [SP, #320]

0x4656a8 LDR	X5, [SP, #120]

0x4656ac LDR	X3, [X7, X10]

0x4656b0 LDR	X25, [X7, X5]

0x4656b4 STR	X3, [SP, #304]

0x4656b8 CMP	X25, X3

0x4656bc B.GE	4667d4

0x4656c0 SUB	X7, X3, X25

0x4656c4 SUB	X1, X7, #1

0x4656c8 CMP	X1, #6

0x4656cc B.LS	466814

0x4656d0 LDR	X0, [SP, #280]

0x4656d4 ADD	X8, X17, X25,LSL #3

0x4656d8 UBFM	X5, X7, #2, #63

0x4656dc DUP	Z5.D, #0

0x4656e0 DUP	Z18.D, X27

0x4656e4 ORR	Z6.D, Z5.D, Z5.D

0x4656e8 DUP	Z21.D, Z24.D[0]

0x4656ec PTRUE	P7.B, VL16

0x4656f0 ADD	X1, X8, X5,LSL #5

0x4656f4 ORR	X3, XZR, X8

0x4656f8 ADD	X0, X0, X25,LSL #3

0x4656fc ADD	X11, X0, #16

0x465700 SUB	X10, X0, X8

0x465704 TBNZ	W5, #0, 465fb4

0x465708 STR	X24, [SP, #328]

0x46570c STR	X19, [SP, #360]

  (984) 0x465710 ADD	X19, X3, #32

  (984) 0x465714 ADD	X24, X10, X3

  (984) 0x465718 LD1D	{Z7.D}, P7/Z, [X3, MUL VL]

  (984) 0x46571c LD1D	{Z17.D}, P7/Z, [X3, #2, MUL VL]

  (984) 0x465720 LD1D	{Z28.D}, P7/Z, [X3, #1, MUL VL]

  (984) 0x465724 SUB	X5, X3, X8

  (984) 0x465728 LD1D	{Z30.D}, P7/Z, [X3, #3, MUL VL]

  (984) 0x46572c ADD	X3, X10, X19

  (984) 0x465730 LD1D	{Z16.D}, P7/Z, [X23, Z7.D,LSL #3]

  (984) 0x465734 LD1D	{Z26.D}, P7/Z, [X23, Z17.D,LSL #3]

  (984) 0x465738 CMPGE	P3.D, P7/Z, Z16.D, Z18.D

  (984) 0x46573c SUB	X0, X19, X8

  (984) 0x465740 CMPGE	P4.D, P7/Z, Z26.D, Z18.D

  (984) 0x465744 LD1D	{Z29.D}, P7/Z, [X23, Z28.D,LSL #3]

  (984) 0x465748 LD1D	{Z23.D}, P4/Z, [X3, MUL VL]

  (984) 0x46574c CMPGE	P5.D, P7/Z, Z29.D, Z18.D

  (984) 0x465750 ADD	X3, X19, #32

  (984) 0x465754 LD1D	{Z19.D}, P7/Z, [X23, Z30.D,LSL #3]

  (984) 0x465758 CMPGE	P0.D, P7/Z, Z19.D, Z18.D

  (984) 0x46575c LD1D	{Z20.D}, P3/Z, [X24, MUL VL]

  (984) 0x465760 ADD	X19, X5, X11

  (984) 0x465764 ADD	X24, X0, X11

  (984) 0x465768 LD1D	{Z0.D}, P5/Z, [X19, MUL VL]

  (984) 0x46576c LD1D	{Z7.D}, P0/Z, [X24, MUL VL]

  (984) 0x465770 FMUL	Z22.D, Z20.D, Z21.D

  (984) 0x465774 FMUL	Z1.D, Z23.D, Z21.D

  (984) 0x465778 FCMLT	P6.D, P3/Z, Z22.D, #0

  (984) 0x46577c FCMLT	P1.D, P4/Z, Z1.D, #0

  (984) 0x465780 FADD	Z6.D, P6/M, Z6.D, Z20.D

  (984) 0x465784 FMUL	Z27.D, Z0.D, Z21.D

  (984) 0x465788 FMUL	Z16.D, Z7.D, Z21.D

  (984) 0x46578c FCMLT	P2.D, P5/Z, Z27.D, #0

  (984) 0x465790 FCMLT	P3.D, P0/Z, Z16.D, #0

  (984) 0x465794 FADD	Z5.D, P2/M, Z5.D, Z0.D

  (984) 0x465798 FADD	Z6.D, P1/M, Z6.D, Z23.D

  (984) 0x46579c FADD	Z5.D, P3/M, Z5.D, Z7.D

  (984) 0x4657a0 CMP	X3, X1

  (984) 0x4657a4 B.NE	465710

0x4657a8 LDR	X24, [SP, #328]

0x4657ac LDR	X19, [SP, #360]

0x4657b0 AND	X8, X7, #8062

0x4657b4 FADD	Z5.D, Z6.D, Z5.D

0x4657b8 FADDV	D18, P7, Z5.D

0x4657bc FADD	D31, D31, D18

0x4657c0 ADD	X11, X8, X25

0x4657c4 ANDS	XZR, X7, #4160

0x4657c8 B.EQ	465930

0x4657cc UBFM	X1, X11, #61, #60

0x4657d0 LDR	X7, [X17, X1]

0x4657d4 LDR	X10, [X23, X7,LSL #3]

0x4657d8 CMP	X27, X10

0x4657dc B.GT	4657f8

0x4657e0 LDR	X5, [SP, #280]

0x4657e4 LDR	D21, [X5, X1]

0x4657e8 FMUL	D6, D21, D24

0x4657ec FADD	D17, D31, D21

0x4657f0 FCMPE	D6, #0

0x4657f4 FCSEL	D31, D17, D31, #4

0x4657f8 LDR	X0, [SP, #304]

0x4657fc ADD	X3, X11, #1

0x465800 CMP	X3, X0

0x465804 B.GE	465930

0x465808 ADD	X7, X1, #8

0x46580c LDR	X8, [X17, X7]

0x465810 LDR	X10, [X23, X8,LSL #3]

0x465814 CMP	X27, X10

0x465818 B.GT	465834

0x46581c LDR	X5, [SP, #280]

0x465820 LDR	D26, [X5, X7]

0x465824 FMUL	D28, D26, D24

0x465828 FADD	D29, D31, D26

0x46582c FCMPE	D28, #0

0x465830 FCSEL	D31, D29, D31, #4

0x465834 LDR	X0, [SP, #304]

0x465838 ADD	X3, X11, #2

0x46583c CMP	X0, X3

0x465840 B.LE	465930

0x465844 ADD	X7, X1, #16

0x465848 LDR	X8, [X17, X7]

0x46584c LDR	X10, [X23, X8,LSL #3]

0x465850 CMP	X27, X10

0x465854 B.GT	465870

0x465858 LDR	X5, [SP, #280]

0x46585c LDR	D30, [X5, X7]

0x465860 FMUL	D19, D30, D24

0x465864 FADD	D20, D31, D30

0x465868 FCMPE	D19, #0

0x46586c FCSEL	D31, D20, D31, #4

0x465870 LDR	X0, [SP, #304]

0x465874 ADD	X3, X11, #3

0x465878 CMP	X0, X3

0x46587c B.LE	465930

0x465880 ADD	X7, X1, #24

0x465884 LDR	X8, [X17, X7]

0x465888 LDR	X10, [X23, X8,LSL #3]

0x46588c CMP	X27, X10

0x465890 B.GT	4658ac

0x465894 LDR	X5, [SP, #280]

0x465898 LDR	D22, [X5, X7]

0x46589c FMUL	D23, D24, D22

0x4658a0 FADD	D1, D31, D22

0x4658a4 FCMPE	D23, #0

0x4658a8 FCSEL	D31, D1, D31, #4

0x4658ac LDR	X0, [SP, #304]

0x4658b0 ADD	X3, X11, #4

0x4658b4 CMP	X0, X3

0x4658b8 B.LE	465930

0x4658bc ADD	X7, X1, #32

0x4658c0 LDR	X8, [X17, X7]

0x4658c4 LDR	X10, [X23, X8,LSL #3]

0x4658c8 CMP	X27, X10

0x4658cc B.GT	4658e8

0x4658d0 LDR	X5, [SP, #280]

0x4658d4 LDR	D0, [X5, X7]

0x4658d8 FMUL	D27, D0, D24

0x4658dc FADD	D7, D31, D0

0x4658e0 FCMPE	D27, #0

0x4658e4 FCSEL	D31, D7, D31, #4

0x4658e8 LDR	X0, [SP, #304]

0x4658ec ADD	X3, X11, #5

0x4658f0 CMP	X0, X3

0x4658f4 B.LE	465930

0x4658f8 ADD	X7, X1, #40

0x4658fc LDR	X8, [X17, X7]

0x465900 LDR	X10, [X23, X8,LSL #3]

0x465904 CMP	X27, X10

0x465908 B.LE	4665dc

0x46590c LDR	X3, [SP, #304]

0x465910 ADD	X11, X11, #6

0x465914 CMP	X3, X11

0x465918 B.LE	465930

0x46591c ADD	X1, X1, #48

0x465920 LDR	X0, [X17, X1]

0x465924 LDR	X7, [X23, X0,LSL #3]

0x465928 CMP	X27, X7

0x46592c B.LE	4665f8

0x465930 FCMP	D31, #0

0x465934 B.EQ	464a30

0x465938 FDIV	D26, D4, D31

0x46593c CMP	X9, X4

0x465940 B.LT	465ae0

0x465944 LDR	X5, [SP, #304]

0x465948 B	465bdc

    (980) 0x46594c SUB	X4, X4, X2

    (980) 0x465950 LDR	X3, [X19, X4,LSL #3]

    (980) 0x465954 CMP	X9, X3

    (980) 0x465958 CCMP	X22, X4, #4, #12

    (980) 0x46595c B.NE	4654f0

    (980) 0x465960 LDR	D30, [X14, X0,LSL #3]

    (980) 0x465964 ADD	X0, X0, #1

    (980) 0x465968 LDR	X1, [X8, X0,LSL #3]

    (980) 0x46596c FADD	D0, D0, D30

    (980) 0x465970 CMP	X10, X1

    (980) 0x465974 CCMP	X2, X1, #0, #12

    (980) 0x465978 B.LE	465504

    (980) 0x46597c ORN	X4, XZR, X1

    (980) 0x465980 LDR	X3, [X23, X4,LSL #3]

    (980) 0x465984 CMP	X27, X3

    (980) 0x465988 B.LE	465518

    (980) 0x46598c ADD	X3, X0, #1

    (980) 0x465990 LDR	X1, [X8, X3,LSL #3]

    (980) 0x465994 CMP	X10, X1

    (980) 0x465998 CCMP	X2, X1, #0, #12

    (980) 0x46599c B.LE	465534

    (980) 0x4659a0 ORN	X4, XZR, X1

    (980) 0x4659a4 LDR	X1, [X23, X4,LSL #3]

    (980) 0x4659a8 CMP	X27, X1

    (980) 0x4659ac B.LE	465548

    (980) 0x4659b0 ADD	X3, X0, #2

    (980) 0x4659b4 LDR	X1, [X8, X3,LSL #3]

    (980) 0x4659b8 CMP	X10, X1

    (980) 0x4659bc CCMP	X2, X1, #0, #12

    (980) 0x4659c0 B.LE	465564

    (980) 0x4659c4 ORN	X4, XZR, X1

    (980) 0x4659c8 LDR	X1, [X23, X4,LSL #3]

    (980) 0x4659cc CMP	X27, X1

    (980) 0x4659d0 B.GT	465580

    (980) 0x4659d4 B	465578

    (973) 0x4659d8 ORR	X24, XZR, X18

    (973) 0x4659dc STR	X19, [SP, #144]

    (973) 0x4659e0 STR	X0, [SP, #248]

      (974) 0x4659e4 LDR	X8, [X12, X2,LSL #3]

      (974) 0x4659e8 ADD	X2, X2, #1

      (974) 0x4659ec UBFM	X5, X8, #61, #60

      (974) 0x4659f0 LDR	X19, [X11, X5]

      (974) 0x4659f4 TBNZ	X19, #63, 465a20

      (974) 0x4659f8 LDR	X0, [X23, X5]

      (974) 0x4659fc UBFM	X18, X4, #61, #60

      (974) 0x465a00 CMP	X27, X0

      (974) 0x465a04 B.LE	465a20

      (974) 0x465a08 STR	X4, [X23, X5]

      (974) 0x465a0c ADD	X4, X4, #1

      (974) 0x465a10 STR	X8, [X14, X18]

      (974) 0x465a14 LDR	X8, [SP, #112]

      (974) 0x465a18 LDR	X7, [X6]

      (974) 0x465a1c STR	D15, [X8, X18]

      (974) 0x465a20 CMP	X7, X2

      (974) 0x465a24 B.GT	4659e4

    (973) 0x465a28 LDR	X2, [X15, X9]

    (973) 0x465a2c ORR	X18, XZR, X24

    (973) 0x465a30 LDR	X19, [SP, #144]

    (973) 0x465a34 LDR	X0, [SP, #248]

    (973) 0x465a38 B	46407c

0x465adc FDIV	D26, D4, D31

0x465ae0 LDR	X25, [X12, X9,LSL #3]

0x465ae4 ORN	X10, XZR, X9

0x465ae8 ADD	X5, X10, X4

0x465aec AND	X11, X5, #4160

0x465af0 LDR	X3, [X19, X25,LSL #3]

0x465af4 CMP	X2, X3

0x465af8 B.GT	4661fc

0x465afc LDR	D31, [X26, X9,LSL #3]

0x465b00 FMUL	D4, D31, D24

0x465b04 FCMPE	D4, #0

0x465b08 B.MI	4661ec

0x465b0c ADD	X3, X9, #1

0x465b10 CMP	X4, X3

0x465b14 B.LE	465bb8

0x465b18 CBZ	X11, 465f84

0x465b1c CMP	X11, #1

0x465b20 B.EQ	465b8c

0x465b24 CMP	X11, #2

0x465b28 B.EQ	465b50

0x465b2c LDR	X9, [X12, X3,LSL #3]

0x465b30 LDR	X0, [X19, X9,LSL #3]

0x465b34 CMP	X2, X0

0x465b38 B.GT	46672c

0x465b3c LDR	D22, [X26, X3,LSL #3]

0x465b40 FMUL	D23, D22, D24

0x465b44 FCMPE	D23, #0

0x465b48 B.MI	46671c

0x465b4c ADD	X3, X3, #1

0x465b50 LDR	X8, [X12, X3,LSL #3]

0x465b54 LDR	X25, [X19, X8,LSL #3]

0x465b58 CMP	X2, X25

0x465b5c B.GT	465b80

0x465b60 LDR	D5, [X26, X3,LSL #3]

0x465b64 FMUL	D18, D5, D24

0x465b68 FCMPE	D18, #0

0x465b6c B.GE	465b88

0x465b70 UBFM	X10, X25, #61, #60

0x465b74 LDR	D21, [X28, X10]

0x465b78 FMADD	D6, D26, D5, D21

0x465b7c STR	D6, [X28, X10]

0x465b80 CMP	X22, X8

0x465b84 B.EQ	466704

0x465b88 ADD	X3, X3, #1

0x465b8c LDR	X5, [X12, X3,LSL #3]

0x465b90 LDR	X11, [X19, X5,LSL #3]

0x465b94 CMP	X2, X11

0x465b98 B.GT	46626c

0x465b9c LDR	D28, [X26, X3,LSL #3]

0x465ba0 FMUL	D29, D28, D24

0x465ba4 FCMPE	D29, #0

0x465ba8 B.MI	46625c

0x465bac ADD	X3, X3, #1

0x465bb0 CMP	X4, X3

0x465bb4 B.GT	465f84

0x465bb8 LDR	X4, [SP, #192]

0x465bbc CMP	X4, #1

0x465bc0 B.LE	464100

0x465bc4 LDR	X8, [SP, #120]

0x465bc8 LDR	X11, [SP, #312]

0x465bcc LDR	X10, [SP, #320]

0x465bd0 LDR	X5, [X10, X11]

0x465bd4 LDR	X25, [X10, X8]

0x465bd8 STR	X5, [SP, #304]

0x465bdc CMP	X25, X5

0x465be0 B.GE	464100

0x465be4 LDR	X0, [SP, #176]

0x465be8 SUB	X1, X5, X25

0x465bec ANDS	X9, X1, #4224

0x465bf0 LDR	X3, [X0, #200]

0x465bf4 B.EQ	466890

0x465bf8 CMP	X9, #1

0x465bfc B.EQ	465d28

0x465c00 CMP	X9, #2

0x465c04 B.EQ	465cf0

0x465c08 CMP	X9, #3

0x465c0c B.EQ	465cc8

0x465c10 CMP	X9, #4

0x465c14 B.EQ	465ca0

0x465c18 CMP	X9, #5

0x465c1c B.EQ	465c78

0x465c20 CMP	X9, #6

0x465c24 B.EQ	465c50

0x465c28 LDR	X7, [X17, X25,LSL #3]

0x465c2c LDR	X4, [X23, X7,LSL #3]

0x465c30 CMP	X27, X4

0x465c34 B.GT	465c4c

0x465c38 LDR	X8, [SP, #280]

0x465c3c LDR	D17, [X8, X25,LSL #3]

0x465c40 FMUL	D4, D17, D24

0x465c44 FCMPE	D4, #0

0x465c48 B.MI	4667c0

0x465c4c ADD	X25, X25, #1

0x465c50 LDR	X11, [X17, X25,LSL #3]

0x465c54 LDR	X5, [X23, X11,LSL #3]

0x465c58 CMP	X27, X5

0x465c5c B.GT	465c74

0x465c60 LDR	X1, [SP, #280]

0x465c64 LDR	D29, [X1, X25,LSL #3]

0x465c68 FMUL	D19, D29, D24

0x465c6c FCMPE	D19, #0

0x465c70 B.MI	4667a0

0x465c74 ADD	X25, X25, #1

0x465c78 LDR	X0, [X17, X25,LSL #3]

0x465c7c LDR	X7, [X23, X0,LSL #3]

0x465c80 CMP	X27, X7

0x465c84 B.GT	465c9c

0x465c88 LDR	X4, [SP, #280]

0x465c8c LDR	D22, [X4, X25,LSL #3]

0x465c90 FMUL	D23, D22, D24

0x465c94 FCMPE	D23, #0

0x465c98 B.MI	46678c

0x465c9c ADD	X25, X25, #1

0x465ca0 LDR	X10, [X17, X25,LSL #3]

0x465ca4 LDR	X11, [X23, X10,LSL #3]

0x465ca8 CMP	X27, X11

0x465cac B.GT	465cc4

0x465cb0 LDR	X5, [SP, #280]

0x465cb4 LDR	D27, [X5, X25,LSL #3]

0x465cb8 FMUL	D7, D27, D24

0x465cbc FCMPE	D7, #0

0x465cc0 B.MI	466778

0x465cc4 ADD	X25, X25, #1

0x465cc8 LDR	X9, [X17, X25,LSL #3]

0x465ccc LDR	X0, [X23, X9,LSL #3]

0x465cd0 CMP	X27, X0

0x465cd4 B.GT	465cec

0x465cd8 LDR	X7, [SP, #280]

0x465cdc LDR	D18, [X7, X25,LSL #3]

0x465ce0 FMUL	D21, D18, D24

0x465ce4 FCMPE	D21, #0

0x465ce8 B.MI	466760

0x465cec ADD	X25, X25, #1

0x465cf0 LDR	X8, [X17, X25,LSL #3]

0x465cf4 LDR	X10, [X23, X8,LSL #3]

0x465cf8 CMP	X27, X10

0x465cfc B.GT	465d24

0x465d00 LDR	X11, [SP, #280]

0x465d04 LDR	D4, [X11, X25,LSL #3]

0x465d08 FMUL	D31, D4, D24

0x465d0c FCMPE	D31, #0

0x465d10 B.GE	465d24

0x465d14 UBFM	X5, X10, #61, #60

0x465d18 LDR	D28, [X3, X5]

0x465d1c FMADD	D29, D26, D4, D28

0x465d20 STR	D29, [X3, X5]

0x465d24 ADD	X25, X25, #1

0x465d28 LDR	X1, [X17, X25,LSL #3]

0x465d2c LDR	X9, [X23, X1,LSL #3]

0x465d30 CMP	X27, X9

0x465d34 B.LE	46668c

0x465d38 LDR	X4, [SP, #304]

0x465d3c ADD	X25, X25, #1

0x465d40 CMP	X25, X4

0x465d44 B.EQ	464100

0x465d48 LDR	X10, [SP, #280]

0x465d4c ORR	X8, XZR, X4

  (982) 0x465d50 LDR	X11, [X17, X25,LSL #3]

  (982) 0x465d54 LDR	X5, [X23, X11,LSL #3]

  (982) 0x465d58 CMP	X27, X5

  (982) 0x465d5c B.GT	465d80

  (982) 0x465d60 LDR	D23, [X10, X25,LSL #3]

  (982) 0x465d64 FMUL	D1, D23, D24

  (982) 0x465d68 FCMPE	D1, #0

  (982) 0x465d6c B.GE	465d80

  (982) 0x465d70 UBFM	X1, X5, #61, #60

  (982) 0x465d74 LDR	D0, [X3, X1]

  (982) 0x465d78 FMADD	D27, D26, D23, D0

  (982) 0x465d7c STR	D27, [X3, X1]

  (982) 0x465d80 ADD	X25, X25, #1

  (982) 0x465d84 LDR	X9, [X17, X25,LSL #3]

  (982) 0x465d88 LDR	X0, [X23, X9,LSL #3]

  (982) 0x465d8c CMP	X27, X0

  (982) 0x465d90 B.GT	465db4

  (982) 0x465d94 LDR	D7, [X10, X25,LSL #3]

  (982) 0x465d98 FMUL	D16, D7, D24

  (982) 0x465d9c FCMPE	D16, #0

  (982) 0x465da0 B.GE	465db4

  (982) 0x465da4 UBFM	X7, X0, #61, #60

  (982) 0x465da8 LDR	D5, [X3, X7]

  (982) 0x465dac FMADD	D18, D26, D7, D5

  (982) 0x465db0 STR	D18, [X3, X7]

  (982) 0x465db4 ADD	X11, X25, #1

  (982) 0x465db8 LDR	X4, [X17, X11,LSL #3]

  (982) 0x465dbc LDR	X5, [X23, X4,LSL #3]

  (982) 0x465dc0 CMP	X27, X5

  (982) 0x465dc4 B.GT	465de8

  (982) 0x465dc8 LDR	D21, [X10, X11,LSL #3]

  (982) 0x465dcc FMUL	D6, D21, D24

  (982) 0x465dd0 FCMPE	D6, #0

  (982) 0x465dd4 B.GE	465de8

  (982) 0x465dd8 UBFM	X1, X5, #61, #60

  (982) 0x465ddc LDR	D17, [X3, X1]

  (982) 0x465de0 FMADD	D4, D26, D21, D17

  (982) 0x465de4 STR	D4, [X3, X1]

  (982) 0x465de8 ADD	X9, X25, #2

  (982) 0x465dec LDR	X0, [X17, X9,LSL #3]

  (982) 0x465df0 LDR	X7, [X23, X0,LSL #3]

  (982) 0x465df4 CMP	X27, X7

  (982) 0x465df8 B.GT	465e1c

  (982) 0x465dfc LDR	D31, [X10, X9,LSL #3]

  (982) 0x465e00 FMUL	D28, D31, D24

  (982) 0x465e04 FCMPE	D28, #0

  (982) 0x465e08 B.GE	465e1c

  (982) 0x465e0c UBFM	X11, X7, #61, #60

  (982) 0x465e10 LDR	D29, [X3, X11]

  (982) 0x465e14 FMADD	D19, D26, D31, D29

  (982) 0x465e18 STR	D19, [X3, X11]

  (982) 0x465e1c ADD	X5, X25, #3

  (982) 0x465e20 LDR	X4, [X17, X5,LSL #3]

  (982) 0x465e24 LDR	X1, [X23, X4,LSL #3]

  (982) 0x465e28 CMP	X27, X1

  (982) 0x465e2c B.GT	465e50

  (982) 0x465e30 LDR	D20, [X10, X5,LSL #3]

  (982) 0x465e34 FMUL	D30, D20, D24

  (982) 0x465e38 FCMPE	D30, #0

  (982) 0x465e3c B.GE	465e50

  (982) 0x465e40 UBFM	X9, X1, #61, #60

  (982) 0x465e44 LDR	D22, [X3, X9]

  (982) 0x465e48 FMADD	D23, D26, D20, D22

  (982) 0x465e4c STR	D23, [X3, X9]

  (982) 0x465e50 ADD	X0, X25, #4

  (982) 0x465e54 LDR	X7, [X17, X0,LSL #3]

  (982) 0x465e58 LDR	X11, [X23, X7,LSL #3]

  (982) 0x465e5c CMP	X27, X11

  (982) 0x465e60 B.GT	465e84

  (982) 0x465e64 LDR	D1, [X10, X0,LSL #3]

  (982) 0x465e68 FMUL	D0, D1, D24

  (982) 0x465e6c FCMPE	D0, #0

  (982) 0x465e70 B.GE	465e84

  (982) 0x465e74 UBFM	X5, X11, #61, #60

  (982) 0x465e78 LDR	D27, [X3, X5]

  (982) 0x465e7c FMADD	D7, D26, D1, D27

  (982) 0x465e80 STR	D7, [X3, X5]

  (982) 0x465e84 ADD	X1, X25, #5

  (982) 0x465e88 LDR	X4, [X17, X1,LSL #3]

  (982) 0x465e8c LDR	X9, [X23, X4,LSL #3]

  (982) 0x465e90 CMP	X27, X9

  (982) 0x465e94 B.GT	465eb8

  (982) 0x465e98 LDR	D16, [X10, X1,LSL #3]

  (982) 0x465e9c FMUL	D5, D16, D24

  (982) 0x465ea0 FCMPE	D5, #0

  (982) 0x465ea4 B.GE	465eb8

  (982) 0x465ea8 UBFM	X0, X9, #61, #60

  (982) 0x465eac LDR	D18, [X3, X0]

  (982) 0x465eb0 FMADD	D21, D26, D16, D18

  (982) 0x465eb4 STR	D21, [X3, X0]

  (982) 0x465eb8 ADD	X7, X25, #6

  (982) 0x465ebc LDR	X11, [X17, X7,LSL #3]

  (982) 0x465ec0 LDR	X5, [X23, X11,LSL #3]

  (982) 0x465ec4 CMP	X27, X5

  (982) 0x465ec8 B.GT	465eec

  (982) 0x465ecc LDR	D6, [X10, X7,LSL #3]

  (982) 0x465ed0 FMUL	D17, D6, D24

  (982) 0x465ed4 FCMPE	D17, #0

  (982) 0x465ed8 B.GE	465eec

  (982) 0x465edc UBFM	X1, X5, #61, #60

  (982) 0x465ee0 LDR	D4, [X3, X1]

  (982) 0x465ee4 FMADD	D31, D26, D6, D4

  (982) 0x465ee8 STR	D31, [X3, X1]

  (982) 0x465eec ADD	X25, X25, #7

  (982) 0x465ef0 CMP	X25, X8

  (982) 0x465ef4 B.NE	465d50

0x465ef8 B	464100

  (983) 0x465efc LDR	D1, [X26, X3,LSL #3]

  (983) 0x465f00 FMUL	D0, D1, D24

  (983) 0x465f04 FCMPE	D0, #0

  (983) 0x465f08 B.MI	4662bc

  (983) 0x465f0c ADD	X8, X3, #1

  (983) 0x465f10 LDR	X3, [X12, X8,LSL #3]

  (983) 0x465f14 LDR	X25, [X19, X3,LSL #3]

  (983) 0x465f18 CMP	X2, X25

  (983) 0x465f1c B.GT	4661cc

  (983) 0x465f20 LDR	D21, [X26, X8,LSL #3]

  (983) 0x465f24 FMUL	D6, D21, D24

  (983) 0x465f28 FCMPE	D6, #0

  (983) 0x465f2c B.MI	4661bc

  (983) 0x465f30 ADD	X11, X8, #1

  (983) 0x465f34 LDR	X5, [X12, X11,LSL #3]

  (983) 0x465f38 LDR	X1, [X19, X5,LSL #3]

  (983) 0x465f3c CMP	X2, X1

  (983) 0x465f40 B.GT	46619c

  (983) 0x465f44 LDR	D19, [X26, X11,LSL #3]

  (983) 0x465f48 FMUL	D30, D19, D24

  (983) 0x465f4c FCMPE	D30, #0

  (983) 0x465f50 B.MI	46618c

  (983) 0x465f54 ADD	X0, X8, #2

  (983) 0x465f58 LDR	X7, [X12, X0,LSL #3]

  (983) 0x465f5c LDR	X3, [X19, X7,LSL #3]

  (983) 0x465f60 CMP	X2, X3

  (983) 0x465f64 B.GT	46616c

  (983) 0x465f68 LDR	D27, [X26, X0,LSL #3]

  (983) 0x465f6c FMUL	D7, D27, D24

  (983) 0x465f70 FCMPE	D7, #0

  (983) 0x465f74 B.MI	46615c

  (983) 0x465f78 ADD	X3, X8, #3

  (983) 0x465f7c CMP	X4, X3

  (983) 0x465f80 B.LE	465bb8

  (983) 0x465f84 LDR	X9, [X12, X3,LSL #3]

  (983) 0x465f88 LDR	X0, [X19, X9,LSL #3]

  (983) 0x465f8c CMP	X2, X0

  (983) 0x465f90 B.LE	465efc

  (983) 0x465f94 CMP	X22, X9

  (983) 0x465f98 B.NE	465f0c

  (983) 0x465f9c LDR	D16, [X26, X3,LSL #3]

  (983) 0x465fa0 FMUL	D5, D16, D24

  (983) 0x465fa4 FMADD	D18, D26, D16, D25

  (983) 0x465fa8 FCMPE	D5, #0

  (983) 0x465fac FCSEL	D25, D18, D25, #4

  (983) 0x465fb0 B	465f0c

0x465fb4 LD1D	{Z30.D}, P7/Z, [X8, MUL VL]

0x465fb8 LD1D	{Z19.D}, P7/Z, [X8, #1, MUL VL]

0x465fbc LD1D	{Z20.D}, P7/Z, [X23, Z30.D,LSL #3]

0x465fc0 LD1D	{Z22.D}, P7/Z, [X23, Z19.D,LSL #3]

0x465fc4 CMPGE	P0.D, P7/Z, Z20.D, Z18.D

0x465fc8 CMPGE	P6.D, P7/Z, Z22.D, Z18.D

0x465fcc ADD	X3, X8, #32

0x465fd0 LD1D	{Z23.D}, P6/Z, [X0, #1, MUL VL]

0x465fd4 ADD	X5, X10, X8

0x465fd8 FMUL	Z0.D, Z23.D, Z21.D

0x465fdc LD1D	{Z1.D}, P0/Z, [X5, MUL VL]

0x465fe0 FCMLT	P1.D, P6/Z, Z0.D, #0

0x465fe4 FMUL	Z27.D, Z1.D, Z21.D

0x465fe8 FCMLT	P2.D, P0/Z, Z27.D, #0

0x465fec MOVPRFX	Z6, Z5

0x465ff0 FADD	Z6.D, P2/M, Z6.D, Z1.D

0x465ff4 FADD	Z5.D, P1/M, Z5.D, Z23.D

0x465ff8 CMP	X3, X1

0x465ffc B.NE	465708

0x466000 B	4657b0

  (979) 0x46603c SUB	X3, X3, X2

  (979) 0x466040 LDR	X9, [SP, #128]

  (979) 0x466044 LDR	X1, [X19, X3,LSL #3]

  (979) 0x466048 CMP	X9, X1

  (979) 0x46604c CCMP	X22, X3, #4, #12

  (979) 0x466050 B.EQ	4654b4

  (979) 0x466054 B	4654bc

0x4660c8 LD1D	{Z7.D}, P5/Z, [X10, #1, MUL VL]

0x4660cc FMUL	Z5.D, Z20.D, Z7.D

0x4660d0 FNEG	Z5.D, P7/M, Z5.D

0x4660d4 ST1D	{Z5.D}, P5, [X10, #1, MUL VL]

0x4660d8 B	464324

  (983) 0x46615c UBFM	X25, X3, #61, #60

  (983) 0x466160 LDR	D16, [X28, X25]

  (983) 0x466164 FMADD	D5, D26, D27, D16

  (983) 0x466168 STR	D5, [X28, X25]

  (983) 0x46616c CMP	X22, X7

  (983) 0x466170 B.NE	465f78

  (983) 0x466174 LDR	D18, [X26, X0,LSL #3]

  (983) 0x466178 FMUL	D21, D18, D24

  (983) 0x46617c FMADD	D6, D26, D18, D25

  (983) 0x466180 FCMPE	D21, #0

  (983) 0x466184 FCSEL	D25, D6, D25, #4

  (983) 0x466188 B	465f78

  (983) 0x46618c UBFM	X9, X1, #61, #60

  (983) 0x466190 LDR	D20, [X28, X9]

  (983) 0x466194 FMADD	D22, D26, D19, D20

  (983) 0x466198 STR	D22, [X28, X9]

  (983) 0x46619c CMP	X22, X5

  (983) 0x4661a0 B.NE	465f54

  (983) 0x4661a4 LDR	D23, [X26, X11,LSL #3]

  (983) 0x4661a8 FMUL	D1, D23, D24

  (983) 0x4661ac FMADD	D0, D26, D23, D25

  (983) 0x4661b0 FCMPE	D1, #0

  (983) 0x4661b4 FCSEL	D25, D0, D25, #4

  (983) 0x4661b8 B	465f54

  (983) 0x4661bc UBFM	X10, X25, #61, #60

  (983) 0x4661c0 LDR	D17, [X28, X10]

  (983) 0x4661c4 FMADD	D4, D26, D21, D17

  (983) 0x4661c8 STR	D4, [X28, X10]

  (983) 0x4661cc CMP	X22, X3

  (983) 0x4661d0 B.NE	465f30

  (983) 0x4661d4 LDR	D31, [X26, X8,LSL #3]

  (983) 0x4661d8 FMUL	D28, D31, D24

  (983) 0x4661dc FMADD	D29, D26, D31, D25

  (983) 0x4661e0 FCMPE	D28, #0

  (983) 0x4661e4 FCSEL	D25, D29, D25, #4

  (983) 0x4661e8 B	465f30

0x4661ec UBFM	X1, X3, #61, #60

0x4661f0 LDR	D28, [X28, X1]

0x4661f4 FMADD	D29, D26, D31, D28

0x4661f8 STR	D29, [X28, X1]

0x4661fc CMP	X22, X25

0x466200 B.NE	465b0c

0x466204 LDR	D19, [X26, X9,LSL #3]

0x466208 FMUL	D30, D19, D24

0x46620c FMADD	D20, D26, D19, D25

0x466210 FCMPE	D30, #0

0x466214 FCSEL	D25, D20, D25, #4

0x466218 B	465b0c

0x46625c UBFM	X1, X11, #61, #60

0x466260 LDR	D19, [X28, X1]

0x466264 FMADD	D30, D26, D28, D19

0x466268 STR	D30, [X28, X1]

0x46626c CMP	X22, X5

0x466270 B.NE	465bac

0x466274 LDR	D20, [X26, X3,LSL #3]

0x466278 FMUL	D22, D20, D24

0x46627c FMADD	D23, D26, D20, D25

0x466280 FCMPE	D22, #0

0x466284 FCSEL	D25, D23, D25, #4

0x466288 B	465bac

0x46628c LDR	X1, [SP, #112]

0x466290 LDR	X10, [SP, #192]

0x466294 LDR	D4, [X26, X1,LSL #3]

0x466298 CMP	X10, #1

0x46629c B.GT	465694

0x4662a0 FCMP	D15, #0

0x4662a4 B.NE	464100

0x4662a8 FADD	D25, D25, D4

0x4662ac B	464100

0x4662b0 FMOV	D31, D15

0x4662b4 ORR	X3, XZR, X9

0x4662b8 B	464860

  (983) 0x4662bc UBFM	X7, X0, #61, #60

  (983) 0x4662c0 LDR	D27, [X28, X7]

  (983) 0x4662c4 FMADD	D7, D26, D1, D27

  (983) 0x4662c8 STR	D7, [X28, X7]

  (983) 0x4662cc B	465f94

  (979) 0x4662d0 ORN	X3, XZR, X9

  (979) 0x4662d4 LDR	X1, [X23, X3,LSL #3]

  (979) 0x4662d8 CMP	X27, X1

  (979) 0x4662dc B.GT	465490

  (979) 0x4662e0 B	465488

  (979) 0x4662e4 ORN	X0, XZR, X9

  (979) 0x4662e8 LDR	X3, [X23, X0,LSL #3]

  (979) 0x4662ec CMP	X27, X3

  (979) 0x4662f0 B.GT	466308

  (979) 0x4662f4 UBFM	X1, X3, #61, #60

  (979) 0x4662f8 LDR	D22, [X14, X4,LSL #3]

  (979) 0x4662fc LDR	D23, [X7, X1]

  (979) 0x466300 FMADD	D1, D16, D22, D23

  (979) 0x466304 STR	D1, [X7, X1]

  (979) 0x466308 ADD	X4, X4, #1

  (979) 0x46630c CMP	X18, X4

  (979) 0x466310 B.EQ	465078

  (979) 0x466314 LDR	X9, [SP, #128]

    (981) 0x466318 LDR	X0, [X8, X4,LSL #3]

    (981) 0x46631c CMP	X10, X0

    (981) 0x466320 CCMP	X2, X0, #0, #12

    (981) 0x466324 B.LE	46645c

    (981) 0x466328 ORN	X3, XZR, X0

    (981) 0x46632c LDR	X1, [X23, X3,LSL #3]

    (981) 0x466330 CMP	X27, X1

    (981) 0x466334 B.LE	46665c

    (981) 0x466338 ADD	X0, X4, #1

    (981) 0x46633c LDR	X4, [X8, X0,LSL #3]

    (981) 0x466340 CMP	X10, X4

    (981) 0x466344 CCMP	X2, X4, #0, #12

    (981) 0x466348 B.GT	466434

    (981) 0x46634c SUB	X1, X4, X2

    (981) 0x466350 LDR	X3, [X19, X1,LSL #3]

    (981) 0x466354 CMP	X9, X3

    (981) 0x466358 B.LE	466644

    (981) 0x46635c CMP	X22, X1

    (981) 0x466360 B.NE	46636c

    (981) 0x466364 LDR	D22, [X14, X0,LSL #3]

    (981) 0x466368 FMADD	D25, D16, D22, D25

    (981) 0x46636c ADD	X3, X0, #1

    (981) 0x466370 LDR	X1, [X8, X3,LSL #3]

    (981) 0x466374 CMP	X10, X1

    (981) 0x466378 CCMP	X2, X1, #0, #12

    (981) 0x46637c B.GT	46640c

    (981) 0x466380 SUB	X1, X1, X2

    (981) 0x466384 LDR	X4, [X19, X1,LSL #3]

    (981) 0x466388 CMP	X9, X4

    (981) 0x46638c B.LE	46662c

    (981) 0x466390 CMP	X22, X1

    (981) 0x466394 B.NE	4663a0

    (981) 0x466398 LDR	D18, [X14, X3,LSL #3]

    (981) 0x46639c FMADD	D25, D16, D18, D25

    (981) 0x4663a0 ADD	X3, X0, #2

    (981) 0x4663a4 LDR	X1, [X8, X3,LSL #3]

    (981) 0x4663a8 CMP	X10, X1

    (981) 0x4663ac CCMP	X2, X1, #0, #12

    (981) 0x4663b0 B.GT	4663e4

    (981) 0x4663b4 SUB	X1, X1, X2

    (981) 0x4663b8 LDR	X4, [X19, X1,LSL #3]

    (981) 0x4663bc CMP	X9, X4

    (981) 0x4663c0 B.LE	466614

    (981) 0x4663c4 CMP	X22, X1

    (981) 0x4663c8 B.NE	4663d4

    (981) 0x4663cc LDR	D26, [X14, X3,LSL #3]

    (981) 0x4663d0 FMADD	D25, D16, D26, D25

    (981) 0x4663d4 ADD	X4, X0, #3

    (981) 0x4663d8 CMP	X18, X4

    (981) 0x4663dc B.NE	466318

  (979) 0x4663e0 B	465078

    (981) 0x4663e4 ORN	X4, XZR, X1

    (981) 0x4663e8 LDR	X1, [X23, X4,LSL #3]

    (981) 0x4663ec CMP	X27, X1

    (981) 0x4663f0 B.GT	4663d4

    (981) 0x4663f4 UBFM	X4, X1, #61, #60

    (981) 0x4663f8 LDR	D21, [X14, X3,LSL #3]

    (981) 0x4663fc LDR	D6, [X7, X4]

    (981) 0x466400 FMADD	D17, D16, D21, D6

    (981) 0x466404 STR	D17, [X7, X4]

    (981) 0x466408 B	4663d4

    (981) 0x46640c ORN	X4, XZR, X1

    (981) 0x466410 LDR	X1, [X23, X4,LSL #3]

    (981) 0x466414 CMP	X27, X1

    (981) 0x466418 B.GT	4663a0

    (981) 0x46641c UBFM	X4, X1, #61, #60

    (981) 0x466420 LDR	D23, [X14, X3,LSL #3]

    (981) 0x466424 LDR	D1, [X7, X4]

    (981) 0x466428 FMADD	D0, D16, D23, D1

    (981) 0x46642c STR	D0, [X7, X4]

    (981) 0x466430 B	4663a0

    (981) 0x466434 ORN	X3, XZR, X4

    (981) 0x466438 LDR	X1, [X23, X3,LSL #3]

    (981) 0x46643c CMP	X27, X1

    (981) 0x466440 B.GT	46636c

    (981) 0x466444 UBFM	X4, X1, #61, #60

    (981) 0x466448 LDR	D26, [X14, X0,LSL #3]

    (981) 0x46644c LDR	D28, [X7, X4]

    (981) 0x466450 FMADD	D29, D16, D26, D28

    (981) 0x466454 STR	D29, [X7, X4]

    (981) 0x466458 B	46636c

    (981) 0x46645c SUB	X3, X0, X2

    (981) 0x466460 LDR	X1, [X19, X3,LSL #3]

    (981) 0x466464 CMP	X9, X1

    (981) 0x466468 B.GT	466480

    (981) 0x46646c UBFM	X0, X1, #61, #60

    (981) 0x466470 LDR	D17, [X14, X4,LSL #3]

    (981) 0x466474 LDR	D4, [X28, X0]

    (981) 0x466478 FMADD	D31, D16, D17, D4

    (981) 0x46647c STR	D31, [X28, X0]

    (981) 0x466480 CMP	X22, X3

    (981) 0x466484 B.NE	466338

    (981) 0x466488 LDR	D24, [X14, X4,LSL #3]

    (981) 0x46648c FMADD	D25, D16, D24, D25

    (981) 0x466490 B	466338

0x4665dc LDR	X5, [SP, #280]

0x4665e0 LDR	D16, [X5, X7]

0x4665e4 FMUL	D5, D16, D24

0x4665e8 FADD	D18, D31, D16

0x4665ec FCMPE	D5, #0

0x4665f0 FCSEL	D31, D18, D31, #4

0x4665f4 B	46590c

0x4665f8 LDR	X8, [SP, #280]

0x4665fc LDR	D21, [X8, X1]

0x466600 FMUL	D6, D21, D24

0x466604 FADD	D17, D31, D21

0x466608 FCMPE	D6, #0

0x46660c FCSEL	D31, D17, D31, #4

0x466610 B	465930

    (981) 0x466614 UBFM	X4, X4, #61, #60

    (981) 0x466618 LDR	D4, [X14, X3,LSL #3]

    (981) 0x46661c LDR	D31, [X28, X4]

    (981) 0x466620 FMADD	D24, D16, D4, D31

    (981) 0x466624 STR	D24, [X28, X4]

    (981) 0x466628 B	4663c4

    (981) 0x46662c UBFM	X4, X4, #61, #60

    (981) 0x466630 LDR	D27, [X14, X3,LSL #3]

    (981) 0x466634 LDR	D7, [X28, X4]

    (981) 0x466638 FMADD	D5, D16, D27, D7

    (981) 0x46663c STR	D5, [X28, X4]

    (981) 0x466640 B	466390

    (981) 0x466644 UBFM	X4, X3, #61, #60

    (981) 0x466648 LDR	D19, [X14, X0,LSL #3]

    (981) 0x46664c LDR	D20, [X28, X4]

    (981) 0x466650 FMADD	D30, D16, D19, D20

    (981) 0x466654 STR	D30, [X28, X4]

    (981) 0x466658 B	46635c

    (981) 0x46665c UBFM	X0, X1, #61, #60

    (981) 0x466660 LDR	D18, [X14, X4,LSL #3]

    (981) 0x466664 LDR	D21, [X7, X0]

    (981) 0x466668 FMADD	D6, D16, D18, D21

    (981) 0x46666c STR	D6, [X7, X0]

    (981) 0x466670 B	466338

  (979) 0x466674 ORN	X3, XZR, X0

  (979) 0x466678 LDR	X9, [X23, X3,LSL #3]

  (979) 0x46667c CMP	X27, X9

  (979) 0x466680 B.LE	465454

  (979) 0x466684 ADD	X0, X4, #1

  (979) 0x466688 B	465460

0x46668c LDR	X0, [SP, #280]

0x466690 LDR	D19, [X0, X25,LSL #3]

0x466694 FMUL	D30, D19, D24

0x466698 FCMPE	D30, #0

0x46669c B.GE	465d38

0x4666a0 UBFM	X7, X9, #61, #60

0x4666a4 LDR	D20, [X3, X7]

0x4666a8 FMADD	D22, D26, D19, D20

0x4666ac STR	D22, [X3, X7]

0x4666b0 B	465d38

0x466704 LDR	D17, [X26, X3,LSL #3]

0x466708 FMUL	D4, D17, D24

0x46670c FMADD	D31, D26, D17, D25

0x466710 FCMPE	D4, #0

0x466714 FCSEL	D25, D31, D25, #4

0x466718 B	465b88

0x46671c UBFM	X7, X0, #61, #60

0x466720 LDR	D1, [X28, X7]

0x466724 FMADD	D0, D26, D22, D1

0x466728 STR	D0, [X28, X7]

0x46672c CMP	X22, X9

0x466730 B.NE	465b4c

0x466734 LDR	D27, [X26, X3,LSL #3]

0x466738 ADD	X3, X3, #1

0x46673c FMUL	D7, D27, D24

0x466740 FMADD	D16, D26, D27, D25

0x466744 FCMPE	D7, #0

0x466748 FCSEL	D25, D16, D25, #4

0x46674c B	465b50

  (979) 0x466750 LDR	D30, [X14, X4,LSL #3]

  (979) 0x466754 ADD	X4, X4, #1

  (979) 0x466758 FMADD	D25, D16, D30, D25

  (979) 0x46675c B	465648

0x466760 UBFM	X4, X0, #61, #60

0x466764 ADD	X25, X25, #1

0x466768 LDR	D6, [X3, X4]

0x46676c FMADD	D17, D26, D18, D6

0x466770 STR	D17, [X3, X4]

0x466774 B	465cf0

0x466778 UBFM	X1, X11, #61, #60

0x46677c LDR	D16, [X3, X1]

0x466780 FMADD	D5, D26, D27, D16

0x466784 STR	D5, [X3, X1]

0x466788 B	465cc4

0x46678c UBFM	X8, X7, #61, #60

0x466790 LDR	D1, [X3, X8]

0x466794 FMADD	D0, D26, D22, D1

0x466798 STR	D0, [X3, X8]

0x46679c B	465c9c

0x4667a0 UBFM	X9, X5, #61, #60

0x4667a4 LDR	D30, [X3, X9]

0x4667a8 FMADD	D20, D26, D29, D30

0x4667ac STR	D20, [X3, X9]

0x4667b0 B	465c74

  (979) 0x4667b4 LDR	D31, [X14, X4,LSL #3]

  (979) 0x4667b8 FMADD	D25, D16, D31, D25

  (979) 0x4667bc B	465600

0x4667c0 UBFM	X10, X4, #61, #60

0x4667c4 LDR	D31, [X3, X10]

0x4667c8 FMADD	D28, D26, D17, D31

0x4667cc STR	D28, [X3, X10]

0x4667d0 B	465c4c

0x4667d4 FCMP	D31, #0

0x4667d8 B.EQ	464a30

0x4667dc FDIV	D26, D4, D31

0x4667e0 CMP	X9, X4

0x4667e4 B.LT	465ae0

0x4667e8 B	464100

  (979) 0x4667ec FCMP	D15, #0

  (979) 0x4667f0 B.EQ	4650d8

  (979) 0x4667f4 B	465078

0x4667f8 MOVZ	X5, #0

0x4667fc B	464464

0x46680c MOVZ	X10, #0

0x466810 B	4642ec

0x466814 ORR	X11, XZR, X25

0x466818 B	4657cc

  (979) 0x466824 ORN	X0, XZR, X9

  (979) 0x466828 LDR	X3, [X23, X0,LSL #3]

  (979) 0x46682c CMP	X27, X3

  (979) 0x466830 B.GT	465644

  (979) 0x466834 UBFM	X1, X3, #61, #60

  (979) 0x466838 LDR	D24, [X14, X4,LSL #3]

  (979) 0x46683c ADD	X4, X4, #1

  (979) 0x466840 LDR	D26, [X7, X1]

  (979) 0x466844 FMADD	D28, D16, D24, D26

  (979) 0x466848 STR	D28, [X7, X1]

  (979) 0x46684c B	465648

  (979) 0x466868 ORN	X9, XZR, X0

  (979) 0x46686c LDR	X3, [X23, X9,LSL #3]

  (979) 0x466870 CMP	X27, X3

  (979) 0x466874 B.GT	465600

  (979) 0x466878 UBFM	X1, X3, #61, #60

  (979) 0x46687c LDR	D5, [X14, X4,LSL #3]

  (979) 0x466880 LDR	D18, [X7, X1]

  (979) 0x466884 FMADD	D21, D16, D5, D18

  (979) 0x466888 STR	D21, [X7, X1]

  (979) 0x46688c B	465600

0x466890 LDR	X10, [SP, #280]

0x466894 LDR	X8, [SP, #304]

0x466898 B	465d50

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c: 1196 - 1756

--------------------------------------------------------------------------------

1196: #pragma omp parallel private(i,my_thread_num,num_threads,start,stop,coarse_counter,jj_counter,jj_counter_offd, P_marker, P_marker_offd,jj,kk,i1,k1,loc_col,jj_begin_row,jj_begin_row_offd,jj_end_row,jj_end_row_offd,diagonal,sum,sgn,jj1,i2,distribute,strong_f_marker)

[...]

1469:        for (i = start; i < stop; i++)

1470:        {

1471:          jj_begin_row = P_diag_i[i];

1472:          jj_begin_row_offd = P_offd_i[i];

1473:          jj_counter = jj_begin_row;

1474:          jj_counter_offd = jj_begin_row_offd;

[...]

1480:          if (CF_marker[i] >= 0)

1481:          {

1482:            P_diag_j[jj_counter]    = fine_to_coarse[i];

1483:            P_diag_data[jj_counter] = one;

[...]

1491:          else if (CF_marker[i] != -3)

1492:          {

1493:            strong_f_marker--;

1494:            for (jj = S_diag_i[i]; jj < S_diag_i[i+1]; jj++)

[...]

1503:              if (CF_marker[i1] >= 0)

1504:              {

1505:                if (P_marker[i1] < jj_begin_row)

1506:                {

1507:                  P_marker[i1] = jj_counter;

1508:                  P_diag_j[jj_counter]    = fine_to_coarse[i1];

1509:                  P_diag_data[jj_counter] = zero;

1510:                  jj_counter++;

1511:                }

1512:              }

1513:              else  if (CF_marker[i1] != -3)

1514:              {

1515:                P_marker[i1] = strong_f_marker;

1516:                for (kk = S_diag_i[i1]; kk < S_diag_i[i1+1]; kk++)

1517:                {

1518:                  k1 = S_diag_j[kk];

1519:                  if (CF_marker[k1] >= 0)

1520:                  {

1521:                    if(P_marker[k1] < jj_begin_row)

1522:                    {

1523:                      P_marker[k1] = jj_counter;

1524:                      P_diag_j[jj_counter] = fine_to_coarse[k1];

1525:                      P_diag_data[jj_counter] = zero;

1526:                      jj_counter++;

1527:                    }

1528:                  }

1529:                }

1530:                if(num_procs > 1)

1531:                {

1532:                  for (kk = S_offd_i[i1]; kk < S_offd_i[i1+1]; kk++)

1533:                  {

1534:                    if(col_offd_S_to_A)

1535:                     k1 = col_offd_S_to_A[S_offd_j[kk]];

1536:                    else

1537:                     k1 = S_offd_j[kk];

1538:                    if(CF_marker_offd[k1] >= 0)

1539:                    {

1540:                      if(P_marker_offd[k1] < jj_begin_row_offd)

1541:                      {

1542:                        P_marker_offd[k1] = jj_counter_offd;

1543:                        P_offd_j[jj_counter_offd] = k1;

1544:                        P_offd_data[jj_counter_offd] = zero;

1545:                        jj_counter_offd++;

[...]

1553:            if ( num_procs > 1)

1554:            {

1555:              for (jj=S_offd_i[i]; jj < S_offd_i[i+1]; jj++)

1556:              {

1557:                i1 = S_offd_j[jj];

1558:                if(col_offd_S_to_A)

1559:                  i1 = col_offd_S_to_A[i1];

1560:                if ( CF_marker_offd[i1] >= 0)

1561:                {

1562:                  if(P_marker_offd[i1] < jj_begin_row_offd)

1563:                  {

1564:                    P_marker_offd[i1] = jj_counter_offd;

1565:                    P_offd_j[jj_counter_offd] = i1;

1566:                    P_offd_data[jj_counter_offd] = zero;

1567:                    jj_counter_offd++;

1568:                  }

1569:                }

1570:                else if (CF_marker_offd[i1] != -3)

1571:                {

1572:                  P_marker_offd[i1] = strong_f_marker;

1573:                  for(kk = Sop_i[i1]; kk < Sop_i[i1+1]; kk++)

1574:                  {

1575:                    k1 = Sop_j[kk];

1576:                    /* Find local col number */

1577:                    if(k1 >= col_1 && k1 < col_n)

1578:                    {

1579:                      loc_col = k1-col_1;

1580:                      if(P_marker[loc_col] < jj_begin_row)

1581:                      {

1582:                        P_marker[loc_col] = jj_counter;

1583:                        P_diag_j[jj_counter] = fine_to_coarse[loc_col];

1584:                        P_diag_data[jj_counter] = zero;

1585:                        jj_counter++;

1586:                      }

1587:                    }

1588:                    else

1589:                    {

1590:                      loc_col = -k1 - 1;

1591:                      if(P_marker_offd[loc_col] < jj_begin_row_offd)

1592:                      {

1593:                        P_marker_offd[loc_col] = jj_counter_offd;

1594:                        P_offd_j[jj_counter_offd]=loc_col;

1595:                        P_offd_data[jj_counter_offd] = zero;

1596:                        jj_counter_offd++;

[...]

1607:            diagonal = A_diag_data[A_diag_i[i]];

1608:

1609:            for (jj = A_diag_i[i]+1; jj < A_diag_i[i+1]; jj++)

1610:            { /* i1 is a c-point and strongly influences i, accumulate

1611:               * a_(i,i1) into interpolation weight */

1612:              i1 = A_diag_j[jj];

1613:              if (P_marker[i1] >= jj_begin_row)

1614:              {

1615:                P_diag_data[P_marker[i1]] += A_diag_data[jj];

1616:              }

1617:              else if(P_marker[i1] == strong_f_marker)

1618:              {

1619:                sum = zero;

1620:                sgn = 1;

1621:                if(A_diag_data[A_diag_i[i1]] < 0) sgn = -1;

1622:                /* Loop over row of A for point i1 and calculate the sum

1623:                 * of the connections to c-points that strongly influence i. */

1624:                for(jj1 = A_diag_i[i1]+1; jj1 < A_diag_i[i1+1]; jj1++)

1625:                {

1626:                  i2 = A_diag_j[jj1];

1627:                  if((P_marker[i2] >= jj_begin_row || i2 == i) && (sgn*A_diag_data[jj1]) < 0)

1628:                    sum += A_diag_data[jj1];

1629:                }

1630:                if(num_procs > 1)

1631:                {

1632:                  for(jj1 = A_offd_i[i1]; jj1< A_offd_i[i1+1]; jj1++)

1633:                  {

1634:                    i2 = A_offd_j[jj1];

1635:                    if(P_marker_offd[i2] >= jj_begin_row_offd &&

1636:                       (sgn*A_offd_data[jj1]) < 0)

1637:                       sum += A_offd_data[jj1];

1638:                  }

1639:                }

1640:                if(sum != 0)

1641:                {

1642:                  distribute = A_diag_data[jj]/sum;

1643:                  /* Loop over row of A for point i1 and do the distribution */

1644:                  for(jj1 = A_diag_i[i1]+1; jj1 < A_diag_i[i1+1]; jj1++)

1645:                  {

1646:                    i2 = A_diag_j[jj1];

1647:                    if(P_marker[i2] >= jj_begin_row && (sgn*A_diag_data[jj1]) < 0)

1648:                       P_diag_data[P_marker[i2]] +=

1649:                       distribute*A_diag_data[jj1];

1650:                        if(i2 == i && (sgn*A_diag_data[jj1]) < 0)

1651:                          diagonal += distribute*A_diag_data[jj1];

1652:                  }

1653:                  if(num_procs > 1)

1654:                  {

1655:                    for(jj1 = A_offd_i[i1]; jj1 < A_offd_i[i1+1]; jj1++)

1656:                    {

1657:                      i2 = A_offd_j[jj1];

1658:                      if(P_marker_offd[i2] >= jj_begin_row_offd &&

1659:                                 (sgn*A_offd_data[jj1]) < 0)

1660:                        P_offd_data[P_marker_offd[i2]] +=

[...]

1667:                  diagonal += A_diag_data[jj];

1668:                }

1669:              }

1670:              /* neighbor i1 weakly influences i, accumulate a_(i,i1) into

1671:               * diagonal */

1672:              else if (CF_marker[i1] != -3)

1673:              {

1674:                if(num_functions == 1 || dof_func[i] == dof_func[i1])

1675:                  diagonal += A_diag_data[jj];

1676:              }

1677:            }

1678:            if(num_procs > 1)

1679:            {

1680:              for(jj = A_offd_i[i]; jj < A_offd_i[i+1]; jj++)

1681:              {

1682:                i1 = A_offd_j[jj];

1683:                if(P_marker_offd[i1] >= jj_begin_row_offd)

1684:                  P_offd_data[P_marker_offd[i1]] += A_offd_data[jj];

1685:                else if(P_marker_offd[i1] == strong_f_marker)

1686:                {

1687:                  sum = zero;

1688:                  for(jj1 = A_ext_i[i1]; jj1 < A_ext_i[i1+1]; jj1++)

1689:                  {

1690:                    k1 = A_ext_j[jj1];

1691:                    if(k1 >= col_1 && k1 < col_n)

1692:                    { /* diag */

1693:                      loc_col = k1 - col_1;

1694:                      if(P_marker[loc_col] >= jj_begin_row || loc_col == i)

1695:                        sum += A_ext_data[jj1];

1696:                    }

1697:                    else

1698:                    {

1699:                      loc_col = -k1 - 1;

1700:                      if(P_marker_offd[loc_col] >= jj_begin_row_offd)

1701:                        sum += A_ext_data[jj1];

1702:                    }

1703:                  }

1704:                  if(sum != 0)

1705:                  {

1706:                    distribute = A_offd_data[jj] / sum;

1707:                    for(jj1 = A_ext_i[i1]; jj1 < A_ext_i[i1+1]; jj1++)

1708:                    {

1709:                      k1 = A_ext_j[jj1];

1710:                      if(k1 >= col_1 && k1 < col_n)

1711:                      { /* diag */

1712:                        loc_col = k1 - col_1;

1713:                        if(P_marker[loc_col] >= jj_begin_row)

1714:                          P_diag_data[P_marker[loc_col]] += distribute*

1715:                           A_ext_data[jj1];

1716:                                if(loc_col == i)

1717:                                  diagonal += distribute*A_ext_data[jj1];

1718:                      }

1719:                      else

1720:                      {

1721:                        loc_col = -k1 - 1;

1722:                        if(P_marker_offd[loc_col] >= jj_begin_row_offd)

1723:                          P_offd_data[P_marker_offd[loc_col]] += distribute*

[...]

1730:                    diagonal += A_offd_data[jj];

1731:                  }

1732:                }

1733:                else if (CF_marker_offd[i1] != -3)

1734:                {

1735:                  if(num_functions == 1 || dof_func[i] == dof_func_offd[i1])

1736:                    diagonal += A_offd_data[jj];

1737:                }

1738:              }

1739:            }

1740:            if (diagonal)

1741:            {

1742:              for(jj = jj_begin_row; jj < jj_end_row; jj++)

1743:                 P_diag_data[jj] /= -diagonal;

1744:              for(jj = jj_begin_row_offd; jj < jj_end_row_offd; jj++)

1745:                 P_offd_data[jj] /= -diagonal;

1746:            }

1747:          }

1748:          strong_f_marker--;

[...]

1754:        if (n_fine)

1755:        {  hypre_TFree(P_marker); }

1756:        if (full_off_procNodes)

Coverage (%)	Name	Source Location	Module
►100.00+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.93
CQA speedup if FP arith vectorized	1.05
CQA speedup if fully vectorized	1.23
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.30
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildExtPIInterp._omp_fn.0
Source	par_lr_interp.c:1196-1196,par_lr_interp.c:1494-1494,par_lr_interp.c:1619-1619,par_lr_interp.c:1624-1637,par_lr_interp.c:1640-1655,par_lr_interp.c:1658-1660,par_lr_interp.c:1667-1667,par_lr_interp.c:1675-1675,par_lr_interp.c:1680-1680,par_lr_interp.c:1684-1684,par_lr_interp.c:1723-1723,par_lr_interp.c:1733-1735,par_lr_interp.c:1740-1745,par_lr_interp.c:1754-1756
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	98.25
CQA cycles if no scalar integer	33.50
CQA cycles if FP arith vectorized	93.95
CQA cycles if fully vectorized	80.16
Front-end cycles	98.25
P0 cycles	68.00
P1 cycles	68.00
P2 cycles	40.25
P3 cycles	40.25
P4 cycles	40.17
P5 cycles	40.17
P6 cycles	40.08
P7 cycles	40.08
P8 cycles	54.00
P9 cycles	54.00
P10 cycles	54.00
P11 cycles	54.00
P12 cycles	75.67
P13 cycles	75.67
P14 cycles	75.67
P15 cycles	3.50
P16 cycles	3.50
DIV/SQRT cycles	8.76 - 17.48
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	788.00
Nb uops	786.00
Nb loads	NA
Nb stores	30.00
Nb stack references	0.00
FLOP/cycle	1.42
Nb FLOP add-sub	35.00
Nb FLOP mul	70.00
Nb FLOP fma	15.00
Nb FLOP div	5.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.61
Bytes prefetched	0.00
Bytes loaded	1904.00
Bytes stored	416.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	25.25
Vectorization ratio load	33.33
Vectorization ratio store	40.00
Vectorization ratio mul	40.00
Vectorization ratio add_sub	28.57
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	18.27
Vector-efficiency ratio all	63.09
Vector-efficiency ratio load	67.33
Vector-efficiency ratio store	73.33
Vector-efficiency ratio mul	70.00
Vector-efficiency ratio add_sub	64.29
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	59.33

Metric	Value
CQA speedup if no scalar integer	2.93
CQA speedup if FP arith vectorized	1.05
CQA speedup if fully vectorized	1.23
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.30
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildExtPIInterp._omp_fn.0
Source	par_lr_interp.c:1196-1196,par_lr_interp.c:1494-1494,par_lr_interp.c:1619-1619,par_lr_interp.c:1624-1637,par_lr_interp.c:1640-1655,par_lr_interp.c:1658-1660,par_lr_interp.c:1667-1667,par_lr_interp.c:1675-1675,par_lr_interp.c:1680-1680,par_lr_interp.c:1684-1684,par_lr_interp.c:1723-1723,par_lr_interp.c:1733-1735,par_lr_interp.c:1740-1745,par_lr_interp.c:1754-1756
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	98.25
CQA cycles if no scalar integer	33.50
CQA cycles if FP arith vectorized	93.95
CQA cycles if fully vectorized	80.16
Front-end cycles	98.25
P0 cycles	68.00
P1 cycles	68.00
P2 cycles	40.25
P3 cycles	40.25
P4 cycles	40.17
P5 cycles	40.17
P6 cycles	40.08
P7 cycles	40.08
P8 cycles	54.00
P9 cycles	54.00
P10 cycles	54.00
P11 cycles	54.00
P12 cycles	75.67
P13 cycles	75.67
P14 cycles	75.67
P15 cycles	3.50
P16 cycles	3.50
DIV/SQRT cycles	8.76 - 17.48
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	788.00
Nb uops	786.00
Nb loads	NA
Nb stores	30.00
Nb stack references	0.00
FLOP/cycle	1.42
Nb FLOP add-sub	35.00
Nb FLOP mul	70.00
Nb FLOP fma	15.00
Nb FLOP div	5.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.61
Bytes prefetched	0.00
Bytes loaded	1904.00
Bytes stored	416.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	25.25
Vectorization ratio load	33.33
Vectorization ratio store	40.00
Vectorization ratio mul	40.00
Vectorization ratio add_sub	28.57
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	18.27
Vector-efficiency ratio all	63.09
Vector-efficiency ratio load	67.33
Vector-efficiency ratio store	73.33
Vector-efficiency ratio mul	70.00
Vector-efficiency ratio add_sub	64.29
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	59.33

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildExtPIInterp._omp_fn.0
Source file and lines	par_lr_interp.c:1196-1756
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1196,1469-1474,1480-1483,1491-1494,1503-1545,1553-1596,1607-1660,1667-1723,1730-1748,1754-1756.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1196,1494,1619,1624-1637,1640-1655,1658-1660,1667,1675,1680,1684,1723,1733-1735,1740-1745,1754-1756.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 98.25 to 33.50 cycles (2.93x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 63% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 98.25 to 80.16 cycles (1.23x speedup).

Details

25% of VPU instructions are used in vector version (process two or more data elements in vector registers):

33% of VPU loads are used in vector version.
40% of VPU stores are used in vector version.
28% of VPU addition or subtraction instructions are used in vector version.
40% of VPU multiply instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
18% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 98.25 to 0.50 cycles (196.50x speedup).

FMA

Detected 15 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 140 FP arithmetical operations:

50: addition or subtraction (15 inside FMA instructions)
85: multiply (15 inside FMA instructions)
5: divide

The binary loop is loading 1904 bytes. The binary loop is storing 416 bytes.

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	788
loop length	3152
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

98.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	68.00	68.00	40.25	40.25	40.17	40.17	40.08	40.08	54.00	54.00	54.00	54.00	75.67	75.67	75.67	3.50	3.50
cycles	68.00	68.00	40.25	40.25	40.17	40.17	40.08	40.08	54.00	54.00	54.00	54.00	75.67	75.67	75.67	3.50	3.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

8.76-17.48

Cycles summary

Front-end	98.25
Overall L1	98.25

Vectorization ratios

INT

all	23%
load	33%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	27%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	40%
add-sub	29%
fma	0%
div/sqrt	0%
other	25%

INT+FP

all	25%
load	33%
store	40%
mul	40%
add-sub	28%
fma	0%
div/sqrt	0%
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 98.25 cycles. At this rate:

20% of peak load performance is reached (19.38 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (4.23 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 464680

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
FCMP D25, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.EQ 463f40 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x9d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X22, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X2, X22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 464324 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xdb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X6, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMOV D19, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FDIV D20, D19, D25	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
SUB X8, X2, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X7, X8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X7, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LS 46680c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x32a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X24, X8, #2, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X1, X28, X6,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X18, X6, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DUP V30.2D, V20.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
UBFM X0, X24, #59, #58	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X3, X0, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X22, X1, X24,LSL #5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
UBFM X2, X3, #5, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X5, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ANDS X6, X5, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 46426c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xd00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 46424c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xce0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 464234 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xcc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q22, [X28, X18]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADD X1, X1, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR Q0, [X1, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FMUL V23.2D, V22.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V27.2D, V0.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FNEG V1.2D, V23.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FNEG V7.2D, V27.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR Q1, [X28, X18]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STUR Q7, [X1, #496]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q5, Q18, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
FMUL V21.2D, V5.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V6.2D, V18.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FNEG V17.2D, V21.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FNEG V4.2D, V6.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STP Q17, Q4, [X1], #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q31, Q24, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
FMUL V26.2D, V31.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V16.2D, V24.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FNEG V28.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FNEG V29.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STP Q28, Q29, [X1], #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
CMP X22, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4642e0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xd74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X10, X8, #8062	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ANDS XZR, X8, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 464324 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xdb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X8, X8, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DUP Z20.D, Z20.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
WHILELO P4.D, XZR, X8	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	3	1	N/A
PTRUE P7.B, VL16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
MOVZ X24, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
WHILELO P5.D, X24, X8	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD X0, X18, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z30.D}, P4/Z, [X28, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FMUL Z27.D, Z20.D, Z30.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FNEG Z27.D, P7/M, Z27.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD X10, X28, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ST1D {Z27.D}, P4, [X10, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
B.NE 4660c8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2b5c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X4, X27	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 463f40 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x9d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X22, X4, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X4, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMOV D18, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
SUB X3, X22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FDIV D25, D18, D25	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
LDR X6, [X4, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X3, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LS 4667f8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x328c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X2, X22, #2, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, X6, X27,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DUP V21.2D, V25.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
UBFM X1, X27, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X7, X2, #59, #58	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X24, X7, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X18, X0, X2,LSL #5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
UBFM X8, X24, #5, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ANDS X4, X10, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 4643e4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xe78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X4, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4643c4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xe58>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X4, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4643ac <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xe40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q6, [X6, X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR Q31, [X0, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FMUL V17.2D, V6.2D, V21.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V24.2D, V31.2D, V21.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FNEG V4.2D, V17.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FNEG V26.2D, V24.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR Q4, [X6, X1]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STUR Q26, [X0, #496]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q16, Q28, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
FMUL V19.2D, V16.2D, V21.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V29.2D, V28.2D, V21.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FNEG V22.2D, V19.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FNEG V23.2D, V29.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STP Q22, Q23, [X0], #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q1, Q0, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
FMUL V20.2D, V1.2D, V21.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V30.2D, V0.2D, V21.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FNEG V27.2D, V20.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FNEG V7.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STP Q27, Q7, [X0], #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
CMP X18, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 464458 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xeec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X5, X22, #8062	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ANDS XZR, X22, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 463f40 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x9d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X27, X27, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X22, X22, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DUP Z25.D, Z25.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
WHILELO P0.D, XZR, X22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	3	1	N/A
PTRUE P1.B, VL16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
LD1D {Z21.D}, P0/Z, [X6, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADD X6, X6, X27,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMUL Z4.D, Z21.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FNEG Z4.D, P1/M, Z4.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ST1D {Z4.D}, P0, [X6, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
MOVZ X5, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
WHILELO P6.D, X5, X22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	3	1	N/A
B.EQ 463f40 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x9d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LD1D {Z31.D}, P6/Z, [X6, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FMUL Z24.D, Z31.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FNEG Z24.D, P1/M, Z24.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ST1D {Z24.D}, P6, [X6, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
B 463f40 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x9d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X27, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X20, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CBNZ X20, 4653e4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1e78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X27, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CBNZ X16, 4653a0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1e34>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP D14, D15, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X29, X30, [SP], #384	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X5, X4, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X0, X5, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X10, X5, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X0, #7	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LS 4662b0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2d44>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X25, X7, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X1, X10, #2, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DUP Z6.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
DUP Z7.D, X22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR Z26.D, Z6.D, Z6.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD X7, X26, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X8, X12, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DUP Z16.D, X2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z17.D, Z24.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
PTRUE P7.B, VL16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
ADD X11, X7, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X25, X8, X1,LSL #5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ORR X3, XZR, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X7, X7, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TBZ W1, #0, 46478c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1220>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LD1D {Z18.D}, P7/Z, [X8, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LD1D {Z19.D}, P7/Z, [X8, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LD1D {Z20.D}, P7/Z, [X19, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
CMPEQ P5.D, P7/Z, Z18.D, Z7.D	1	0	0	0	0	0	0	1	0	1	0	0	0	0	0	0	0	0	4	1	vect (100.0%)
CMPGE P14.D, P7/Z, Z20.D, Z16.D	1	0	0	0	0	0	0	1	0	1	0	0	0	0	0	0	0	0	4	1	vect (100.0%)
LD1D {Z21.D}, P7/Z, [X19, Z19.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
CMPEQ P6.D, P7/Z, Z19.D, Z7.D	1	0	0	0	0	0	0	1	0	1	0	0	0	0	0	0	0	0	4	1	vect (100.0%)
CMPGE P15.D, P7/Z, Z21.D, Z16.D	1	0	0	0	0	0	0	1	0	1	0	0	0	0	0	0	0	0	4	1	vect (100.0%)
ADD X3, X8, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR P0.B, P7/Z, P5.B, P14.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
ORR P1.B, P7/Z, P6.B, P15.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
LD1D {Z22.D}, P0/Z, [X11, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LD1D {Z23.D}, P1/Z, [X7, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FMUL Z1.D, Z22.D, Z17.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL Z0.D, Z23.D, Z17.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FCMLT P2.D, P0/Z, Z1.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
FCMLT P3.D, P1/Z, Z0.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z26, Z6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FADD Z26.D, P2/M, Z26.D, Z22.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD Z6.D, P3/M, Z6.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
CMP X3, X25	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 464844 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x12d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X8, X10, #8062	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FADD Z6.D, Z26.D, Z6.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADDV D7, P7, Z6.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	vect (100.0%)
FADD D31, D15, D7	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X3, X8, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ANDS XZR, X10, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 464a14 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x14a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X25, X3, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X10, [X12, X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X19, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X2, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X10, X22, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
B.NE 46488c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1320>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D16, [X26, X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D17, D16, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FADD D26, D31, D16	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMPE D17, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D31, D26, D31, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X7, X3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X7, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 464a14 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x14a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X25, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X5, [X12, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X19, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X2, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X22, X5, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
B.NE 4648c4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1358>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D28, [X26, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D29, D28, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FADD D30, D31, D28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMPE D29, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D31, D30, D31, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X8, X3, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X4, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 464a14 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x14a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X11, X25, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X7, [X12, X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X19, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X2, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X7, X22, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
B.NE 4648fc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1390>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D4, [X26, X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D5, D4, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FADD D18, D31, D4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMPE D5, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D31, D18, D31, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X0, X3, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X4, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 464a14 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x14a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X5, X25, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X1, [X12, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X19, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X2, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X22, X1, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
B.NE 464934 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x13c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D19, [X26, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D20, D19, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FADD D21, D31, D19	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMPE D20, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D31, D21, D31, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X11, X3, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X4, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 464a14 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x14a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X25, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X7, [X12, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X19, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X2, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X22, X7, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
B.NE 46496c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1400>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D22, [X26, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D23, D22, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FADD D1, D31, D22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMPE D23, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D31, D1, D31, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X5, X3, #5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X4, X5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 464a14 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x14a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X1, X25, #40	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [X12, X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X19, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X2, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X22, X8, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
B.NE 4649a4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1438>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D0, [X26, X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D27, D0, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FADD D6, D31, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMPE D27, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D31, D6, D31, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X0, X3, #6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X4, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 464a14 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x14a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X5, X25, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X7, [X12, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X19, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X2, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X22, X7, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
B.NE 4649dc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1470>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D7, [X26, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D16, D7, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FADD D17, D31, D7	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMPE D16, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D31, D17, D31, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X3, X3, #7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X4, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 464a14 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x14a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X25, X25, #56	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X1, [X12, X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X19, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X2, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X22, X1, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
B.NE 464a14 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x14a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D26, [X26, X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D28, D24, D26	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FADD D29, D31, D26	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMPE D28, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D31, D29, D31, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
LDR X11, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D4, [X26, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
CMP X0, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 4656a0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D31, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.NE 465adc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2570>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FADD D25, D25, D4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
B 464100 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xb94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X6, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [X6, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X6, X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X5, X18	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4641a0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xc34>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X24, XZR, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X25, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X25, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X10, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X0, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X0, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X0, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X6, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X18, X14, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X8, X14, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X12, X9, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X12, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 46508c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1b20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X4, XZR, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X11, XZR, X24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X12, X9, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X25, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 4641a0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xc34>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 546e20 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 464688 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x111c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D31, D15	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
LDR X10, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X7, X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X7, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X25, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4667d4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3268>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X7, X3, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X1, X7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X1, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LS 466814 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x32a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X17, X25,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X5, X7, #2, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DUP Z5.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
DUP Z18.D, X27	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR Z6.D, Z5.D, Z5.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP Z21.D, Z24.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
PTRUE P7.B, VL16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
ADD X1, X8, X5,LSL #5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ORR X3, XZR, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, X0, X25,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X11, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X10, X0, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TBNZ W5, #0, 465fb4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2a48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X24, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X19, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X24, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X19, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
AND X8, X7, #8062	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FADD Z5.D, Z6.D, Z5.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADDV D18, P7, Z5.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	vect (100.0%)
FADD D31, D31, D18	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X11, X8, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ANDS XZR, X7, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 465930 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x23c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X1, X11, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X7, [X17, X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X23, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X27, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 4657f8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x228c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D21, [X5, X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D6, D21, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FADD D17, D31, D21	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMPE D6, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D31, D17, D31, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
LDR X0, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X3, X11, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X3, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 465930 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x23c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X7, X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [X17, X7]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X23, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X27, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 465834 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x22c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D26, [X5, X7]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D28, D26, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FADD D29, D31, D26	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMPE D28, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D31, D29, D31, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
LDR X0, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X3, X11, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X0, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 465930 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x23c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X7, X1, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [X17, X7]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X23, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X27, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 465870 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2304>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D30, [X5, X7]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D19, D30, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FADD D20, D31, D30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMPE D19, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D31, D20, D31, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
LDR X0, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X3, X11, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X0, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 465930 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x23c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X7, X1, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [X17, X7]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X23, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X27, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 4658ac <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2340>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D22, [X5, X7]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D23, D24, D22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FADD D1, D31, D22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMPE D23, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D31, D1, D31, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
LDR X0, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X3, X11, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X0, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 465930 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x23c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X7, X1, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [X17, X7]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X23, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X27, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 4658e8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x237c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D0, [X5, X7]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D27, D0, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FADD D7, D31, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMPE D27, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D31, D7, D31, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
LDR X0, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X3, X11, #5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X0, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 465930 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x23c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X7, X1, #40	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [X17, X7]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X23, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X27, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4665dc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3070>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X11, X11, #6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X3, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 465930 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x23c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X1, X1, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X0, [X17, X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X27, X7	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4665f8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x308c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D31, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.EQ 464a30 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x14c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV D26, D4, D31	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
CMP X9, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 465ae0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2574>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 465bdc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2670>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV D26, D4, D31	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
LDR X25, [X12, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORN X10, XZR, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, X10, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND X11, X5, #4160	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X3, [X19, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X2, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 4661fc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2c90>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D31, [X26, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D4, D31, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FCMPE D4, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.MI 4661ec <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2c80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X3, X9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X4, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 465bb8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x264c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ X11, 465f84 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2a18>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X11, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 465b8c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2620>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X11, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 465b50 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x25e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X12, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X19, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X2, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 46672c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x31c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D22, [X26, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D23, D22, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FCMPE D23, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.MI 46671c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x31b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X3, X3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [X12, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X19, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X2, X25	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 465b80 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2614>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D5, [X26, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D18, D5, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FCMPE D18, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.GE 465b88 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x261c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X10, X25, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D21, [X28, X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMADD D6, D26, D5, D21	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
STR D6, [X28, X10]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X22, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 466704 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3198>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X3, X3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X5, [X12, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X19, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X2, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 46626c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2d00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D28, [X26, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D29, D28, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FCMPE D29, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.MI 46625c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2cf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X3, X3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X4, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 465f84 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2a18>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X4, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 464100 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xb94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X10, X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X10, X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X5, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X25, X5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 464100 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xb94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X1, X5, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ANDS X9, X1, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LDR X3, [X0, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B.EQ 466890 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3324>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 465d28 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x27bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 465cf0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2784>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 465cc8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x275c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 465ca0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2734>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 465c78 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x270c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 465c50 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x26e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X7, [X17, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X23, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X27, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 465c4c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x26e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D17, [X8, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D4, D17, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FCMPE D4, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.MI 4667c0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3254>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X25, X25, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X11, [X17, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X23, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X27, X5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 465c74 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2708>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D29, [X1, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D19, D29, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FCMPE D19, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.MI 4667a0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3234>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X25, X25, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X0, [X17, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X27, X7	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 465c9c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2730>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D22, [X4, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D23, D22, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FCMPE D23, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.MI 46678c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3220>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X25, X25, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X10, [X17, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X23, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X27, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 465cc4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2758>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D27, [X5, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D7, D27, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FCMPE D7, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.MI 466778 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x320c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X25, X25, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X9, [X17, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X23, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X27, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 465cec <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2780>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X7, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D18, [X7, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D21, D18, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FCMPE D21, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.MI 466760 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x31f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X25, X25, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [X17, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X23, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X27, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 465d24 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x27b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D4, [X11, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D31, D4, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FCMPE D31, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.GE 465d24 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x27b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X5, X10, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D28, [X3, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMADD D29, D26, D4, D28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
STR D29, [X3, X5]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
ADD X25, X25, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X1, [X17, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X27, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 46668c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X25, X25, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X25, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 464100 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xb94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X8, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 464100 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xb94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LD1D {Z30.D}, P7/Z, [X8, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LD1D {Z19.D}, P7/Z, [X8, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LD1D {Z20.D}, P7/Z, [X23, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LD1D {Z22.D}, P7/Z, [X23, Z19.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
CMPGE P0.D, P7/Z, Z20.D, Z18.D	1	0	0	0	0	0	0	1	0	1	0	0	0	0	0	0	0	0	4	1	vect (100.0%)
CMPGE P6.D, P7/Z, Z22.D, Z18.D	1	0	0	0	0	0	0	1	0	1	0	0	0	0	0	0	0	0	4	1	vect (100.0%)
ADD X3, X8, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z23.D}, P6/Z, [X0, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADD X5, X10, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMUL Z0.D, Z23.D, Z21.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
LD1D {Z1.D}, P0/Z, [X5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FCMLT P1.D, P6/Z, Z0.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
FMUL Z27.D, Z1.D, Z21.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FCMLT P2.D, P0/Z, Z27.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z6, Z5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FADD Z6.D, P2/M, Z6.D, Z1.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD Z5.D, P1/M, Z5.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
CMP X3, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 465708 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x219c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4657b0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2244>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LD1D {Z7.D}, P5/Z, [X10, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FMUL Z5.D, Z20.D, Z7.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FNEG Z5.D, P7/M, Z5.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ST1D {Z5.D}, P5, [X10, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
B 464324 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xdb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X1, X3, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D28, [X28, X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMADD D29, D26, D31, D28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
STR D29, [X28, X1]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X22, X25	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 465b0c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x25a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D19, [X26, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D30, D19, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FMADD D20, D26, D19, D25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
FCMPE D30, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D25, D20, D25, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
B 465b0c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x25a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X1, X11, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D19, [X28, X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMADD D30, D26, D28, D19	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
STR D30, [X28, X1]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X22, X5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 465bac <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2640>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D20, [X26, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D22, D20, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FMADD D23, D26, D20, D25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
FCMPE D22, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D25, D23, D25, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
B 465bac <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2640>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D4, [X26, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
CMP X10, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 465694 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D15, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.NE 464100 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xb94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FADD D25, D25, D4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
B 464100 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xb94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D31, D15	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ORR X3, XZR, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 464860 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x12f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D16, [X5, X7]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D5, D16, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FADD D18, D31, D16	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMPE D5, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D31, D18, D31, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
B 46590c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x23a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D21, [X8, X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D6, D21, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FADD D17, D31, D21	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMPE D6, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D31, D17, D31, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
B 465930 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x23c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D19, [X0, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D30, D19, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FCMPE D30, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.GE 465d38 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x27cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X7, X9, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D20, [X3, X7]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMADD D22, D26, D19, D20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
STR D22, [X3, X7]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
B 465d38 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x27cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D17, [X26, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D4, D17, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FMADD D31, D26, D17, D25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
FCMPE D4, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D25, D31, D25, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
B 465b88 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x261c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X7, X0, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D1, [X28, X7]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMADD D0, D26, D22, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
STR D0, [X28, X7]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X22, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 465b4c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x25e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D27, [X26, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X3, X3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMUL D7, D27, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FMADD D16, D26, D27, D25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
FCMPE D7, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D25, D16, D25, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
B 465b50 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x25e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X4, X0, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X25, X25, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D6, [X3, X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMADD D17, D26, D18, D6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
STR D17, [X3, X4]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
B 465cf0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2784>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X1, X11, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D16, [X3, X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMADD D5, D26, D27, D16	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
STR D5, [X3, X1]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
B 465cc4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2758>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X8, X7, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D1, [X3, X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMADD D0, D26, D22, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
STR D0, [X3, X8]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
B 465c9c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2730>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X9, X5, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D30, [X3, X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMADD D20, D26, D29, D30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
STR D20, [X3, X9]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
B 465c74 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2708>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X10, X4, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D31, [X3, X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMADD D28, D26, D17, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
STR D28, [X3, X10]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
B 465c4c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x26e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D31, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.EQ 464a30 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x14c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV D26, D4, D31	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
CMP X9, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 465ae0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2574>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 464100 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xb94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X5, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 464464 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xef8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X10, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 4642ec <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xd80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X11, XZR, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 4657cc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2260>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 465d50 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x27e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_BoomerAMGBuildExtPIInterp._omp_fn.0
Source file and lines	par_lr_interp.c:1196-1756
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

25% of VPU instructions are used in vector version (process two or more data elements in vector registers):

33% of VPU loads are used in vector version.
40% of VPU stores are used in vector version.
28% of VPU addition or subtraction instructions are used in vector version.
40% of VPU multiply instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
18% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 98.25 to 0.50 cycles (196.50x speedup).

FMA

Detected 15 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 140 FP arithmetical operations:

50: addition or subtraction (15 inside FMA instructions)
85: multiply (15 inside FMA instructions)
5: divide

The binary loop is loading 1904 bytes. The binary loop is storing 416 bytes.

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	788
loop length	3152
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

98.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	68.00	68.00	40.25	40.25	40.17	40.17	40.08	40.08	54.00	54.00	54.00	54.00	75.67	75.67	75.67	3.50	3.50
cycles	68.00	68.00	40.25	40.25	40.17	40.17	40.08	40.08	54.00	54.00	54.00	54.00	75.67	75.67	75.67	3.50	3.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

8.76-17.48

Cycles summary

Front-end	98.25
Overall L1	98.25

Vectorization ratios

INT

all	23%
load	33%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	27%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	40%
add-sub	29%
fma	0%
div/sqrt	0%
other	25%

INT+FP

all	25%
load	33%
store	40%
mul	40%
add-sub	28%
fma	0%
div/sqrt	0%
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 98.25 cycles. At this rate:

20% of peak load performance is reached (19.38 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (4.23 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 464680

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
FCMP D25, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.EQ 463f40 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x9d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X22, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X2, X22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 464324 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xdb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X6, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMOV D19, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FDIV D20, D19, D25	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
SUB X8, X2, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X7, X8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X7, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LS 46680c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x32a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X24, X8, #2, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X1, X28, X6,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X18, X6, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DUP V30.2D, V20.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
UBFM X0, X24, #59, #58	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X3, X0, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X22, X1, X24,LSL #5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
UBFM X2, X3, #5, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X5, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ANDS X6, X5, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 46426c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xd00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 46424c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xce0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 464234 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xcc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q22, [X28, X18]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADD X1, X1, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR Q0, [X1, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FMUL V23.2D, V22.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V27.2D, V0.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FNEG V1.2D, V23.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FNEG V7.2D, V27.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR Q1, [X28, X18]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STUR Q7, [X1, #496]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q5, Q18, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
FMUL V21.2D, V5.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V6.2D, V18.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FNEG V17.2D, V21.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FNEG V4.2D, V6.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STP Q17, Q4, [X1], #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q31, Q24, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
FMUL V26.2D, V31.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V16.2D, V24.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FNEG V28.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FNEG V29.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STP Q28, Q29, [X1], #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
CMP X22, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4642e0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xd74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X10, X8, #8062	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ANDS XZR, X8, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 464324 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xdb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X8, X8, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DUP Z20.D, Z20.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
WHILELO P4.D, XZR, X8	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	3	1	N/A
PTRUE P7.B, VL16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
MOVZ X24, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
WHILELO P5.D, X24, X8	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD X0, X18, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z30.D}, P4/Z, [X28, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FMUL Z27.D, Z20.D, Z30.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FNEG Z27.D, P7/M, Z27.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD X10, X28, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ST1D {Z27.D}, P4, [X10, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
B.NE 4660c8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2b5c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X4, X27	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 463f40 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x9d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X22, X4, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X4, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMOV D18, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
SUB X3, X22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FDIV D25, D18, D25	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
LDR X6, [X4, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X3, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LS 4667f8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x328c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X2, X22, #2, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, X6, X27,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DUP V21.2D, V25.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
UBFM X1, X27, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X7, X2, #59, #58	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X24, X7, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X18, X0, X2,LSL #5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
UBFM X8, X24, #5, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ANDS X4, X10, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 4643e4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xe78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X4, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4643c4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xe58>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X4, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4643ac <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xe40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q6, [X6, X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR Q31, [X0, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FMUL V17.2D, V6.2D, V21.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V24.2D, V31.2D, V21.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FNEG V4.2D, V17.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FNEG V26.2D, V24.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR Q4, [X6, X1]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STUR Q26, [X0, #496]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q16, Q28, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
FMUL V19.2D, V16.2D, V21.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V29.2D, V28.2D, V21.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FNEG V22.2D, V19.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FNEG V23.2D, V29.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STP Q22, Q23, [X0], #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q1, Q0, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
FMUL V20.2D, V1.2D, V21.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V30.2D, V0.2D, V21.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FNEG V27.2D, V20.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FNEG V7.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STP Q27, Q7, [X0], #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
CMP X18, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 464458 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xeec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X5, X22, #8062	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ANDS XZR, X22, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 463f40 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x9d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X27, X27, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X22, X22, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DUP Z25.D, Z25.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
WHILELO P0.D, XZR, X22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	3	1	N/A
PTRUE P1.B, VL16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
LD1D {Z21.D}, P0/Z, [X6, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADD X6, X6, X27,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMUL Z4.D, Z21.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FNEG Z4.D, P1/M, Z4.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ST1D {Z4.D}, P0, [X6, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
MOVZ X5, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
WHILELO P6.D, X5, X22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	3	1	N/A
B.EQ 463f40 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x9d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LD1D {Z31.D}, P6/Z, [X6, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FMUL Z24.D, Z31.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FNEG Z24.D, P1/M, Z24.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ST1D {Z24.D}, P6, [X6, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
B 463f40 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x9d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X27, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X20, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CBNZ X20, 4653e4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1e78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X27, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CBNZ X16, 4653a0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1e34>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP D14, D15, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X29, X30, [SP], #384	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X5, X4, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X0, X5, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X10, X5, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X0, #7	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LS 4662b0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2d44>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X25, X7, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X1, X10, #2, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DUP Z6.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
DUP Z7.D, X22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR Z26.D, Z6.D, Z6.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD X7, X26, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X8, X12, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DUP Z16.D, X2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z17.D, Z24.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
PTRUE P7.B, VL16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
ADD X11, X7, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X25, X8, X1,LSL #5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ORR X3, XZR, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X7, X7, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TBZ W1, #0, 46478c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1220>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LD1D {Z18.D}, P7/Z, [X8, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LD1D {Z19.D}, P7/Z, [X8, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LD1D {Z20.D}, P7/Z, [X19, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
CMPEQ P5.D, P7/Z, Z18.D, Z7.D	1	0	0	0	0	0	0	1	0	1	0	0	0	0	0	0	0	0	4	1	vect (100.0%)
CMPGE P14.D, P7/Z, Z20.D, Z16.D	1	0	0	0	0	0	0	1	0	1	0	0	0	0	0	0	0	0	4	1	vect (100.0%)
LD1D {Z21.D}, P7/Z, [X19, Z19.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
CMPEQ P6.D, P7/Z, Z19.D, Z7.D	1	0	0	0	0	0	0	1	0	1	0	0	0	0	0	0	0	0	4	1	vect (100.0%)
CMPGE P15.D, P7/Z, Z21.D, Z16.D	1	0	0	0	0	0	0	1	0	1	0	0	0	0	0	0	0	0	4	1	vect (100.0%)
ADD X3, X8, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR P0.B, P7/Z, P5.B, P14.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
ORR P1.B, P7/Z, P6.B, P15.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
LD1D {Z22.D}, P0/Z, [X11, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LD1D {Z23.D}, P1/Z, [X7, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FMUL Z1.D, Z22.D, Z17.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL Z0.D, Z23.D, Z17.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FCMLT P2.D, P0/Z, Z1.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
FCMLT P3.D, P1/Z, Z0.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z26, Z6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FADD Z26.D, P2/M, Z26.D, Z22.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD Z6.D, P3/M, Z6.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
CMP X3, X25	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 464844 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x12d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X8, X10, #8062	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FADD Z6.D, Z26.D, Z6.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADDV D7, P7, Z6.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	vect (100.0%)
FADD D31, D15, D7	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X3, X8, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ANDS XZR, X10, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 464a14 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x14a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X25, X3, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X10, [X12, X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X19, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X2, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X10, X22, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
B.NE 46488c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1320>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D16, [X26, X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D17, D16, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FADD D26, D31, D16	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMPE D17, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D31, D26, D31, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X7, X3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X7, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 464a14 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x14a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X25, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X5, [X12, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X19, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X2, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X22, X5, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
B.NE 4648c4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1358>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D28, [X26, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D29, D28, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FADD D30, D31, D28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMPE D29, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D31, D30, D31, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X8, X3, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X4, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 464a14 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x14a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X11, X25, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X7, [X12, X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X19, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X2, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X7, X22, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
B.NE 4648fc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1390>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D4, [X26, X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D5, D4, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FADD D18, D31, D4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMPE D5, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D31, D18, D31, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X0, X3, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X4, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 464a14 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x14a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X5, X25, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X1, [X12, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X19, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X2, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X22, X1, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
B.NE 464934 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x13c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D19, [X26, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D20, D19, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FADD D21, D31, D19	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMPE D20, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D31, D21, D31, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X11, X3, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X4, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 464a14 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x14a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X25, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X7, [X12, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X19, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X2, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X22, X7, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
B.NE 46496c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1400>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D22, [X26, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D23, D22, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FADD D1, D31, D22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMPE D23, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D31, D1, D31, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X5, X3, #5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X4, X5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 464a14 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x14a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X1, X25, #40	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [X12, X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X19, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X2, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X22, X8, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
B.NE 4649a4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1438>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D0, [X26, X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D27, D0, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FADD D6, D31, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMPE D27, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D31, D6, D31, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X0, X3, #6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X4, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 464a14 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x14a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X5, X25, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X7, [X12, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X19, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X2, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X22, X7, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
B.NE 4649dc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1470>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D7, [X26, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D16, D7, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FADD D17, D31, D7	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMPE D16, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D31, D17, D31, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X3, X3, #7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X4, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 464a14 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x14a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X25, X25, #56	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X1, [X12, X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X19, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X2, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X22, X1, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
B.NE 464a14 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x14a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D26, [X26, X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D28, D24, D26	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FADD D29, D31, D26	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMPE D28, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D31, D29, D31, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
LDR X11, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D4, [X26, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
CMP X0, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 4656a0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D31, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.NE 465adc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2570>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FADD D25, D25, D4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
B 464100 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xb94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X6, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [X6, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X6, X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X5, X18	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4641a0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xc34>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X24, XZR, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X25, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X25, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X10, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X0, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X0, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X0, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X6, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X18, X14, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X8, X14, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X12, X9, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X12, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 46508c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1b20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X4, XZR, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X11, XZR, X24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X12, X9, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X25, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 4641a0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xc34>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 546e20 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 464688 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x111c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D31, D15	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
LDR X10, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X7, X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X7, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X25, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4667d4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3268>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X7, X3, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X1, X7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X1, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LS 466814 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x32a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X17, X25,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X5, X7, #2, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DUP Z5.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
DUP Z18.D, X27	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR Z6.D, Z5.D, Z5.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP Z21.D, Z24.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
PTRUE P7.B, VL16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
ADD X1, X8, X5,LSL #5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ORR X3, XZR, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, X0, X25,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X11, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X10, X0, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TBNZ W5, #0, 465fb4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2a48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X24, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X19, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X24, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X19, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
AND X8, X7, #8062	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FADD Z5.D, Z6.D, Z5.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADDV D18, P7, Z5.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	vect (100.0%)
FADD D31, D31, D18	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X11, X8, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ANDS XZR, X7, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 465930 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x23c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X1, X11, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X7, [X17, X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X23, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X27, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 4657f8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x228c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D21, [X5, X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D6, D21, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FADD D17, D31, D21	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMPE D6, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D31, D17, D31, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
LDR X0, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X3, X11, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X3, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 465930 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x23c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X7, X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [X17, X7]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X23, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X27, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 465834 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x22c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D26, [X5, X7]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D28, D26, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FADD D29, D31, D26	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMPE D28, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D31, D29, D31, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
LDR X0, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X3, X11, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X0, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 465930 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x23c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X7, X1, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [X17, X7]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X23, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X27, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 465870 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2304>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D30, [X5, X7]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D19, D30, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FADD D20, D31, D30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMPE D19, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D31, D20, D31, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
LDR X0, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X3, X11, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X0, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 465930 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x23c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X7, X1, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [X17, X7]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X23, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X27, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 4658ac <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2340>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D22, [X5, X7]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D23, D24, D22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FADD D1, D31, D22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMPE D23, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D31, D1, D31, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
LDR X0, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X3, X11, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X0, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 465930 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x23c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X7, X1, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [X17, X7]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X23, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X27, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 4658e8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x237c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D0, [X5, X7]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D27, D0, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FADD D7, D31, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMPE D27, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D31, D7, D31, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
LDR X0, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X3, X11, #5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X0, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 465930 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x23c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X7, X1, #40	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [X17, X7]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X23, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X27, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4665dc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3070>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X11, X11, #6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X3, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 465930 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x23c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X1, X1, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X0, [X17, X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X27, X7	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4665f8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x308c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D31, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.EQ 464a30 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x14c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV D26, D4, D31	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
CMP X9, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 465ae0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2574>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 465bdc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2670>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV D26, D4, D31	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
LDR X25, [X12, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORN X10, XZR, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, X10, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND X11, X5, #4160	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X3, [X19, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X2, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 4661fc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2c90>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D31, [X26, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D4, D31, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FCMPE D4, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.MI 4661ec <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2c80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X3, X9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X4, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 465bb8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x264c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ X11, 465f84 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2a18>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X11, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 465b8c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2620>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X11, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 465b50 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x25e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X12, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X19, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X2, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 46672c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x31c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D22, [X26, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D23, D22, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FCMPE D23, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.MI 46671c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x31b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X3, X3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [X12, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X19, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X2, X25	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 465b80 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2614>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D5, [X26, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D18, D5, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FCMPE D18, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.GE 465b88 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x261c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X10, X25, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D21, [X28, X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMADD D6, D26, D5, D21	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
STR D6, [X28, X10]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X22, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 466704 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3198>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X3, X3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X5, [X12, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X19, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X2, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 46626c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2d00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D28, [X26, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D29, D28, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FCMPE D29, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.MI 46625c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2cf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X3, X3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X4, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 465f84 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2a18>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X4, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 464100 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xb94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X10, X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X10, X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X5, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X25, X5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 464100 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xb94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X1, X5, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ANDS X9, X1, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LDR X3, [X0, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B.EQ 466890 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3324>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 465d28 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x27bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 465cf0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2784>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 465cc8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x275c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 465ca0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2734>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 465c78 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x270c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 465c50 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x26e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X7, [X17, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X23, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X27, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 465c4c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x26e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D17, [X8, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D4, D17, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FCMPE D4, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.MI 4667c0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3254>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X25, X25, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X11, [X17, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X23, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X27, X5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 465c74 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2708>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D29, [X1, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D19, D29, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FCMPE D19, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.MI 4667a0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3234>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X25, X25, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X0, [X17, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X27, X7	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 465c9c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2730>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D22, [X4, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D23, D22, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FCMPE D23, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.MI 46678c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3220>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X25, X25, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X10, [X17, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X23, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X27, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 465cc4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2758>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D27, [X5, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D7, D27, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FCMPE D7, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.MI 466778 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x320c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X25, X25, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X9, [X17, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X23, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X27, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 465cec <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2780>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X7, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D18, [X7, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D21, D18, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FCMPE D21, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.MI 466760 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x31f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X25, X25, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [X17, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X23, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X27, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 465d24 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x27b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D4, [X11, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D31, D4, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FCMPE D31, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.GE 465d24 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x27b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X5, X10, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D28, [X3, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMADD D29, D26, D4, D28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
STR D29, [X3, X5]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
ADD X25, X25, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X1, [X17, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X27, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 46668c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X25, X25, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X25, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 464100 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xb94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X8, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 464100 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xb94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LD1D {Z30.D}, P7/Z, [X8, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LD1D {Z19.D}, P7/Z, [X8, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LD1D {Z20.D}, P7/Z, [X23, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LD1D {Z22.D}, P7/Z, [X23, Z19.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
CMPGE P0.D, P7/Z, Z20.D, Z18.D	1	0	0	0	0	0	0	1	0	1	0	0	0	0	0	0	0	0	4	1	vect (100.0%)
CMPGE P6.D, P7/Z, Z22.D, Z18.D	1	0	0	0	0	0	0	1	0	1	0	0	0	0	0	0	0	0	4	1	vect (100.0%)
ADD X3, X8, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z23.D}, P6/Z, [X0, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADD X5, X10, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMUL Z0.D, Z23.D, Z21.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
LD1D {Z1.D}, P0/Z, [X5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FCMLT P1.D, P6/Z, Z0.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
FMUL Z27.D, Z1.D, Z21.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FCMLT P2.D, P0/Z, Z27.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z6, Z5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FADD Z6.D, P2/M, Z6.D, Z1.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD Z5.D, P1/M, Z5.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
CMP X3, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 465708 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x219c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4657b0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2244>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LD1D {Z7.D}, P5/Z, [X10, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FMUL Z5.D, Z20.D, Z7.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FNEG Z5.D, P7/M, Z5.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ST1D {Z5.D}, P5, [X10, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
B 464324 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xdb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X1, X3, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D28, [X28, X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMADD D29, D26, D31, D28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
STR D29, [X28, X1]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X22, X25	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 465b0c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x25a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D19, [X26, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D30, D19, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FMADD D20, D26, D19, D25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
FCMPE D30, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D25, D20, D25, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
B 465b0c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x25a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X1, X11, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D19, [X28, X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMADD D30, D26, D28, D19	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
STR D30, [X28, X1]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X22, X5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 465bac <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2640>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D20, [X26, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D22, D20, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FMADD D23, D26, D20, D25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
FCMPE D22, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D25, D23, D25, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
B 465bac <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2640>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D4, [X26, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
CMP X10, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 465694 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D15, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.NE 464100 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xb94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FADD D25, D25, D4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
B 464100 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xb94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D31, D15	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ORR X3, XZR, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 464860 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x12f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D16, [X5, X7]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D5, D16, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FADD D18, D31, D16	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMPE D5, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D31, D18, D31, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
B 46590c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x23a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D21, [X8, X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D6, D21, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FADD D17, D31, D21	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMPE D6, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D31, D17, D31, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
B 465930 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x23c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D19, [X0, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D30, D19, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FCMPE D30, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.GE 465d38 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x27cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X7, X9, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D20, [X3, X7]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMADD D22, D26, D19, D20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
STR D22, [X3, X7]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
B 465d38 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x27cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D17, [X26, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D4, D17, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FMADD D31, D26, D17, D25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
FCMPE D4, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D25, D31, D25, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
B 465b88 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x261c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X7, X0, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D1, [X28, X7]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMADD D0, D26, D22, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
STR D0, [X28, X7]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X22, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 465b4c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x25e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D27, [X26, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X3, X3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMUL D7, D27, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FMADD D16, D26, D27, D25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
FCMPE D7, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D25, D16, D25, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
B 465b50 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x25e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X4, X0, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X25, X25, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D6, [X3, X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMADD D17, D26, D18, D6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
STR D17, [X3, X4]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
B 465cf0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2784>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X1, X11, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D16, [X3, X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMADD D5, D26, D27, D16	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
STR D5, [X3, X1]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
B 465cc4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2758>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X8, X7, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D1, [X3, X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMADD D0, D26, D22, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
STR D0, [X3, X8]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
B 465c9c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2730>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X9, X5, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D30, [X3, X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMADD D20, D26, D29, D30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
STR D20, [X3, X9]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
B 465c74 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2708>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X10, X4, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D31, [X3, X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMADD D28, D26, D17, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
STR D28, [X3, X10]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
B 465c4c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x26e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D31, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.EQ 464a30 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x14c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV D26, D4, D31	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
CMP X9, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 465ae0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2574>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 464100 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xb94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X5, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 464464 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xef8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X10, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 4642ec <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xd80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X11, XZR, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 4657cc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2260>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 465d50 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x27e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code