OV - exec - Loop 945

	Loop Id: 945	Module: exec	Source: par_multi_interp.c:550-576 [...]	Coverage: 0.05%

0x45f3a8 ADD	X9, X27, X4,LSL #3

0x45f3ac LDR	X5, [X27, X4,LSL #3]

0x45f3b0 UBFM	X2, X5, #61, #60

0x45f3b4 ADD	X7, X2, #8

0x45f3b8 LDR	X0, [X6, X2]

0x45f3bc LDR	X3, [X6, X7]

0x45f3c0 CMP	X0, X3

0x45f3c4 B.GE	45f540

0x45f3c8 SUB	X16, X3, X0

0x45f3cc ANDS	X18, X16, #4224

0x45f3d0 B.EQ	45f498

0x45f3d4 CMP	X18, #1

0x45f3d8 B.EQ	45f47c

0x45f3dc CMP	X18, #2

0x45f3e0 B.EQ	45f468

0x45f3e4 CMP	X18, #3

0x45f3e8 B.EQ	45f454

0x45f3ec CMP	X18, #4

0x45f3f0 B.EQ	45f440

0x45f3f4 CMP	X18, #5

0x45f3f8 B.EQ	45f42c

0x45f3fc CMP	X18, #6

0x45f400 B.EQ	45f418

0x45f404 LDR	X1, [X20, X0,LSL #3]

0x45f408 ADD	X0, X0, #1

0x45f40c LDR	X17, [X22, X1,LSL #3]

0x45f410 CMP	X17, X19

0x45f414 B.EQ	45f814

0x45f418 LDR	X13, [X20, X0,LSL #3]

0x45f41c ADD	X0, X0, #1

0x45f420 LDR	X12, [X22, X13,LSL #3]

0x45f424 CMP	X12, X19

0x45f428 B.EQ	45f814

0x45f42c LDR	X14, [X20, X0,LSL #3]

0x45f430 ADD	X0, X0, #1

0x45f434 LDR	X15, [X22, X14,LSL #3]

0x45f438 CMP	X15, X19

0x45f43c B.EQ	45f814

0x45f440 LDR	X10, [X20, X0,LSL #3]

0x45f444 ADD	X0, X0, #1

0x45f448 LDR	X16, [X22, X10,LSL #3]

0x45f44c CMP	X16, X19

0x45f450 B.EQ	45f814

0x45f454 LDR	X18, [X20, X0,LSL #3]

0x45f458 ADD	X0, X0, #1

0x45f45c LDR	X1, [X22, X18,LSL #3]

0x45f460 CMP	X1, X19

0x45f464 B.EQ	45f814

0x45f468 LDR	X17, [X20, X0,LSL #3]

0x45f46c ADD	X0, X0, #1

0x45f470 LDR	X13, [X22, X17,LSL #3]

0x45f474 CMP	X13, X19

0x45f478 B.EQ	45f814

0x45f47c LDR	X12, [X20, X0,LSL #3]

0x45f480 LDR	X14, [X22, X12,LSL #3]

0x45f484 CMP	X14, X19

0x45f488 B.EQ	45f814

0x45f48c ADD	X0, X0, #1

0x45f490 CMP	X0, X3

0x45f494 B.EQ	45f540

  (947) 0x45f498 LDR	X18, [X20, X0,LSL #3]

  (947) 0x45f49c ADD	X10, X0, #1

  (947) 0x45f4a0 ADD	X16, X0, #3

  (947) 0x45f4a4 ADD	X15, X0, #4

  (947) 0x45f4a8 ADD	X14, X0, #5

  (947) 0x45f4ac ADD	X13, X0, #6

  (947) 0x45f4b0 ADD	X17, X0, #7

  (947) 0x45f4b4 ADD	X12, X10, #1

  (947) 0x45f4b8 ADD	X0, X0, #8

  (947) 0x45f4bc LDR	X1, [X22, X18,LSL #3]

  (947) 0x45f4c0 CMP	X1, X19

  (947) 0x45f4c4 B.EQ	45f814

  (947) 0x45f4c8 LDR	X10, [X20, X10,LSL #3]

  (947) 0x45f4cc LDR	X18, [X22, X10,LSL #3]

  (947) 0x45f4d0 CMP	X18, X19

  (947) 0x45f4d4 B.EQ	45f814

  (947) 0x45f4d8 LDR	X12, [X20, X12,LSL #3]

  (947) 0x45f4dc LDR	X1, [X22, X12,LSL #3]

  (947) 0x45f4e0 CMP	X1, X19

  (947) 0x45f4e4 B.EQ	45f814

  (947) 0x45f4e8 LDR	X16, [X20, X16,LSL #3]

  (947) 0x45f4ec LDR	X10, [X22, X16,LSL #3]

  (947) 0x45f4f0 CMP	X10, X19

  (947) 0x45f4f4 B.EQ	45f814

  (947) 0x45f4f8 LDR	X15, [X20, X15,LSL #3]

  (947) 0x45f4fc LDR	X18, [X22, X15,LSL #3]

  (947) 0x45f500 CMP	X18, X19

  (947) 0x45f504 B.EQ	45f814

  (947) 0x45f508 LDR	X14, [X20, X14,LSL #3]

  (947) 0x45f50c LDR	X12, [X22, X14,LSL #3]

  (947) 0x45f510 CMP	X12, X19

  (947) 0x45f514 B.EQ	45f814

  (947) 0x45f518 LDR	X13, [X20, X13,LSL #3]

  (947) 0x45f51c LDR	X1, [X22, X13,LSL #3]

  (947) 0x45f520 CMP	X1, X19

  (947) 0x45f524 B.EQ	45f814

  (947) 0x45f528 LDR	X17, [X20, X17,LSL #3]

  (947) 0x45f52c LDR	X16, [X22, X17,LSL #3]

  (947) 0x45f530 CMP	X16, X19

  (947) 0x45f534 B.EQ	45f814

  (947) 0x45f538 CMP	X0, X3

  (947) 0x45f53c B.NE	45f498

0x45f540 LDR	X3, [X8, X7]

0x45f544 LDR	X0, [X8, X2]

0x45f548 CMP	X0, X3

0x45f54c B.GE	45f6c8

0x45f550 SUB	X7, X3, X0

0x45f554 ANDS	X10, X7, #4224

0x45f558 B.EQ	45f620

0x45f55c CMP	X10, #1

0x45f560 B.EQ	45f604

0x45f564 CMP	X10, #2

0x45f568 B.EQ	45f5f0

0x45f56c CMP	X10, #3

0x45f570 B.EQ	45f5dc

0x45f574 CMP	X10, #4

0x45f578 B.EQ	45f5c8

0x45f57c CMP	X10, #5

0x45f580 B.EQ	45f5b4

0x45f584 CMP	X10, #6

0x45f588 B.EQ	45f5a0

0x45f58c LDR	X15, [X21, X0,LSL #3]

0x45f590 ADD	X0, X0, #1

0x45f594 LDR	X18, [X26, X15,LSL #3]

0x45f598 CMP	X18, X19

0x45f59c B.EQ	45f814

0x45f5a0 LDR	X14, [X21, X0,LSL #3]

0x45f5a4 ADD	X0, X0, #1

0x45f5a8 LDR	X12, [X26, X14,LSL #3]

0x45f5ac CMP	X12, X19

0x45f5b0 B.EQ	45f814

0x45f5b4 LDR	X13, [X21, X0,LSL #3]

0x45f5b8 ADD	X0, X0, #1

0x45f5bc LDR	X1, [X26, X13,LSL #3]

0x45f5c0 CMP	X1, X19

0x45f5c4 B.EQ	45f814

0x45f5c8 LDR	X17, [X21, X0,LSL #3]

0x45f5cc ADD	X0, X0, #1

0x45f5d0 LDR	X16, [X26, X17,LSL #3]

0x45f5d4 CMP	X16, X19

0x45f5d8 B.EQ	45f814

0x45f5dc LDR	X7, [X21, X0,LSL #3]

0x45f5e0 ADD	X0, X0, #1

0x45f5e4 LDR	X10, [X26, X7,LSL #3]

0x45f5e8 CMP	X10, X19

0x45f5ec B.EQ	45f814

0x45f5f0 LDR	X15, [X21, X0,LSL #3]

0x45f5f4 ADD	X0, X0, #1

0x45f5f8 LDR	X18, [X26, X15,LSL #3]

0x45f5fc CMP	X18, X19

0x45f600 B.EQ	45f814

0x45f604 LDR	X14, [X21, X0,LSL #3]

0x45f608 LDR	X12, [X26, X14,LSL #3]

0x45f60c CMP	X12, X19

0x45f610 B.EQ	45f814

0x45f614 ADD	X0, X0, #1

0x45f618 CMP	X0, X3

0x45f61c B.EQ	45f6c8

  (946) 0x45f620 LDR	X17, [X21, X0,LSL #3]

  (946) 0x45f624 ADD	X1, X0, #1

  (946) 0x45f628 ADD	X10, X0, #3

  (946) 0x45f62c ADD	X15, X0, #4

  (946) 0x45f630 ADD	X18, X0, #5

  (946) 0x45f634 ADD	X7, X0, #6

  (946) 0x45f638 ADD	X13, X0, #7

  (946) 0x45f63c ADD	X16, X1, #1

  (946) 0x45f640 ADD	X0, X0, #8

  (946) 0x45f644 LDR	X14, [X26, X17,LSL #3]

  (946) 0x45f648 CMP	X14, X19

  (946) 0x45f64c B.EQ	45f814

  (946) 0x45f650 LDR	X12, [X21, X1,LSL #3]

  (946) 0x45f654 LDR	X1, [X26, X12,LSL #3]

  (946) 0x45f658 CMP	X1, X19

  (946) 0x45f65c B.EQ	45f814

  (946) 0x45f660 LDR	X17, [X21, X16,LSL #3]

  (946) 0x45f664 LDR	X16, [X26, X17,LSL #3]

  (946) 0x45f668 CMP	X16, X19

  (946) 0x45f66c B.EQ	45f814

  (946) 0x45f670 LDR	X10, [X21, X10,LSL #3]

  (946) 0x45f674 LDR	X14, [X26, X10,LSL #3]

  (946) 0x45f678 CMP	X14, X19

  (946) 0x45f67c B.EQ	45f814

  (946) 0x45f680 LDR	X15, [X21, X15,LSL #3]

  (946) 0x45f684 LDR	X12, [X26, X15,LSL #3]

  (946) 0x45f688 CMP	X12, X19

  (946) 0x45f68c B.EQ	45f814

  (946) 0x45f690 LDR	X18, [X21, X18,LSL #3]

  (946) 0x45f694 LDR	X1, [X26, X18,LSL #3]

  (946) 0x45f698 CMP	X1, X19

  (946) 0x45f69c B.EQ	45f814

  (946) 0x45f6a0 LDR	X7, [X21, X7,LSL #3]

  (946) 0x45f6a4 LDR	X17, [X26, X7,LSL #3]

  (946) 0x45f6a8 CMP	X17, X19

  (946) 0x45f6ac B.EQ	45f814

  (946) 0x45f6b0 LDR	X13, [X21, X13,LSL #3]

  (946) 0x45f6b4 LDR	X16, [X26, X13,LSL #3]

  (946) 0x45f6b8 CMP	X16, X19

  (946) 0x45f6bc B.EQ	45f814

  (946) 0x45f6c0 CMP	X0, X3

  (946) 0x45f6c4 B.NE	45f620

0x45f6c8 SUB	X4, X4, #1

0x45f6cc CMP	X23, X4

0x45f6d0 B.LE	45f3a8

0x45f814 UBFM	X3, X23, #61, #60

0x45f818 ADD	X23, X23, #1

0x45f81c LDR	X0, [X27, X3]

0x45f820 STR	X0, [X9]

0x45f824 STR	X5, [X27, X3]

0x45f828 STR	X28, [X22, X2]

0x45f82c B	45f6cc

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 550 - 576

--------------------------------------------------------------------------------

550:       for (i = pass_array_size-1; i > cnt-1; i--)

551:       {

552:          i1 = pass_array[i];

553:          no_break = 1;

554:          for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

555:          {

556:             j1 = S_diag_j[j];

557:             if (assigned[j1] == pass-1)

[...]

568:             for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

569:             {

570:                j1 = S_offd_j[j];

571:                if (assigned_offd[j1] == pass-1)

572:                {

573:                   pass_array[i++] = pass_array[cnt];

574:                   pass_array[cnt++] = i1;

575:                   assigned[i1] = pass;

576:                   break;

Coverage (%)	Name	Source Location	Module
►100.00+	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.08
Bottlenecks	P0, P1,
Function	hypre_BoomerAMGBuildMultipass
Source	par_multi_interp.c:550-554,par_multi_interp.c:557-557,par_multi_interp.c:568-568,par_multi_interp.c:571-576
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	17.00
CQA cycles if no scalar integer	17.00
CQA cycles if FP arith vectorized	17.00
CQA cycles if fully vectorized	8.50
Front-end cycles	15.75
P0 cycles	17.00
P1 cycles	17.00
P2 cycles	9.25
P3 cycles	9.25
P4 cycles	9.17
P5 cycles	9.17
P6 cycles	9.08
P7 cycles	9.08
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	12.50
P13 cycles	12.17
P14 cycles	12.33
P15 cycles	1.50
P16 cycles	1.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	126.00
Nb uops	126.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.41
Bytes prefetched	0.00
Bytes loaded	272.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.08
Bottlenecks	P0, P1,
Function	hypre_BoomerAMGBuildMultipass
Source	par_multi_interp.c:550-554,par_multi_interp.c:557-557,par_multi_interp.c:568-568,par_multi_interp.c:571-576
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	17.00
CQA cycles if no scalar integer	17.00
CQA cycles if FP arith vectorized	17.00
CQA cycles if fully vectorized	8.50
Front-end cycles	15.75
P0 cycles	17.00
P1 cycles	17.00
P2 cycles	9.25
P3 cycles	9.25
P4 cycles	9.17
P5 cycles	9.17
P6 cycles	9.08
P7 cycles	9.08
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	12.50
P13 cycles	12.17
P14 cycles	12.33
P15 cycles	1.50
P16 cycles	1.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	126.00
Nb uops	126.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.41
Bytes prefetched	0.00
Bytes loaded	272.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass
Source file and lines	par_multi_interp.c:550-576
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:550-557,568-576.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:550-554,557,568,571-576.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 1820 paths individually, rerun with max-paths=1820
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 1820 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 17.00 to 8.50 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 272 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	126
loop length	504
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

15.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	17.00	17.00	9.25	9.25	9.17	9.17	9.08	9.08	0.00	0.00	0.00	0.00	12.50	12.17	12.33	1.50	1.50
cycles	17.00	17.00	9.25	9.25	9.17	9.17	9.08	9.08	0.00	0.00	0.00	0.00	12.50	12.17	12.33	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.75
Overall L1	17.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.00 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.41 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 45f3a8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
ADD X9, X27, X4,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X5, [X27, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
UBFM X2, X5, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X7, X2, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X0, [X6, X2]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X6, X7]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 45f540 <hypre_BoomerAMGBuildMultipass+0xf40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X16, X3, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS X18, X16, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.EQ 45f498 <hypre_BoomerAMGBuildMultipass+0xe98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X18, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f47c <hypre_BoomerAMGBuildMultipass+0xe7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X18, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f468 <hypre_BoomerAMGBuildMultipass+0xe68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X18, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f454 <hypre_BoomerAMGBuildMultipass+0xe54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X18, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f440 <hypre_BoomerAMGBuildMultipass+0xe40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X18, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f42c <hypre_BoomerAMGBuildMultipass+0xe2c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X18, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f418 <hypre_BoomerAMGBuildMultipass+0xe18>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X17, [X22, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X17, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f814 <hypre_BoomerAMGBuildMultipass+0x1214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X12, [X22, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X12, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f814 <hypre_BoomerAMGBuildMultipass+0x1214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X15, [X22, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X15, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f814 <hypre_BoomerAMGBuildMultipass+0x1214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X16, [X22, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X16, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f814 <hypre_BoomerAMGBuildMultipass+0x1214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X1, [X22, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f814 <hypre_BoomerAMGBuildMultipass+0x1214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X13, [X22, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X13, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f814 <hypre_BoomerAMGBuildMultipass+0x1214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X22, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X14, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f814 <hypre_BoomerAMGBuildMultipass+0x1214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CMP X0, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f540 <hypre_BoomerAMGBuildMultipass+0xf40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [X8, X7]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X8, X2]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 45f6c8 <hypre_BoomerAMGBuildMultipass+0x10c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X7, X3, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ANDS X10, X7, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.EQ 45f620 <hypre_BoomerAMGBuildMultipass+0x1020>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f604 <hypre_BoomerAMGBuildMultipass+0x1004>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f5f0 <hypre_BoomerAMGBuildMultipass+0xff0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f5dc <hypre_BoomerAMGBuildMultipass+0xfdc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f5c8 <hypre_BoomerAMGBuildMultipass+0xfc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f5b4 <hypre_BoomerAMGBuildMultipass+0xfb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f5a0 <hypre_BoomerAMGBuildMultipass+0xfa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X18, [X26, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X18, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f814 <hypre_BoomerAMGBuildMultipass+0x1214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X12, [X26, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X12, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f814 <hypre_BoomerAMGBuildMultipass+0x1214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X1, [X26, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f814 <hypre_BoomerAMGBuildMultipass+0x1214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X16, [X26, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X16, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f814 <hypre_BoomerAMGBuildMultipass+0x1214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X7, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X10, [X26, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X10, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f814 <hypre_BoomerAMGBuildMultipass+0x1214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X18, [X26, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X18, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f814 <hypre_BoomerAMGBuildMultipass+0x1214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X26, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X12, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f814 <hypre_BoomerAMGBuildMultipass+0x1214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CMP X0, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f6c8 <hypre_BoomerAMGBuildMultipass+0x10c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CMP X23, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 45f3a8 <hypre_BoomerAMGBuildMultipass+0xda8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X3, X23, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X23, X23, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X0, [X27, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X9]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X5, [X27, X3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X28, [X22, X2]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 45f6cc <hypre_BoomerAMGBuildMultipass+0x10cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_BoomerAMGBuildMultipass
Source file and lines	par_multi_interp.c:550-576
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 1820 paths individually, rerun with max-paths=1820
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 272 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	126
loop length	504
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

15.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	17.00	17.00	9.25	9.25	9.17	9.17	9.08	9.08	0.00	0.00	0.00	0.00	12.50	12.17	12.33	1.50	1.50
cycles	17.00	17.00	9.25	9.25	9.17	9.17	9.08	9.08	0.00	0.00	0.00	0.00	12.50	12.17	12.33	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.75
Overall L1	17.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.00 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.41 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 45f3a8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
ADD X9, X27, X4,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X5, [X27, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
UBFM X2, X5, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X7, X2, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X0, [X6, X2]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X6, X7]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 45f540 <hypre_BoomerAMGBuildMultipass+0xf40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X16, X3, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS X18, X16, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.EQ 45f498 <hypre_BoomerAMGBuildMultipass+0xe98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X18, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f47c <hypre_BoomerAMGBuildMultipass+0xe7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X18, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f468 <hypre_BoomerAMGBuildMultipass+0xe68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X18, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f454 <hypre_BoomerAMGBuildMultipass+0xe54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X18, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f440 <hypre_BoomerAMGBuildMultipass+0xe40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X18, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f42c <hypre_BoomerAMGBuildMultipass+0xe2c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X18, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f418 <hypre_BoomerAMGBuildMultipass+0xe18>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X17, [X22, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X17, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f814 <hypre_BoomerAMGBuildMultipass+0x1214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X12, [X22, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X12, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f814 <hypre_BoomerAMGBuildMultipass+0x1214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X15, [X22, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X15, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f814 <hypre_BoomerAMGBuildMultipass+0x1214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X16, [X22, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X16, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f814 <hypre_BoomerAMGBuildMultipass+0x1214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X1, [X22, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f814 <hypre_BoomerAMGBuildMultipass+0x1214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X13, [X22, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X13, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f814 <hypre_BoomerAMGBuildMultipass+0x1214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X22, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X14, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f814 <hypre_BoomerAMGBuildMultipass+0x1214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CMP X0, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f540 <hypre_BoomerAMGBuildMultipass+0xf40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [X8, X7]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X8, X2]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 45f6c8 <hypre_BoomerAMGBuildMultipass+0x10c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X7, X3, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ANDS X10, X7, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.EQ 45f620 <hypre_BoomerAMGBuildMultipass+0x1020>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f604 <hypre_BoomerAMGBuildMultipass+0x1004>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f5f0 <hypre_BoomerAMGBuildMultipass+0xff0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f5dc <hypre_BoomerAMGBuildMultipass+0xfdc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f5c8 <hypre_BoomerAMGBuildMultipass+0xfc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f5b4 <hypre_BoomerAMGBuildMultipass+0xfb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f5a0 <hypre_BoomerAMGBuildMultipass+0xfa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X18, [X26, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X18, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f814 <hypre_BoomerAMGBuildMultipass+0x1214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X12, [X26, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X12, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f814 <hypre_BoomerAMGBuildMultipass+0x1214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X1, [X26, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f814 <hypre_BoomerAMGBuildMultipass+0x1214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X16, [X26, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X16, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f814 <hypre_BoomerAMGBuildMultipass+0x1214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X7, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X10, [X26, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X10, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f814 <hypre_BoomerAMGBuildMultipass+0x1214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X18, [X26, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X18, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f814 <hypre_BoomerAMGBuildMultipass+0x1214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X26, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X12, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f814 <hypre_BoomerAMGBuildMultipass+0x1214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CMP X0, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45f6c8 <hypre_BoomerAMGBuildMultipass+0x10c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CMP X23, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 45f3a8 <hypre_BoomerAMGBuildMultipass+0xda8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X3, X23, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X23, X23, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X0, [X27, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X9]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X5, [X27, X3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X28, [X22, X2]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 45f6cc <hypre_BoomerAMGBuildMultipass+0x10cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code