OV - exec - Loop 868

	Loop Id: 868	Module: exec	Source: par_multi_interp.c:1593-1660 [...]	Coverage: 0.06%

0x45d104 LDR	X3, [X17]

0x45d108 LDR	X30, [SP, #136]

0x45d10c UBFM	X5, X3, #61, #60

0x45d110 ADD	X14, X5, #8

0x45d114 LDR	X2, [X12, X5]

0x45d118 LDR	X16, [X12, X14]

0x45d11c LDR	X0, [X30, X5]

0x45d120 ADD	X9, X0, X16

0x45d124 SUB	X1, X9, X2

0x45d128 CMP	X0, X1

0x45d12c B.GE	45d260

0x45d130 LDR	X2, [SP, #184]

0x45d134 UBFM	X16, X0, #61, #60

0x45d138 LDR	X4, [X2, #8]

0x45d13c ADD	X30, X4, X1,LSL #3

0x45d140 ADD	X0, X4, X0,LSL #3

0x45d144 SUB	X9, X30, X0

0x45d148 SUB	X1, X9, #8

0x45d14c UBFM	X2, X1, #3, #63

0x45d150 ADD	X9, X2, #1

0x45d154 ANDS	X1, X9, #4224

0x45d158 B.EQ	45d1ec

0x45d15c CMP	X1, #1

0x45d160 B.EQ	45d1d8

0x45d164 CMP	X1, #2

0x45d168 B.EQ	45d1cc

0x45d16c CMP	X1, #3

0x45d170 B.EQ	45d1c0

0x45d174 CMP	X1, #4

0x45d178 B.EQ	45d1b4

0x45d17c CMP	X1, #5

0x45d180 B.EQ	45d1a8

0x45d184 CMP	X1, #6

0x45d188 B.EQ	45d19c

0x45d18c LDR	X16, [X4, X16]

0x45d190 ADD	X0, X0, #8

0x45d194 LDR	X4, [X22, X16,LSL #3]

0x45d198 STR	X3, [X20, X4,LSL #3]

0x45d19c LDR	X2, [X0], #8

0x45d1a0 LDR	X9, [X22, X2,LSL #3]

0x45d1a4 STR	X3, [X20, X9,LSL #3]

0x45d1a8 LDR	X1, [X0], #8

0x45d1ac LDR	X16, [X22, X1,LSL #3]

0x45d1b0 STR	X3, [X20, X16,LSL #3]

0x45d1b4 LDR	X4, [X0], #8

0x45d1b8 LDR	X2, [X22, X4,LSL #3]

0x45d1bc STR	X3, [X20, X2,LSL #3]

0x45d1c0 LDR	X9, [X0], #8

0x45d1c4 LDR	X1, [X22, X9,LSL #3]

0x45d1c8 STR	X3, [X20, X1,LSL #3]

0x45d1cc LDR	X16, [X0], #8

0x45d1d0 LDR	X4, [X22, X16,LSL #3]

0x45d1d4 STR	X3, [X20, X4,LSL #3]

0x45d1d8 LDR	X2, [X0], #8

0x45d1dc LDR	X9, [X22, X2,LSL #3]

0x45d1e0 STR	X3, [X20, X9,LSL #3]

0x45d1e4 CMP	X30, X0

0x45d1e8 B.EQ	45d25c

  (877) 0x45d1ec ORR	X1, XZR, X0

  (877) 0x45d1f0 ADD	X0, X0, #64

  (877) 0x45d1f4 LDR	X16, [X1], #8

  (877) 0x45d1f8 LDR	X4, [X22, X16,LSL #3]

  (877) 0x45d1fc STR	X3, [X20, X4,LSL #3]

  (877) 0x45d200 LDUR	X2, [X0, #456]

  (877) 0x45d204 LDR	X9, [X22, X2,LSL #3]

  (877) 0x45d208 STR	X3, [X20, X9,LSL #3]

  (877) 0x45d20c LDR	X1, [X1, #8]

  (877) 0x45d210 LDR	X16, [X22, X1,LSL #3]

  (877) 0x45d214 STR	X3, [X20, X16,LSL #3]

  (877) 0x45d218 LDUR	X4, [X0, #472]

  (877) 0x45d21c LDR	X2, [X22, X4,LSL #3]

  (877) 0x45d220 STR	X3, [X20, X2,LSL #3]

  (877) 0x45d224 LDUR	X9, [X0, #480]

  (877) 0x45d228 LDR	X1, [X22, X9,LSL #3]

  (877) 0x45d22c STR	X3, [X20, X1,LSL #3]

  (877) 0x45d230 LDUR	X16, [X0, #488]

  (877) 0x45d234 LDR	X4, [X22, X16,LSL #3]

  (877) 0x45d238 STR	X3, [X20, X4,LSL #3]

  (877) 0x45d23c LDUR	X2, [X0, #496]

  (877) 0x45d240 LDR	X9, [X22, X2,LSL #3]

  (877) 0x45d244 STR	X3, [X20, X9,LSL #3]

  (877) 0x45d248 LDUR	X1, [X0, #504]

  (877) 0x45d24c LDR	X16, [X22, X1,LSL #3]

  (877) 0x45d250 STR	X3, [X20, X16,LSL #3]

  (877) 0x45d254 CMP	X30, X0

  (877) 0x45d258 B.NE	45d1ec

0x45d25c LDR	X2, [X12, X5]

0x45d260 MOVI	D4, #0

0x45d264 ADD	X30, X11, X14

0x45d268 LDR	X0, [X11, X5]

0x45d26c LDR	X9, [X11, X14]

0x45d270 FMOV	D29, D4

0x45d274 ADD	X0, X0, #1

0x45d278 CMP	X0, X9

0x45d27c B.GE	45d318

0x45d280 CMP	X10, #1

0x45d284 B.EQ	45d9e4

0x45d288 ORR	X16, XZR, X19

0x45d28c LDR	X19, [SP, #160]

0x45d290 STP	X8, X6, [SP, #112]

0x45d294 HINT	#0

0x45d298 HINT	#0

0x45d29c HINT	#0

  (876) 0x45d2a0 LDR	X4, [X25, X0,LSL #3]

  (876) 0x45d2a4 UBFM	X1, X4, #61, #60

  (876) 0x45d2a8 LDR	X6, [X26, X1]

  (876) 0x45d2ac CMN	X6, #3

  (876) 0x45d2b0 B.EQ	45d2cc

  (876) 0x45d2b4 LDR	X6, [X27, X5]

  (876) 0x45d2b8 LDR	X8, [X27, X1]

  (876) 0x45d2bc CMP	X6, X8

  (876) 0x45d2c0 B.NE	45d2cc

  (876) 0x45d2c4 LDR	D21, [X28, X0,LSL #3]

  (876) 0x45d2c8 FADD	D4, D4, D21

  (876) 0x45d2cc CMN	X4, #1

  (876) 0x45d2d0 B.EQ	45d304

  (876) 0x45d2d4 LDR	X4, [X20, X1]

  (876) 0x45d2d8 CMP	X3, X4

  (876) 0x45d2dc B.NE	45d304

  (876) 0x45d2e0 LDR	D20, [X28, X0,LSL #3]

  (876) 0x45d2e4 UBFM	X9, X2, #61, #60

  (876) 0x45d2e8 ADD	X2, X2, #1

  (876) 0x45d2ec LDR	X1, [X19, X1]

  (876) 0x45d2f0 LDR	X6, [SP, #104]

  (876) 0x45d2f4 FADD	D29, D29, D20

  (876) 0x45d2f8 STR	D20, [X7, X9]

  (876) 0x45d2fc STR	X1, [X6, X9]

  (876) 0x45d300 LDR	X9, [X30]

  (876) 0x45d304 ADD	X0, X0, #1

  (876) 0x45d308 CMP	X0, X9

  (876) 0x45d30c B.LT	45d2a0

0x45d310 LDP	X8, X6, [SP, #112]

0x45d314 ORR	X19, XZR, X16

0x45d318 LDR	X0, [SP, #128]

0x45d31c LDR	X30, [X18, X14]

0x45d320 LDR	X1, [X18, X5]

0x45d324 LDR	X0, [X0, X5]

0x45d328 ADD	X16, X0, X30

0x45d32c SUB	X4, X16, X1

0x45d330 CMP	X0, X4

0x45d334 B.GE	45d468

0x45d338 LDR	X9, [SP, #176]

0x45d33c UBFM	X30, X0, #61, #60

0x45d340 LDR	X16, [X9, #8]

0x45d344 ADD	X4, X16, X4,LSL #3

0x45d348 ADD	X0, X16, X0,LSL #3

0x45d34c SUB	X1, X4, X0

0x45d350 SUB	X9, X1, #8

0x45d354 UBFM	X1, X9, #3, #63

0x45d358 ADD	X9, X1, #1

0x45d35c ANDS	X1, X9, #4224

0x45d360 B.EQ	45d3f4

0x45d364 CMP	X1, #1

0x45d368 B.EQ	45d3e0

0x45d36c CMP	X1, #2

0x45d370 B.EQ	45d3d4

0x45d374 CMP	X1, #3

0x45d378 B.EQ	45d3c8

0x45d37c CMP	X1, #4

0x45d380 B.EQ	45d3bc

0x45d384 CMP	X1, #5

0x45d388 B.EQ	45d3b0

0x45d38c CMP	X1, #6

0x45d390 B.EQ	45d3a4

0x45d394 LDR	X30, [X16, X30]

0x45d398 ADD	X0, X0, #8

0x45d39c LDR	X16, [X21, X30,LSL #3]

0x45d3a0 STR	X3, [X19, X16,LSL #3]

0x45d3a4 LDR	X9, [X0], #8

0x45d3a8 LDR	X1, [X21, X9,LSL #3]

0x45d3ac STR	X3, [X19, X1,LSL #3]

0x45d3b0 LDR	X30, [X0], #8

0x45d3b4 LDR	X16, [X21, X30,LSL #3]

0x45d3b8 STR	X3, [X19, X16,LSL #3]

0x45d3bc LDR	X9, [X0], #8

0x45d3c0 LDR	X1, [X21, X9,LSL #3]

0x45d3c4 STR	X3, [X19, X1,LSL #3]

0x45d3c8 LDR	X30, [X0], #8

0x45d3cc LDR	X16, [X21, X30,LSL #3]

0x45d3d0 STR	X3, [X19, X16,LSL #3]

0x45d3d4 LDR	X9, [X0], #8

0x45d3d8 LDR	X1, [X21, X9,LSL #3]

0x45d3dc STR	X3, [X19, X1,LSL #3]

0x45d3e0 LDR	X30, [X0], #8

0x45d3e4 LDR	X16, [X21, X30,LSL #3]

0x45d3e8 STR	X3, [X19, X16,LSL #3]

0x45d3ec CMP	X0, X4

0x45d3f0 B.EQ	45d464

  (874) 0x45d3f4 ORR	X1, XZR, X0

  (874) 0x45d3f8 ADD	X0, X0, #64

  (874) 0x45d3fc LDR	X9, [X1], #8

  (874) 0x45d400 LDR	X30, [X21, X9,LSL #3]

  (874) 0x45d404 STR	X3, [X19, X30,LSL #3]

  (874) 0x45d408 LDUR	X16, [X0, #456]

  (874) 0x45d40c LDR	X9, [X21, X16,LSL #3]

  (874) 0x45d410 STR	X3, [X19, X9,LSL #3]

  (874) 0x45d414 LDR	X1, [X1, #8]

  (874) 0x45d418 LDR	X30, [X21, X1,LSL #3]

  (874) 0x45d41c STR	X3, [X19, X30,LSL #3]

  (874) 0x45d420 LDUR	X16, [X0, #472]

  (874) 0x45d424 LDR	X9, [X21, X16,LSL #3]

  (874) 0x45d428 STR	X3, [X19, X9,LSL #3]

  (874) 0x45d42c LDUR	X1, [X0, #480]

  (874) 0x45d430 LDR	X30, [X21, X1,LSL #3]

  (874) 0x45d434 STR	X3, [X19, X30,LSL #3]

  (874) 0x45d438 LDUR	X16, [X0, #488]

  (874) 0x45d43c LDR	X9, [X21, X16,LSL #3]

  (874) 0x45d440 STR	X3, [X19, X9,LSL #3]

  (874) 0x45d444 LDUR	X1, [X0, #496]

  (874) 0x45d448 LDR	X30, [X21, X1,LSL #3]

  (874) 0x45d44c STR	X3, [X19, X30,LSL #3]

  (874) 0x45d450 LDUR	X16, [X0, #504]

  (874) 0x45d454 LDR	X9, [X21, X16,LSL #3]

  (874) 0x45d458 STR	X3, [X19, X9,LSL #3]

  (874) 0x45d45c CMP	X0, X4

  (874) 0x45d460 B.NE	45d3f4

0x45d464 LDR	X1, [X18, X5]

0x45d468 LDR	X4, [SP, #144]

0x45d46c LDR	X0, [X4, X5]

0x45d470 ADD	X16, X4, X14

0x45d474 LDR	X14, [X4, X14]

0x45d478 CMP	X0, X14

0x45d47c B.GE	45dae4

0x45d480 LDR	X30, [SP, #192]

0x45d484 CBZ	X30, 45da54

0x45d488 ORR	X30, XZR, X21

0x45d48c LDR	X21, [SP, #168]

0x45d490 STP	X7, X2, [SP, #112]

0x45d494 B	45d4ec

  (873) 0x45d498 LDR	X2, [X27, X5]

  (873) 0x45d49c LDR	X7, [X13, X4]

  (873) 0x45d4a0 CMP	X2, X7

  (873) 0x45d4a4 B.EQ	45d50c

  (873) 0x45d4a8 CMN	X9, #1

  (873) 0x45d4ac B.EQ	45d4e0

  (873) 0x45d4b0 LDR	X9, [X19, X4]

  (873) 0x45d4b4 CMP	X3, X9

  (873) 0x45d4b8 B.NE	45d4e0

  (873) 0x45d4bc LDR	D5, [X15, X0,LSL #3]

  (873) 0x45d4c0 UBFM	X14, X1, #61, #60

  (873) 0x45d4c4 ADD	X1, X1, #1

  (873) 0x45d4c8 LDR	X4, [X21, X4]

  (873) 0x45d4cc LDR	X2, [SP, #96]

  (873) 0x45d4d0 FADD	D29, D29, D5

  (873) 0x45d4d4 STR	D5, [X6, X14]

  (873) 0x45d4d8 STR	X4, [X2, X14]

  (873) 0x45d4dc LDR	X14, [X16]

  (873) 0x45d4e0 ADD	X0, X0, #1

  (873) 0x45d4e4 CMP	X0, X14

  (873) 0x45d4e8 B.GE	45d598

  (873) 0x45d4ec LDR	X7, [X24, X0,LSL #3]

  (873) 0x45d4f0 LDR	X9, [X8, X7,LSL #3]

  (873) 0x45d4f4 UBFM	X4, X9, #61, #60

  (873) 0x45d4f8 LDR	X2, [X23, X4]

  (873) 0x45d4fc CMN	X2, #3

  (873) 0x45d500 B.EQ	45d4a8

  (873) 0x45d504 CMP	X10, #1

  (873) 0x45d508 B.NE	45d498

  (873) 0x45d50c LDR	D6, [X15, X0,LSL #3]

  (873) 0x45d510 FADD	D4, D4, D6

  (873) 0x45d514 B	45d4a8

0x45d598 LDP	X7, X2, [SP, #112]

0x45d59c ORR	X21, XZR, X30

0x45d5a0 LDR	X4, [X18, X5]

0x45d5a4 LDR	X3, [X11, X5]

0x45d5a8 LDR	D27, [X28, X3,LSL #3]

0x45d5ac FMUL	D0, D29, D27

0x45d5b0 FCMP	D0, #0

0x45d5b4 B.EQ	45d5c0

0x45d5b8 FNEG	D1, D4

0x45d5bc FDIV	D31, D1, D0

0x45d5c0 LDR	X3, [X12, X5]

0x45d5c4 CMP	X3, X2

0x45d5c8 B.GE	45d7bc

0x45d5cc SUB	X9, X2, X3

0x45d5d0 SUB	X5, X9, #1

0x45d5d4 CMP	X5, #2

0x45d5d8 B.LS	45d774

0x45d5dc UBFM	X30, X9, #2, #63

0x45d5e0 ADD	X0, X7, X3,LSL #3

0x45d5e4 DUP	V26.2D, V31.D[0]

0x45d5e8 UBFM	X16, X3, #61, #60

0x45d5ec UBFM	X14, X30, #59, #58

0x45d5f0 SUB	X14, X14, #32

0x45d5f4 ADD	X5, X0, X30,LSL #5

0x45d5f8 UBFM	X30, X14, #5, #63

0x45d5fc ADD	X14, X30, #1

0x45d600 ANDS	X30, X14, #4224

0x45d604 B.EQ	45d6bc

0x45d608 CMP	X30, #1

0x45d60c B.EQ	45d6a4

0x45d610 CMP	X30, #2

0x45d614 B.EQ	45d694

0x45d618 CMP	X30, #3

0x45d61c B.EQ	45d684

0x45d620 CMP	X30, #4

0x45d624 B.EQ	45d674

0x45d628 CMP	X30, #5

0x45d62c B.EQ	45d664

0x45d630 CMP	X30, #6

0x45d634 B.EQ	45d654

0x45d638 LDR	Q2, [X7, X16]

0x45d63c ADD	X0, X0, #32

0x45d640 LDUR	Q3, [X0, #496]

0x45d644 FMUL	V22.2D, V2.2D, V26.2D

0x45d648 FMUL	V23.2D, V3.2D, V26.2D

0x45d64c STR	Q22, [X7, X16]

0x45d650 STUR	Q23, [X0, #496]

0x45d654 LDP	Q24, Q30, [X0]

0x45d658 FMUL	V25.2D, V24.2D, V26.2D

0x45d65c FMUL	V19.2D, V30.2D, V26.2D

0x45d660 STP	Q25, Q19, [X0], #32

0x45d664 LDP	Q4, Q28, [X0]

0x45d668 FMUL	V29.2D, V4.2D, V26.2D

0x45d66c FMUL	V21.2D, V28.2D, V26.2D

0x45d670 STP	Q29, Q21, [X0], #32

0x45d674 LDP	Q20, Q6, [X0]

0x45d678 FMUL	V5.2D, V20.2D, V26.2D

0x45d67c FMUL	V16.2D, V6.2D, V26.2D

0x45d680 STP	Q5, Q16, [X0], #32

0x45d684 LDP	Q7, Q18, [X0]

0x45d688 FMUL	V17.2D, V7.2D, V26.2D

0x45d68c FMUL	V27.2D, V18.2D, V26.2D

0x45d690 STP	Q17, Q27, [X0], #32

0x45d694 LDP	Q0, Q1, [X0]

0x45d698 FMUL	V2.2D, V0.2D, V26.2D

0x45d69c FMUL	V22.2D, V1.2D, V26.2D

0x45d6a0 STP	Q2, Q22, [X0], #32

0x45d6a4 LDP	Q3, Q23, [X0]

0x45d6a8 FMUL	V24.2D, V3.2D, V26.2D

0x45d6ac FMUL	V30.2D, V23.2D, V26.2D

0x45d6b0 STP	Q24, Q30, [X0], #32

0x45d6b4 CMP	X5, X0

0x45d6b8 B.EQ	45d764

0x45d6bc STP	X19, X8, [SP, #112]

0x45d6c0 STR	X21, [SP, #200]

  (870) 0x45d6c4 LDP	Q25, Q19, [X0]

  (870) 0x45d6c8 ORR	X19, XZR, X0

  (870) 0x45d6cc LDP	Q29, Q21, [X0, #32]

  (870) 0x45d6d0 LDP	Q20, Q5, [X0, #64]

  (870) 0x45d6d4 LDP	Q17, Q27, [X0, #96]

  (870) 0x45d6d8 LDP	Q30, Q2, [X0, #128]

  (870) 0x45d6dc FMUL	V4.2D, V25.2D, V26.2D

  (870) 0x45d6e0 LDP	Q0, Q1, [X0, #160]

  (870) 0x45d6e4 FMUL	V28.2D, V19.2D, V26.2D

  (870) 0x45d6e8 LDP	Q24, Q25, [X0, #192]

  (870) 0x45d6ec FMUL	V6.2D, V29.2D, V26.2D

  (870) 0x45d6f0 LDP	Q22, Q23, [X0, #224]

  (870) 0x45d6f4 ADD	X0, X0, #256

  (870) 0x45d6f8 FMUL	V16.2D, V21.2D, V26.2D

  (870) 0x45d6fc FMUL	V7.2D, V20.2D, V26.2D

  (870) 0x45d700 FMUL	V18.2D, V5.2D, V26.2D

  (870) 0x45d704 FMUL	V3.2D, V17.2D, V26.2D

  (870) 0x45d708 FMUL	V19.2D, V27.2D, V26.2D

  (870) 0x45d70c FMUL	V29.2D, V0.2D, V26.2D

  (870) 0x45d710 FMUL	V21.2D, V1.2D, V26.2D

  (870) 0x45d714 STUR	Q7, [X0, #320]

  (870) 0x45d718 FMUL	V20.2D, V24.2D, V26.2D

  (870) 0x45d71c STUR	Q18, [X0, #336]

  (870) 0x45d720 FMUL	V5.2D, V25.2D, V26.2D

  (870) 0x45d724 STP	Q4, Q28, [X0, #1792]

  (870) 0x45d728 FMUL	V4.2D, V30.2D, V26.2D

  (870) 0x45d72c FMUL	V28.2D, V2.2D, V26.2D

  (870) 0x45d730 STP	Q6, Q16, [X0, #1824]

  (870) 0x45d734 FMUL	V6.2D, V22.2D, V26.2D

  (870) 0x45d738 FMUL	V16.2D, V23.2D, V26.2D

  (870) 0x45d73c STP	Q3, Q19, [X0, #1888]

  (870) 0x45d740 STP	Q4, Q28, [X0, #1920]

  (870) 0x45d744 STP	Q29, Q21, [X0, #1952]

  (870) 0x45d748 STP	Q20, Q5, [X0, #1984]

  (870) 0x45d74c STUR	Q6, [X0, #480]

  (870) 0x45d750 STR	Q16, [X19, #240]

  (870) 0x45d754 CMP	X5, X0

  (870) 0x45d758 B.NE	45d6c4

0x45d75c LDR	X21, [SP, #200]

0x45d760 LDP	X19, X8, [SP, #112]

0x45d764 ANDS	XZR, X9, #4160

0x45d768 B.EQ	45d7bc

0x45d76c AND	X9, X9, #8062

0x45d770 ADD	X3, X3, X9

0x45d774 UBFM	X16, X3, #61, #60

0x45d778 ADD	X5, X3, #1

0x45d77c LDR	D26, [X7, X16]

0x45d780 FMUL	D7, D26, D31

0x45d784 STR	D7, [X7, X16]

0x45d788 CMP	X2, X5

0x45d78c B.LE	45d7bc

0x45d790 ADD	X14, X16, #8

0x45d794 ADD	X30, X3, #2

0x45d798 LDR	D18, [X7, X14]

0x45d79c FMUL	D17, D18, D31

0x45d7a0 STR	D17, [X7, X14]

0x45d7a4 CMP	X2, X30

0x45d7a8 B.LE	45d7bc

0x45d7ac ADD	X2, X16, #16

0x45d7b0 LDR	D27, [X7, X2]

0x45d7b4 FMUL	D30, D27, D31

0x45d7b8 STR	D30, [X7, X2]

0x45d7bc CMP	X1, X4

0x45d7c0 B.LE	45d9ac

0x45d7c4 SUB	X3, X1, X4

0x45d7c8 SUB	X0, X3, #1

0x45d7cc CMP	X0, #2

0x45d7d0 B.LS	45d964

0x45d7d4 UBFM	X16, X3, #2, #63

0x45d7d8 ADD	X0, X6, X4,LSL #3

0x45d7dc DUP	V28.2D, V31.D[0]

0x45d7e0 UBFM	X9, X4, #61, #60

0x45d7e4 UBFM	X5, X16, #59, #58

0x45d7e8 SUB	X14, X5, #32

0x45d7ec ADD	X2, X0, X16,LSL #5

0x45d7f0 UBFM	X30, X14, #5, #63

0x45d7f4 ADD	X16, X30, #1

0x45d7f8 ANDS	X5, X16, #4224

0x45d7fc B.EQ	45d8b4

0x45d800 CMP	X5, #1

0x45d804 B.EQ	45d89c

0x45d808 CMP	X5, #2

0x45d80c B.EQ	45d88c

0x45d810 CMP	X5, #3

0x45d814 B.EQ	45d87c

0x45d818 CMP	X5, #4

0x45d81c B.EQ	45d86c

0x45d820 CMP	X5, #5

0x45d824 B.EQ	45d85c

0x45d828 CMP	X5, #6

0x45d82c B.EQ	45d84c

0x45d830 LDR	Q2, [X6, X9]

0x45d834 ADD	X0, X0, #32

0x45d838 LDUR	Q1, [X0, #496]

0x45d83c FMUL	V0.2D, V2.2D, V28.2D

0x45d840 FMUL	V24.2D, V1.2D, V28.2D

0x45d844 STR	Q0, [X6, X9]

0x45d848 STUR	Q24, [X0, #496]

0x45d84c LDP	Q25, Q22, [X0]

0x45d850 FMUL	V23.2D, V25.2D, V28.2D

0x45d854 FMUL	V3.2D, V22.2D, V28.2D

0x45d858 STP	Q23, Q3, [X0], #32

0x45d85c LDP	Q19, Q4, [X0]

0x45d860 FMUL	V29.2D, V19.2D, V28.2D

0x45d864 FMUL	V21.2D, V4.2D, V28.2D

0x45d868 STP	Q29, Q21, [X0], #32

0x45d86c LDP	Q20, Q5, [X0]

0x45d870 FMUL	V6.2D, V20.2D, V28.2D

0x45d874 FMUL	V16.2D, V5.2D, V28.2D

0x45d878 STP	Q6, Q16, [X0], #32

0x45d87c LDP	Q26, Q7, [X0]

0x45d880 FMUL	V18.2D, V26.2D, V28.2D

0x45d884 FMUL	V17.2D, V7.2D, V28.2D

0x45d888 STP	Q18, Q17, [X0], #32

0x45d88c LDP	Q27, Q2, [X0]

0x45d890 FMUL	V30.2D, V27.2D, V28.2D

0x45d894 FMUL	V0.2D, V2.2D, V28.2D

0x45d898 STP	Q30, Q0, [X0], #32

0x45d89c LDP	Q1, Q24, [X0]

0x45d8a0 FMUL	V25.2D, V1.2D, V28.2D

0x45d8a4 FMUL	V22.2D, V24.2D, V28.2D

0x45d8a8 STP	Q25, Q22, [X0], #32

0x45d8ac CMP	X2, X0

0x45d8b0 B.EQ	45d954

0x45d8b4 STR	X3, [SP, #112]

  (869) 0x45d8b8 LDP	Q23, Q3, [X0]

  (869) 0x45d8bc ORR	X9, XZR, X0

  (869) 0x45d8c0 LDP	Q29, Q5, [X0, #32]

  (869) 0x45d8c4 LDP	Q6, Q20, [X0, #64]

  (869) 0x45d8c8 LDP	Q17, Q18, [X0, #96]

  (869) 0x45d8cc LDP	Q30, Q0, [X0, #128]

  (869) 0x45d8d0 FMUL	V19.2D, V23.2D, V28.2D

  (869) 0x45d8d4 LDP	Q1, Q24, [X0, #160]

  (869) 0x45d8d8 FMUL	V4.2D, V3.2D, V28.2D

  (869) 0x45d8dc LDP	Q25, Q22, [X0, #192]

  (869) 0x45d8e0 FMUL	V21.2D, V29.2D, V28.2D

  (869) 0x45d8e4 LDP	Q2, Q27, [X0, #224]

  (869) 0x45d8e8 ADD	X0, X0, #256

  (869) 0x45d8ec FMUL	V16.2D, V5.2D, V28.2D

  (869) 0x45d8f0 FMUL	V26.2D, V6.2D, V28.2D

  (869) 0x45d8f4 FMUL	V7.2D, V20.2D, V28.2D

  (869) 0x45d8f8 FMUL	V23.2D, V17.2D, V28.2D

  (869) 0x45d8fc FMUL	V29.2D, V30.2D, V28.2D

  (869) 0x45d900 FMUL	V20.2D, V0.2D, V28.2D

  (869) 0x45d904 FMUL	V5.2D, V1.2D, V28.2D

  (869) 0x45d908 STUR	Q26, [X0, #320]

  (869) 0x45d90c FMUL	V6.2D, V24.2D, V28.2D

  (869) 0x45d910 STUR	Q7, [X0, #336]

  (869) 0x45d914 FMUL	V3.2D, V25.2D, V28.2D

  (869) 0x45d918 STP	Q19, Q4, [X0, #1792]

  (869) 0x45d91c FMUL	V19.2D, V18.2D, V28.2D

  (869) 0x45d920 FMUL	V4.2D, V22.2D, V28.2D

  (869) 0x45d924 STP	Q21, Q16, [X0, #1824]

  (869) 0x45d928 FMUL	V21.2D, V2.2D, V28.2D

  (869) 0x45d92c FMUL	V16.2D, V27.2D, V28.2D

  (869) 0x45d930 STP	Q23, Q19, [X0, #1888]

  (869) 0x45d934 STP	Q29, Q20, [X0, #1920]

  (869) 0x45d938 STP	Q5, Q6, [X0, #1952]

  (869) 0x45d93c STP	Q3, Q4, [X0, #1984]

  (869) 0x45d940 STUR	Q21, [X0, #480]

  (869) 0x45d944 STR	Q16, [X9, #240]

  (869) 0x45d948 CMP	X2, X0

  (869) 0x45d94c B.NE	45d8b8

0x45d950 LDR	X3, [SP, #112]

0x45d954 ANDS	XZR, X3, #4160

0x45d958 B.EQ	45d9ac

0x45d95c AND	X14, X3, #8062

0x45d960 ADD	X4, X4, X14

0x45d964 UBFM	X30, X4, #61, #60

0x45d968 ADD	X2, X4, #1

0x45d96c LDR	D28, [X6, X30]

0x45d970 FMUL	D26, D28, D31

0x45d974 STR	D26, [X6, X30]

0x45d978 CMP	X1, X2

0x45d97c B.LE	45d9ac

0x45d980 ADD	X16, X30, #8

0x45d984 ADD	X4, X4, #2

0x45d988 LDR	D7, [X6, X16]

0x45d98c FMUL	D17, D7, D31

0x45d990 STR	D17, [X6, X16]

0x45d994 CMP	X1, X4

0x45d998 B.LE	45d9ac

0x45d99c ADD	X1, X30, #16

0x45d9a0 LDR	D18, [X6, X1]

0x45d9a4 FMUL	D30, D18, D31

0x45d9a8 STR	D30, [X6, X1]

0x45d9ac LDR	X5, [SP, #152]

0x45d9b0 ADD	X17, X17, #8

0x45d9b4 CMP	X17, X5

0x45d9b8 B.NE	45d104

0x45d9e4 LDR	X16, [SP, #160]

0x45d9e8 STR	X5, [SP, #112]

  (875) 0x45d9ec LDR	X1, [X25, X0,LSL #3]

  (875) 0x45d9f0 UBFM	X4, X1, #61, #60

  (875) 0x45d9f4 LDR	X5, [X26, X4]

  (875) 0x45d9f8 CMN	X5, #3

  (875) 0x45d9fc B.EQ	45da08

  (875) 0x45da00 LDR	D19, [X28, X0,LSL #3]

  (875) 0x45da04 FADD	D4, D4, D19

  (875) 0x45da08 CMN	X1, #1

  (875) 0x45da0c B.EQ	45da40

  (875) 0x45da10 LDR	X1, [X20, X4]

  (875) 0x45da14 CMP	X3, X1

  (875) 0x45da18 B.NE	45da40

  (875) 0x45da1c LDR	D28, [X28, X0,LSL #3]

  (875) 0x45da20 UBFM	X9, X2, #61, #60

  (875) 0x45da24 ADD	X2, X2, #1

  (875) 0x45da28 LDR	X4, [X16, X4]

  (875) 0x45da2c LDR	X5, [SP, #104]

  (875) 0x45da30 FADD	D29, D29, D28

  (875) 0x45da34 STR	D28, [X7, X9]

  (875) 0x45da38 STR	X4, [X5, X9]

  (875) 0x45da3c LDR	X9, [X30]

  (875) 0x45da40 ADD	X0, X0, #1

  (875) 0x45da44 CMP	X0, X9

  (875) 0x45da48 B.LT	45d9ec

0x45da4c LDR	X5, [SP, #112]

0x45da50 B	45d318

0x45da54 CMP	X10, #1

0x45da58 B.EQ	45daec

0x45da5c LDR	X30, [SP, #168]

0x45da60 ORR	X9, XZR, X8

0x45da64 STP	X7, X2, [SP, #112]

  (872) 0x45da68 LDR	X8, [X24, X0,LSL #3]

  (872) 0x45da6c UBFM	X4, X8, #61, #60

  (872) 0x45da70 LDR	X7, [X23, X4]

  (872) 0x45da74 CMN	X7, #3

  (872) 0x45da78 B.EQ	45da94

  (872) 0x45da7c LDR	X2, [X13, X4]

  (872) 0x45da80 LDR	X7, [X27, X5]

  (872) 0x45da84 CMP	X2, X7

  (872) 0x45da88 B.NE	45da94

  (872) 0x45da8c LDR	D18, [X15, X0,LSL #3]

  (872) 0x45da90 FADD	D4, D4, D18

  (872) 0x45da94 CMN	X8, #1

  (872) 0x45da98 B.EQ	45dacc

  (872) 0x45da9c LDR	X8, [X19, X4]

  (872) 0x45daa0 CMP	X3, X8

  (872) 0x45daa4 B.NE	45dacc

  (872) 0x45daa8 LDR	D17, [X15, X0,LSL #3]

  (872) 0x45daac UBFM	X14, X1, #61, #60

  (872) 0x45dab0 ADD	X1, X1, #1

  (872) 0x45dab4 LDR	X4, [X30, X4]

  (872) 0x45dab8 LDR	X2, [SP, #96]

  (872) 0x45dabc FADD	D29, D29, D17

  (872) 0x45dac0 STR	D17, [X6, X14]

  (872) 0x45dac4 STR	X4, [X2, X14]

  (872) 0x45dac8 LDR	X14, [X16]

  (872) 0x45dacc ADD	X0, X0, #1

  (872) 0x45dad0 CMP	X14, X0

  (872) 0x45dad4 B.GT	45da68

0x45dad8 LDP	X7, X2, [SP, #112]

0x45dadc ORR	X8, XZR, X9

0x45dae0 B	45d5a0

0x45dae4 ORR	X4, XZR, X1

0x45dae8 B	45d5a4

0x45daec LDR	X30, [SP, #168]

0x45daf0 STR	X2, [SP, #112]

0x45daf4 HINT	#0

0x45daf8 HINT	#0

0x45dafc HINT	#0

  (871) 0x45db00 LDR	X4, [X24, X0,LSL #3]

  (871) 0x45db04 UBFM	X9, X4, #61, #60

  (871) 0x45db08 LDR	X2, [X23, X9]

  (871) 0x45db0c CMN	X2, #3

  (871) 0x45db10 B.EQ	45db1c

  (871) 0x45db14 LDR	D16, [X15, X0,LSL #3]

  (871) 0x45db18 FADD	D4, D4, D16

  (871) 0x45db1c CMN	X4, #1

  (871) 0x45db20 B.EQ	45db54

  (871) 0x45db24 LDR	X4, [X19, X9]

  (871) 0x45db28 CMP	X3, X4

  (871) 0x45db2c B.NE	45db54

  (871) 0x45db30 LDR	D7, [X15, X0,LSL #3]

  (871) 0x45db34 UBFM	X14, X1, #61, #60

  (871) 0x45db38 ADD	X1, X1, #1

  (871) 0x45db3c LDR	X9, [X30, X9]

  (871) 0x45db40 LDR	X2, [SP, #96]

  (871) 0x45db44 FADD	D29, D29, D7

  (871) 0x45db48 STR	D7, [X6, X14]

  (871) 0x45db4c STR	X9, [X2, X14]

  (871) 0x45db50 LDR	X14, [X16]

  (871) 0x45db54 ADD	X0, X0, #1

  (871) 0x45db58 CMP	X14, X0

  (871) 0x45db5c B.GT	45db00

0x45db60 LDR	X2, [SP, #112]

0x45db64 B	45d5a0

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1593 - 1660

--------------------------------------------------------------------------------

1593:            {   tmp_marker_offd[i] = -1; }

[...]

1605:            for (i=thread_start; i < thread_stop; i++)

1606:            {

1607:              i1 = pass_array[i];

1608:              sum_C = 0;

1609:              sum_N = 0;

1610:              j_start = P_diag_start[i1];

1611:              j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1];

1612:              for (j=j_start; j < j_end; j++)

1613:              {

1614:                 k1 = P_diag_pass[1][j];

1615:                 tmp_marker[C_array[k1]] = i1;

1616:              }

1617:              cnt = P_diag_i[i1];

1618:              for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1619:              {

1620:                 j1 = A_diag_j[j];

1621:                 if (CF_marker[j1] != -3 &&

1622:                    (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1623:                    sum_N += A_diag_data[j];

1624:                 if (j1 != -1 && tmp_marker[j1] == i1)

1625:                 {

1626:                    P_diag_data[cnt] = A_diag_data[j];

1627:                    P_diag_j[cnt++] = fine_to_coarse[j1];

1628:                    sum_C += A_diag_data[j];

1629:                 }

1630:              }

1631:              j_start = P_offd_start[i1];

1632:              j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1];

1633:              for (j=j_start; j < j_end; j++)

1634:              {

1635:                 k1 = P_offd_pass[1][j];

1636:                 tmp_marker_offd[C_array_offd[k1]] = i1;

1637:              }

1638:              cnt_offd = P_offd_i[i1];

1639:              for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++)

1640:              {

1641:                 if (col_offd_S_to_A)

1642:                     j1 = map_A_to_S[A_offd_j[j]];

1643:                 else

1644:                     j1 = A_offd_j[j];

1645:                 if (CF_marker_offd[j1] != -3 &&

1646:                   (num_functions == 1 || dof_func[i1] == dof_func_offd[j1]))

1647:                     sum_N += A_offd_data[j];

1648:                 if (j1 != -1 && tmp_marker_offd[j1] == i1)

1649:                 {

1650:                    P_offd_data[cnt_offd] = A_offd_data[j];

1651:                    P_offd_j[cnt_offd++] = map_S_to_new[j1];

1652:                    sum_C += A_offd_data[j];

1653:                 }

1654:              }

1655:              diagonal = A_diag_data[A_diag_i[i1]];

1656:              if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal);

1657:              for (j=P_diag_i[i1]; j < cnt; j++)

1658:                 P_diag_data[j] *= alfa;

1659:              for (j=P_offd_i[i1]; j < cnt_offd; j++)

1660:                 P_offd_data[j] *= alfa;

Coverage (%)	Name	Source Location	Module
►98.53+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.47+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:1669	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.96
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.13
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P12, P13, P14,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.9
Source	par_multi_interp.c:1593-1593,par_multi_interp.c:1605-1618,par_multi_interp.c:1631-1639,par_multi_interp.c:1655-1660
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	44.33
CQA cycles if no scalar integer	15.00
CQA cycles if FP arith vectorized	44.33
CQA cycles if fully vectorized	39.17
Front-end cycles	43.63
P0 cycles	28.00
P1 cycles	28.00
P2 cycles	23.75
P3 cycles	23.75
P4 cycles	23.67
P5 cycles	23.67
P6 cycles	23.58
P7 cycles	23.58
P8 cycles	16.00
P9 cycles	16.00
P10 cycles	16.00
P11 cycles	16.00
P12 cycles	44.33
P13 cycles	44.33
P14 cycles	44.33
P15 cycles	11.00
P16 cycles	11.00
DIV/SQRT cycles	1.75 - 3.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	355.00
Nb uops	349.00
Nb loads	NA
Nb stores	44.00
Nb stack references	0.00
FLOP/cycle	1.44
Nb FLOP add-sub	0.00
Nb FLOP mul	63.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	39.88
Bytes prefetched	0.00
Bytes loaded	1064.00
Bytes stored	704.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	40.26
Vectorization ratio load	69.57
Vectorization ratio store	36.36
Vectorization ratio mul	80.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	3.92
Vector-efficiency ratio all	71.43
Vector-efficiency ratio load	84.78
Vector-efficiency ratio store	72.73
Vector-efficiency ratio mul	90.00
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	51.96

Metric	Value
CQA speedup if no scalar integer	2.96
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.13
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P12, P13, P14,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.9
Source	par_multi_interp.c:1593-1593,par_multi_interp.c:1605-1618,par_multi_interp.c:1631-1639,par_multi_interp.c:1655-1660
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	44.33
CQA cycles if no scalar integer	15.00
CQA cycles if FP arith vectorized	44.33
CQA cycles if fully vectorized	39.17
Front-end cycles	43.63
P0 cycles	28.00
P1 cycles	28.00
P2 cycles	23.75
P3 cycles	23.75
P4 cycles	23.67
P5 cycles	23.67
P6 cycles	23.58
P7 cycles	23.58
P8 cycles	16.00
P9 cycles	16.00
P10 cycles	16.00
P11 cycles	16.00
P12 cycles	44.33
P13 cycles	44.33
P14 cycles	44.33
P15 cycles	11.00
P16 cycles	11.00
DIV/SQRT cycles	1.75 - 3.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	355.00
Nb uops	349.00
Nb loads	NA
Nb stores	44.00
Nb stack references	0.00
FLOP/cycle	1.44
Nb FLOP add-sub	0.00
Nb FLOP mul	63.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	39.88
Bytes prefetched	0.00
Bytes loaded	1064.00
Bytes stored	704.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	40.26
Vectorization ratio load	69.57
Vectorization ratio store	36.36
Vectorization ratio mul	80.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	3.92
Vector-efficiency ratio all	71.43
Vector-efficiency ratio load	84.78
Vector-efficiency ratio store	72.73
Vector-efficiency ratio mul	90.00
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	51.96

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass._omp_fn.9
Source file and lines	par_multi_interp.c:1593-1660
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1593,1605-1660.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1593,1605-1618,1631-1639,1655-1660.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 44.33 to 15.00 cycles (2.96x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 71% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 44.33 to 39.17 cycles (1.13x speedup).

Details

40% of VPU instructions are used in vector version (process two or more data elements in vector registers):

69% of VPU loads are used in vector version.
36% of VPU stores are used in vector version.
80% of VPU multiply instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
3% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 64 FP arithmetical operations:

63: multiply
1: divide

The binary loop is loading 1064 bytes. The binary loop is storing 704 bytes.

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	355
loop length	1420
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

43.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	28.00	28.00	23.75	23.75	23.67	23.67	23.58	23.58	16.00	16.00	16.00	16.00	44.33	44.33	44.33	11.00	11.00
cycles	28.00	28.00	23.75	23.75	23.67	23.67	23.58	23.58	16.00	16.00	16.00	16.00	44.33	44.33	44.33	11.00	11.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

1.75-3.50

Cycles summary

Front-end	43.63
Overall L1	44.33

Vectorization ratios

INT

all	29%
load	69%
store	36%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	4%

all	71%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	80%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

INT+FP

all	40%
load	69%
store	36%
mul	80%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	3%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 44.33 cycles. At this rate:

24% of peak load performance is reached (24.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (15.88 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 45d104

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR X3, [X17]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X30, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X5, X3, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X14, X5, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X2, [X12, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X12, X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X30, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X0, X16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X1, X9, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X0, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 45d260 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x270>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X16, X0, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X4, [X2, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X30, X4, X1,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, X4, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X9, X30, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X1, X9, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X2, X1, #3, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X9, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ANDS X1, X9, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 45d1ec <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x1fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d1d8 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x1e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d1cc <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x1dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d1c0 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x1d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d1b4 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x1c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d1a8 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x1b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d19c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x1ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [X4, X16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X4, [X22, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X2, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X22, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X20, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X1, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X22, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X20, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X4, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X22, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X20, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X9, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X22, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X20, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X16, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X22, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X2, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X22, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X20, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X30, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d25c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x26c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [X12, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVI D4, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X30, X11, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X0, [X11, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X11, X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMOV D29, D4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X0, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 45d318 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x328>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d9e4 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x9f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X16, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X19, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X8, X6, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDP X8, X6, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ORR X19, XZR, X16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X0, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X30, [X18, X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X18, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X0, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X16, X0, X30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X16, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X0, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 45d468 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x478>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X30, X0, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X16, [X9, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X4, X16, X4,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, X16, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X1, X4, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X9, X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X1, X9, #3, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X9, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ANDS X1, X9, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 45d3f4 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x404>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d3e0 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x3f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d3d4 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x3e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d3c8 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x3d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d3bc <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x3cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d3b0 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x3c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d3a4 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x3b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [X16, X30]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X16, [X21, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X19, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X9, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X21, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X19, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X30, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X21, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X19, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X9, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X21, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X19, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X30, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X21, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X19, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X9, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X21, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X19, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X30, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X21, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X19, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X0, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d464 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x474>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [X18, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X4, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X16, X4, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X14, [X4, X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 45dae4 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xaf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X30, 45da54 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xa64>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X30, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X21, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X7, X2, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
B 45d4ec <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x4fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X7, X2, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ORR X21, XZR, X30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X4, [X18, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X11, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D27, [X28, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D0, D29, D27	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FCMP D0, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.EQ 45d5c0 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x5d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FNEG D1, D4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FDIV D31, D1, D0	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
LDR X3, [X12, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X3, X2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 45d7bc <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x7cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X9, X2, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X5, X9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X5, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LS 45d774 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x784>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X30, X9, #2, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, X7, X3,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DUP V26.2D, V31.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
UBFM X16, X3, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X14, X30, #59, #58	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X14, X14, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, X0, X30,LSL #5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
UBFM X30, X14, #5, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X14, X30, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ANDS X30, X14, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 45d6bc <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x6cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d6a4 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x6b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d694 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x6a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d684 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x694>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d674 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x684>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d664 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x674>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d654 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x664>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q2, [X7, X16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR Q3, [X0, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FMUL V22.2D, V2.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V23.2D, V3.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
STR Q22, [X7, X16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STUR Q23, [X0, #496]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q24, Q30, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
FMUL V25.2D, V24.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V19.2D, V30.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
STP Q25, Q19, [X0], #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q4, Q28, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
FMUL V29.2D, V4.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V21.2D, V28.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
STP Q29, Q21, [X0], #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q20, Q6, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
FMUL V5.2D, V20.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V16.2D, V6.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
STP Q5, Q16, [X0], #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q7, Q18, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
FMUL V17.2D, V7.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V27.2D, V18.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
STP Q17, Q27, [X0], #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q0, Q1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
FMUL V2.2D, V0.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V22.2D, V1.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
STP Q2, Q22, [X0], #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q3, Q23, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
FMUL V24.2D, V3.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V30.2D, V23.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
STP Q24, Q30, [X0], #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
CMP X5, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d764 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x774>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X19, X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X21, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X21, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X19, X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ANDS XZR, X9, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d7bc <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x7cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X9, X9, #8062	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, X3, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X16, X3, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, X3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D26, [X7, X16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D7, D26, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
STR D7, [X7, X16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X2, X5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 45d7bc <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x7cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X14, X16, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X30, X3, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D18, [X7, X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D17, D18, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
STR D17, [X7, X14]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X2, X30	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 45d7bc <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x7cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X16, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D27, [X7, X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D30, D27, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
STR D30, [X7, X2]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X1, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 45d9ac <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x9bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X3, X1, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X0, X3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X0, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LS 45d964 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x974>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X16, X3, #2, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, X6, X4,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DUP V28.2D, V31.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
UBFM X9, X4, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X5, X16, #59, #58	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X14, X5, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X2, X0, X16,LSL #5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
UBFM X30, X14, #5, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X16, X30, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ANDS X5, X16, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 45d8b4 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x8c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d89c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x8ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d88c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x89c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d87c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x88c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d86c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x87c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d85c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x86c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d84c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x85c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q2, [X6, X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR Q1, [X0, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FMUL V0.2D, V2.2D, V28.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V24.2D, V1.2D, V28.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
STR Q0, [X6, X9]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STUR Q24, [X0, #496]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q25, Q22, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
FMUL V23.2D, V25.2D, V28.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V3.2D, V22.2D, V28.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
STP Q23, Q3, [X0], #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q19, Q4, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
FMUL V29.2D, V19.2D, V28.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V21.2D, V4.2D, V28.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
STP Q29, Q21, [X0], #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q20, Q5, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
FMUL V6.2D, V20.2D, V28.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V16.2D, V5.2D, V28.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
STP Q6, Q16, [X0], #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q26, Q7, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
FMUL V18.2D, V26.2D, V28.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V17.2D, V7.2D, V28.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
STP Q18, Q17, [X0], #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q27, Q2, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
FMUL V30.2D, V27.2D, V28.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V0.2D, V2.2D, V28.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
STP Q30, Q0, [X0], #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q1, Q24, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
FMUL V25.2D, V1.2D, V28.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V22.2D, V24.2D, V28.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
STP Q25, Q22, [X0], #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
CMP X2, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d954 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x964>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X3, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X3, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ANDS XZR, X3, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d9ac <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x9bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X14, X3, #8062	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X4, X4, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X30, X4, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X2, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D28, [X6, X30]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D26, D28, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
STR D26, [X6, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X1, X2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 45d9ac <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x9bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X16, X30, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X4, X4, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D7, [X6, X16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D17, D7, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
STR D17, [X6, X16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X1, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 45d9ac <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x9bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X1, X30, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D18, [X6, X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D30, D18, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
STR D30, [X6, X1]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR X5, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X17, X17, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X17, X5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 45d104 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X5, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X5, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 45d318 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x328>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 45daec <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xafc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X9, XZR, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X7, X2, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X7, X2, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ORR X8, XZR, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 45d5a0 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x5b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X4, XZR, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 45d5a4 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x5b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR X2, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 45d5a0 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x5b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_BoomerAMGBuildMultipass._omp_fn.9
Source file and lines	par_multi_interp.c:1593-1660
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

40% of VPU instructions are used in vector version (process two or more data elements in vector registers):

69% of VPU loads are used in vector version.
36% of VPU stores are used in vector version.
80% of VPU multiply instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
3% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 64 FP arithmetical operations:

63: multiply
1: divide

The binary loop is loading 1064 bytes. The binary loop is storing 704 bytes.

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	355
loop length	1420
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

43.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	28.00	28.00	23.75	23.75	23.67	23.67	23.58	23.58	16.00	16.00	16.00	16.00	44.33	44.33	44.33	11.00	11.00
cycles	28.00	28.00	23.75	23.75	23.67	23.67	23.58	23.58	16.00	16.00	16.00	16.00	44.33	44.33	44.33	11.00	11.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

1.75-3.50

Cycles summary

Front-end	43.63
Overall L1	44.33

Vectorization ratios

INT

all	29%
load	69%
store	36%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	4%

all	71%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	80%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

INT+FP

all	40%
load	69%
store	36%
mul	80%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	3%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 44.33 cycles. At this rate:

24% of peak load performance is reached (24.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (15.88 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 45d104

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR X3, [X17]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X30, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X5, X3, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X14, X5, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X2, [X12, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X12, X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X30, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X0, X16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X1, X9, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X0, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 45d260 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x270>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X16, X0, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X4, [X2, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X30, X4, X1,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, X4, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X9, X30, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X1, X9, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X2, X1, #3, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X9, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ANDS X1, X9, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 45d1ec <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x1fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d1d8 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x1e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d1cc <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x1dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d1c0 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x1d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d1b4 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x1c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d1a8 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x1b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d19c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x1ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [X4, X16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X4, [X22, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X2, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X22, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X20, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X1, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X22, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X20, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X4, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X22, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X20, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X9, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X22, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X20, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X16, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X22, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X2, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X22, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X20, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X30, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d25c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x26c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [X12, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVI D4, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X30, X11, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X0, [X11, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X11, X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMOV D29, D4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X0, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 45d318 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x328>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d9e4 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x9f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X16, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X19, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X8, X6, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDP X8, X6, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ORR X19, XZR, X16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X0, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X30, [X18, X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X18, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X0, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X16, X0, X30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X16, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X0, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 45d468 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x478>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X30, X0, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X16, [X9, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X4, X16, X4,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, X16, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X1, X4, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X9, X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X1, X9, #3, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X9, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ANDS X1, X9, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 45d3f4 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x404>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d3e0 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x3f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d3d4 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x3e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d3c8 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x3d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d3bc <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x3cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d3b0 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x3c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d3a4 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x3b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [X16, X30]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X16, [X21, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X19, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X9, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X21, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X19, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X30, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X21, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X19, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X9, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X21, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X19, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X30, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X21, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X19, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X9, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X21, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X19, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X30, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X21, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X19, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X0, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d464 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x474>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [X18, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X4, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X16, X4, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X14, [X4, X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 45dae4 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xaf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X30, 45da54 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xa64>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X30, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X21, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X7, X2, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
B 45d4ec <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x4fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X7, X2, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ORR X21, XZR, X30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X4, [X18, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X11, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D27, [X28, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D0, D29, D27	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FCMP D0, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.EQ 45d5c0 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x5d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FNEG D1, D4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FDIV D31, D1, D0	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
LDR X3, [X12, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X3, X2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 45d7bc <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x7cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X9, X2, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X5, X9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X5, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LS 45d774 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x784>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X30, X9, #2, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, X7, X3,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DUP V26.2D, V31.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
UBFM X16, X3, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X14, X30, #59, #58	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X14, X14, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, X0, X30,LSL #5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
UBFM X30, X14, #5, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X14, X30, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ANDS X30, X14, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 45d6bc <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x6cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d6a4 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x6b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d694 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x6a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d684 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x694>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d674 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x684>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d664 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x674>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d654 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x664>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q2, [X7, X16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR Q3, [X0, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FMUL V22.2D, V2.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V23.2D, V3.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
STR Q22, [X7, X16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STUR Q23, [X0, #496]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q24, Q30, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
FMUL V25.2D, V24.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V19.2D, V30.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
STP Q25, Q19, [X0], #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q4, Q28, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
FMUL V29.2D, V4.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V21.2D, V28.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
STP Q29, Q21, [X0], #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q20, Q6, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
FMUL V5.2D, V20.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V16.2D, V6.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
STP Q5, Q16, [X0], #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q7, Q18, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
FMUL V17.2D, V7.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V27.2D, V18.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
STP Q17, Q27, [X0], #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q0, Q1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
FMUL V2.2D, V0.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V22.2D, V1.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
STP Q2, Q22, [X0], #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q3, Q23, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
FMUL V24.2D, V3.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V30.2D, V23.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
STP Q24, Q30, [X0], #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
CMP X5, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d764 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x774>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X19, X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X21, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X21, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X19, X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ANDS XZR, X9, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d7bc <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x7cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X9, X9, #8062	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, X3, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X16, X3, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, X3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D26, [X7, X16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D7, D26, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
STR D7, [X7, X16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X2, X5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 45d7bc <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x7cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X14, X16, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X30, X3, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D18, [X7, X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D17, D18, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
STR D17, [X7, X14]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X2, X30	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 45d7bc <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x7cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X16, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D27, [X7, X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D30, D27, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
STR D30, [X7, X2]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X1, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 45d9ac <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x9bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X3, X1, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X0, X3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X0, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LS 45d964 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x974>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X16, X3, #2, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, X6, X4,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DUP V28.2D, V31.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
UBFM X9, X4, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X5, X16, #59, #58	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X14, X5, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X2, X0, X16,LSL #5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
UBFM X30, X14, #5, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X16, X30, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ANDS X5, X16, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 45d8b4 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x8c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d89c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x8ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d88c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x89c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d87c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x88c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d86c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x87c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d85c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x86c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d84c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x85c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q2, [X6, X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR Q1, [X0, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FMUL V0.2D, V2.2D, V28.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V24.2D, V1.2D, V28.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
STR Q0, [X6, X9]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STUR Q24, [X0, #496]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q25, Q22, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
FMUL V23.2D, V25.2D, V28.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V3.2D, V22.2D, V28.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
STP Q23, Q3, [X0], #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q19, Q4, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
FMUL V29.2D, V19.2D, V28.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V21.2D, V4.2D, V28.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
STP Q29, Q21, [X0], #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q20, Q5, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
FMUL V6.2D, V20.2D, V28.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V16.2D, V5.2D, V28.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
STP Q6, Q16, [X0], #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q26, Q7, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
FMUL V18.2D, V26.2D, V28.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V17.2D, V7.2D, V28.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
STP Q18, Q17, [X0], #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q27, Q2, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
FMUL V30.2D, V27.2D, V28.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V0.2D, V2.2D, V28.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
STP Q30, Q0, [X0], #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q1, Q24, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
FMUL V25.2D, V1.2D, V28.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL V22.2D, V24.2D, V28.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
STP Q25, Q22, [X0], #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
CMP X2, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d954 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x964>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X3, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X3, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ANDS XZR, X3, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45d9ac <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x9bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X14, X3, #8062	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X4, X4, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X30, X4, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X2, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D28, [X6, X30]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D26, D28, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
STR D26, [X6, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X1, X2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 45d9ac <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x9bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X16, X30, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X4, X4, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D7, [X6, X16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D17, D7, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
STR D17, [X6, X16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X1, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 45d9ac <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x9bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X1, X30, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D18, [X6, X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D30, D18, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
STR D30, [X6, X1]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR X5, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X17, X17, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X17, X5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 45d104 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X5, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X5, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 45d318 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x328>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 45daec <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xafc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X9, XZR, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X7, X2, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X7, X2, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ORR X8, XZR, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 45d5a0 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x5b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X4, XZR, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 45d5a4 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x5b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR X2, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 45d5a0 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x5b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code