OV - exec - Loop 823

	Loop Id: 823	Module: exec	Source: par_multi_interp.c:939-999 [...]	Coverage: 0.06%

0x458410 LDR	X14, [SP, #104]

0x458414 LDR	X0, [X14, X15,LSL #3]

0x458418 UBFM	X10, X0, #61, #60

0x45841c ADD	X1, X10, #8

0x458420 STR	X6, [X18, X10]

0x458424 ADD	X4, X12, X1

0x458428 STR	X5, [X16, X10]

0x45842c LDR	X3, [X12, X10]

0x458430 LDR	X8, [X12, X1]

0x458434 CMP	X3, X8

0x458438 B.GE	4587a8

0x45843c ORR	X28, XZR, X24

0x458440 STR	X9, [SP, #128]

0x458444 ORR	X9, XZR, X4

0x458448 B	458458

  (826) 0x45844c ADD	X3, X3, #1

  (826) 0x458450 CMP	X3, X8

  (826) 0x458454 B.GE	4587a0

  (826) 0x458458 LDR	X24, [X27, X3,LSL #3]

  (826) 0x45845c UBFM	X2, X24, #61, #60

  (826) 0x458460 LDR	X17, [X25, X2]

  (826) 0x458464 STR	X2, [SP, #96]

  (826) 0x458468 CMP	X17, X7

  (826) 0x45846c B.NE	45844c

  (826) 0x458470 ADD	X17, X2, #8

  (826) 0x458474 LDR	X8, [X18, X2]

  (826) 0x458478 LDR	X14, [X23, X17]

  (826) 0x45847c ADD	X4, X8, X14

  (826) 0x458480 CMP	X8, X4

  (826) 0x458484 B.GE	458600

  (826) 0x458488 LDR	X24, [SP, #144]

  (826) 0x45848c UBFM	X2, X8, #61, #60

  (826) 0x458490 LDUR	X24, [X24, #504]

  (826) 0x458494 ADD	X14, X24, X4,LSL #3

  (826) 0x458498 ADD	X4, X24, X8,LSL #3

  (826) 0x45849c SUB	X8, X14, X4

  (826) 0x4584a0 SUB	X8, X8, #8

  (826) 0x4584a4 UBFM	X8, X8, #3, #63

  (826) 0x4584a8 ADD	X8, X8, #1

  (826) 0x4584ac ANDS	X8, X8, #4160

  (826) 0x4584b0 B.EQ	458550

  (826) 0x4584b4 CMP	X8, #1

  (826) 0x4584b8 B.EQ	45851c

  (826) 0x4584bc CMP	X8, #2

  (826) 0x4584c0 B.EQ	4584f0

  (826) 0x4584c4 LDR	X24, [X24, X2]

  (826) 0x4584c8 UBFM	X2, X24, #61, #60

  (826) 0x4584cc LDR	X8, [X20, X2]

  (826) 0x4584d0 CMP	X0, X8

  (826) 0x4584d4 B.EQ	4584ec

  (826) 0x4584d8 LDR	X24, [X23, X1]

  (826) 0x4584dc ADD	X6, X6, #1

  (826) 0x4584e0 ADD	X8, X24, #1

  (826) 0x4584e4 STR	X8, [X23, X1]

  (826) 0x4584e8 STR	X0, [X20, X2]

  (826) 0x4584ec ADD	X4, X4, #8

  (826) 0x4584f0 LDR	X2, [X4]

  (826) 0x4584f4 UBFM	X8, X2, #61, #60

  (826) 0x4584f8 LDR	X24, [X20, X8]

  (826) 0x4584fc CMP	X0, X24

  (826) 0x458500 B.EQ	458518

  (826) 0x458504 LDR	X2, [X23, X1]

  (826) 0x458508 ADD	X6, X6, #1

  (826) 0x45850c ADD	X24, X2, #1

  (826) 0x458510 STR	X24, [X23, X1]

  (826) 0x458514 STR	X0, [X20, X8]

  (826) 0x458518 ADD	X4, X4, #8

  (826) 0x45851c LDR	X8, [X4]

  (826) 0x458520 UBFM	X2, X8, #61, #60

  (826) 0x458524 LDR	X24, [X20, X2]

  (826) 0x458528 CMP	X0, X24

  (826) 0x45852c B.EQ	458544

  (826) 0x458530 LDR	X8, [X23, X1]

  (826) 0x458534 ADD	X6, X6, #1

  (826) 0x458538 ADD	X24, X8, #1

  (826) 0x45853c STR	X24, [X23, X1]

  (826) 0x458540 STR	X0, [X20, X2]

  (826) 0x458544 ADD	X4, X4, #8

  (826) 0x458548 CMP	X14, X4

  (826) 0x45854c B.EQ	458600

    (828) 0x458550 LDR	X2, [X4]

    (828) 0x458554 ADD	X8, X4, #8

    (828) 0x458558 UBFM	X2, X2, #61, #60

    (828) 0x45855c LDR	X24, [X20, X2]

    (828) 0x458560 CMP	X0, X24

    (828) 0x458564 B.EQ	45857c

    (828) 0x458568 LDR	X24, [X23, X1]

    (828) 0x45856c ADD	X6, X6, #1

    (828) 0x458570 ADD	X24, X24, #1

    (828) 0x458574 STR	X24, [X23, X1]

    (828) 0x458578 STR	X0, [X20, X2]

    (828) 0x45857c LDR	X4, [X4, #8]

    (828) 0x458580 UBFM	X2, X4, #61, #60

    (828) 0x458584 LDR	X24, [X20, X2]

    (828) 0x458588 CMP	X0, X24

    (828) 0x45858c B.EQ	4585a4

    (828) 0x458590 LDR	X4, [X23, X1]

    (828) 0x458594 ADD	X6, X6, #1

    (828) 0x458598 ADD	X24, X4, #1

    (828) 0x45859c STR	X24, [X23, X1]

    (828) 0x4585a0 STR	X0, [X20, X2]

    (828) 0x4585a4 LDR	X2, [X8, #8]

    (828) 0x4585a8 ADD	X4, X8, #24

    (828) 0x4585ac UBFM	X2, X2, #61, #60

    (828) 0x4585b0 LDR	X24, [X20, X2]

    (828) 0x4585b4 CMP	X0, X24

    (828) 0x4585b8 B.EQ	4585d0

    (828) 0x4585bc LDR	X24, [X23, X1]

    (828) 0x4585c0 ADD	X6, X6, #1

    (828) 0x4585c4 ADD	X24, X24, #1

    (828) 0x4585c8 STR	X24, [X23, X1]

    (828) 0x4585cc STR	X0, [X20, X2]

    (828) 0x4585d0 LDR	X8, [X8, #16]

    (828) 0x4585d4 UBFM	X2, X8, #61, #60

    (828) 0x4585d8 LDR	X24, [X20, X2]

    (828) 0x4585dc CMP	X0, X24

    (828) 0x4585e0 B.EQ	4585f8

    (828) 0x4585e4 LDR	X8, [X23, X1]

    (828) 0x4585e8 ADD	X6, X6, #1

    (828) 0x4585ec ADD	X24, X8, #1

    (828) 0x4585f0 STR	X24, [X23, X1]

    (828) 0x4585f4 STR	X0, [X20, X2]

    (828) 0x4585f8 CMP	X14, X4

    (828) 0x4585fc B.NE	458550

  (826) 0x458600 LDR	X14, [SP, #96]

  (826) 0x458604 LDR	X17, [X21, X17]

  (826) 0x458608 LDR	X4, [X16, X14]

  (826) 0x45860c ADD	X2, X4, X17

  (826) 0x458610 CMP	X4, X2

  (826) 0x458614 B.GE	45878c

  (826) 0x458618 LDUR	X17, [X30, #504]

  (826) 0x45861c UBFM	X24, X4, #61, #60

  (826) 0x458620 ADD	X8, X17, X2,LSL #3

  (826) 0x458624 ADD	X2, X17, X4,LSL #3

  (826) 0x458628 SUB	X14, X8, X2

  (826) 0x45862c SUB	X4, X14, #8

  (826) 0x458630 UBFM	X14, X4, #3, #63

  (826) 0x458634 ADD	X4, X14, #1

  (826) 0x458638 ANDS	X14, X4, #4160

  (826) 0x45863c B.EQ	4586dc

  (826) 0x458640 CMP	X14, #1

  (826) 0x458644 B.EQ	4586a8

  (826) 0x458648 CMP	X14, #2

  (826) 0x45864c B.EQ	45867c

  (826) 0x458650 LDR	X24, [X17, X24]

  (826) 0x458654 UBFM	X17, X24, #61, #60

  (826) 0x458658 LDR	X4, [X19, X17]

  (826) 0x45865c CMP	X0, X4

  (826) 0x458660 B.EQ	458678

  (826) 0x458664 LDR	X14, [X21, X1]

  (826) 0x458668 ADD	X5, X5, #1

  (826) 0x45866c ADD	X24, X14, #1

  (826) 0x458670 STR	X24, [X21, X1]

  (826) 0x458674 STR	X0, [X19, X17]

  (826) 0x458678 ADD	X2, X2, #8

  (826) 0x45867c LDR	X17, [X2]

  (826) 0x458680 UBFM	X4, X17, #61, #60

  (826) 0x458684 LDR	X14, [X19, X4]

  (826) 0x458688 CMP	X0, X14

  (826) 0x45868c B.EQ	4586a4

  (826) 0x458690 LDR	X24, [X21, X1]

  (826) 0x458694 ADD	X5, X5, #1

  (826) 0x458698 ADD	X17, X24, #1

  (826) 0x45869c STR	X17, [X21, X1]

  (826) 0x4586a0 STR	X0, [X19, X4]

  (826) 0x4586a4 ADD	X2, X2, #8

  (826) 0x4586a8 LDR	X4, [X2]

  (826) 0x4586ac UBFM	X24, X4, #61, #60

  (826) 0x4586b0 LDR	X14, [X19, X24]

  (826) 0x4586b4 CMP	X0, X14

  (826) 0x4586b8 B.EQ	4586d0

  (826) 0x4586bc LDR	X17, [X21, X1]

  (826) 0x4586c0 ADD	X5, X5, #1

  (826) 0x4586c4 ADD	X4, X17, #1

  (826) 0x4586c8 STR	X4, [X21, X1]

  (826) 0x4586cc STR	X0, [X19, X24]

  (826) 0x4586d0 ADD	X2, X2, #8

  (826) 0x4586d4 CMP	X2, X8

  (826) 0x4586d8 B.EQ	45878c

    (827) 0x4586dc LDR	X14, [X2]

    (827) 0x4586e0 ADD	X24, X2, #8

    (827) 0x4586e4 UBFM	X4, X14, #61, #60

    (827) 0x4586e8 LDR	X17, [X19, X4]

    (827) 0x4586ec CMP	X0, X17

    (827) 0x4586f0 B.EQ	458708

    (827) 0x4586f4 LDR	X14, [X21, X1]

    (827) 0x4586f8 ADD	X5, X5, #1

    (827) 0x4586fc ADD	X17, X14, #1

    (827) 0x458700 STR	X17, [X21, X1]

    (827) 0x458704 STR	X0, [X19, X4]

    (827) 0x458708 LDR	X2, [X2, #8]

    (827) 0x45870c UBFM	X14, X2, #61, #60

    (827) 0x458710 LDR	X4, [X19, X14]

    (827) 0x458714 CMP	X0, X4

    (827) 0x458718 B.EQ	458730

    (827) 0x45871c LDR	X17, [X21, X1]

    (827) 0x458720 ADD	X5, X5, #1

    (827) 0x458724 ADD	X2, X17, #1

    (827) 0x458728 STR	X2, [X21, X1]

    (827) 0x45872c STR	X0, [X19, X14]

    (827) 0x458730 LDR	X14, [X24, #8]

    (827) 0x458734 ADD	X2, X24, #24

    (827) 0x458738 UBFM	X4, X14, #61, #60

    (827) 0x45873c LDR	X17, [X19, X4]

    (827) 0x458740 CMP	X0, X17

    (827) 0x458744 B.EQ	45875c

    (827) 0x458748 LDR	X14, [X21, X1]

    (827) 0x45874c ADD	X5, X5, #1

    (827) 0x458750 ADD	X17, X14, #1

    (827) 0x458754 STR	X17, [X21, X1]

    (827) 0x458758 STR	X0, [X19, X4]

    (827) 0x45875c LDR	X24, [X24, #16]

    (827) 0x458760 UBFM	X4, X24, #61, #60

    (827) 0x458764 LDR	X14, [X19, X4]

    (827) 0x458768 CMP	X0, X14

    (827) 0x45876c B.EQ	458784

    (827) 0x458770 LDR	X17, [X21, X1]

    (827) 0x458774 ADD	X5, X5, #1

    (827) 0x458778 ADD	X24, X17, #1

    (827) 0x45877c STR	X24, [X21, X1]

    (827) 0x458780 STR	X0, [X19, X4]

    (827) 0x458784 CMP	X2, X8

    (827) 0x458788 B.NE	4586dc

  (826) 0x45878c LDR	X8, [X9]

  (826) 0x458790 ADD	X3, X3, #1

  (826) 0x458794 CMP	X3, X8

  (826) 0x458798 B.LT	458458

0x45879c HINT	#0

0x4587a0 LDR	X9, [SP, #128]

0x4587a4 ORR	X24, XZR, X28

0x4587a8 LDR	X3, [X11, X10]

0x4587ac ADD	X10, X11, X1

0x4587b0 LDR	X4, [X11, X1]

0x4587b4 CMP	X3, X4

0x4587b8 B.GE	4588e8

0x4587bc LDP	X14, X28, [SP, #112]

0x4587c0 ORR	X2, XZR, X10

0x4587c4 B	4587d4

  (824) 0x4587c8 ADD	X3, X3, #1

  (824) 0x4587cc CMP	X3, X4

  (824) 0x4587d0 B.GE	4588e8

  (824) 0x4587d4 LDR	X17, [X26, X3,LSL #3]

  (824) 0x4587d8 UBFM	X8, X17, #61, #60

  (824) 0x4587dc LDR	X10, [X24, X8]

  (824) 0x4587e0 CMP	X10, X7

  (824) 0x4587e4 B.NE	4587c8

  (824) 0x4587e8 ADD	X17, X14, X8

  (824) 0x4587ec LDR	X8, [X13, X8]

  (824) 0x4587f0 LDR	X10, [X17, #8]

  (824) 0x4587f4 ADD	X10, X8, X10

  (824) 0x4587f8 CMP	X8, X10

  (824) 0x4587fc B.GE	4587c8

  (824) 0x458800 LDR	X17, [X28, X22]

  (824) 0x458804 UBFM	X4, X8, #61, #60

  (824) 0x458808 STR	X4, [SP, #96]

  (824) 0x45880c ADD	X10, X17, X10,LSL #3

  (824) 0x458810 ADD	X4, X17, X8,LSL #3

  (824) 0x458814 SUB	X8, X10, X4

  (824) 0x458818 SUB	X8, X8, #8

  (824) 0x45881c UBFM	X8, X8, #3, #63

  (824) 0x458820 ADD	X8, X8, #1

  (824) 0x458824 ANDS	X8, X8, #4160

  (824) 0x458828 B.EQ	458b24

  (824) 0x45882c CMP	X8, #1

  (824) 0x458830 B.EQ	4588a0

  (824) 0x458834 CMP	X8, #2

  (824) 0x458838 B.EQ	458870

  (824) 0x45883c LDR	X8, [SP, #96]

  (824) 0x458840 LDR	X17, [X17, X8]

  (824) 0x458844 TBNZ	X17, #63, 458c44

  (824) 0x458848 UBFM	X8, X17, #61, #60

  (824) 0x45884c LDR	X17, [X19, X8]

  (824) 0x458850 CMP	X0, X17

  (824) 0x458854 B.EQ	45886c

  (824) 0x458858 LDR	X17, [X21, X1]

  (824) 0x45885c ADD	X5, X5, #1

  (824) 0x458860 ADD	X17, X17, #1

  (824) 0x458864 STR	X17, [X21, X1]

  (824) 0x458868 STR	X0, [X19, X8]

  (824) 0x45886c ADD	X4, X4, #8

  (824) 0x458870 LDR	X8, [X4]

  (824) 0x458874 TBNZ	X8, #63, 458c18

  (824) 0x458878 UBFM	X8, X8, #61, #60

  (824) 0x45887c LDR	X17, [X19, X8]

  (824) 0x458880 CMP	X0, X17

  (824) 0x458884 B.EQ	45889c

  (824) 0x458888 LDR	X17, [X21, X1]

  (824) 0x45888c ADD	X5, X5, #1

  (824) 0x458890 ADD	X17, X17, #1

  (824) 0x458894 STR	X17, [X21, X1]

  (824) 0x458898 STR	X0, [X19, X8]

  (824) 0x45889c ADD	X4, X4, #8

  (824) 0x4588a0 LDR	X8, [X4]

  (824) 0x4588a4 TBNZ	X8, #63, 458bec

  (824) 0x4588a8 UBFM	X8, X8, #61, #60

  (824) 0x4588ac LDR	X17, [X19, X8]

  (824) 0x4588b0 CMP	X0, X17

  (824) 0x4588b4 B.EQ	4588cc

  (824) 0x4588b8 LDR	X17, [X21, X1]

  (824) 0x4588bc ADD	X5, X5, #1

  (824) 0x4588c0 ADD	X17, X17, #1

  (824) 0x4588c4 STR	X17, [X21, X1]

  (824) 0x4588c8 STR	X0, [X19, X8]

  (824) 0x4588cc ADD	X4, X4, #8

  (824) 0x4588d0 CMP	X4, X10

  (824) 0x4588d4 B.NE	458b24

  (824) 0x4588d8 LDR	X4, [X2]

  (824) 0x4588dc ADD	X3, X3, #1

  (824) 0x4588e0 CMP	X3, X4

  (824) 0x4588e4 B.LT	4587d4

0x4588e8 ADD	X15, X15, #1

0x4588ec CMP	X9, X15

0x4588f0 B.GT	458410

    (825) 0x458a6c UBFM	X8, X8, #61, #60

    (825) 0x458a70 LDR	X17, [X19, X8]

    (825) 0x458a74 CMP	X0, X17

    (825) 0x458a78 B.EQ	458a90

    (825) 0x458a7c LDR	X17, [X21, X1]

    (825) 0x458a80 ADD	X5, X5, #1

    (825) 0x458a84 ADD	X17, X17, #1

    (825) 0x458a88 STR	X17, [X21, X1]

    (825) 0x458a8c STR	X0, [X19, X8]

    (825) 0x458a90 LDR	X8, [X4, #8]

    (825) 0x458a94 ADD	X4, X4, #8

    (825) 0x458a98 TBNZ	X8, #63, 458b60

    (825) 0x458a9c UBFM	X8, X8, #61, #60

    (825) 0x458aa0 LDR	X17, [X19, X8]

    (825) 0x458aa4 CMP	X0, X17

    (825) 0x458aa8 B.EQ	458ac0

    (825) 0x458aac LDR	X17, [X21, X1]

    (825) 0x458ab0 ADD	X5, X5, #1

    (825) 0x458ab4 ADD	X17, X17, #1

    (825) 0x458ab8 STR	X17, [X21, X1]

    (825) 0x458abc STR	X0, [X19, X8]

    (825) 0x458ac0 LDR	X8, [X4, #8]

    (825) 0x458ac4 TBNZ	X8, #63, 458b90

    (825) 0x458ac8 UBFM	X8, X8, #61, #60

    (825) 0x458acc LDR	X17, [X19, X8]

    (825) 0x458ad0 CMP	X0, X17

    (825) 0x458ad4 B.EQ	458aec

    (825) 0x458ad8 LDR	X17, [X21, X1]

    (825) 0x458adc ADD	X5, X5, #1

    (825) 0x458ae0 ADD	X17, X17, #1

    (825) 0x458ae4 STR	X17, [X21, X1]

    (825) 0x458ae8 STR	X0, [X19, X8]

    (825) 0x458aec LDR	X8, [X4, #16]

    (825) 0x458af0 TBNZ	X8, #63, 458bc0

    (825) 0x458af4 UBFM	X8, X8, #61, #60

    (825) 0x458af8 LDR	X17, [X19, X8]

    (825) 0x458afc CMP	X0, X17

    (825) 0x458b00 B.EQ	458b18

    (825) 0x458b04 LDR	X17, [X21, X1]

    (825) 0x458b08 ADD	X5, X5, #1

    (825) 0x458b0c ADD	X17, X17, #1

    (825) 0x458b10 STR	X17, [X21, X1]

    (825) 0x458b14 STR	X0, [X19, X8]

    (825) 0x458b18 ADD	X4, X4, #24

    (825) 0x458b1c CMP	X4, X10

    (825) 0x458b20 B.EQ	4588d8

    (825) 0x458b24 LDR	X8, [X4]

    (825) 0x458b28 TBZ	X8, #63, 458a6c

    (825) 0x458b2c ORN	X8, XZR, X8

    (825) 0x458b30 UBFM	X8, X8, #61, #60

    (825) 0x458b34 LDR	X17, [X20, X8]

    (825) 0x458b38 CMP	X0, X17

    (825) 0x458b3c B.EQ	458a90

    (825) 0x458b40 LDR	X17, [X23, X1]

    (825) 0x458b44 ADD	X6, X6, #1

    (825) 0x458b48 ADD	X4, X4, #8

    (825) 0x458b4c ADD	X17, X17, #1

    (825) 0x458b50 STR	X17, [X23, X1]

    (825) 0x458b54 STR	X0, [X20, X8]

    (825) 0x458b58 LDR	X8, [X4]

    (825) 0x458b5c TBZ	X8, #63, 458a9c

    (825) 0x458b60 ORN	X8, XZR, X8

    (825) 0x458b64 UBFM	X8, X8, #61, #60

    (825) 0x458b68 LDR	X17, [X20, X8]

    (825) 0x458b6c CMP	X0, X17

    (825) 0x458b70 B.EQ	458ac0

    (825) 0x458b74 LDR	X17, [X23, X1]

    (825) 0x458b78 ADD	X6, X6, #1

    (825) 0x458b7c ADD	X17, X17, #1

    (825) 0x458b80 STR	X17, [X23, X1]

    (825) 0x458b84 STR	X0, [X20, X8]

    (825) 0x458b88 LDR	X8, [X4, #8]

    (825) 0x458b8c TBZ	X8, #63, 458ac8

    (825) 0x458b90 ORN	X8, XZR, X8

    (825) 0x458b94 UBFM	X8, X8, #61, #60

    (825) 0x458b98 LDR	X17, [X20, X8]

    (825) 0x458b9c CMP	X0, X17

    (825) 0x458ba0 B.EQ	458aec

    (825) 0x458ba4 LDR	X17, [X23, X1]

    (825) 0x458ba8 ADD	X6, X6, #1

    (825) 0x458bac ADD	X17, X17, #1

    (825) 0x458bb0 STR	X17, [X23, X1]

    (825) 0x458bb4 STR	X0, [X20, X8]

    (825) 0x458bb8 LDR	X8, [X4, #16]

    (825) 0x458bbc TBZ	X8, #63, 458af4

    (825) 0x458bc0 ORN	X8, XZR, X8

    (825) 0x458bc4 UBFM	X8, X8, #61, #60

    (825) 0x458bc8 LDR	X17, [X20, X8]

    (825) 0x458bcc CMP	X0, X17

    (825) 0x458bd0 B.EQ	458b18

    (825) 0x458bd4 LDR	X17, [X23, X1]

    (825) 0x458bd8 ADD	X6, X6, #1

    (825) 0x458bdc ADD	X17, X17, #1

    (825) 0x458be0 STR	X17, [X23, X1]

    (825) 0x458be4 STR	X0, [X20, X8]

    (825) 0x458be8 B	458b18

  (824) 0x458bec ORN	X8, XZR, X8

  (824) 0x458bf0 UBFM	X8, X8, #61, #60

  (824) 0x458bf4 LDR	X17, [X20, X8]

  (824) 0x458bf8 CMP	X0, X17

  (824) 0x458bfc B.EQ	4588cc

  (824) 0x458c00 LDR	X17, [X23, X1]

  (824) 0x458c04 ADD	X6, X6, #1

  (824) 0x458c08 ADD	X17, X17, #1

  (824) 0x458c0c STR	X17, [X23, X1]

  (824) 0x458c10 STR	X0, [X20, X8]

  (824) 0x458c14 B	4588cc

  (824) 0x458c18 ORN	X8, XZR, X8

  (824) 0x458c1c UBFM	X8, X8, #61, #60

  (824) 0x458c20 LDR	X17, [X20, X8]

  (824) 0x458c24 CMP	X0, X17

  (824) 0x458c28 B.EQ	45889c

  (824) 0x458c2c LDR	X17, [X23, X1]

  (824) 0x458c30 ADD	X6, X6, #1

  (824) 0x458c34 ADD	X17, X17, #1

  (824) 0x458c38 STR	X17, [X23, X1]

  (824) 0x458c3c STR	X0, [X20, X8]

  (824) 0x458c40 B	45889c

  (824) 0x458c44 ORN	X8, XZR, X17

  (824) 0x458c48 UBFM	X8, X8, #61, #60

  (824) 0x458c4c LDR	X17, [X20, X8]

  (824) 0x458c50 CMP	X0, X17

  (824) 0x458c54 B.EQ	45886c

  (824) 0x458c58 LDR	X17, [X23, X1]

  (824) 0x458c5c ADD	X6, X6, #1

  (824) 0x458c60 ADD	X17, X17, #1

  (824) 0x458c64 STR	X17, [X23, X1]

  (824) 0x458c68 STR	X0, [X20, X8]

  (824) 0x458c6c B	45886c

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 939 - 999

--------------------------------------------------------------------------------

939:           for (i=thread_start; i < thread_stop; i++)

940:           {

941:              i1 = pass_array[i];

942:              P_diag_start[i1] = cnt_nz;

943:              P_offd_start[i1] = cnt_nz_offd;

944:              for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

945:              {

946:                 j1 = S_diag_j[j];

947:                 if (assigned[j1] == pass-1)

948:                 {

949:                    j_start = P_diag_start[j1];

950:                    j_end = j_start+P_diag_i[j1+1];

951:                    for (k=j_start; k < j_end; k++)

952:                    {

953:                       k1 = P_diag_pass[pass-1][k];

954:                       if (P_marker[k1] != i1)

955:                       {

956:                          cnt_nz++;

957:                          P_diag_i[i1+1]++;

958:                          P_marker[k1] = i1;

959:                       }

960:                    }

961:                    j_start = P_offd_start[j1];

962:                    j_end = j_start+P_offd_i[j1+1];

963:                    for (k=j_start; k < j_end; k++)

964:                    {

965:                       k1 = P_offd_pass[pass-1][k];

966:                       if (P_marker_offd[k1] != i1)

967:                       {

968:                          cnt_nz_offd++;

969:                          P_offd_i[i1+1]++;

970:                          P_marker_offd[k1] = i1;

[...]

976:              for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

977:              {

978:                 j1 = S_offd_j[j];

979:                 if (assigned_offd[j1] == pass-1)

980:                 {

981:                    j_start = Pext_start[j1];

982:                    j_end = j_start+Pext_i[j1+1];

983:                    for (k=j_start; k < j_end; k++)

984:                    {

985:                       k1 = Pext_pass[pass][k];

986:                       if (k1 < 0)

987:                       {

988:                          if (P_marker[-k1-1] != i1)

989:                          {

990:                             cnt_nz++;

991:                             P_diag_i[i1+1]++;

992:                             P_marker[-k1-1] = i1;

993:                          }

994:                       }

995:                       else if (P_marker_offd[k1] != i1)

996:                       {

997:                          cnt_nz_offd++;

998:                          P_offd_i[i1+1]++;

999:                          P_marker_offd[k1] = i1;

Coverage (%)	Name	Source Location	Module
►99.32+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	P12,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source	par_multi_interp.c:939-944,par_multi_interp.c:976-976
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.83
CQA cycles if no scalar integer	3.83
CQA cycles if FP arith vectorized	3.83
CQA cycles if fully vectorized	1.92
Front-end cycles	3.50
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	2.08
P3 cycles	2.08
P4 cycles	2.00
P5 cycles	2.00
P6 cycles	1.92
P7 cycles	1.92
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	3.83
P13 cycles	3.50
P14 cycles	3.67
P15 cycles	1.50
P16 cycles	1.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	29.00
Nb uops	28.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	25.04
Bytes prefetched	0.00
Bytes loaded	72.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	P12,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source	par_multi_interp.c:939-944,par_multi_interp.c:976-976
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.83
CQA cycles if no scalar integer	3.83
CQA cycles if FP arith vectorized	3.83
CQA cycles if fully vectorized	1.92
Front-end cycles	3.50
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	2.08
P3 cycles	2.08
P4 cycles	2.00
P5 cycles	2.00
P6 cycles	1.92
P7 cycles	1.92
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	3.83
P13 cycles	3.50
P14 cycles	3.67
P15 cycles	1.50
P16 cycles	1.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	29.00
Nb uops	28.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	25.04
Bytes prefetched	0.00
Bytes loaded	72.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source file and lines	par_multi_interp.c:939-999
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:939-970,976-999.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:939-944,976.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.83 to 1.92 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 72 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	29
loop length	116
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	2.08	2.08	2.00	2.00	1.92	1.92	0.00	0.00	0.00	0.00	3.83	3.50	3.67	1.50	1.50
cycles	2.50	2.50	2.08	2.08	2.00	2.00	1.92	1.92	0.00	0.00	0.00	0.00	3.83	3.50	3.67	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.50
Overall L1	3.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.83 cycles. At this rate:

19% of peak load performance is reached (18.78 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.26 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 458410

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR X14, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X14, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
UBFM X10, X0, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, X10, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X6, [X18, X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X4, X12, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X5, [X16, X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X3, [X12, X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X8, [X12, X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X3, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4587a8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x55c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X28, XZR, X24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X9, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X9, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 458458 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x20c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
LDR X9, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X24, XZR, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X3, [X11, X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X10, X11, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X4, [X11, X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X3, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4588e8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x69c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X14, X28, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ORR X2, XZR, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 4587d4 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x588>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X15, X15, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X9, X15	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.GT 458410 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source file and lines	par_multi_interp.c:939-999
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

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potential
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Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.83 to 1.92 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 72 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	29
loop length	116
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	2.08	2.08	2.00	2.00	1.92	1.92	0.00	0.00	0.00	0.00	3.83	3.50	3.67	1.50	1.50
cycles	2.50	2.50	2.08	2.08	2.00	2.00	1.92	1.92	0.00	0.00	0.00	0.00	3.83	3.50	3.67	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.50
Overall L1	3.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.83 cycles. At this rate:

19% of peak load performance is reached (18.78 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.26 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 458410

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR X14, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X14, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
UBFM X10, X0, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, X10, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X6, [X18, X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X4, X12, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X5, [X16, X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X3, [X12, X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X8, [X12, X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X3, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4587a8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x55c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X28, XZR, X24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X9, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X9, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 458458 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x20c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
LDR X9, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X24, XZR, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X3, [X11, X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X10, X11, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X4, [X11, X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X3, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4588e8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x69c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X14, X28, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ORR X2, XZR, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 4587d4 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x588>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X15, X15, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X9, X15	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.GT 458410 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code