OV - exec - Loop 818

	Loop Id: 818	Module: exec	Source: par_multi_interp.c:1075-1099	Coverage: 0.75%

0x458f18 ADD	X3, X3, #1

0x458f1c CMP	X3, X13

0x458f20 B.GE	459260

0x458f24 LDR	X24, [X27, X3,LSL #3]

0x458f28 UBFM	X1, X24, #61, #60

0x458f2c LDR	X16, [X25, X1]

0x458f30 CMP	X16, X7

0x458f34 B.NE	458f18

0x458f38 LDR	X21, [SP, #152]

0x458f3c ADD	X16, X1, #8

0x458f40 LDR	X13, [X23, X16]

0x458f44 LDR	X5, [X21, X1]

0x458f48 ADD	X13, X5, X13

0x458f4c CMP	X5, X13

0x458f50 B.GE	4590d8

0x458f54 LDR	X24, [SP, #160]

0x458f58 UBFM	X21, X5, #61, #60

0x458f5c STR	X21, [SP, #144]

0x458f60 LDUR	X24, [X24, #504]

0x458f64 ADD	X13, X24, X13,LSL #3

0x458f68 ADD	X5, X24, X5,LSL #3

0x458f6c SUB	X21, X13, X5

0x458f70 STR	X13, [SP, #96]

0x458f74 SUB	X21, X21, #8

0x458f78 UBFM	X21, X21, #3, #63

0x458f7c ADD	X21, X21, #1

0x458f80 ANDS	X21, X21, #4160

0x458f84 B.EQ	459020

0x458f88 CMP	X21, #1

0x458f8c B.EQ	458fec

0x458f90 CMP	X21, #2

0x458f94 B.EQ	458fc4

0x458f98 LDR	X13, [SP, #144]

0x458f9c LDR	X24, [X24, X13]

0x458fa0 UBFM	X21, X24, #61, #60

0x458fa4 LDR	X13, [X20, X21]

0x458fa8 CMP	X13, X0

0x458fac B.EQ	458fc0

0x458fb0 LDR	X13, [X10, X22]

0x458fb4 STR	X24, [X13, X4,LSL #3]

0x458fb8 ADD	X4, X4, #1

0x458fbc STR	X0, [X20, X21]

0x458fc0 ADD	X5, X5, #8

0x458fc4 LDR	X24, [X5]

0x458fc8 UBFM	X21, X24, #61, #60

0x458fcc LDR	X13, [X20, X21]

0x458fd0 CMP	X13, X0

0x458fd4 B.EQ	458fe8

0x458fd8 LDR	X13, [X10, X22]

0x458fdc STR	X24, [X13, X4,LSL #3]

0x458fe0 ADD	X4, X4, #1

0x458fe4 STR	X0, [X20, X21]

0x458fe8 ADD	X5, X5, #8

0x458fec LDR	X24, [X5]

0x458ff0 UBFM	X21, X24, #61, #60

0x458ff4 LDR	X13, [X20, X21]

0x458ff8 CMP	X13, X0

0x458ffc B.EQ	459010

0x459000 LDR	X13, [X10, X22]

0x459004 STR	X24, [X13, X4,LSL #3]

0x459008 ADD	X4, X4, #1

0x45900c STR	X0, [X20, X21]

0x459010 LDR	X13, [SP, #96]

0x459014 ADD	X5, X5, #8

0x459018 CMP	X13, X5

0x45901c B.EQ	4590d8

0x459020 ORR	X24, XZR, X2

0x459024 STR	X1, [SP, #96]

0x459028 STR	X19, [SP, #144]

  (820) 0x45902c LDR	X21, [X5]

  (820) 0x459030 ADD	X2, X5, #8

  (820) 0x459034 UBFM	X19, X21, #61, #60

  (820) 0x459038 LDR	X1, [X20, X19]

  (820) 0x45903c CMP	X1, X0

  (820) 0x459040 B.EQ	459054

  (820) 0x459044 LDR	X1, [X10, X22]

  (820) 0x459048 STR	X21, [X1, X4,LSL #3]

  (820) 0x45904c ADD	X4, X4, #1

  (820) 0x459050 STR	X0, [X20, X19]

  (820) 0x459054 LDR	X19, [X5, #8]

  (820) 0x459058 UBFM	X5, X19, #61, #60

  (820) 0x45905c LDR	X21, [X20, X5]

  (820) 0x459060 CMP	X21, X0

  (820) 0x459064 B.EQ	459078

  (820) 0x459068 LDR	X1, [X10, X22]

  (820) 0x45906c STR	X19, [X1, X4,LSL #3]

  (820) 0x459070 ADD	X4, X4, #1

  (820) 0x459074 STR	X0, [X20, X5]

  (820) 0x459078 LDR	X21, [X2, #8]

  (820) 0x45907c ADD	X5, X2, #24

  (820) 0x459080 UBFM	X19, X21, #61, #60

  (820) 0x459084 LDR	X1, [X20, X19]

  (820) 0x459088 CMP	X1, X0

  (820) 0x45908c B.EQ	4590a0

  (820) 0x459090 LDR	X1, [X10, X22]

  (820) 0x459094 STR	X21, [X1, X4,LSL #3]

  (820) 0x459098 ADD	X4, X4, #1

  (820) 0x45909c STR	X0, [X20, X19]

  (820) 0x4590a0 LDR	X19, [X2, #16]

  (820) 0x4590a4 UBFM	X2, X19, #61, #60

  (820) 0x4590a8 LDR	X21, [X20, X2]

  (820) 0x4590ac CMP	X21, X0

  (820) 0x4590b0 B.EQ	4590c4

  (820) 0x4590b4 LDR	X1, [X10, X22]

  (820) 0x4590b8 STR	X19, [X1, X4,LSL #3]

  (820) 0x4590bc ADD	X4, X4, #1

  (820) 0x4590c0 STR	X0, [X20, X2]

  (820) 0x4590c4 CMP	X13, X5

  (820) 0x4590c8 B.NE	45902c

0x4590cc LDR	X1, [SP, #96]

0x4590d0 ORR	X2, XZR, X24

0x4590d4 LDR	X19, [SP, #144]

0x4590d8 LDR	X13, [SP, #136]

0x4590dc LDR	X16, [X18, X16]

0x4590e0 LDR	X24, [X13, X1]

0x4590e4 ADD	X5, X24, X16

0x4590e8 CMP	X24, X5

0x4590ec B.GE	45924c

0x4590f0 LDR	X1, [SP, #168]

0x4590f4 UBFM	X21, X24, #61, #60

0x4590f8 LDUR	X16, [X1, #504]

0x4590fc ADD	X1, X16, X24,LSL #3

0x459100 ADD	X5, X16, X5,LSL #3

0x459104 SUB	X13, X5, X1

0x459108 SUB	X24, X13, #8

0x45910c UBFM	X13, X24, #3, #63

0x459110 ADD	X24, X13, #1

0x459114 ANDS	X13, X24, #4160

0x459118 B.EQ	4591ac

0x45911c CMP	X13, #1

0x459120 B.EQ	45917c

0x459124 CMP	X13, #2

0x459128 B.EQ	459154

0x45912c LDR	X16, [X16, X21]

0x459130 UBFM	X24, X16, #61, #60

0x459134 LDR	X21, [X19, X24]

0x459138 CMP	X21, X0

0x45913c B.EQ	459150

0x459140 LDR	X13, [X8, X22]

0x459144 STR	X16, [X13, X2,LSL #3]

0x459148 ADD	X2, X2, #1

0x45914c STR	X0, [X19, X24]

0x459150 ADD	X1, X1, #8

0x459154 LDR	X16, [X1]

0x459158 UBFM	X24, X16, #61, #60

0x45915c LDR	X21, [X19, X24]

0x459160 CMP	X21, X0

0x459164 B.EQ	459178

0x459168 LDR	X13, [X8, X22]

0x45916c STR	X16, [X13, X2,LSL #3]

0x459170 ADD	X2, X2, #1

0x459174 STR	X0, [X19, X24]

0x459178 ADD	X1, X1, #8

0x45917c LDR	X16, [X1]

0x459180 UBFM	X24, X16, #61, #60

0x459184 LDR	X21, [X19, X24]

0x459188 CMP	X21, X0

0x45918c B.EQ	4591a0

0x459190 LDR	X13, [X8, X22]

0x459194 STR	X16, [X13, X2,LSL #3]

0x459198 ADD	X2, X2, #1

0x45919c STR	X0, [X19, X24]

0x4591a0 ADD	X1, X1, #8

0x4591a4 CMP	X1, X5

0x4591a8 B.EQ	45924c

  (819) 0x4591ac LDR	X21, [X1]

  (819) 0x4591b0 ADD	X13, X1, #8

  (819) 0x4591b4 UBFM	X16, X21, #61, #60

  (819) 0x4591b8 LDR	X24, [X19, X16]

  (819) 0x4591bc CMP	X24, X0

  (819) 0x4591c0 B.EQ	4591d4

  (819) 0x4591c4 LDR	X24, [X8, X22]

  (819) 0x4591c8 STR	X21, [X24, X2,LSL #3]

  (819) 0x4591cc ADD	X2, X2, #1

  (819) 0x4591d0 STR	X0, [X19, X16]

  (819) 0x4591d4 LDR	X16, [X1, #8]

  (819) 0x4591d8 UBFM	X1, X16, #61, #60

  (819) 0x4591dc LDR	X21, [X19, X1]

  (819) 0x4591e0 CMP	X21, X0

  (819) 0x4591e4 B.EQ	4591f8

  (819) 0x4591e8 LDR	X24, [X8, X22]

  (819) 0x4591ec STR	X16, [X24, X2,LSL #3]

  (819) 0x4591f0 ADD	X2, X2, #1

  (819) 0x4591f4 STR	X0, [X19, X1]

  (819) 0x4591f8 LDR	X21, [X13, #8]

  (819) 0x4591fc ADD	X1, X13, #24

  (819) 0x459200 UBFM	X16, X21, #61, #60

  (819) 0x459204 LDR	X24, [X19, X16]

  (819) 0x459208 CMP	X24, X0

  (819) 0x45920c B.EQ	459220

  (819) 0x459210 LDR	X24, [X8, X22]

  (819) 0x459214 STR	X21, [X24, X2,LSL #3]

  (819) 0x459218 ADD	X2, X2, #1

  (819) 0x45921c STR	X0, [X19, X16]

  (819) 0x459220 LDR	X16, [X13, #16]

  (819) 0x459224 UBFM	X13, X16, #61, #60

  (819) 0x459228 LDR	X21, [X19, X13]

  (819) 0x45922c CMP	X21, X0

  (819) 0x459230 B.EQ	459244

  (819) 0x459234 LDR	X24, [X8, X22]

  (819) 0x459238 STR	X16, [X24, X2,LSL #3]

  (819) 0x45923c ADD	X2, X2, #1

  (819) 0x459240 STR	X0, [X19, X13]

  (819) 0x459244 CMP	X1, X5

  (819) 0x459248 B.NE	4591ac

0x45924c LDR	X13, [X6]

0x459250 ADD	X3, X3, #1

0x459254 CMP	X3, X13

0x459258 B.LT	458f24

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1075 - 1099

--------------------------------------------------------------------------------

1075:              for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

1076:              {

1077:                 j1 = S_diag_j[j];

1078:                 if (assigned[j1] == pass-1)

1079:                 {

1080:                    j_start = P_diag_start[j1];

1081:                    j_end = j_start+P_diag_i[j1+1];

1082:                    for (k=j_start; k < j_end; k++)

1083:                    {

1084:                       k1 = P_diag_pass[pass-1][k];

1085:                       if (P_marker[k1] != -i1-1)

1086:                       {

1087:                           P_diag_pass[pass][cnt_nz++] = k1;

1088:                           P_marker[k1] = -i1-1;

1089:                       }

1090:                    }

1091:                    j_start = P_offd_start[j1];

1092:                    j_end = j_start+P_offd_i[j1+1];

1093:                    for (k=j_start; k < j_end; k++)

1094:                    {

1095:                       k1 = P_offd_pass[pass-1][k];

1096:                       if (P_marker_offd[k1] != -i1-1)

1097:                       {

1098:                          P_offd_pass[pass][cnt_nz_offd++] = k1;

1099:                          P_marker_offd[k1] = -i1-1;

Coverage (%)	Name	Source Location	Module
►99.05+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	P12, P13, P14,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source	par_multi_interp.c:1075-1075,par_multi_interp.c:1078-1088,par_multi_interp.c:1091-1099
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	17.00
CQA cycles if no scalar integer	17.00
CQA cycles if FP arith vectorized	17.00
CQA cycles if fully vectorized	8.50
Front-end cycles	16.13
P0 cycles	9.50
P1 cycles	9.50
P2 cycles	9.92
P3 cycles	9.92
P4 cycles	9.83
P5 cycles	9.83
P6 cycles	9.75
P7 cycles	9.75
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	17.00
P13 cycles	17.00
P14 cycles	17.00
P15 cycles	8.00
P16 cycles	8.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	129.00
Nb uops	129.00
Nb loads	NA
Nb stores	16.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	280.00
Bytes stored	128.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	P12, P13, P14,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source	par_multi_interp.c:1075-1075,par_multi_interp.c:1078-1088,par_multi_interp.c:1091-1099
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	17.00
CQA cycles if no scalar integer	17.00
CQA cycles if FP arith vectorized	17.00
CQA cycles if fully vectorized	8.50
Front-end cycles	16.13
P0 cycles	9.50
P1 cycles	9.50
P2 cycles	9.92
P3 cycles	9.92
P4 cycles	9.83
P5 cycles	9.83
P6 cycles	9.75
P7 cycles	9.75
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	17.00
P13 cycles	17.00
P14 cycles	17.00
P15 cycles	8.00
P16 cycles	8.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	129.00
Nb uops	129.00
Nb loads	NA
Nb stores	16.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	280.00
Bytes stored	128.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source file and lines	par_multi_interp.c:1075-1099
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1075-1099.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1075,1078-1088,1091-1099.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 65026 paths individually, rerun with max-paths=65026
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 65026 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 17.00 to 8.50 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 280 bytes. The binary loop is storing 128 bytes.

General properties

nb instructions	129
loop length	516
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

16.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	9.50	9.50	9.92	9.92	9.83	9.83	9.75	9.75	0.00	0.00	0.00	0.00	17.00	17.00	17.00	8.00	8.00
cycles	9.50	9.50	9.92	9.92	9.83	9.83	9.75	9.75	0.00	0.00	0.00	0.00	17.00	17.00	17.00	8.00	8.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.13
Overall L1	17.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.00 cycles. At this rate:

17% of peak load performance is reached (16.47 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
15% of peak store performance is reached (7.53 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 458f24

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
ADD X3, X3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CMP X3, X13	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 459260 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1014>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X24, [X27, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X1, X24, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X16, [X25, X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X16, X7	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 458f18 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xccc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X21, [SP, #152]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X16, X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X13, [X23, X16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X21, X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X13, X5, X13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CMP X5, X13	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4590d8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xe8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X24, [SP, #160]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X21, X5, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR X21, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X24, [X24, #504]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X13, X24, X13,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X5, X24, X5,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SUB X21, X13, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR X13, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X21, X21, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
UBFM X21, X21, #3, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X21, X21, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ANDS X21, X21, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.EQ 459020 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xdd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X21, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 458fec <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xda0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X21, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 458fc4 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xd78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #144]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X24, [X24, X13]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X21, X24, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X13, [X20, X21]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X13, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 458fc0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xd74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X10, X22]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X24, [X13, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR X0, [X20, X21]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X5, X5, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X24, [X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X21, X24, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X13, [X20, X21]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X13, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 458fe8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xd9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X10, X22]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X24, [X13, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR X0, [X20, X21]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X5, X5, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X24, [X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X21, X24, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X13, [X20, X21]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X13, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 459010 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xdc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X10, X22]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X24, [X13, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR X0, [X20, X21]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X13, [SP, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X5, X5, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CMP X13, X5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4590d8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xe8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR X1, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X1, [SP, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X2, XZR, X24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [SP, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X18, X16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X24, [X13, X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X5, X24, X16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CMP X24, X5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 45924c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1000>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #168]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X21, X24, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDUR X16, [X1, #504]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, X16, X24,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X5, X16, X5,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SUB X13, X5, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SUB X24, X13, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
UBFM X13, X24, #3, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X24, X13, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ANDS X13, X24, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.EQ 4591ac <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xf60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45917c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xf30>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 459154 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xf08>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [X16, X21]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X24, X16, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X21, [X19, X24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X21, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 459150 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xf04>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X8, X22]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X16, [X13, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR X0, [X19, X24]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X1, X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X16, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X24, X16, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X21, [X19, X24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X21, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 459178 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xf2c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X8, X22]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X16, [X13, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR X0, [X19, X24]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X1, X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X16, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X24, X16, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X21, [X19, X24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X21, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4591a0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xf54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X8, X22]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X16, [X13, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR X0, [X19, X24]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X1, X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CMP X1, X5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45924c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1000>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X6]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X3, X3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CMP X3, X13	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.LT 458f24 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xcd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source file and lines	par_multi_interp.c:1075-1099
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 65026 paths individually, rerun with max-paths=65026
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 280 bytes. The binary loop is storing 128 bytes.

General properties

nb instructions	129
loop length	516
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

16.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	9.50	9.50	9.92	9.92	9.83	9.83	9.75	9.75	0.00	0.00	0.00	0.00	17.00	17.00	17.00	8.00	8.00
cycles	9.50	9.50	9.92	9.92	9.83	9.83	9.75	9.75	0.00	0.00	0.00	0.00	17.00	17.00	17.00	8.00	8.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.13
Overall L1	17.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.00 cycles. At this rate:

17% of peak load performance is reached (16.47 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
15% of peak store performance is reached (7.53 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 458f24

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
ADD X3, X3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CMP X3, X13	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 459260 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1014>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X24, [X27, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X1, X24, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X16, [X25, X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X16, X7	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 458f18 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xccc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X21, [SP, #152]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X16, X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X13, [X23, X16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X21, X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X13, X5, X13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CMP X5, X13	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4590d8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xe8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X24, [SP, #160]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X21, X5, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR X21, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X24, [X24, #504]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X13, X24, X13,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X5, X24, X5,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SUB X21, X13, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR X13, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X21, X21, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
UBFM X21, X21, #3, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X21, X21, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ANDS X21, X21, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.EQ 459020 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xdd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X21, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 458fec <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xda0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X21, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 458fc4 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xd78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #144]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X24, [X24, X13]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X21, X24, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X13, [X20, X21]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X13, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 458fc0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xd74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X10, X22]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X24, [X13, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR X0, [X20, X21]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X5, X5, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X24, [X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X21, X24, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X13, [X20, X21]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X13, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 458fe8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xd9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X10, X22]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X24, [X13, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR X0, [X20, X21]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X5, X5, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X24, [X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X21, X24, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X13, [X20, X21]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X13, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 459010 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xdc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X10, X22]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X24, [X13, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR X0, [X20, X21]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X13, [SP, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X5, X5, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CMP X13, X5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4590d8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xe8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR X1, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X1, [SP, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X2, XZR, X24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [SP, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X18, X16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X24, [X13, X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X5, X24, X16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CMP X24, X5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 45924c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1000>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #168]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X21, X24, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDUR X16, [X1, #504]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, X16, X24,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X5, X16, X5,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SUB X13, X5, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SUB X24, X13, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
UBFM X13, X24, #3, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X24, X13, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ANDS X13, X24, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.EQ 4591ac <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xf60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45917c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xf30>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 459154 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xf08>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [X16, X21]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X24, X16, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X21, [X19, X24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X21, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 459150 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xf04>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X8, X22]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X16, [X13, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR X0, [X19, X24]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X1, X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X16, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X24, X16, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X21, [X19, X24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X21, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 459178 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xf2c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X8, X22]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X16, [X13, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR X0, [X19, X24]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X1, X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X16, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X24, X16, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X21, [X19, X24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X21, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4591a0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xf54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X8, X22]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X16, [X13, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR X0, [X19, X24]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X1, X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CMP X1, X5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45924c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1000>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X6]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X3, X3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CMP X3, X13	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.LT 458f24 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xcd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code