OV - exec - Loop 815

	Loop Id: 815	Module: exec	Source: par_multi_interp.c:1072-1125	Coverage: 0.08%

0x458ee0 LDR	X21, [SP, #104]

0x458ee4 LDR	X6, [X21, X9,LSL #3]

0x458ee8 UBFM	X15, X6, #61, #60

0x458eec ORN	X0, XZR, X6

0x458ef0 ADD	X14, X15, #8

0x458ef4 LDR	X3, [X12, X15]

0x458ef8 ADD	X5, X12, X14

0x458efc LDR	X13, [X12, X14]

0x458f00 CMP	X3, X13

0x458f04 B.GE	459268

0x458f08 ORR	X28, XZR, X24

0x458f0c STR	X6, [SP, #128]

0x458f10 ORR	X6, XZR, X5

0x458f14 B	458f24

  (818) 0x458f18 ADD	X3, X3, #1

  (818) 0x458f1c CMP	X3, X13

  (818) 0x458f20 B.GE	459260

  (818) 0x458f24 LDR	X24, [X27, X3,LSL #3]

  (818) 0x458f28 UBFM	X1, X24, #61, #60

  (818) 0x458f2c LDR	X16, [X25, X1]

  (818) 0x458f30 CMP	X16, X7

  (818) 0x458f34 B.NE	458f18

  (818) 0x458f38 LDR	X21, [SP, #152]

  (818) 0x458f3c ADD	X16, X1, #8

  (818) 0x458f40 LDR	X13, [X23, X16]

  (818) 0x458f44 LDR	X5, [X21, X1]

  (818) 0x458f48 ADD	X13, X5, X13

  (818) 0x458f4c CMP	X5, X13

  (818) 0x458f50 B.GE	4590d8

  (818) 0x458f54 LDR	X24, [SP, #160]

  (818) 0x458f58 UBFM	X21, X5, #61, #60

  (818) 0x458f5c STR	X21, [SP, #144]

  (818) 0x458f60 LDUR	X24, [X24, #504]

  (818) 0x458f64 ADD	X13, X24, X13,LSL #3

  (818) 0x458f68 ADD	X5, X24, X5,LSL #3

  (818) 0x458f6c SUB	X21, X13, X5

  (818) 0x458f70 STR	X13, [SP, #96]

  (818) 0x458f74 SUB	X21, X21, #8

  (818) 0x458f78 UBFM	X21, X21, #3, #63

  (818) 0x458f7c ADD	X21, X21, #1

  (818) 0x458f80 ANDS	X21, X21, #4160

  (818) 0x458f84 B.EQ	459020

  (818) 0x458f88 CMP	X21, #1

  (818) 0x458f8c B.EQ	458fec

  (818) 0x458f90 CMP	X21, #2

  (818) 0x458f94 B.EQ	458fc4

  (818) 0x458f98 LDR	X13, [SP, #144]

  (818) 0x458f9c LDR	X24, [X24, X13]

  (818) 0x458fa0 UBFM	X21, X24, #61, #60

  (818) 0x458fa4 LDR	X13, [X20, X21]

  (818) 0x458fa8 CMP	X13, X0

  (818) 0x458fac B.EQ	458fc0

  (818) 0x458fb0 LDR	X13, [X10, X22]

  (818) 0x458fb4 STR	X24, [X13, X4,LSL #3]

  (818) 0x458fb8 ADD	X4, X4, #1

  (818) 0x458fbc STR	X0, [X20, X21]

  (818) 0x458fc0 ADD	X5, X5, #8

  (818) 0x458fc4 LDR	X24, [X5]

  (818) 0x458fc8 UBFM	X21, X24, #61, #60

  (818) 0x458fcc LDR	X13, [X20, X21]

  (818) 0x458fd0 CMP	X13, X0

  (818) 0x458fd4 B.EQ	458fe8

  (818) 0x458fd8 LDR	X13, [X10, X22]

  (818) 0x458fdc STR	X24, [X13, X4,LSL #3]

  (818) 0x458fe0 ADD	X4, X4, #1

  (818) 0x458fe4 STR	X0, [X20, X21]

  (818) 0x458fe8 ADD	X5, X5, #8

  (818) 0x458fec LDR	X24, [X5]

  (818) 0x458ff0 UBFM	X21, X24, #61, #60

  (818) 0x458ff4 LDR	X13, [X20, X21]

  (818) 0x458ff8 CMP	X13, X0

  (818) 0x458ffc B.EQ	459010

  (818) 0x459000 LDR	X13, [X10, X22]

  (818) 0x459004 STR	X24, [X13, X4,LSL #3]

  (818) 0x459008 ADD	X4, X4, #1

  (818) 0x45900c STR	X0, [X20, X21]

  (818) 0x459010 LDR	X13, [SP, #96]

  (818) 0x459014 ADD	X5, X5, #8

  (818) 0x459018 CMP	X13, X5

  (818) 0x45901c B.EQ	4590d8

  (818) 0x459020 ORR	X24, XZR, X2

  (818) 0x459024 STR	X1, [SP, #96]

  (818) 0x459028 STR	X19, [SP, #144]

    (820) 0x45902c LDR	X21, [X5]

    (820) 0x459030 ADD	X2, X5, #8

    (820) 0x459034 UBFM	X19, X21, #61, #60

    (820) 0x459038 LDR	X1, [X20, X19]

    (820) 0x45903c CMP	X1, X0

    (820) 0x459040 B.EQ	459054

    (820) 0x459044 LDR	X1, [X10, X22]

    (820) 0x459048 STR	X21, [X1, X4,LSL #3]

    (820) 0x45904c ADD	X4, X4, #1

    (820) 0x459050 STR	X0, [X20, X19]

    (820) 0x459054 LDR	X19, [X5, #8]

    (820) 0x459058 UBFM	X5, X19, #61, #60

    (820) 0x45905c LDR	X21, [X20, X5]

    (820) 0x459060 CMP	X21, X0

    (820) 0x459064 B.EQ	459078

    (820) 0x459068 LDR	X1, [X10, X22]

    (820) 0x45906c STR	X19, [X1, X4,LSL #3]

    (820) 0x459070 ADD	X4, X4, #1

    (820) 0x459074 STR	X0, [X20, X5]

    (820) 0x459078 LDR	X21, [X2, #8]

    (820) 0x45907c ADD	X5, X2, #24

    (820) 0x459080 UBFM	X19, X21, #61, #60

    (820) 0x459084 LDR	X1, [X20, X19]

    (820) 0x459088 CMP	X1, X0

    (820) 0x45908c B.EQ	4590a0

    (820) 0x459090 LDR	X1, [X10, X22]

    (820) 0x459094 STR	X21, [X1, X4,LSL #3]

    (820) 0x459098 ADD	X4, X4, #1

    (820) 0x45909c STR	X0, [X20, X19]

    (820) 0x4590a0 LDR	X19, [X2, #16]

    (820) 0x4590a4 UBFM	X2, X19, #61, #60

    (820) 0x4590a8 LDR	X21, [X20, X2]

    (820) 0x4590ac CMP	X21, X0

    (820) 0x4590b0 B.EQ	4590c4

    (820) 0x4590b4 LDR	X1, [X10, X22]

    (820) 0x4590b8 STR	X19, [X1, X4,LSL #3]

    (820) 0x4590bc ADD	X4, X4, #1

    (820) 0x4590c0 STR	X0, [X20, X2]

    (820) 0x4590c4 CMP	X13, X5

    (820) 0x4590c8 B.NE	45902c

  (818) 0x4590cc LDR	X1, [SP, #96]

  (818) 0x4590d0 ORR	X2, XZR, X24

  (818) 0x4590d4 LDR	X19, [SP, #144]

  (818) 0x4590d8 LDR	X13, [SP, #136]

  (818) 0x4590dc LDR	X16, [X18, X16]

  (818) 0x4590e0 LDR	X24, [X13, X1]

  (818) 0x4590e4 ADD	X5, X24, X16

  (818) 0x4590e8 CMP	X24, X5

  (818) 0x4590ec B.GE	45924c

  (818) 0x4590f0 LDR	X1, [SP, #168]

  (818) 0x4590f4 UBFM	X21, X24, #61, #60

  (818) 0x4590f8 LDUR	X16, [X1, #504]

  (818) 0x4590fc ADD	X1, X16, X24,LSL #3

  (818) 0x459100 ADD	X5, X16, X5,LSL #3

  (818) 0x459104 SUB	X13, X5, X1

  (818) 0x459108 SUB	X24, X13, #8

  (818) 0x45910c UBFM	X13, X24, #3, #63

  (818) 0x459110 ADD	X24, X13, #1

  (818) 0x459114 ANDS	X13, X24, #4160

  (818) 0x459118 B.EQ	4591ac

  (818) 0x45911c CMP	X13, #1

  (818) 0x459120 B.EQ	45917c

  (818) 0x459124 CMP	X13, #2

  (818) 0x459128 B.EQ	459154

  (818) 0x45912c LDR	X16, [X16, X21]

  (818) 0x459130 UBFM	X24, X16, #61, #60

  (818) 0x459134 LDR	X21, [X19, X24]

  (818) 0x459138 CMP	X21, X0

  (818) 0x45913c B.EQ	459150

  (818) 0x459140 LDR	X13, [X8, X22]

  (818) 0x459144 STR	X16, [X13, X2,LSL #3]

  (818) 0x459148 ADD	X2, X2, #1

  (818) 0x45914c STR	X0, [X19, X24]

  (818) 0x459150 ADD	X1, X1, #8

  (818) 0x459154 LDR	X16, [X1]

  (818) 0x459158 UBFM	X24, X16, #61, #60

  (818) 0x45915c LDR	X21, [X19, X24]

  (818) 0x459160 CMP	X21, X0

  (818) 0x459164 B.EQ	459178

  (818) 0x459168 LDR	X13, [X8, X22]

  (818) 0x45916c STR	X16, [X13, X2,LSL #3]

  (818) 0x459170 ADD	X2, X2, #1

  (818) 0x459174 STR	X0, [X19, X24]

  (818) 0x459178 ADD	X1, X1, #8

  (818) 0x45917c LDR	X16, [X1]

  (818) 0x459180 UBFM	X24, X16, #61, #60

  (818) 0x459184 LDR	X21, [X19, X24]

  (818) 0x459188 CMP	X21, X0

  (818) 0x45918c B.EQ	4591a0

  (818) 0x459190 LDR	X13, [X8, X22]

  (818) 0x459194 STR	X16, [X13, X2,LSL #3]

  (818) 0x459198 ADD	X2, X2, #1

  (818) 0x45919c STR	X0, [X19, X24]

  (818) 0x4591a0 ADD	X1, X1, #8

  (818) 0x4591a4 CMP	X1, X5

  (818) 0x4591a8 B.EQ	45924c

    (819) 0x4591ac LDR	X21, [X1]

    (819) 0x4591b0 ADD	X13, X1, #8

    (819) 0x4591b4 UBFM	X16, X21, #61, #60

    (819) 0x4591b8 LDR	X24, [X19, X16]

    (819) 0x4591bc CMP	X24, X0

    (819) 0x4591c0 B.EQ	4591d4

    (819) 0x4591c4 LDR	X24, [X8, X22]

    (819) 0x4591c8 STR	X21, [X24, X2,LSL #3]

    (819) 0x4591cc ADD	X2, X2, #1

    (819) 0x4591d0 STR	X0, [X19, X16]

    (819) 0x4591d4 LDR	X16, [X1, #8]

    (819) 0x4591d8 UBFM	X1, X16, #61, #60

    (819) 0x4591dc LDR	X21, [X19, X1]

    (819) 0x4591e0 CMP	X21, X0

    (819) 0x4591e4 B.EQ	4591f8

    (819) 0x4591e8 LDR	X24, [X8, X22]

    (819) 0x4591ec STR	X16, [X24, X2,LSL #3]

    (819) 0x4591f0 ADD	X2, X2, #1

    (819) 0x4591f4 STR	X0, [X19, X1]

    (819) 0x4591f8 LDR	X21, [X13, #8]

    (819) 0x4591fc ADD	X1, X13, #24

    (819) 0x459200 UBFM	X16, X21, #61, #60

    (819) 0x459204 LDR	X24, [X19, X16]

    (819) 0x459208 CMP	X24, X0

    (819) 0x45920c B.EQ	459220

    (819) 0x459210 LDR	X24, [X8, X22]

    (819) 0x459214 STR	X21, [X24, X2,LSL #3]

    (819) 0x459218 ADD	X2, X2, #1

    (819) 0x45921c STR	X0, [X19, X16]

    (819) 0x459220 LDR	X16, [X13, #16]

    (819) 0x459224 UBFM	X13, X16, #61, #60

    (819) 0x459228 LDR	X21, [X19, X13]

    (819) 0x45922c CMP	X21, X0

    (819) 0x459230 B.EQ	459244

    (819) 0x459234 LDR	X24, [X8, X22]

    (819) 0x459238 STR	X16, [X24, X2,LSL #3]

    (819) 0x45923c ADD	X2, X2, #1

    (819) 0x459240 STR	X0, [X19, X13]

    (819) 0x459244 CMP	X1, X5

    (819) 0x459248 B.NE	4591ac

  (818) 0x45924c LDR	X13, [X6]

  (818) 0x459250 ADD	X3, X3, #1

  (818) 0x459254 CMP	X3, X13

  (818) 0x459258 B.LT	458f24

0x45925c HINT	#0

0x459260 LDR	X6, [SP, #128]

0x459264 ORR	X24, XZR, X28

0x459268 ORN	X6, XZR, X6

0x45926c LDR	X1, [X11, X15]

0x459270 ADD	X15, X11, X14

0x459274 LDR	X3, [X11, X14]

0x459278 CMP	X3, X1

0x45927c B.LE	4593a0

0x459280 LDP	X21, X28, [SP, #112]

0x459284 B	459294

  (816) 0x459288 ADD	X1, X1, #1

  (816) 0x45928c CMP	X1, X3

  (816) 0x459290 B.GE	4593a0

  (816) 0x459294 LDR	X0, [X26, X1,LSL #3]

  (816) 0x459298 UBFM	X14, X0, #61, #60

  (816) 0x45929c LDR	X5, [X24, X14]

  (816) 0x4592a0 CMP	X5, X7

  (816) 0x4592a4 B.NE	459288

  (816) 0x4592a8 ADD	X16, X21, X14

  (816) 0x4592ac LDR	X0, [X17, X14]

  (816) 0x4592b0 LDR	X13, [X16, #8]

  (816) 0x4592b4 ADD	X5, X0, X13

  (816) 0x4592b8 CMP	X0, X5

  (816) 0x4592bc B.GE	459288

  (816) 0x4592c0 LDR	X16, [X28, X22]

  (816) 0x4592c4 UBFM	X14, X0, #61, #60

  (816) 0x4592c8 ADD	X5, X16, X5,LSL #3

  (816) 0x4592cc ADD	X0, X16, X0,LSL #3

  (816) 0x4592d0 SUB	X3, X5, X0

  (816) 0x4592d4 SUB	X13, X3, #8

  (816) 0x4592d8 UBFM	X3, X13, #3, #63

  (816) 0x4592dc ADD	X13, X3, #1

  (816) 0x4592e0 ANDS	X3, X13, #4160

  (816) 0x4592e4 B.EQ	459468

  (816) 0x4592e8 CMP	X3, #1

  (816) 0x4592ec B.EQ	459350

  (816) 0x4592f0 CMP	X3, #2

  (816) 0x4592f4 B.EQ	459324

  (816) 0x4592f8 LDR	X16, [X16, X14]

  (816) 0x4592fc TBNZ	X16, #63, 4595ac

  (816) 0x459300 UBFM	X13, X16, #61, #60

  (816) 0x459304 LDR	X14, [X19, X13]

  (816) 0x459308 CMP	X14, X6

  (816) 0x45930c B.EQ	459320

  (816) 0x459310 LDR	X3, [X8, X22]

  (816) 0x459314 STR	X16, [X3, X2,LSL #3]

  (816) 0x459318 ADD	X2, X2, #1

  (816) 0x45931c STR	X6, [X19, X13]

  (816) 0x459320 ADD	X0, X0, #8

  (816) 0x459324 LDR	X3, [X0]

  (816) 0x459328 TBNZ	X3, #63, 459580

  (816) 0x45932c UBFM	X13, X3, #61, #60

  (816) 0x459330 LDR	X14, [X19, X13]

  (816) 0x459334 CMP	X14, X6

  (816) 0x459338 B.EQ	45934c

  (816) 0x45933c LDR	X16, [X8, X22]

  (816) 0x459340 STR	X3, [X16, X2,LSL #3]

  (816) 0x459344 ADD	X2, X2, #1

  (816) 0x459348 STR	X6, [X19, X13]

  (816) 0x45934c ADD	X0, X0, #8

  (816) 0x459350 LDR	X16, [X0]

  (816) 0x459354 TBNZ	X16, #63, 459554

  (816) 0x459358 UBFM	X13, X16, #61, #60

  (816) 0x45935c LDR	X14, [X19, X13]

  (816) 0x459360 CMP	X14, X6

  (816) 0x459364 B.EQ	459378

  (816) 0x459368 LDR	X3, [X8, X22]

  (816) 0x45936c STR	X16, [X3, X2,LSL #3]

  (816) 0x459370 ADD	X2, X2, #1

  (816) 0x459374 STR	X6, [X19, X13]

  (816) 0x459378 ADD	X0, X0, #8

  (816) 0x45937c CMP	X0, X5

  (816) 0x459380 B.NE	459468

  (816) 0x459384 LDR	X3, [X15]

  (816) 0x459388 ADD	X1, X1, #1

  (816) 0x45938c CMP	X1, X3

  (816) 0x459390 B.LT	459294

0x459394 HINT	#0

0x459398 HINT	#0

0x45939c HINT	#0

0x4593a0 ADD	X9, X9, #1

0x4593a4 CMP	X30, X9

0x4593a8 B.GT	458ee0

    (817) 0x4593ec UBFM	X13, X16, #61, #60

    (817) 0x4593f0 LDR	X14, [X19, X13]

    (817) 0x4593f4 CMP	X14, X6

    (817) 0x4593f8 B.EQ	45940c

    (817) 0x4593fc LDR	X3, [X8, X22]

    (817) 0x459400 STR	X16, [X3, X2,LSL #3]

    (817) 0x459404 ADD	X2, X2, #1

    (817) 0x459408 STR	X6, [X19, X13]

    (817) 0x45940c LDR	X3, [X0, #8]

    (817) 0x459410 TBNZ	X3, #63, 4594cc

    (817) 0x459414 UBFM	X13, X3, #61, #60

    (817) 0x459418 LDR	X14, [X19, X13]

    (817) 0x45941c CMP	X14, X6

    (817) 0x459420 B.EQ	459434

    (817) 0x459424 LDR	X16, [X8, X22]

    (817) 0x459428 STR	X3, [X16, X2,LSL #3]

    (817) 0x45942c ADD	X2, X2, #1

    (817) 0x459430 STR	X6, [X19, X13]

    (817) 0x459434 LDR	X16, [X0, #16]

    (817) 0x459438 TBNZ	X16, #63, 4594fc

    (817) 0x45943c UBFM	X13, X16, #61, #60

    (817) 0x459440 LDR	X14, [X19, X13]

    (817) 0x459444 CMP	X14, X6

    (817) 0x459448 B.EQ	45945c

    (817) 0x45944c LDR	X3, [X8, X22]

    (817) 0x459450 STR	X16, [X3, X2,LSL #3]

    (817) 0x459454 ADD	X2, X2, #1

    (817) 0x459458 STR	X6, [X19, X13]

    (817) 0x45945c ADD	X0, X0, #24

    (817) 0x459460 CMP	X0, X5

    (817) 0x459464 B.EQ	459384

    (817) 0x459468 LDR	X3, [X0]

    (817) 0x45946c TBNZ	X3, #63, 459528

    (817) 0x459470 UBFM	X13, X3, #61, #60

    (817) 0x459474 LDR	X14, [X19, X13]

    (817) 0x459478 CMP	X14, X6

    (817) 0x45947c B.EQ	459490

    (817) 0x459480 LDR	X16, [X8, X22]

    (817) 0x459484 STR	X3, [X16, X2,LSL #3]

    (817) 0x459488 ADD	X2, X2, #1

    (817) 0x45948c STR	X6, [X19, X13]

    (817) 0x459490 LDR	X16, [X0, #8]

    (817) 0x459494 ADD	X0, X0, #8

    (817) 0x459498 TBZ	X16, #63, 4593ec

    (817) 0x45949c ORN	X13, XZR, X16

    (817) 0x4594a0 UBFM	X13, X13, #61, #60

    (817) 0x4594a4 LDR	X14, [X20, X13]

    (817) 0x4594a8 CMP	X14, X6

    (817) 0x4594ac B.EQ	45940c

    (817) 0x4594b0 LDR	X14, [X10, X22]

    (817) 0x4594b4 ORN	X16, XZR, X16

    (817) 0x4594b8 STR	X16, [X14, X4,LSL #3]

    (817) 0x4594bc ADD	X4, X4, #1

    (817) 0x4594c0 STR	X6, [X20, X13]

    (817) 0x4594c4 LDR	X3, [X0, #8]

    (817) 0x4594c8 TBZ	X3, #63, 459414

    (817) 0x4594cc ORN	X13, XZR, X3

    (817) 0x4594d0 UBFM	X16, X13, #61, #60

    (817) 0x4594d4 LDR	X14, [X20, X16]

    (817) 0x4594d8 CMP	X14, X6

    (817) 0x4594dc B.EQ	459434

    (817) 0x4594e0 LDR	X13, [X10, X22]

    (817) 0x4594e4 ORN	X3, XZR, X3

    (817) 0x4594e8 STR	X3, [X13, X4,LSL #3]

    (817) 0x4594ec ADD	X4, X4, #1

    (817) 0x4594f0 STR	X6, [X20, X16]

    (817) 0x4594f4 LDR	X16, [X0, #16]

    (817) 0x4594f8 TBZ	X16, #63, 45943c

    (817) 0x4594fc ORN	X13, XZR, X16

    (817) 0x459500 UBFM	X13, X13, #61, #60

    (817) 0x459504 LDR	X14, [X20, X13]

    (817) 0x459508 CMP	X14, X6

    (817) 0x45950c B.EQ	45945c

    (817) 0x459510 LDR	X14, [X10, X22]

    (817) 0x459514 ORN	X16, XZR, X16

    (817) 0x459518 STR	X16, [X14, X4,LSL #3]

    (817) 0x45951c ADD	X4, X4, #1

    (817) 0x459520 STR	X6, [X20, X13]

    (817) 0x459524 B	45945c

    (817) 0x459528 ORN	X13, XZR, X3

    (817) 0x45952c UBFM	X16, X13, #61, #60

    (817) 0x459530 LDR	X14, [X20, X16]

    (817) 0x459534 CMP	X14, X6

    (817) 0x459538 B.EQ	459490

    (817) 0x45953c LDR	X13, [X10, X22]

    (817) 0x459540 ORN	X3, XZR, X3

    (817) 0x459544 STR	X3, [X13, X4,LSL #3]

    (817) 0x459548 ADD	X4, X4, #1

    (817) 0x45954c STR	X6, [X20, X16]

    (817) 0x459550 B	459490

  (816) 0x459554 ORN	X13, XZR, X16

  (816) 0x459558 UBFM	X13, X13, #61, #60

  (816) 0x45955c LDR	X14, [X20, X13]

  (816) 0x459560 CMP	X14, X6

  (816) 0x459564 B.EQ	459378

  (816) 0x459568 LDR	X14, [X10, X22]

  (816) 0x45956c ORN	X16, XZR, X16

  (816) 0x459570 STR	X16, [X14, X4,LSL #3]

  (816) 0x459574 ADD	X4, X4, #1

  (816) 0x459578 STR	X6, [X20, X13]

  (816) 0x45957c B	459378

  (816) 0x459580 ORN	X13, XZR, X3

  (816) 0x459584 UBFM	X16, X13, #61, #60

  (816) 0x459588 LDR	X14, [X20, X16]

  (816) 0x45958c CMP	X14, X6

  (816) 0x459590 B.EQ	45934c

  (816) 0x459594 LDR	X13, [X10, X22]

  (816) 0x459598 ORN	X3, XZR, X3

  (816) 0x45959c STR	X3, [X13, X4,LSL #3]

  (816) 0x4595a0 ADD	X4, X4, #1

  (816) 0x4595a4 STR	X6, [X20, X16]

  (816) 0x4595a8 B	45934c

  (816) 0x4595ac ORN	X13, XZR, X16

  (816) 0x4595b0 UBFM	X13, X13, #61, #60

  (816) 0x4595b4 LDR	X14, [X20, X13]

  (816) 0x4595b8 CMP	X14, X6

  (816) 0x4595bc B.EQ	459320

  (816) 0x4595c0 LDR	X14, [X10, X22]

  (816) 0x4595c4 ORN	X16, XZR, X16

  (816) 0x4595c8 STR	X16, [X14, X4,LSL #3]

  (816) 0x4595cc ADD	X4, X4, #1

  (816) 0x4595d0 STR	X6, [X20, X13]

  (816) 0x4595d4 B	459320

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1072 - 1125

--------------------------------------------------------------------------------

1072:           for (i=thread_start; i < thread_stop; i++)

1073:           {

1074:              i1 = pass_array[i];

1075:              for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

1076:              {

1077:                 j1 = S_diag_j[j];

1078:                 if (assigned[j1] == pass-1)

1079:                 {

1080:                    j_start = P_diag_start[j1];

1081:                    j_end = j_start+P_diag_i[j1+1];

1082:                    for (k=j_start; k < j_end; k++)

1083:                    {

1084:                       k1 = P_diag_pass[pass-1][k];

1085:                       if (P_marker[k1] != -i1-1)

1086:                       {

1087:                           P_diag_pass[pass][cnt_nz++] = k1;

1088:                           P_marker[k1] = -i1-1;

1089:                       }

1090:                    }

1091:                    j_start = P_offd_start[j1];

1092:                    j_end = j_start+P_offd_i[j1+1];

1093:                    for (k=j_start; k < j_end; k++)

1094:                    {

1095:                       k1 = P_offd_pass[pass-1][k];

1096:                       if (P_marker_offd[k1] != -i1-1)

1097:                       {

1098:                          P_offd_pass[pass][cnt_nz_offd++] = k1;

1099:                          P_marker_offd[k1] = -i1-1;

1100:                       }

1101:                    }

1102:                 }

1103:              }

1104:              for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

1105:              {

1106:                 j1 = S_offd_j[j];

1107:                 if (assigned_offd[j1] == pass-1)

1108:                 {

1109:                    j_start = Pext_start[j1];

1110:                    j_end = j_start+Pext_i[j1+1];

1111:                    for (k=j_start; k < j_end; k++)

1112:                    {

1113:                       k1 = Pext_pass[pass][k];

1114:                       if (k1 < 0)

1115:                       {

1116:                          if (P_marker[-k1-1] != -i1-1)

1117:                          {

1118:                             P_diag_pass[pass][cnt_nz++] = -k1-1;

1119:                             P_marker[-k1-1] = -i1-1;

1120:                          }

1121:                       }

1122:                       else if (P_marker_offd[k1] != -i1-1)

1123:                       {

1124:                          P_offd_pass[pass][cnt_nz_offd++] = k1;

1125:                          P_marker_offd[k1] = -i1-1;

Coverage (%)	Name	Source Location	Module
►98.48+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.52+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:891	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source	par_multi_interp.c:1072-1075,par_multi_interp.c:1104-1104,par_multi_interp.c:1122-1122
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.38
CQA cycles if no scalar integer	3.38
CQA cycles if FP arith vectorized	3.38
CQA cycles if fully vectorized	1.69
Front-end cycles	3.38
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	2.17
P5 cycles	2.17
P6 cycles	2.08
P7 cycles	2.08
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	3.17
P13 cycles	2.83
P14 cycles	3.00
P15 cycles	0.50
P16 cycles	0.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	27.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.70
Bytes prefetched	0.00
Bytes loaded	72.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source	par_multi_interp.c:1072-1075,par_multi_interp.c:1104-1104,par_multi_interp.c:1122-1122
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.38
CQA cycles if no scalar integer	3.38
CQA cycles if FP arith vectorized	3.38
CQA cycles if fully vectorized	1.69
Front-end cycles	3.38
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	2.17
P5 cycles	2.17
P6 cycles	2.08
P7 cycles	2.08
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	3.17
P13 cycles	2.83
P14 cycles	3.00
P15 cycles	0.50
P16 cycles	0.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	27.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.70
Bytes prefetched	0.00
Bytes loaded	72.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source file and lines	par_multi_interp.c:1072-1125
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1072-1125.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1072-1075,1104,1122.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.38 to 1.69 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 72 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	31
loop length	124
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	2.25	2.25	2.17	2.17	2.08	2.08	0.00	0.00	0.00	0.00	3.17	2.83	3.00	0.50	0.50
cycles	2.50	2.50	2.25	2.25	2.17	2.17	2.08	2.08	0.00	0.00	0.00	0.00	3.17	2.83	3.00	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.38
Overall L1	3.38

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.38 cycles. At this rate:

22% of peak load performance is reached (21.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.37 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 458ee0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR X21, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X21, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
UBFM X15, X6, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORN X0, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X14, X15, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X3, [X12, X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X5, X12, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X13, [X12, X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X3, X13	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 459268 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x101c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X28, XZR, X24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X6, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X6, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 458f24 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xcd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
LDR X6, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X24, XZR, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORN X6, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X1, [X11, X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X15, X11, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X3, [X11, X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X3, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4593a0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1154>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X21, X28, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
B 459294 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1048>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ADD X9, X9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X30, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.GT 458ee0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xc94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source file and lines	par_multi_interp.c:1072-1125
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.38 to 1.69 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 72 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	31
loop length	124
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	2.25	2.25	2.17	2.17	2.08	2.08	0.00	0.00	0.00	0.00	3.17	2.83	3.00	0.50	0.50
cycles	2.50	2.50	2.25	2.25	2.17	2.17	2.08	2.08	0.00	0.00	0.00	0.00	3.17	2.83	3.00	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.38
Overall L1	3.38

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.38 cycles. At this rate:

22% of peak load performance is reached (21.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.37 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 458ee0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR X21, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X21, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
UBFM X15, X6, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORN X0, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X14, X15, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X3, [X12, X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X5, X12, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X13, [X12, X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X3, X13	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 459268 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x101c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X28, XZR, X24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X6, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X6, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 458f24 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xcd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
LDR X6, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X24, XZR, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORN X6, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X1, [X11, X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X15, X11, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X3, [X11, X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X3, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4593a0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1154>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X21, X28, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
B 459294 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1048>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ADD X9, X9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X30, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.GT 458ee0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xc94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code