OV - exec - Loop 4023

	Loop Id: 4023	Module: exec	Source: vector.c:416-416	Coverage: 0.34%

0x53ef18 LDP	Q2, Q3, [X14]    [3]

0x53ef1c ORR	X13, XZR, X14

0x53ef20 LDP	Q28, Q18, [X14, #96]    [3]

0x53ef24 LDP	Q21, Q22, [X14, #32]    [3]

0x53ef28 LDP	Q19, Q20, [X14, #64]    [3]

0x53ef2c LDP	Q23, Q24, [X14, #128]    [3]

0x53ef30 FMUL	V17.2D, V2.2D, V30.2D

0x53ef34 LDP	Q25, Q27, [X14, #160]    [3]

0x53ef38 FMUL	V4.2D, V3.2D, V30.2D

0x53ef3c LDP	Q26, Q0, [X14, #192]    [3]

0x53ef40 FMUL	V21.2D, V21.2D, V30.2D

0x53ef44 LDP	Q1, Q29, [X14, #224]    [3]

0x53ef48 ADD	X14, X14, #256

0x53ef4c FMUL	V22.2D, V22.2D, V30.2D

0x53ef50 FMUL	V19.2D, V19.2D, V30.2D

0x53ef54 FMUL	V20.2D, V20.2D, V30.2D

0x53ef58 FMUL	V7.2D, V23.2D, V30.2D

0x53ef5c FMUL	V16.2D, V24.2D, V30.2D

0x53ef60 FMUL	V5.2D, V25.2D, V30.2D

0x53ef64 FMUL	V6.2D, V27.2D, V30.2D

0x53ef68 FMUL	V3.2D, V26.2D, V30.2D

0x53ef6c FMUL	V2.2D, V1.2D, V30.2D

0x53ef70 STP	Q17, Q4, [X14, #1792]    [2]

0x53ef74 FMUL	V17.2D, V28.2D, V30.2D

0x53ef78 FMUL	V4.2D, V0.2D, V30.2D

0x53ef7c FMUL	V28.2D, V18.2D, V30.2D

0x53ef80 STUR	Q2, [X14, #480]    [2]

0x53ef84 FMUL	V18.2D, V29.2D, V30.2D

0x53ef88 STP	Q21, Q22, [X14, #1824]    [2]

0x53ef8c STP	Q19, Q20, [X14, #1856]    [2]

0x53ef90 STP	Q17, Q28, [X14, #1888]    [2]

0x53ef94 STP	Q7, Q16, [X14, #1920]    [2]

0x53ef98 STP	Q5, Q6, [X14, #1952]    [2]

0x53ef9c STP	Q3, Q4, [X14, #1984]    [2]

0x53efa0 STR	Q18, [X13, #240]    [1]

0x53efa4 CMP	X14, X9

0x53efa8 B.NE	53ef18

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/vector.c: 416 - 416

--------------------------------------------------------------------------------

416:       y_data[i] *= alpha;

Coverage (%)	Name	Source Location	Module
►99.63+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	P8, P9, P10, P11,
Function	hypre_SeqVectorScale._omp_fn.0
Source	vector.c:416-416
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.25
CQA cycles if no scalar integer	6.25
CQA cycles if FP arith vectorized	6.25
CQA cycles if fully vectorized	6.25
Front-end cycles	4.63
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.58
P3 cycles	0.58
P4 cycles	0.50
P5 cycles	0.50
P6 cycles	0.42
P7 cycles	0.42
P8 cycles	6.25
P9 cycles	6.25
P10 cycles	6.25
P11 cycles	6.25
P12 cycles	5.83
P13 cycles	5.50
P14 cycles	5.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	37.00
Nb uops	37.00
Nb loads	NA
Nb stores	9.00
Nb stack references	0.00
FLOP/cycle	5.12
Nb FLOP add-sub	0.00
Nb FLOP mul	32.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	81.92
Bytes prefetched	0.00
Bytes loaded	256.00
Bytes stored	256.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	P8, P9, P10, P11,
Function	hypre_SeqVectorScale._omp_fn.0
Source	vector.c:416-416
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.25
CQA cycles if no scalar integer	6.25
CQA cycles if FP arith vectorized	6.25
CQA cycles if fully vectorized	6.25
Front-end cycles	4.63
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.58
P3 cycles	0.58
P4 cycles	0.50
P5 cycles	0.50
P6 cycles	0.42
P7 cycles	0.42
P8 cycles	6.25
P9 cycles	6.25
P10 cycles	6.25
P11 cycles	6.25
P12 cycles	5.83
P13 cycles	5.50
P14 cycles	5.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	37.00
Nb uops	37.00
Nb loads	NA
Nb stores	9.00
Nb stack references	0.00
FLOP/cycle	5.12
Nb FLOP add-sub	0.00
Nb FLOP mul	32.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	81.92
Bytes prefetched	0.00
Bytes loaded	256.00
Bytes stored	256.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_SeqVectorScale._omp_fn.0
Source file and lines	vector.c:416-416
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/vector.c:416.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

32: multiply

The binary loop is loading 256 bytes. The binary loop is storing 256 bytes.

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	37
loop length	148
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.58	0.58	0.50	0.50	0.42	0.42	6.25	6.25	6.25	6.25	5.83	5.50	5.67	0.00	0.00
cycles	0.50	0.50	0.58	0.58	0.50	0.50	0.42	0.42	6.25	6.25	6.25	6.25	5.83	5.50	5.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.63
Data deps.	1.00
Overall L1	6.25

Vectorization ratios

INT

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.25 cycles. At this rate:

42% of peak load performance is reached (40.96 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
85% of peak store performance is reached (40.96 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 53ef18

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDP Q2, Q3, [X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ORR X13, XZR, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDP Q28, Q18, [X14, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
LDP Q21, Q22, [X14, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
LDP Q19, Q20, [X14, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
LDP Q23, Q24, [X14, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FMUL V17.2D, V2.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LDP Q25, Q27, [X14, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FMUL V4.2D, V3.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LDP Q26, Q0, [X14, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FMUL V21.2D, V21.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LDP Q1, Q29, [X14, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ADD X14, X14, #256	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMUL V22.2D, V22.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V19.2D, V19.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V20.2D, V20.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V7.2D, V23.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V16.2D, V24.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V5.2D, V25.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V6.2D, V27.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V3.2D, V26.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V2.2D, V1.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
STP Q17, Q4, [X14, #1792]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	1	vect (100.0%)
FMUL V17.2D, V28.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V4.2D, V0.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V28.2D, V18.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
STUR Q2, [X14, #480]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
FMUL V18.2D, V29.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
STP Q21, Q22, [X14, #1824]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	1	vect (100.0%)
STP Q19, Q20, [X14, #1856]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	1	vect (100.0%)
STP Q17, Q28, [X14, #1888]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	1	vect (100.0%)
STP Q7, Q16, [X14, #1920]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	1	vect (100.0%)
STP Q5, Q6, [X14, #1952]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	1	vect (100.0%)
STP Q3, Q4, [X14, #1984]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	1	vect (100.0%)
STR Q18, [X13, #240]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
CMP X14, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 53ef18 <hypre_SeqVectorScale._omp_fn.0+0x12c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_SeqVectorScale._omp_fn.0
Source file and lines	vector.c:416-416
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/vector.c:416.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

32: multiply

The binary loop is loading 256 bytes. The binary loop is storing 256 bytes.

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	37
loop length	148
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.58	0.58	0.50	0.50	0.42	0.42	6.25	6.25	6.25	6.25	5.83	5.50	5.67	0.00	0.00
cycles	0.50	0.50	0.58	0.58	0.50	0.50	0.42	0.42	6.25	6.25	6.25	6.25	5.83	5.50	5.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.63
Data deps.	1.00
Overall L1	6.25

Vectorization ratios

INT

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.25 cycles. At this rate:

42% of peak load performance is reached (40.96 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
85% of peak store performance is reached (40.96 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 53ef18

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDP Q2, Q3, [X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ORR X13, XZR, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDP Q28, Q18, [X14, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
LDP Q21, Q22, [X14, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
LDP Q19, Q20, [X14, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
LDP Q23, Q24, [X14, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FMUL V17.2D, V2.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LDP Q25, Q27, [X14, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FMUL V4.2D, V3.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LDP Q26, Q0, [X14, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FMUL V21.2D, V21.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LDP Q1, Q29, [X14, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ADD X14, X14, #256	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMUL V22.2D, V22.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V19.2D, V19.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V20.2D, V20.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V7.2D, V23.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V16.2D, V24.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V5.2D, V25.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V6.2D, V27.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V3.2D, V26.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V2.2D, V1.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
STP Q17, Q4, [X14, #1792]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	1	vect (100.0%)
FMUL V17.2D, V28.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V4.2D, V0.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V28.2D, V18.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
STUR Q2, [X14, #480]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
FMUL V18.2D, V29.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
STP Q21, Q22, [X14, #1824]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	1	vect (100.0%)
STP Q19, Q20, [X14, #1856]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	1	vect (100.0%)
STP Q17, Q28, [X14, #1888]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	1	vect (100.0%)
STP Q7, Q16, [X14, #1920]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	1	vect (100.0%)
STP Q5, Q6, [X14, #1952]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	1	vect (100.0%)
STP Q3, Q4, [X14, #1984]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	1	vect (100.0%)
STR Q18, [X13, #240]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
CMP X14, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 53ef18 <hypre_SeqVectorScale._omp_fn.0+0x12c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code