OV - exec - Loop 4018

0x53e978 ADD	X13, X14, #32

0x53e97c STR	Q31, [X14, #32]    [3]

0x53e980 ADD	X14, X14, #256

0x53e984 STP	Q31, Q31, [X14, #1792]    [2]

0x53e988 STP	Q31, Q31, [X13, #16]    [1]

0x53e98c STUR	Q31, [X14, #336]    [2]

0x53e990 STP	Q31, Q31, [X14, #1888]    [2]

0x53e994 STP	Q31, Q31, [X14, #1920]    [2]

0x53e998 STP	Q31, Q31, [X14, #1952]    [2]

0x53e99c STP	Q31, Q31, [X14, #1984]    [2]

0x53e9a0 STP	Q31, Q31, [X14, #2016]    [2]

0x53e9a4 CMP	X9, X14

0x53e9a8 B.NE	53e978

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/vector.c: 271 - 271

--------------------------------------------------------------------------------

271:       vector_data[i] = value;

Coverage (%)	Name	Source Location	Module
►97.70+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►2.30+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	hypre_SeqVectorSetConstantValu[...]	vector.c:278	exec
○	hypre_PCGSolve	pcg.c:542	exec
○	main	amg.c:419	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.77
Bottlenecks	P8, P9, P12, P13,
Function	hypre_SeqVectorSetConstantValues._omp_fn.0
Source	vector.c:271-271
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.50
CQA cycles if no scalar integer	4.50
CQA cycles if FP arith vectorized	4.50
CQA cycles if fully vectorized	4.50
Front-end cycles	1.63
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.58
P3 cycles	0.58
P4 cycles	0.50
P5 cycles	0.50
P6 cycles	0.42
P7 cycles	0.42
P8 cycles	4.50
P9 cycles	4.50
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	4.50
P13 cycles	4.50
P14 cycles	0.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	13.00
Nb uops	13.00
Nb loads	NA
Nb stores	9.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	56.89
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	256.00
Stride 0	0.00
Stride 1	0.00
Stride n	1.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	NA
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.77
Bottlenecks	P8, P9, P12, P13,
Function	hypre_SeqVectorSetConstantValues._omp_fn.0
Source	vector.c:271-271
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.50
CQA cycles if no scalar integer	4.50
CQA cycles if FP arith vectorized	4.50
CQA cycles if fully vectorized	4.50
Front-end cycles	1.63
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.58
P3 cycles	0.58
P4 cycles	0.50
P5 cycles	0.50
P6 cycles	0.42
P7 cycles	0.42
P8 cycles	4.50
P9 cycles	4.50
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	4.50
P13 cycles	4.50
P14 cycles	0.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	13.00
Nb uops	13.00
Nb loads	NA
Nb stores	9.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	56.89
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	256.00
Stride 0	0.00
Stride 1	0.00
Stride n	1.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	NA
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_SeqVectorSetConstantValues._omp_fn.0
Source file and lines	vector.c:271-271
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/vector.c:271.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 256 bytes.

General properties

nb instructions	13
loop length	52
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.58	0.58	0.50	0.50	0.42	0.42	4.50	4.50	0.00	0.00	4.50	4.50	0.00	0.00	0.00
cycles	0.50	0.50	0.58	0.58	0.50	0.50	0.42	0.42	4.50	4.50	0.00	0.00	4.50	4.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.63
Data deps.	1.00
Overall L1	4.50

Vectorization ratios

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.50 cycles. At this rate:

118% of peak store performance is reached (56.89 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 53e978

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	Latency	Recip. throughput	Vectorization
ADD X13, X14, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
STR Q31, [X14, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
ADD X14, X14, #256	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
STP Q31, Q31, [X14, #1792]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	1	vect (100.0%)
STP Q31, Q31, [X13, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	1	vect (100.0%)
STUR Q31, [X14, #336]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STP Q31, Q31, [X14, #1888]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	1	vect (100.0%)
STP Q31, Q31, [X14, #1920]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	1	vect (100.0%)
STP Q31, Q31, [X14, #1952]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	1	vect (100.0%)
STP Q31, Q31, [X14, #1984]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	1	vect (100.0%)
STP Q31, Q31, [X14, #2016]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	1	vect (100.0%)
CMP X9, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	1	0.33	N/A
B.NE 53e978 <hypre_SeqVectorSetConstantValues._omp_fn.0+0xd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_SeqVectorSetConstantValues._omp_fn.0
Source file and lines	vector.c:271-271
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/vector.c:271.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 256 bytes.

General properties

nb instructions	13
loop length	52
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.58	0.58	0.50	0.50	0.42	0.42	4.50	4.50	0.00	0.00	4.50	4.50	0.00	0.00	0.00
cycles	0.50	0.50	0.58	0.58	0.50	0.50	0.42	0.42	4.50	4.50	0.00	0.00	4.50	4.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.63
Data deps.	1.00
Overall L1	4.50

Vectorization ratios

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.50 cycles. At this rate:

118% of peak store performance is reached (56.89 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 53e978

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	Latency	Recip. throughput	Vectorization
ADD X13, X14, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
STR Q31, [X14, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
ADD X14, X14, #256	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
STP Q31, Q31, [X14, #1792]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	1	vect (100.0%)
STP Q31, Q31, [X13, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	1	vect (100.0%)
STUR Q31, [X14, #336]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STP Q31, Q31, [X14, #1888]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	1	vect (100.0%)
STP Q31, Q31, [X14, #1920]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	1	vect (100.0%)
STP Q31, Q31, [X14, #1952]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	1	vect (100.0%)
STP Q31, Q31, [X14, #1984]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	1	vect (100.0%)
STP Q31, Q31, [X14, #2016]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	1	vect (100.0%)
CMP X9, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	1	0.33	N/A
B.NE 53e978 <hypre_SeqVectorSetConstantValues._omp_fn.0+0xd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code