OV - exec - Loop 3962

	Loop Id: 3962	Module: exec	Source: csr_matvec.c:310-312	Coverage: 7.09%

0x53aaac LD1D	{Z24.D}, P6/Z, [X0, MUL VL]    [1]

0x53aab0 LD1D	{Z3.D}, P6/Z, [X0, #2, MUL VL]    [1]

0x53aab4 LD1D	{Z22.D}, P6/Z, [X0, #4, MUL VL]    [1]

0x53aab8 LD1D	{Z6.D}, P6/Z, [X0, #1, MUL VL]    [1]

0x53aabc LD1D	{Z15.D}, P6/Z, [X0, #6, MUL VL]    [1]

0x53aac0 LD1D	{Z26.D}, P6/Z, [X0, #3, MUL VL]    [1]

0x53aac4 LD1D	{Z18.D}, P6/Z, [X0, #5, MUL VL]    [1]

0x53aac8 LD1D	{Z23.D}, P6/Z, [X0, #7, MUL VL]    [1]

0x53aacc ADD	X0, X0, #128

0x53aad0 LD1D	{Z2.D}, P6/Z, [X18, MUL VL]    [2]

0x53aad4 LD1D	{Z4.D}, P6/Z, [X19, Z24.D,LSL #3]    [3]

0x53aad8 LD1D	{Z29.D}, P6/Z, [X18, #1, MUL VL]    [2]

0x53aadc LD1D	{Z20.D}, P6/Z, [X18, #2, MUL VL]    [2]

0x53aae0 LD1D	{Z1.D}, P6/Z, [X18, #4, MUL VL]    [2]

0x53aae4 LD1D	{Z19.D}, P6/Z, [X18, #6, MUL VL]    [2]

0x53aae8 LD1D	{Z16.D}, P6/Z, [X18, #3, MUL VL]    [2]

0x53aaec LD1D	{Z0.D}, P6/Z, [X18, #5, MUL VL]    [2]

0x53aaf0 LD1D	{Z24.D}, P6/Z, [X18, #7, MUL VL]    [2]

0x53aaf4 FMLS	Z30.D, P6/M, Z4.D, Z2.D

0x53aaf8 LD1D	{Z28.D}, P6/Z, [X19, Z3.D,LSL #3]    [3]

0x53aafc LD1D	{Z5.D}, P6/Z, [X19, Z22.D,LSL #3]    [3]

0x53ab00 FMLS	Z30.D, P6/M, Z28.D, Z20.D

0x53ab04 LD1D	{Z7.D}, P6/Z, [X19, Z6.D,LSL #3]    [3]

0x53ab08 FMLS	Z30.D, P6/M, Z5.D, Z1.D

0x53ab0c FMLS	Z14.D, P6/M, Z7.D, Z29.D

0x53ab10 LD1D	{Z21.D}, P6/Z, [X19, Z15.D,LSL #3]    [3]

0x53ab14 LD1D	{Z27.D}, P6/Z, [X19, Z26.D,LSL #3]    [3]

0x53ab18 LD1D	{Z17.D}, P6/Z, [X19, Z18.D,LSL #3]    [3]

0x53ab1c FMLS	Z14.D, P6/M, Z27.D, Z16.D

0x53ab20 LD1D	{Z25.D}, P6/Z, [X19, Z23.D,LSL #3]    [3]

0x53ab24 FMLS	Z14.D, P6/M, Z17.D, Z0.D

0x53ab28 ADD	X18, X18, #128

0x53ab2c FMLS	Z30.D, P6/M, Z21.D, Z19.D

0x53ab30 FMLS	Z14.D, P6/M, Z25.D, Z24.D

0x53ab34 CMP	X14, X0

0x53ab38 B.NE	53aaac

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 310 - 312

--------------------------------------------------------------------------------

310:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

311:                {

312:                   tempx -= A_data[jj] * x_data[A_j[jj]];

Coverage (%)	Name	Source Location	Module
►98.89+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.02+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	hypre_CSRMatrixMatvecOutOfPlac[...]	csr_matvec.c:243	exec
○	hypre_ParCSRMatrixMatvecOutOfP[...]	par_csr_matvec.c:216	exec
○	hypre_BoomerAMGCycle	par_cycle.c:429	exec
○	hypre_BoomerAMGSolve	par_amg_solve.c:235	exec
○	hypre_PCGSolve	pcg.c:545	exec
○	main	amg.c:419	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.78
Bottlenecks
Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6
Source	csr_matvec.c:310-312
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	8.00
Front-end cycles	4.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.58
P3 cycles	0.58
P4 cycles	0.50
P5 cycles	0.50
P6 cycles	0.42
P7 cycles	0.42
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	2.00
P11 cycles	2.00
P12 cycles	8.00
P13 cycles	8.00
P14 cycles	8.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	36.00
Nb uops	36.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	4.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	16.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	48.00
Bytes prefetched	0.00
Bytes loaded	384.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	2.00
Stride unknown	0.00
Stride indirect	1.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.78
Bottlenecks
Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6
Source	csr_matvec.c:310-312
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	8.00
Front-end cycles	4.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.58
P3 cycles	0.58
P4 cycles	0.50
P5 cycles	0.50
P6 cycles	0.42
P7 cycles	0.42
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	2.00
P11 cycles	2.00
P12 cycles	8.00
P13 cycles	8.00
P14 cycles	8.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	36.00
Nb uops	36.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	4.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	16.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	48.00
Bytes prefetched	0.00
Bytes loaded	384.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	2.00
Stride unknown	0.00
Stride indirect	1.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6
Source file and lines	csr_matvec.c:310-312
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:310-312.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

FMA

Detected 16 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

16: addition or subtraction (all inside FMA instructions)
16: multiply (all inside FMA instructions)

The binary loop is loading 384 bytes.

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	36
loop length	144
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.58	0.58	0.50	0.50	0.42	0.42	2.00	2.00	2.00	2.00	8.00	8.00	8.00	0.00	0.00
cycles	0.50	0.50	0.58	0.58	0.50	0.50	0.42	0.42	2.00	2.00	2.00	2.00	8.00	8.00	8.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	4.50
Data deps.	8.00
Overall L1	8.00

Vectorization ratios

INT

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

50% of peak load performance is reached (48.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 53aaac

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LD1D {Z24.D}, P6/Z, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z3.D}, P6/Z, [X0, #2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z22.D}, P6/Z, [X0, #4, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z6.D}, P6/Z, [X0, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z15.D}, P6/Z, [X0, #6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z26.D}, P6/Z, [X0, #3, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z18.D}, P6/Z, [X0, #5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z23.D}, P6/Z, [X0, #7, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X0, X0, #128	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z2.D}, P6/Z, [X18, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z4.D}, P6/Z, [X19, Z24.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z29.D}, P6/Z, [X18, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z20.D}, P6/Z, [X18, #2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z1.D}, P6/Z, [X18, #4, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z19.D}, P6/Z, [X18, #6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z16.D}, P6/Z, [X18, #3, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z0.D}, P6/Z, [X18, #5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z24.D}, P6/Z, [X18, #7, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLS Z30.D, P6/M, Z4.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LD1D {Z28.D}, P6/Z, [X19, Z3.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z5.D}, P6/Z, [X19, Z22.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLS Z30.D, P6/M, Z28.D, Z20.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LD1D {Z7.D}, P6/Z, [X19, Z6.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLS Z30.D, P6/M, Z5.D, Z1.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLS Z14.D, P6/M, Z7.D, Z29.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LD1D {Z21.D}, P6/Z, [X19, Z15.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z27.D}, P6/Z, [X19, Z26.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z17.D}, P6/Z, [X19, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLS Z14.D, P6/M, Z27.D, Z16.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LD1D {Z25.D}, P6/Z, [X19, Z23.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLS Z14.D, P6/M, Z17.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
ADD X18, X18, #128	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMLS Z30.D, P6/M, Z21.D, Z19.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLS Z14.D, P6/M, Z25.D, Z24.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
CMP X14, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 53aaac <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1248>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6
Source file and lines	csr_matvec.c:310-312
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:310-312.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

FMA

Detected 16 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

16: addition or subtraction (all inside FMA instructions)
16: multiply (all inside FMA instructions)

The binary loop is loading 384 bytes.

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	36
loop length	144
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.58	0.58	0.50	0.50	0.42	0.42	2.00	2.00	2.00	2.00	8.00	8.00	8.00	0.00	0.00
cycles	0.50	0.50	0.58	0.58	0.50	0.50	0.42	0.42	2.00	2.00	2.00	2.00	8.00	8.00	8.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	4.50
Data deps.	8.00
Overall L1	8.00

Vectorization ratios

INT

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

50% of peak load performance is reached (48.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 53aaac

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LD1D {Z24.D}, P6/Z, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z3.D}, P6/Z, [X0, #2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z22.D}, P6/Z, [X0, #4, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z6.D}, P6/Z, [X0, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z15.D}, P6/Z, [X0, #6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z26.D}, P6/Z, [X0, #3, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z18.D}, P6/Z, [X0, #5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z23.D}, P6/Z, [X0, #7, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X0, X0, #128	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z2.D}, P6/Z, [X18, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z4.D}, P6/Z, [X19, Z24.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z29.D}, P6/Z, [X18, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z20.D}, P6/Z, [X18, #2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z1.D}, P6/Z, [X18, #4, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z19.D}, P6/Z, [X18, #6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z16.D}, P6/Z, [X18, #3, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z0.D}, P6/Z, [X18, #5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z24.D}, P6/Z, [X18, #7, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLS Z30.D, P6/M, Z4.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LD1D {Z28.D}, P6/Z, [X19, Z3.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z5.D}, P6/Z, [X19, Z22.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLS Z30.D, P6/M, Z28.D, Z20.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LD1D {Z7.D}, P6/Z, [X19, Z6.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLS Z30.D, P6/M, Z5.D, Z1.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLS Z14.D, P6/M, Z7.D, Z29.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LD1D {Z21.D}, P6/Z, [X19, Z15.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z27.D}, P6/Z, [X19, Z26.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z17.D}, P6/Z, [X19, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLS Z14.D, P6/M, Z27.D, Z16.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LD1D {Z25.D}, P6/Z, [X19, Z23.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLS Z14.D, P6/M, Z17.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
ADD X18, X18, #128	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMLS Z30.D, P6/M, Z21.D, Z19.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLS Z14.D, P6/M, Z25.D, Z24.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
CMP X14, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 53aaac <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1248>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code