OV - exec - Loop 3961

	Loop Id: 3961	Module: exec	Source: csr_matvec.c:307-314	Coverage: 5.97%

0x53a9c4 LDR	X2, [X24, X20,LSL #3]

0x53a9c8 LDR	X10, [X13, X20,LSL #3]

0x53a9cc LDR	D31, [X26, X20,LSL #3]

0x53a9d0 CMP	X2, X10

0x53a9d4 B.GE	53abcc

0x53a9d8 SUB	X11, X10, X2

0x53a9dc SUB	X3, X11, #1

0x53a9e0 CMP	X3, #3

0x53a9e4 B.LS	53ab58

0x53a9e8 UBFM	X9, X11, #2, #63

0x53a9ec ADD	X0, X21, X2,LSL #3

0x53a9f0 DUP	Z14.D, #0

0x53a9f4 ORR	Z30.D, Z14.D, Z14.D

0x53a9f8 UBFM	X12, X9, #59, #58

0x53a9fc ADD	X18, X22, X2,LSL #3

0x53aa00 SUB	X16, X12, #32

0x53aa04 ADD	X14, X0, X9,LSL #5

0x53aa08 UBFM	X15, X16, #5, #63

0x53aa0c ADD	X17, X15, #1

0x53aa10 ANDS	X27, X17, #4160

0x53aa14 B.EQ	53aaac

0x53aa18 CMP	X27, #1

0x53aa1c B.EQ	53aa7c

0x53aa20 CMP	X27, #2

0x53aa24 B.EQ	53aa54

0x53aa28 LD1D	{Z22.D}, P6/Z, [X0, MUL VL]

0x53aa2c LD1D	{Z23.D}, P6/Z, [X18, MUL VL]

0x53aa30 LD1D	{Z6.D}, P6/Z, [X0, #1, MUL VL]

0x53aa34 LD1D	{Z29.D}, P6/Z, [X18, #1, MUL VL]

0x53aa38 ADD	X0, X0, #32

0x53aa3c ADD	X18, X18, #32

0x53aa40 LD1D	{Z15.D}, P6/Z, [X19, Z22.D,LSL #3]

0x53aa44 LD1D	{Z28.D}, P6/Z, [X19, Z6.D,LSL #3]

0x53aa48 MOVPRFX	Z30, Z14

0x53aa4c FMLS	Z30.D, P6/M, Z15.D, Z23.D

0x53aa50 FMLS	Z14.D, P6/M, Z28.D, Z29.D

0x53aa54 LD1D	{Z26.D}, P6/Z, [X0, MUL VL]

0x53aa58 LD1D	{Z20.D}, P6/Z, [X18, MUL VL]

0x53aa5c LD1D	{Z5.D}, P6/Z, [X0, #1, MUL VL]

0x53aa60 LD1D	{Z1.D}, P6/Z, [X18, #1, MUL VL]

0x53aa64 ADD	X0, X0, #32

0x53aa68 ADD	X18, X18, #32

0x53aa6c LD1D	{Z7.D}, P6/Z, [X19, Z26.D,LSL #3]

0x53aa70 LD1D	{Z21.D}, P6/Z, [X19, Z5.D,LSL #3]

0x53aa74 FMLS	Z30.D, P6/M, Z7.D, Z20.D

0x53aa78 FMLS	Z14.D, P6/M, Z21.D, Z1.D

0x53aa7c LD1D	{Z19.D}, P6/Z, [X0, MUL VL]

0x53aa80 LD1D	{Z17.D}, P6/Z, [X0, #1, MUL VL]

0x53aa84 ADD	X0, X0, #32

0x53aa88 LD1D	{Z16.D}, P6/Z, [X18, MUL VL]

0x53aa8c LD1D	{Z25.D}, P6/Z, [X18, #1, MUL VL]

0x53aa90 LD1D	{Z27.D}, P6/Z, [X19, Z19.D,LSL #3]

0x53aa94 LD1D	{Z0.D}, P6/Z, [X19, Z17.D,LSL #3]

0x53aa98 ADD	X18, X18, #32

0x53aa9c FMLS	Z30.D, P6/M, Z27.D, Z16.D

0x53aaa0 FMLS	Z14.D, P6/M, Z0.D, Z25.D

0x53aaa4 CMP	X14, X0

0x53aaa8 B.EQ	53ab3c

  (3962) 0x53aaac LD1D	{Z24.D}, P6/Z, [X0, MUL VL]

  (3962) 0x53aab0 LD1D	{Z3.D}, P6/Z, [X0, #2, MUL VL]

  (3962) 0x53aab4 LD1D	{Z22.D}, P6/Z, [X0, #4, MUL VL]

  (3962) 0x53aab8 LD1D	{Z6.D}, P6/Z, [X0, #1, MUL VL]

  (3962) 0x53aabc LD1D	{Z15.D}, P6/Z, [X0, #6, MUL VL]

  (3962) 0x53aac0 LD1D	{Z26.D}, P6/Z, [X0, #3, MUL VL]

  (3962) 0x53aac4 LD1D	{Z18.D}, P6/Z, [X0, #5, MUL VL]

  (3962) 0x53aac8 LD1D	{Z23.D}, P6/Z, [X0, #7, MUL VL]

  (3962) 0x53aacc ADD	X0, X0, #128

  (3962) 0x53aad0 LD1D	{Z2.D}, P6/Z, [X18, MUL VL]

  (3962) 0x53aad4 LD1D	{Z4.D}, P6/Z, [X19, Z24.D,LSL #3]

  (3962) 0x53aad8 LD1D	{Z29.D}, P6/Z, [X18, #1, MUL VL]

  (3962) 0x53aadc LD1D	{Z20.D}, P6/Z, [X18, #2, MUL VL]

  (3962) 0x53aae0 LD1D	{Z1.D}, P6/Z, [X18, #4, MUL VL]

  (3962) 0x53aae4 LD1D	{Z19.D}, P6/Z, [X18, #6, MUL VL]

  (3962) 0x53aae8 LD1D	{Z16.D}, P6/Z, [X18, #3, MUL VL]

  (3962) 0x53aaec LD1D	{Z0.D}, P6/Z, [X18, #5, MUL VL]

  (3962) 0x53aaf0 LD1D	{Z24.D}, P6/Z, [X18, #7, MUL VL]

  (3962) 0x53aaf4 FMLS	Z30.D, P6/M, Z4.D, Z2.D

  (3962) 0x53aaf8 LD1D	{Z28.D}, P6/Z, [X19, Z3.D,LSL #3]

  (3962) 0x53aafc LD1D	{Z5.D}, P6/Z, [X19, Z22.D,LSL #3]

  (3962) 0x53ab00 FMLS	Z30.D, P6/M, Z28.D, Z20.D

  (3962) 0x53ab04 LD1D	{Z7.D}, P6/Z, [X19, Z6.D,LSL #3]

  (3962) 0x53ab08 FMLS	Z30.D, P6/M, Z5.D, Z1.D

  (3962) 0x53ab0c FMLS	Z14.D, P6/M, Z7.D, Z29.D

  (3962) 0x53ab10 LD1D	{Z21.D}, P6/Z, [X19, Z15.D,LSL #3]

  (3962) 0x53ab14 LD1D	{Z27.D}, P6/Z, [X19, Z26.D,LSL #3]

  (3962) 0x53ab18 LD1D	{Z17.D}, P6/Z, [X19, Z18.D,LSL #3]

  (3962) 0x53ab1c FMLS	Z14.D, P6/M, Z27.D, Z16.D

  (3962) 0x53ab20 LD1D	{Z25.D}, P6/Z, [X19, Z23.D,LSL #3]

  (3962) 0x53ab24 FMLS	Z14.D, P6/M, Z17.D, Z0.D

  (3962) 0x53ab28 ADD	X18, X18, #128

  (3962) 0x53ab2c FMLS	Z30.D, P6/M, Z21.D, Z19.D

  (3962) 0x53ab30 FMLS	Z14.D, P6/M, Z25.D, Z24.D

  (3962) 0x53ab34 CMP	X14, X0

  (3962) 0x53ab38 B.NE	53aaac

0x53ab3c AND	X30, X11, #8062

0x53ab40 FADD	Z14.D, Z14.D, Z30.D

0x53ab44 FADDV	D30, P6, Z14.D

0x53ab48 FADD	D31, D31, D30

0x53ab4c ADD	X2, X2, X30

0x53ab50 ANDS	XZR, X11, #4160

0x53ab54 B.EQ	53abcc

0x53ab58 UBFM	X6, X2, #61, #60

0x53ab5c ADD	X1, X2, #1

0x53ab60 LDR	X5, [X21, X6]

0x53ab64 LDR	D2, [X22, X6]

0x53ab68 LDR	D4, [X19, X5,LSL #3]

0x53ab6c FMSUB	D31, D2, D4, D31

0x53ab70 CMP	X1, X10

0x53ab74 B.GE	53abcc

0x53ab78 ADD	X7, X6, #8

0x53ab7c ADD	X1, X2, #2

0x53ab80 LDR	X4, [X21, X7]

0x53ab84 LDR	D22, [X22, X7]

0x53ab88 LDR	D3, [X19, X4,LSL #3]

0x53ab8c FMSUB	D31, D3, D22, D31

0x53ab90 CMP	X10, X1

0x53ab94 B.LE	53abcc

0x53ab98 ADD	X8, X6, #16

0x53ab9c ADD	X11, X2, #3

0x53aba0 LDR	X3, [X21, X8]

0x53aba4 LDR	D6, [X22, X8]

0x53aba8 LDR	D29, [X19, X3,LSL #3]

0x53abac FMSUB	D31, D29, D6, D31

0x53abb0 CMP	X10, X11

0x53abb4 B.LE	53abcc

0x53abb8 ADD	X10, X6, #24

0x53abbc LDR	X9, [X21, X10]

0x53abc0 LDR	D15, [X22, X10]

0x53abc4 LDR	D26, [X19, X9,LSL #3]

0x53abc8 FMSUB	D31, D26, D15, D31

0x53abcc STR	D31, [X25, X20,LSL #3]

0x53abd0 ADD	X20, X20, #1

0x53abd4 CMP	X23, X20

0x53abd8 B.NE	53a9c4

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 307 - 314

--------------------------------------------------------------------------------

307:             for (i = iBegin; i < iEnd; i++)

308:             {

309:                tempx = b_data[i];

310:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

311:                {

312:                   tempx -= A_data[jj] * x_data[A_j[jj]];

313:                }

314:                y_data[i] = tempx;

Coverage (%)	Name	Source Location	Module
►99.04+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.29
CQA speedup if FP arith vectorized	1.03
CQA speedup if fully vectorized	1.25
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	micro-operation queue,
Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6
Source	csr_matvec.c:307-314
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.25
CQA cycles if no scalar integer	9.50
CQA cycles if FP arith vectorized	11.94
CQA cycles if fully vectorized	9.82
Front-end cycles	12.25
P0 cycles	5.50
P1 cycles	5.50
P2 cycles	6.17
P3 cycles	6.17
P4 cycles	6.17
P5 cycles	6.17
P6 cycles	6.17
P7 cycles	6.17
P8 cycles	4.25
P9 cycles	4.25
P10 cycles	4.25
P11 cycles	4.25
P12 cycles	11.50
P13 cycles	11.17
P14 cycles	11.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	98.00
Nb uops	98.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	3.02
Nb FLOP add-sub	5.00
Nb FLOP mul	0.00
Nb FLOP fma	16.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	33.96
Bytes prefetched	0.00
Bytes loaded	408.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	40.91
Vectorization ratio load	64.29
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	18.18
Vectorization ratio fma	60.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	6.25
Vector-efficiency ratio all	70.55
Vector-efficiency ratio load	82.14
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	59.09
Vector-efficiency ratio fma	80.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	53.52

Metric	Value
CQA speedup if no scalar integer	1.29
CQA speedup if FP arith vectorized	1.03
CQA speedup if fully vectorized	1.25
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	micro-operation queue,
Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6
Source	csr_matvec.c:307-314
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.25
CQA cycles if no scalar integer	9.50
CQA cycles if FP arith vectorized	11.94
CQA cycles if fully vectorized	9.82
Front-end cycles	12.25
P0 cycles	5.50
P1 cycles	5.50
P2 cycles	6.17
P3 cycles	6.17
P4 cycles	6.17
P5 cycles	6.17
P6 cycles	6.17
P7 cycles	6.17
P8 cycles	4.25
P9 cycles	4.25
P10 cycles	4.25
P11 cycles	4.25
P12 cycles	11.50
P13 cycles	11.17
P14 cycles	11.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	98.00
Nb uops	98.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	3.02
Nb FLOP add-sub	5.00
Nb FLOP mul	0.00
Nb FLOP fma	16.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	33.96
Bytes prefetched	0.00
Bytes loaded	408.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	40.91
Vectorization ratio load	64.29
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	18.18
Vectorization ratio fma	60.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	6.25
Vector-efficiency ratio all	70.55
Vector-efficiency ratio load	82.14
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	59.09
Vector-efficiency ratio fma	80.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	53.52

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6
Source file and lines	csr_matvec.c:307-314
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:307-314.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 40 paths individually, rerun with max-paths=40
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 40 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.25 to 9.50 cycles (1.29x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 70% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 12.25 to 9.82 cycles (1.25x speedup).

Details

40% of VPU instructions are used in vector version (process two or more data elements in vector registers):

64% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
18% of VPU addition or subtraction instructions are used in vector version.
60% of VPU fused multiply-add instructions are used in vector version.
6% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 16 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 37 FP arithmetical operations:

21: addition or subtraction (16 inside FMA instructions)
16: multiply (all inside FMA instructions)

The binary loop is loading 408 bytes. The binary loop is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.09 FP operations per loaded or stored byte.

General properties

nb instructions	98
loop length	392
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

12.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	5.50	5.50	6.17	6.17	6.17	6.17	6.17	6.17	4.25	4.25	4.25	4.25	11.50	11.17	11.33	0.00	0.00
cycles	5.50	5.50	6.17	6.17	6.17	6.17	6.17	6.17	4.25	4.25	4.25	4.25	11.50	11.17	11.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.25
Overall L1	12.25

Vectorization ratios

INT

all	35%
load	64%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	61%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	60%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	40%
load	64%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	60%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.25 cycles. At this rate:

34% of peak load performance is reached (33.31 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.65 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 53a9c4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X2, [X24, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
LDR X10, [X13, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D31, [X26, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
CMP X2, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 53abcc <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1368>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X11, X10, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X3, X11, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP X3, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LS 53ab58 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x12f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X9, X11, #2, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, X21, X2,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
DUP Z14.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (6.3%)
ORR Z30.D, Z14.D, Z14.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
UBFM X12, X9, #59, #58	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X18, X22, X2,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SUB X16, X12, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X14, X0, X9,LSL #5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
UBFM X15, X16, #5, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X17, X15, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS X27, X17, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 53aaac <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1248>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X27, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 53aa7c <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1218>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X27, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 53aa54 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x11f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LD1D {Z22.D}, P6/Z, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z23.D}, P6/Z, [X18, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z6.D}, P6/Z, [X0, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z29.D}, P6/Z, [X18, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X18, X18, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z15.D}, P6/Z, [X19, Z22.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z28.D}, P6/Z, [X19, Z6.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
MOVPRFX Z30, Z14	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FMLS Z30.D, P6/M, Z15.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLS Z14.D, P6/M, Z28.D, Z29.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LD1D {Z26.D}, P6/Z, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z20.D}, P6/Z, [X18, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z5.D}, P6/Z, [X0, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z1.D}, P6/Z, [X18, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X18, X18, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z7.D}, P6/Z, [X19, Z26.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z21.D}, P6/Z, [X19, Z5.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLS Z30.D, P6/M, Z7.D, Z20.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLS Z14.D, P6/M, Z21.D, Z1.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LD1D {Z19.D}, P6/Z, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z17.D}, P6/Z, [X0, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z16.D}, P6/Z, [X18, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z25.D}, P6/Z, [X18, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z27.D}, P6/Z, [X19, Z19.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z0.D}, P6/Z, [X19, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X18, X18, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMLS Z30.D, P6/M, Z27.D, Z16.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLS Z14.D, P6/M, Z0.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
CMP X14, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 53ab3c <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x12d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X30, X11, #8062	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
FADD Z14.D, Z14.D, Z30.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FADDV D30, P6, Z14.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	vect (100.0%)
FADD D31, D31, D30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
ADD X2, X2, X30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS XZR, X11, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 53abcc <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1368>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X6, X2, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X5, [X21, X6]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D2, [X22, X6]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D4, [X19, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMSUB D31, D2, D4, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
CMP X1, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 53abcc <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1368>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X7, X6, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, X2, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X4, [X21, X7]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D22, [X22, X7]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D3, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMSUB D31, D3, D22, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
CMP X10, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 53abcc <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1368>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X6, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X11, X2, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X3, [X21, X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D6, [X22, X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D29, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMSUB D31, D29, D6, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
CMP X10, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 53abcc <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1368>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X10, X6, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X9, [X21, X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D15, [X22, X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D26, [X19, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMSUB D31, D26, D15, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D31, [X25, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X20, X20, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP X23, X20	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 53a9c4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6
Source file and lines	csr_matvec.c:307-314
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:307-314.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 40 paths individually, rerun with max-paths=40
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.25 to 9.50 cycles (1.29x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

40% of VPU instructions are used in vector version (process two or more data elements in vector registers):

64% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
18% of VPU addition or subtraction instructions are used in vector version.
60% of VPU fused multiply-add instructions are used in vector version.
6% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 16 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 37 FP arithmetical operations:

21: addition or subtraction (16 inside FMA instructions)
16: multiply (all inside FMA instructions)

The binary loop is loading 408 bytes. The binary loop is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.09 FP operations per loaded or stored byte.

General properties

nb instructions	98
loop length	392
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

12.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	5.50	5.50	6.17	6.17	6.17	6.17	6.17	6.17	4.25	4.25	4.25	4.25	11.50	11.17	11.33	0.00	0.00
cycles	5.50	5.50	6.17	6.17	6.17	6.17	6.17	6.17	4.25	4.25	4.25	4.25	11.50	11.17	11.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.25
Overall L1	12.25

Vectorization ratios

INT

all	35%
load	64%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	61%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	60%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	40%
load	64%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	60%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.25 cycles. At this rate:

34% of peak load performance is reached (33.31 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.65 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 53a9c4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X2, [X24, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
LDR X10, [X13, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D31, [X26, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
CMP X2, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 53abcc <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1368>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X11, X10, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X3, X11, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP X3, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LS 53ab58 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x12f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X9, X11, #2, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, X21, X2,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
DUP Z14.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (6.3%)
ORR Z30.D, Z14.D, Z14.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
UBFM X12, X9, #59, #58	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X18, X22, X2,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SUB X16, X12, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X14, X0, X9,LSL #5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
UBFM X15, X16, #5, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X17, X15, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS X27, X17, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 53aaac <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1248>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X27, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 53aa7c <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1218>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X27, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 53aa54 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x11f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LD1D {Z22.D}, P6/Z, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z23.D}, P6/Z, [X18, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z6.D}, P6/Z, [X0, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z29.D}, P6/Z, [X18, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X18, X18, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z15.D}, P6/Z, [X19, Z22.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z28.D}, P6/Z, [X19, Z6.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
MOVPRFX Z30, Z14	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FMLS Z30.D, P6/M, Z15.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLS Z14.D, P6/M, Z28.D, Z29.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LD1D {Z26.D}, P6/Z, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z20.D}, P6/Z, [X18, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z5.D}, P6/Z, [X0, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z1.D}, P6/Z, [X18, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X18, X18, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z7.D}, P6/Z, [X19, Z26.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z21.D}, P6/Z, [X19, Z5.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLS Z30.D, P6/M, Z7.D, Z20.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLS Z14.D, P6/M, Z21.D, Z1.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LD1D {Z19.D}, P6/Z, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z17.D}, P6/Z, [X0, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z16.D}, P6/Z, [X18, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z25.D}, P6/Z, [X18, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z27.D}, P6/Z, [X19, Z19.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z0.D}, P6/Z, [X19, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X18, X18, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMLS Z30.D, P6/M, Z27.D, Z16.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLS Z14.D, P6/M, Z0.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
CMP X14, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 53ab3c <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x12d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X30, X11, #8062	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
FADD Z14.D, Z14.D, Z30.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FADDV D30, P6, Z14.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	vect (100.0%)
FADD D31, D31, D30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
ADD X2, X2, X30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS XZR, X11, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 53abcc <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1368>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X6, X2, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X5, [X21, X6]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D2, [X22, X6]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D4, [X19, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMSUB D31, D2, D4, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
CMP X1, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 53abcc <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1368>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X7, X6, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, X2, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X4, [X21, X7]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D22, [X22, X7]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D3, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMSUB D31, D3, D22, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
CMP X10, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 53abcc <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1368>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X6, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X11, X2, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X3, [X21, X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D6, [X22, X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D29, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMSUB D31, D29, D6, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
CMP X10, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 53abcc <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1368>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X10, X6, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X9, [X21, X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D15, [X22, X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D26, [X19, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMSUB D31, D26, D15, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D31, [X25, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X20, X20, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP X23, X20	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 53a9c4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code