OV - exec - Loop 3953

	Loop Id: 3953	Module: exec	Source: csr_matvec.c:334-341	Coverage: 1.39%

0x53ae20 LDR	X2, [X24, X20,LSL #3]

0x53ae24 LDR	X30, [X13, X20,LSL #3]

0x53ae28 LDR	D31, [X26, X20,LSL #3]

0x53ae2c CMP	X2, X30

0x53ae30 B.GE	53b028

0x53ae34 SUB	X27, X30, X2

0x53ae38 SUB	X18, X27, #1

0x53ae3c CMP	X18, #3

0x53ae40 B.LS	53afb4

0x53ae44 UBFM	X6, X27, #2, #63

0x53ae48 ADD	X0, X21, X2,LSL #3

0x53ae4c DUP	Z29.D, #0

0x53ae50 ORR	Z15.D, Z29.D, Z29.D

0x53ae54 UBFM	X4, X6, #59, #58

0x53ae58 ADD	X11, X22, X2,LSL #3

0x53ae5c SUB	X7, X4, #32

0x53ae60 ADD	X5, X0, X6,LSL #5

0x53ae64 UBFM	X3, X7, #5, #63

0x53ae68 ADD	X8, X3, #1

0x53ae6c ANDS	X10, X8, #4160

0x53ae70 B.EQ	53af08

0x53ae74 CMP	X10, #1

0x53ae78 B.EQ	53aed8

0x53ae7c CMP	X10, #2

0x53ae80 B.EQ	53aeb0

0x53ae84 LD1D	{Z20.D}, P4/Z, [X0, MUL VL]

0x53ae88 LD1D	{Z1.D}, P4/Z, [X11, MUL VL]

0x53ae8c LD1D	{Z5.D}, P4/Z, [X0, #1, MUL VL]

0x53ae90 LD1D	{Z19.D}, P4/Z, [X11, #1, MUL VL]

0x53ae94 ADD	X0, X0, #32

0x53ae98 ADD	X11, X11, #32

0x53ae9c LD1D	{Z21.D}, P4/Z, [X19, Z20.D,LSL #3]

0x53aea0 LD1D	{Z3.D}, P4/Z, [X19, Z5.D,LSL #3]

0x53aea4 MOVPRFX	Z15, Z29

0x53aea8 FMLA	Z15.D, P4/M, Z21.D, Z1.D

0x53aeac FMLA	Z29.D, P4/M, Z3.D, Z19.D

0x53aeb0 LD1D	{Z24.D}, P4/Z, [X0, MUL VL]

0x53aeb4 LD1D	{Z7.D}, P4/Z, [X11, MUL VL]

0x53aeb8 LD1D	{Z16.D}, P4/Z, [X0, #1, MUL VL]

0x53aebc LD1D	{Z27.D}, P4/Z, [X11, #1, MUL VL]

0x53aec0 ADD	X0, X0, #32

0x53aec4 ADD	X11, X11, #32

0x53aec8 LD1D	{Z0.D}, P4/Z, [X19, Z24.D,LSL #3]

0x53aecc LD1D	{Z18.D}, P4/Z, [X19, Z16.D,LSL #3]

0x53aed0 FMLA	Z15.D, P4/M, Z0.D, Z7.D

0x53aed4 FMLA	Z29.D, P4/M, Z18.D, Z27.D

0x53aed8 LD1D	{Z4.D}, P4/Z, [X0, MUL VL]

0x53aedc LD1D	{Z17.D}, P4/Z, [X0, #1, MUL VL]

0x53aee0 ADD	X0, X0, #32

0x53aee4 LD1D	{Z22.D}, P4/Z, [X11, MUL VL]

0x53aee8 LD1D	{Z2.D}, P4/Z, [X11, #1, MUL VL]

0x53aeec LD1D	{Z14.D}, P4/Z, [X19, Z4.D,LSL #3]

0x53aef0 LD1D	{Z6.D}, P4/Z, [X19, Z17.D,LSL #3]

0x53aef4 ADD	X11, X11, #32

0x53aef8 FMLA	Z15.D, P4/M, Z14.D, Z22.D

0x53aefc FMLA	Z29.D, P4/M, Z6.D, Z2.D

0x53af00 CMP	X5, X0

0x53af04 B.EQ	53af98

  (3954) 0x53af08 LD1D	{Z23.D}, P4/Z, [X0, MUL VL]

  (3954) 0x53af0c LD1D	{Z30.D}, P4/Z, [X0, #2, MUL VL]

  (3954) 0x53af10 LD1D	{Z20.D}, P4/Z, [X0, #4, MUL VL]

  (3954) 0x53af14 LD1D	{Z1.D}, P4/Z, [X0, #1, MUL VL]

  (3954) 0x53af18 LD1D	{Z21.D}, P4/Z, [X0, #6, MUL VL]

  (3954) 0x53af1c LD1D	{Z7.D}, P4/Z, [X0, #3, MUL VL]

  (3954) 0x53af20 LD1D	{Z16.D}, P4/Z, [X0, #5, MUL VL]

  (3954) 0x53af24 LD1D	{Z0.D}, P4/Z, [X0, #7, MUL VL]

  (3954) 0x53af28 ADD	X0, X0, #128

  (3954) 0x53af2c LD1D	{Z28.D}, P4/Z, [X11, MUL VL]

  (3954) 0x53af30 LD1D	{Z26.D}, P4/Z, [X19, Z23.D,LSL #3]

  (3954) 0x53af34 LD1D	{Z5.D}, P4/Z, [X11, #1, MUL VL]

  (3954) 0x53af38 LD1D	{Z3.D}, P4/Z, [X11, #2, MUL VL]

  (3954) 0x53af3c LD1D	{Z24.D}, P4/Z, [X11, #4, MUL VL]

  (3954) 0x53af40 LD1D	{Z4.D}, P4/Z, [X11, #6, MUL VL]

  (3954) 0x53af44 LD1D	{Z22.D}, P4/Z, [X11, #3, MUL VL]

  (3954) 0x53af48 LD1D	{Z6.D}, P4/Z, [X11, #5, MUL VL]

  (3954) 0x53af4c LD1D	{Z23.D}, P4/Z, [X11, #7, MUL VL]

  (3954) 0x53af50 FMLA	Z15.D, P4/M, Z26.D, Z28.D

  (3954) 0x53af54 LD1D	{Z25.D}, P4/Z, [X19, Z30.D,LSL #3]

  (3954) 0x53af58 LD1D	{Z19.D}, P4/Z, [X19, Z20.D,LSL #3]

  (3954) 0x53af5c FMLA	Z15.D, P4/M, Z25.D, Z3.D

  (3954) 0x53af60 LD1D	{Z27.D}, P4/Z, [X19, Z1.D,LSL #3]

  (3954) 0x53af64 FMLA	Z15.D, P4/M, Z19.D, Z24.D

  (3954) 0x53af68 FMLA	Z29.D, P4/M, Z27.D, Z5.D

  (3954) 0x53af6c LD1D	{Z18.D}, P4/Z, [X19, Z21.D,LSL #3]

  (3954) 0x53af70 LD1D	{Z14.D}, P4/Z, [X19, Z7.D,LSL #3]

  (3954) 0x53af74 LD1D	{Z17.D}, P4/Z, [X19, Z16.D,LSL #3]

  (3954) 0x53af78 FMLA	Z29.D, P4/M, Z14.D, Z22.D

  (3954) 0x53af7c LD1D	{Z2.D}, P4/Z, [X19, Z0.D,LSL #3]

  (3954) 0x53af80 FMLA	Z29.D, P4/M, Z17.D, Z6.D

  (3954) 0x53af84 ADD	X11, X11, #128

  (3954) 0x53af88 FMLA	Z15.D, P4/M, Z18.D, Z4.D

  (3954) 0x53af8c FMLA	Z29.D, P4/M, Z2.D, Z23.D

  (3954) 0x53af90 CMP	X5, X0

  (3954) 0x53af94 B.NE	53af08

0x53af98 AND	X9, X27, #8062

0x53af9c FADD	Z29.D, Z29.D, Z15.D

0x53afa0 FADDV	D15, P4, Z29.D

0x53afa4 FADD	D31, D31, D15

0x53afa8 ADD	X2, X2, X9

0x53afac ANDS	XZR, X27, #4160

0x53afb0 B.EQ	53b028

0x53afb4 UBFM	X12, X2, #61, #60

0x53afb8 ADD	X1, X2, #1

0x53afbc LDR	X16, [X21, X12]

0x53afc0 LDR	D28, [X22, X12]

0x53afc4 LDR	D26, [X19, X16,LSL #3]

0x53afc8 FMADD	D31, D28, D26, D31

0x53afcc CMP	X1, X30

0x53afd0 B.GE	53b028

0x53afd4 ADD	X14, X12, #8

0x53afd8 ADD	X1, X2, #2

0x53afdc LDR	X15, [X21, X14]

0x53afe0 LDR	D30, [X22, X14]

0x53afe4 LDR	D20, [X19, X15,LSL #3]

0x53afe8 FMADD	D31, D30, D20, D31

0x53afec CMP	X30, X1

0x53aff0 B.LE	53b028

0x53aff4 ADD	X17, X12, #16

0x53aff8 ADD	X27, X2, #3

0x53affc LDR	X18, [X21, X17]

0x53b000 LDR	D1, [X22, X17]

0x53b004 LDR	D5, [X19, X18,LSL #3]

0x53b008 FMADD	D31, D1, D5, D31

0x53b00c CMP	X30, X27

0x53b010 B.LE	53b028

0x53b014 ADD	X30, X12, #24

0x53b018 LDR	X6, [X21, X30]

0x53b01c LDR	D21, [X22, X30]

0x53b020 LDR	D7, [X19, X6,LSL #3]

0x53b024 FMADD	D31, D7, D21, D31

0x53b028 STR	D31, [X25, X20,LSL #3]

0x53b02c ADD	X20, X20, #1

0x53b030 CMP	X23, X20

0x53b034 B.NE	53ae20

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 334 - 341

--------------------------------------------------------------------------------

334:             for (i = iBegin; i < iEnd; i++)

335:             {

336:                tempx = b_data[i];

337:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

338:                {

339:                   tempx += A_data[jj] * x_data[A_j[jj]];

340:                }

341:                y_data[i] = tempx;

Coverage (%)	Name	Source Location	Module
►99.06+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.29
CQA speedup if FP arith vectorized	1.03
CQA speedup if fully vectorized	1.25
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	micro-operation queue,
Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6
Source	csr_matvec.c:334-341
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.25
CQA cycles if no scalar integer	9.50
CQA cycles if FP arith vectorized	11.94
CQA cycles if fully vectorized	9.82
Front-end cycles	12.25
P0 cycles	5.50
P1 cycles	5.50
P2 cycles	6.17
P3 cycles	6.17
P4 cycles	6.17
P5 cycles	6.17
P6 cycles	6.17
P7 cycles	6.17
P8 cycles	4.25
P9 cycles	4.25
P10 cycles	4.25
P11 cycles	4.25
P12 cycles	11.50
P13 cycles	11.17
P14 cycles	11.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	98.00
Nb uops	98.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	3.02
Nb FLOP add-sub	5.00
Nb FLOP mul	0.00
Nb FLOP fma	16.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	33.96
Bytes prefetched	0.00
Bytes loaded	408.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	40.91
Vectorization ratio load	64.29
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	18.18
Vectorization ratio fma	60.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	6.25
Vector-efficiency ratio all	70.55
Vector-efficiency ratio load	82.14
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	59.09
Vector-efficiency ratio fma	80.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	53.52

Metric	Value
CQA speedup if no scalar integer	1.29
CQA speedup if FP arith vectorized	1.03
CQA speedup if fully vectorized	1.25
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	micro-operation queue,
Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6
Source	csr_matvec.c:334-341
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.25
CQA cycles if no scalar integer	9.50
CQA cycles if FP arith vectorized	11.94
CQA cycles if fully vectorized	9.82
Front-end cycles	12.25
P0 cycles	5.50
P1 cycles	5.50
P2 cycles	6.17
P3 cycles	6.17
P4 cycles	6.17
P5 cycles	6.17
P6 cycles	6.17
P7 cycles	6.17
P8 cycles	4.25
P9 cycles	4.25
P10 cycles	4.25
P11 cycles	4.25
P12 cycles	11.50
P13 cycles	11.17
P14 cycles	11.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	98.00
Nb uops	98.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	3.02
Nb FLOP add-sub	5.00
Nb FLOP mul	0.00
Nb FLOP fma	16.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	33.96
Bytes prefetched	0.00
Bytes loaded	408.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	40.91
Vectorization ratio load	64.29
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	18.18
Vectorization ratio fma	60.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	6.25
Vector-efficiency ratio all	70.55
Vector-efficiency ratio load	82.14
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	59.09
Vector-efficiency ratio fma	80.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	53.52

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6
Source file and lines	csr_matvec.c:334-341
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:334-341.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 40 paths individually, rerun with max-paths=40
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 40 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.25 to 9.50 cycles (1.29x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 70% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 12.25 to 9.82 cycles (1.25x speedup).

Details

40% of VPU instructions are used in vector version (process two or more data elements in vector registers):

64% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
18% of VPU addition or subtraction instructions are used in vector version.
60% of VPU fused multiply-add instructions are used in vector version.
6% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 16 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 37 FP arithmetical operations:

21: addition or subtraction (16 inside FMA instructions)
16: multiply (all inside FMA instructions)

The binary loop is loading 408 bytes. The binary loop is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.09 FP operations per loaded or stored byte.

General properties

nb instructions	98
loop length	392
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

12.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	5.50	5.50	6.17	6.17	6.17	6.17	6.17	6.17	4.25	4.25	4.25	4.25	11.50	11.17	11.33	0.00	0.00
cycles	5.50	5.50	6.17	6.17	6.17	6.17	6.17	6.17	4.25	4.25	4.25	4.25	11.50	11.17	11.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.25
Overall L1	12.25

Vectorization ratios

INT

all	35%
load	64%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	61%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	60%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	40%
load	64%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	60%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.25 cycles. At this rate:

34% of peak load performance is reached (33.31 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.65 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 53ae20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X2, [X24, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
LDR X30, [X13, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D31, [X26, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
CMP X2, X30	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 53b028 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x17c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X27, X30, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X18, X27, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP X18, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LS 53afb4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1750>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X6, X27, #2, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, X21, X2,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
DUP Z29.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (6.3%)
ORR Z15.D, Z29.D, Z29.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
UBFM X4, X6, #59, #58	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X11, X22, X2,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SUB X7, X4, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X5, X0, X6,LSL #5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
UBFM X3, X7, #5, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X8, X3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS X10, X8, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 53af08 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x16a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 53aed8 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1674>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 53aeb0 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x164c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LD1D {Z20.D}, P4/Z, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z1.D}, P4/Z, [X11, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z5.D}, P4/Z, [X0, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z19.D}, P4/Z, [X11, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X11, X11, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z21.D}, P4/Z, [X19, Z20.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z3.D}, P4/Z, [X19, Z5.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
MOVPRFX Z15, Z29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FMLA Z15.D, P4/M, Z21.D, Z1.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA Z29.D, P4/M, Z3.D, Z19.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LD1D {Z24.D}, P4/Z, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z7.D}, P4/Z, [X11, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z16.D}, P4/Z, [X0, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z27.D}, P4/Z, [X11, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X11, X11, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z0.D}, P4/Z, [X19, Z24.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z18.D}, P4/Z, [X19, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA Z15.D, P4/M, Z0.D, Z7.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA Z29.D, P4/M, Z18.D, Z27.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LD1D {Z4.D}, P4/Z, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z17.D}, P4/Z, [X0, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z22.D}, P4/Z, [X11, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z2.D}, P4/Z, [X11, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z14.D}, P4/Z, [X19, Z4.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z6.D}, P4/Z, [X19, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X11, X11, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMLA Z15.D, P4/M, Z14.D, Z22.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA Z29.D, P4/M, Z6.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
CMP X5, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 53af98 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1734>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X9, X27, #8062	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
FADD Z29.D, Z29.D, Z15.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FADDV D15, P4, Z29.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	vect (100.0%)
FADD D31, D31, D15	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
ADD X2, X2, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS XZR, X27, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 53b028 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x17c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X12, X2, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X16, [X21, X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D28, [X22, X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D26, [X19, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D31, D28, D26, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
CMP X1, X30	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 53b028 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x17c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X14, X12, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, X2, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X15, [X21, X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D30, [X22, X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D20, [X19, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D31, D30, D20, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
CMP X30, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 53b028 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x17c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X17, X12, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X27, X2, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X18, [X21, X17]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D1, [X22, X17]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D5, [X19, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D31, D1, D5, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
CMP X30, X27	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 53b028 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x17c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X30, X12, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X6, [X21, X30]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D21, [X22, X30]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D7, [X19, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D31, D7, D21, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D31, [X25, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X20, X20, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP X23, X20	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 53ae20 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x15bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6
Source file and lines	csr_matvec.c:334-341
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:334-341.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 40 paths individually, rerun with max-paths=40
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.25 to 9.50 cycles (1.29x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

40% of VPU instructions are used in vector version (process two or more data elements in vector registers):

64% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
18% of VPU addition or subtraction instructions are used in vector version.
60% of VPU fused multiply-add instructions are used in vector version.
6% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 16 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 37 FP arithmetical operations:

21: addition or subtraction (16 inside FMA instructions)
16: multiply (all inside FMA instructions)

The binary loop is loading 408 bytes. The binary loop is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.09 FP operations per loaded or stored byte.

General properties

nb instructions	98
loop length	392
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

12.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	5.50	5.50	6.17	6.17	6.17	6.17	6.17	6.17	4.25	4.25	4.25	4.25	11.50	11.17	11.33	0.00	0.00
cycles	5.50	5.50	6.17	6.17	6.17	6.17	6.17	6.17	4.25	4.25	4.25	4.25	11.50	11.17	11.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.25
Overall L1	12.25

Vectorization ratios

INT

all	35%
load	64%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	61%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	60%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	40%
load	64%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	60%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.25 cycles. At this rate:

34% of peak load performance is reached (33.31 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.65 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 53ae20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X2, [X24, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
LDR X30, [X13, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D31, [X26, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
CMP X2, X30	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 53b028 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x17c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X27, X30, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X18, X27, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP X18, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LS 53afb4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1750>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X6, X27, #2, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, X21, X2,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
DUP Z29.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (6.3%)
ORR Z15.D, Z29.D, Z29.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
UBFM X4, X6, #59, #58	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X11, X22, X2,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SUB X7, X4, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X5, X0, X6,LSL #5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
UBFM X3, X7, #5, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X8, X3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS X10, X8, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 53af08 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x16a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 53aed8 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1674>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 53aeb0 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x164c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LD1D {Z20.D}, P4/Z, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z1.D}, P4/Z, [X11, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z5.D}, P4/Z, [X0, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z19.D}, P4/Z, [X11, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X11, X11, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z21.D}, P4/Z, [X19, Z20.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z3.D}, P4/Z, [X19, Z5.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
MOVPRFX Z15, Z29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FMLA Z15.D, P4/M, Z21.D, Z1.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA Z29.D, P4/M, Z3.D, Z19.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LD1D {Z24.D}, P4/Z, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z7.D}, P4/Z, [X11, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z16.D}, P4/Z, [X0, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z27.D}, P4/Z, [X11, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X11, X11, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z0.D}, P4/Z, [X19, Z24.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z18.D}, P4/Z, [X19, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA Z15.D, P4/M, Z0.D, Z7.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA Z29.D, P4/M, Z18.D, Z27.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LD1D {Z4.D}, P4/Z, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z17.D}, P4/Z, [X0, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z22.D}, P4/Z, [X11, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z2.D}, P4/Z, [X11, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z14.D}, P4/Z, [X19, Z4.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z6.D}, P4/Z, [X19, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X11, X11, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMLA Z15.D, P4/M, Z14.D, Z22.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA Z29.D, P4/M, Z6.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
CMP X5, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 53af98 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1734>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X9, X27, #8062	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
FADD Z29.D, Z29.D, Z15.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FADDV D15, P4, Z29.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	vect (100.0%)
FADD D31, D31, D15	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
ADD X2, X2, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS XZR, X27, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 53b028 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x17c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X12, X2, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X16, [X21, X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D28, [X22, X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D26, [X19, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D31, D28, D26, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
CMP X1, X30	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 53b028 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x17c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X14, X12, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, X2, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X15, [X21, X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D30, [X22, X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D20, [X19, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D31, D30, D20, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
CMP X30, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 53b028 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x17c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X17, X12, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X27, X2, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X18, [X21, X17]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D1, [X22, X17]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D5, [X19, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D31, D1, D5, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
CMP X30, X27	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 53b028 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x17c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X30, X12, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X6, [X21, X30]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D21, [X22, X30]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D7, [X19, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D31, D7, D21, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D31, [X25, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X20, X20, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP X23, X20	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 53ae20 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x15bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code