OV - exec - Loop 3944

	Loop Id: 3944	Module: exec	Source: csr_matvec.c:256-263	Coverage: 5.35%

0x539b80 SUB	X5, X8, X7

0x539b84 SUB	X4, X5, #1

0x539b88 CMP	X4, #3

0x539b8c B.LS	53a99c

0x539b90 UBFM	X0, X5, #2, #63

0x539b94 ADD	X1, X21, X7,LSL #3

0x539b98 DUP	Z29.D, #0

0x539b9c ORR	Z31.D, Z29.D, Z29.D

0x539ba0 UBFM	X11, X0, #59, #58

0x539ba4 ADD	X12, X22, X7,LSL #3

0x539ba8 SUB	X10, X11, #32

0x539bac ADD	X9, X1, X0,LSL #5

0x539bb0 UBFM	X3, X10, #5, #63

0x539bb4 ADD	X16, X3, #1

0x539bb8 ANDS	X14, X16, #4160

0x539bbc B.EQ	539c54

0x539bc0 CMP	X14, #1

0x539bc4 B.EQ	539c24

0x539bc8 CMP	X14, #2

0x539bcc B.EQ	539bfc

0x539bd0 LD1D	{Z0.D}, P2/Z, [X1, MUL VL]

0x539bd4 LD1D	{Z15.D}, P2/Z, [X12, MUL VL]

0x539bd8 LD1D	{Z4.D}, P2/Z, [X1, #1, MUL VL]

0x539bdc LD1D	{Z28.D}, P2/Z, [X12, #1, MUL VL]

0x539be0 ADD	X1, X1, #32

0x539be4 ADD	X12, X12, #32

0x539be8 LD1D	{Z25.D}, P2/Z, [X19, Z0.D,LSL #3]

0x539bec LD1D	{Z3.D}, P2/Z, [X19, Z4.D,LSL #3]

0x539bf0 MOVPRFX	Z31, Z29

0x539bf4 FMLA	Z31.D, P2/M, Z25.D, Z15.D

0x539bf8 FMLA	Z29.D, P2/M, Z3.D, Z28.D

0x539bfc LD1D	{Z23.D}, P2/Z, [X1, MUL VL]

0x539c00 LD1D	{Z20.D}, P2/Z, [X12, MUL VL]

0x539c04 LD1D	{Z26.D}, P2/Z, [X1, #1, MUL VL]

0x539c08 LD1D	{Z1.D}, P2/Z, [X12, #1, MUL VL]

0x539c0c ADD	X1, X1, #32

0x539c10 ADD	X12, X12, #32

0x539c14 LD1D	{Z18.D}, P2/Z, [X19, Z23.D,LSL #3]

0x539c18 LD1D	{Z21.D}, P2/Z, [X19, Z26.D,LSL #3]

0x539c1c FMLA	Z31.D, P2/M, Z18.D, Z20.D

0x539c20 FMLA	Z29.D, P2/M, Z21.D, Z1.D

0x539c24 LD1D	{Z7.D}, P2/Z, [X1, MUL VL]

0x539c28 LD1D	{Z16.D}, P2/Z, [X1, #1, MUL VL]

0x539c2c ADD	X1, X1, #32

0x539c30 LD1D	{Z6.D}, P2/Z, [X12, MUL VL]

0x539c34 LD1D	{Z19.D}, P2/Z, [X12, #1, MUL VL]

0x539c38 LD1D	{Z14.D}, P2/Z, [X19, Z7.D,LSL #3]

0x539c3c LD1D	{Z17.D}, P2/Z, [X19, Z16.D,LSL #3]

0x539c40 ADD	X12, X12, #32

0x539c44 FMLA	Z31.D, P2/M, Z14.D, Z6.D

0x539c48 FMLA	Z29.D, P2/M, Z17.D, Z19.D

0x539c4c CMP	X9, X1

0x539c50 B.EQ	539ce4

  (3945) 0x539c54 LD1D	{Z24.D}, P2/Z, [X1, MUL VL]

  (3945) 0x539c58 LD1D	{Z30.D}, P2/Z, [X1, #2, MUL VL]

  (3945) 0x539c5c LD1D	{Z15.D}, P2/Z, [X1, #4, MUL VL]

  (3945) 0x539c60 LD1D	{Z5.D}, P2/Z, [X1, #1, MUL VL]

  (3945) 0x539c64 LD1D	{Z20.D}, P2/Z, [X1, #6, MUL VL]

  (3945) 0x539c68 LD1D	{Z0.D}, P2/Z, [X1, #3, MUL VL]

  (3945) 0x539c6c LD1D	{Z26.D}, P2/Z, [X1, #5, MUL VL]

  (3945) 0x539c70 LD1D	{Z23.D}, P2/Z, [X1, #7, MUL VL]

  (3945) 0x539c74 ADD	X1, X1, #128

  (3945) 0x539c78 LD1D	{Z22.D}, P2/Z, [X12, MUL VL]

  (3945) 0x539c7c LD1D	{Z27.D}, P2/Z, [X12, #1, MUL VL]

  (3945) 0x539c80 LD1D	{Z28.D}, P2/Z, [X12, #2, MUL VL]

  (3945) 0x539c84 LD1D	{Z3.D}, P2/Z, [X12, #4, MUL VL]

  (3945) 0x539c88 LD1D	{Z21.D}, P2/Z, [X12, #6, MUL VL]

  (3945) 0x539c8c LD1D	{Z16.D}, P2/Z, [X12, #3, MUL VL]

  (3945) 0x539c90 LD1D	{Z6.D}, P2/Z, [X12, #5, MUL VL]

  (3945) 0x539c94 LD1D	{Z19.D}, P2/Z, [X12, #7, MUL VL]

  (3945) 0x539c98 LD1D	{Z2.D}, P2/Z, [X19, Z24.D,LSL #3]

  (3945) 0x539c9c LD1D	{Z4.D}, P2/Z, [X19, Z30.D,LSL #3]

  (3945) 0x539ca0 FMLA	Z31.D, P2/M, Z2.D, Z22.D

  (3945) 0x539ca4 LD1D	{Z25.D}, P2/Z, [X19, Z15.D,LSL #3]

  (3945) 0x539ca8 FMLA	Z31.D, P2/M, Z4.D, Z28.D

  (3945) 0x539cac LD1D	{Z1.D}, P2/Z, [X19, Z5.D,LSL #3]

  (3945) 0x539cb0 FMLA	Z31.D, P2/M, Z25.D, Z3.D

  (3945) 0x539cb4 FMLA	Z29.D, P2/M, Z1.D, Z27.D

  (3945) 0x539cb8 LD1D	{Z18.D}, P2/Z, [X19, Z20.D,LSL #3]

  (3945) 0x539cbc LD1D	{Z7.D}, P2/Z, [X19, Z0.D,LSL #3]

  (3945) 0x539cc0 LD1D	{Z14.D}, P2/Z, [X19, Z26.D,LSL #3]

  (3945) 0x539cc4 FMLA	Z29.D, P2/M, Z7.D, Z16.D

  (3945) 0x539cc8 LD1D	{Z17.D}, P2/Z, [X19, Z23.D,LSL #3]

  (3945) 0x539ccc FMLA	Z29.D, P2/M, Z14.D, Z6.D

  (3945) 0x539cd0 ADD	X12, X12, #128

  (3945) 0x539cd4 FMLA	Z31.D, P2/M, Z18.D, Z21.D

  (3945) 0x539cd8 FMLA	Z29.D, P2/M, Z17.D, Z19.D

  (3945) 0x539cdc CMP	X9, X1

  (3945) 0x539ce0 B.NE	539c54

0x539ce4 FADD	Z29.D, Z29.D, Z31.D

0x539ce8 FADDV	D31, P2, Z29.D

0x539cec ANDS	XZR, X5, #4160

0x539cf0 B.EQ	539d70

0x539cf4 AND	X15, X5, #8062

0x539cf8 ADD	X7, X7, X15

0x539cfc UBFM	X13, X7, #61, #60

0x539d00 ADD	X17, X7, #1

0x539d04 LDR	X2, [X21, X13]

0x539d08 LDR	D24, [X22, X13]

0x539d0c LDR	D22, [X19, X2,LSL #3]

0x539d10 FMADD	D31, D24, D22, D31

0x539d14 CMP	X17, X8

0x539d18 B.GE	539d70

0x539d1c ADD	X27, X13, #8

0x539d20 ADD	X1, X7, #2

0x539d24 LDR	X18, [X21, X27]

0x539d28 LDR	D30, [X22, X27]

0x539d2c LDR	D2, [X19, X18,LSL #3]

0x539d30 FMADD	D31, D30, D2, D31

0x539d34 CMP	X1, X8

0x539d38 B.GE	539d70

0x539d3c ADD	X30, X13, #16

0x539d40 ADD	X6, X7, #3

0x539d44 LDR	X7, [X21, X30]

0x539d48 LDR	D15, [X22, X30]

0x539d4c LDR	D5, [X19, X7,LSL #3]

0x539d50 FMADD	D31, D15, D5, D31

0x539d54 CMP	X6, X8

0x539d58 B.GE	539d70

0x539d5c ADD	X8, X13, #24

0x539d60 LDR	X5, [X21, X8]

0x539d64 LDR	D27, [X22, X8]

0x539d68 LDR	D20, [X19, X5,LSL #3]

0x539d6c FMADD	D31, D20, D27, D31

0x539d70 STR	D31, [X25, X20,LSL #3]

0x539d74 ADD	X20, X20, #1

0x539d78 CMP	X23, X20

0x539d7c B.EQ	539b30

0x539d80 LDR	X7, [X24, X20,LSL #3]

0x539d84 LDR	X8, [X26, X20,LSL #3]

0x539d88 CMP	X7, X8

0x539d8c B.LT	539b80

0x53a99c MOVI	D31, #0

0x53a9a0 B	539cfc

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 256 - 263

--------------------------------------------------------------------------------

256:             for (i = iBegin; i < iEnd; i++)

257:             {

258:                tempx = 0.0;

259:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

260:                {

261:                   tempx += A_data[jj] * x_data[A_j[jj]];

262:                }

263:                y_data[i] = tempx;

Coverage (%)	Name	Source Location	Module
►99.13+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.20
CQA speedup if FP arith vectorized	1.02
CQA speedup if fully vectorized	1.22
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.10
Bottlenecks	micro-operation queue,
Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6
Source	csr_matvec.c:256-263
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.25
CQA cycles if no scalar integer	10.17
CQA cycles if FP arith vectorized	12.00
CQA cycles if fully vectorized	10.07
Front-end cycles	12.25
P0 cycles	6.00
P1 cycles	6.00
P2 cycles	6.17
P3 cycles	6.17
P4 cycles	6.17
P5 cycles	6.17
P6 cycles	6.17
P7 cycles	6.17
P8 cycles	4.25
P9 cycles	4.25
P10 cycles	4.25
P11 cycles	4.25
P12 cycles	11.17
P13 cycles	10.83
P14 cycles	11.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	98.00
Nb uops	98.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	2.94
Nb FLOP add-sub	4.00
Nb FLOP mul	0.00
Nb FLOP fma	16.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	33.31
Bytes prefetched	0.00
Bytes loaded	400.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	42.86
Vectorization ratio load	69.23
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	25.00
Vectorization ratio fma	60.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	5.56
Vector-efficiency ratio all	71.53
Vector-efficiency ratio load	84.62
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	62.50
Vector-efficiency ratio fma	80.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	53.13

Metric	Value
CQA speedup if no scalar integer	1.20
CQA speedup if FP arith vectorized	1.02
CQA speedup if fully vectorized	1.22
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.10
Bottlenecks	micro-operation queue,
Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6
Source	csr_matvec.c:256-263
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.25
CQA cycles if no scalar integer	10.17
CQA cycles if FP arith vectorized	12.00
CQA cycles if fully vectorized	10.07
Front-end cycles	12.25
P0 cycles	6.00
P1 cycles	6.00
P2 cycles	6.17
P3 cycles	6.17
P4 cycles	6.17
P5 cycles	6.17
P6 cycles	6.17
P7 cycles	6.17
P8 cycles	4.25
P9 cycles	4.25
P10 cycles	4.25
P11 cycles	4.25
P12 cycles	11.17
P13 cycles	10.83
P14 cycles	11.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	98.00
Nb uops	98.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	2.94
Nb FLOP add-sub	4.00
Nb FLOP mul	0.00
Nb FLOP fma	16.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	33.31
Bytes prefetched	0.00
Bytes loaded	400.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	42.86
Vectorization ratio load	69.23
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	25.00
Vectorization ratio fma	60.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	5.56
Vector-efficiency ratio all	71.53
Vector-efficiency ratio load	84.62
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	62.50
Vector-efficiency ratio fma	80.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	53.13

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6
Source file and lines	csr_matvec.c:256-263
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:256-263.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.25 to 10.17 cycles (1.20x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 71% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 12.25 to 10.07 cycles (1.22x speedup).

Details

42% of VPU instructions are used in vector version (process two or more data elements in vector registers):

69% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
25% of VPU addition or subtraction instructions are used in vector version.
60% of VPU fused multiply-add instructions are used in vector version.
5% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 16 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 36 FP arithmetical operations:

20: addition or subtraction (16 inside FMA instructions)
16: multiply (all inside FMA instructions)

The binary loop is loading 400 bytes. The binary loop is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.09 FP operations per loaded or stored byte.

General properties

nb instructions	98
loop length	392
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

12.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	6.00	6.00	6.17	6.17	6.17	6.17	6.17	6.17	4.25	4.25	4.25	4.25	11.17	10.83	11.00	0.00	0.00
cycles	6.00	6.00	6.17	6.17	6.17	6.17	6.17	6.17	4.25	4.25	4.25	4.25	11.17	10.83	11.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.25
Overall L1	12.25

Vectorization ratios

INT

all	37%
load	69%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	5%

all	66%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	60%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	42%
load	69%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	60%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	5%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.25 cycles. At this rate:

34% of peak load performance is reached (32.65 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.65 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 539d70

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB X5, X8, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X5, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X4, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LS 53a99c <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1138>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X0, X5, #2, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X1, X21, X7,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
DUP Z29.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (6.3%)
ORR Z31.D, Z29.D, Z29.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
UBFM X11, X0, #59, #58	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X12, X22, X7,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SUB X10, X11, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X9, X1, X0,LSL #5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
UBFM X3, X10, #5, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X16, X3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS X14, X16, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 539c54 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x3f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 539c24 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x3c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 539bfc <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x398>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LD1D {Z0.D}, P2/Z, [X1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z15.D}, P2/Z, [X12, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z4.D}, P2/Z, [X1, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z28.D}, P2/Z, [X12, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X1, X1, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X12, X12, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z25.D}, P2/Z, [X19, Z0.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z3.D}, P2/Z, [X19, Z4.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
MOVPRFX Z31, Z29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FMLA Z31.D, P2/M, Z25.D, Z15.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA Z29.D, P2/M, Z3.D, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LD1D {Z23.D}, P2/Z, [X1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z20.D}, P2/Z, [X12, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z26.D}, P2/Z, [X1, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z1.D}, P2/Z, [X12, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X1, X1, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X12, X12, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z18.D}, P2/Z, [X19, Z23.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z21.D}, P2/Z, [X19, Z26.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA Z31.D, P2/M, Z18.D, Z20.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA Z29.D, P2/M, Z21.D, Z1.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LD1D {Z7.D}, P2/Z, [X1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z16.D}, P2/Z, [X1, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X1, X1, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z6.D}, P2/Z, [X12, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z19.D}, P2/Z, [X12, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z14.D}, P2/Z, [X19, Z7.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z17.D}, P2/Z, [X19, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X12, X12, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMLA Z31.D, P2/M, Z14.D, Z6.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA Z29.D, P2/M, Z17.D, Z19.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
CMP X9, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 539ce4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x480>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FADD Z29.D, Z29.D, Z31.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FADDV D31, P2, Z29.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	vect (100.0%)
ANDS XZR, X5, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 539d70 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x50c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X15, X5, #8062	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X7, X7, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X13, X7, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X17, X7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X2, [X21, X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D24, [X22, X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D22, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D31, D24, D22, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
CMP X17, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 539d70 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x50c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X27, X13, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, X7, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X18, [X21, X27]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D30, [X22, X27]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D2, [X19, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D31, D30, D2, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
CMP X1, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 539d70 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x50c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X30, X13, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, X7, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X7, [X21, X30]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D15, [X22, X30]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D5, [X19, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D31, D15, D5, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
CMP X6, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 539d70 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x50c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X13, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X5, [X21, X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D27, [X22, X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D20, [X19, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D31, D20, D27, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D31, [X25, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X20, X20, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP X23, X20	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 539b30 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X7, [X24, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X8, [X26, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X7, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 539b80 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x31c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVI D31, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
B 539cfc <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x498>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6
Source file and lines	csr_matvec.c:256-263
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:256-263.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

42% of VPU instructions are used in vector version (process two or more data elements in vector registers):

69% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
25% of VPU addition or subtraction instructions are used in vector version.
60% of VPU fused multiply-add instructions are used in vector version.
5% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 16 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 36 FP arithmetical operations:

20: addition or subtraction (16 inside FMA instructions)
16: multiply (all inside FMA instructions)

The binary loop is loading 400 bytes. The binary loop is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.09 FP operations per loaded or stored byte.

General properties

nb instructions	98
loop length	392
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

12.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	6.00	6.00	6.17	6.17	6.17	6.17	6.17	6.17	4.25	4.25	4.25	4.25	11.17	10.83	11.00	0.00	0.00
cycles	6.00	6.00	6.17	6.17	6.17	6.17	6.17	6.17	4.25	4.25	4.25	4.25	11.17	10.83	11.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.25
Overall L1	12.25

Vectorization ratios

INT

all	37%
load	69%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	5%

all	66%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	60%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	42%
load	69%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	60%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	5%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.25 cycles. At this rate:

34% of peak load performance is reached (32.65 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.65 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 539d70

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB X5, X8, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X5, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X4, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LS 53a99c <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1138>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X0, X5, #2, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X1, X21, X7,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
DUP Z29.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (6.3%)
ORR Z31.D, Z29.D, Z29.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
UBFM X11, X0, #59, #58	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X12, X22, X7,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SUB X10, X11, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X9, X1, X0,LSL #5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
UBFM X3, X10, #5, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X16, X3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS X14, X16, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 539c54 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x3f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 539c24 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x3c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 539bfc <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x398>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LD1D {Z0.D}, P2/Z, [X1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z15.D}, P2/Z, [X12, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z4.D}, P2/Z, [X1, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z28.D}, P2/Z, [X12, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X1, X1, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X12, X12, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z25.D}, P2/Z, [X19, Z0.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z3.D}, P2/Z, [X19, Z4.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
MOVPRFX Z31, Z29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FMLA Z31.D, P2/M, Z25.D, Z15.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA Z29.D, P2/M, Z3.D, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LD1D {Z23.D}, P2/Z, [X1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z20.D}, P2/Z, [X12, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z26.D}, P2/Z, [X1, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z1.D}, P2/Z, [X12, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X1, X1, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X12, X12, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z18.D}, P2/Z, [X19, Z23.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z21.D}, P2/Z, [X19, Z26.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA Z31.D, P2/M, Z18.D, Z20.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA Z29.D, P2/M, Z21.D, Z1.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LD1D {Z7.D}, P2/Z, [X1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z16.D}, P2/Z, [X1, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X1, X1, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z6.D}, P2/Z, [X12, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z19.D}, P2/Z, [X12, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z14.D}, P2/Z, [X19, Z7.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z17.D}, P2/Z, [X19, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X12, X12, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMLA Z31.D, P2/M, Z14.D, Z6.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA Z29.D, P2/M, Z17.D, Z19.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
CMP X9, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 539ce4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x480>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FADD Z29.D, Z29.D, Z31.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FADDV D31, P2, Z29.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	vect (100.0%)
ANDS XZR, X5, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 539d70 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x50c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X15, X5, #8062	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X7, X7, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X13, X7, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X17, X7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X2, [X21, X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D24, [X22, X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D22, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D31, D24, D22, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
CMP X17, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 539d70 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x50c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X27, X13, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, X7, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X18, [X21, X27]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D30, [X22, X27]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D2, [X19, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D31, D30, D2, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
CMP X1, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 539d70 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x50c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X30, X13, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, X7, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X7, [X21, X30]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D15, [X22, X30]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D5, [X19, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D31, D15, D5, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
CMP X6, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 539d70 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x50c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X13, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X5, [X21, X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D27, [X22, X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D20, [X19, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D31, D20, D27, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D31, [X25, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X20, X20, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP X23, X20	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 539b30 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X7, [X24, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X8, [X26, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X7, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 539b80 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x31c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVI D31, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
B 539cfc <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x498>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code