OV - exec - Loop 3821

	Loop Id: 3821	Module: exec	Source: csr_matop.c:380-500 [...]	Coverage: 0.03%

0x5321e4 SUB	X6, X0, #1

0x5321e8 SDIV	X7, X0, X25

0x5321ec ADD	X15, X0, #1

0x5321f0 ADD	X18, X0, #2

0x5321f4 ADD	X1, X0, #3

0x5321f8 ORR	X3, XZR, X18

0x5321fc SDIV	X8, X6, X25

0x532200 SDIV	X11, X15, X25

0x532204 MSUB	X9, X7, X25, X0

0x532208 ADD	X0, X0, #4

0x53220c SDIV	X12, X18, X25

0x532210 MSUB	X10, X8, X25, X6

0x532214 MADD	X16, X9, X27, X7

0x532218 MSUB	X30, X11, X25, X15

0x53221c MADD	X14, X10, X27, X8

0x532220 UBFM	X13, X16, #61, #60

0x532224 SDIV	X6, X1, X25

0x532228 LDR	X17, [X20, X13]    [2]

0x53222c LDR	X2, [X20, X14,LSL #3]    [2]

0x532230 MADD	X4, X30, X27, X11

0x532234 ORR	X11, XZR, X12

0x532238 MSUB	X18, X12, X25, X18

0x53223c UBFM	X7, X4, #61, #60

0x532240 ADD	X5, X17, X2

0x532244 MADD	X10, X18, X27, X12

0x532248 MSUB	X2, X11, X25, X3

0x53224c STR	X5, [X20, X13]    [2]

0x532250 LDR	X15, [X20, X16,LSL #3]    [2]

0x532254 UBFM	X14, X10, #61, #60

0x532258 MSUB	X16, X6, X25, X1

0x53225c MADD	X1, X2, X27, X11

0x532260 LDR	X8, [X20, X7]    [2]

0x532264 MADD	X12, X16, X27, X6

0x532268 UBFM	X30, X12, #61, #60

0x53226c ADD	X9, X8, X15

0x532270 STR	X9, [X20, X7]    [2]

0x532274 LDR	X13, [X20, X4,LSL #3]    [2]

0x532278 LDR	X17, [X20, X14]    [2]

0x53227c LDR	X7, [SP, #112]    [1]

0x532280 ADD	X3, X17, X13

0x532284 STR	X3, [X20, X14]    [2]

0x532288 LDR	X4, [X20, X30]    [2]

0x53228c LDR	X5, [X20, X1,LSL #3]    [2]

0x532290 ADD	X6, X4, X5

0x532294 STR	X6, [X20, X30]    [2]

0x532298 CMP	X0, X7

0x53229c B.NE	5321e4

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c: 380 - 500

--------------------------------------------------------------------------------

380:   return idx%dim1*dim2 + idx/dim1;

[...]

496:    for (i = my_thread_num*num_colsA + 1; i < (my_thread_num + 1)*num_colsA; ++i) {

497:      HYPRE_Int transpose_i = transpose_idx(i, num_threads, num_colsA);

498:      HYPRE_Int transpose_i_minus_1 = transpose_idx(i - 1, num_threads, num_colsA);

499:

500:      bucket[transpose_i] += bucket[transpose_i_minus_1];

Coverage (%)	Name	Source Location	Module
►100.00+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.47 - 5.88
Bottlenecks	P8, P10,
Function	hypre_CSRMatrixTranspose._omp_fn.0
Source	csr_matop.c:380-380,csr_matop.c:496-500
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	25.00 - 100.00
CQA cycles if no scalar integer	25.00 - 100.00
CQA cycles if FP arith vectorized	25.00 - 100.00
CQA cycles if fully vectorized	12.50 - 50.00
Front-end cycles	5.88
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	3.17
P3 cycles	3.25
P4 cycles	3.17
P5 cycles	3.17
P6 cycles	17.00
P7 cycles	3.25
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	4.33
P13 cycles	4.33
P14 cycles	4.33
P15 cycles	2.00
P16 cycles	2.00
DIV/SQRT cycles	25.00 - 100.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	47.00
Nb uops	47.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	0.00 - 0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.04 - 4.16
Bytes prefetched	0.00
Bytes loaded	72.00
Bytes stored	32.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	1.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.47 - 5.88
Bottlenecks	P8, P10,
Function	hypre_CSRMatrixTranspose._omp_fn.0
Source	csr_matop.c:380-380,csr_matop.c:496-500
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	25.00 - 100.00
CQA cycles if no scalar integer	25.00 - 100.00
CQA cycles if FP arith vectorized	25.00 - 100.00
CQA cycles if fully vectorized	12.50 - 50.00
Front-end cycles	5.88
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	3.17
P3 cycles	3.25
P4 cycles	3.17
P5 cycles	3.17
P6 cycles	17.00
P7 cycles	3.25
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	4.33
P13 cycles	4.33
P14 cycles	4.33
P15 cycles	2.00
P16 cycles	2.00
DIV/SQRT cycles	25.00 - 100.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	47.00
Nb uops	47.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	0.00 - 0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.04 - 4.16
Bytes prefetched	0.00
Bytes loaded	72.00
Bytes stored	32.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	1.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_CSRMatrixTranspose._omp_fn.0
Source file and lines	csr_matop.c:380-500
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:380,496-500.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 100.00 to 50.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 72 bytes. The binary loop is storing 32 bytes.

General properties

nb instructions	47
loop length	188
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	3.17	3.25	3.17	3.17	17.00	3.25	0.00	0.00	0.00	0.00	4.33	4.33	4.33	2.00	2.00
cycles	0.50	0.50	3.17	3.25	3.17	3.17	17.00	3.25	0.00	0.00	0.00	0.00	4.33	4.33	4.33	2.00	2.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	25.00-100.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.88
Data deps.	1.00
Overall L1	25.00-100.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 100.00 cycles. At this rate:

0% of peak load performance is reached (0.72 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.32 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 5321e4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB X6, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
SDIV X7, X0, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	N/A
ADD X15, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X18, X0, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X1, X0, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ORR X3, XZR, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
SDIV X8, X6, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
SDIV X11, X15, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
MSUB X9, X7, X25, X0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
ADD X0, X0, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SDIV X12, X18, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
MSUB X10, X8, X25, X6	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
MADD X16, X9, X27, X7	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
MSUB X30, X11, X25, X15	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
MADD X14, X10, X27, X8	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
UBFM X13, X16, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SDIV X6, X1, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
LDR X17, [X20, X13]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X2, [X20, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MADD X4, X30, X27, X11	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ORR X11, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MSUB X18, X12, X25, X18	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
UBFM X7, X4, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X5, X17, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MADD X10, X18, X27, X12	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
MSUB X2, X11, X25, X3	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
STR X5, [X20, X13]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X15, [X20, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
UBFM X14, X10, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MSUB X16, X6, X25, X1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
MADD X1, X2, X27, X11	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X8, [X20, X7]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MADD X12, X16, X27, X6	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
UBFM X30, X12, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X9, X8, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STR X9, [X20, X7]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X13, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X20, X14]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X7, [SP, #112]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X3, X17, X13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STR X3, [X20, X14]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X4, [X20, X30]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X20, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X6, X4, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STR X6, [X20, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X0, X7	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.NE 5321e4 <hypre_CSRMatrixTranspose._omp_fn.0+0x1bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_CSRMatrixTranspose._omp_fn.0
Source file and lines	csr_matop.c:380-500
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:380,496-500.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 72 bytes. The binary loop is storing 32 bytes.

General properties

nb instructions	47
loop length	188
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	3.17	3.25	3.17	3.17	17.00	3.25	0.00	0.00	0.00	0.00	4.33	4.33	4.33	2.00	2.00
cycles	0.50	0.50	3.17	3.25	3.17	3.17	17.00	3.25	0.00	0.00	0.00	0.00	4.33	4.33	4.33	2.00	2.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	25.00-100.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.88
Data deps.	1.00
Overall L1	25.00-100.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 100.00 cycles. At this rate:

0% of peak load performance is reached (0.72 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.32 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 5321e4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB X6, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
SDIV X7, X0, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	N/A
ADD X15, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X18, X0, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X1, X0, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ORR X3, XZR, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
SDIV X8, X6, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
SDIV X11, X15, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
MSUB X9, X7, X25, X0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
ADD X0, X0, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SDIV X12, X18, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
MSUB X10, X8, X25, X6	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
MADD X16, X9, X27, X7	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
MSUB X30, X11, X25, X15	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
MADD X14, X10, X27, X8	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
UBFM X13, X16, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SDIV X6, X1, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
LDR X17, [X20, X13]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X2, [X20, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MADD X4, X30, X27, X11	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ORR X11, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MSUB X18, X12, X25, X18	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
UBFM X7, X4, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X5, X17, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MADD X10, X18, X27, X12	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
MSUB X2, X11, X25, X3	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
STR X5, [X20, X13]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X15, [X20, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
UBFM X14, X10, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MSUB X16, X6, X25, X1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
MADD X1, X2, X27, X11	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X8, [X20, X7]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MADD X12, X16, X27, X6	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
UBFM X30, X12, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X9, X8, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STR X9, [X20, X7]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X13, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X20, X14]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X7, [SP, #112]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X3, X17, X13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STR X3, [X20, X14]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X4, [X20, X30]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X20, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X6, X4, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STR X6, [X20, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X0, X7	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.NE 5321e4 <hypre_CSRMatrixTranspose._omp_fn.0+0x1bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code