OV - exec - Loop 3583

	Loop Id: 3583	Module: exec	Source: IJMatrix_parcsr.c:3240-3500 [...]	Coverage: 0.02%

0x51f640 LDR	X30, [SP, #136]

0x51f644 LDP	X16, X17, [SP, #120]

0x51f648 LDR	X3, [X30]

0x51f64c LDR	X25, [X17, X27,LSL #3]

0x51f650 LDR	X12, [X16, X27,LSL #3]

0x51f654 CMP	X25, X3

0x51f658 B.LT	51fa18

0x51f65c LDR	X1, [X18]

0x51f660 CMP	X25, X1

0x51f664 B.GE	51fa18

0x51f668 LDR	X16, [SP, #176]

0x51f66c SUB	X30, X25, X3

0x51f670 UBFM	X13, X30, #61, #60

0x51f674 CBNZ	X16, 51fd58

0x51fa18 LDR	X2, [SP, #144]

0x51fa1c CBNZ	X2, 51fa50

  (3584) 0x51fa20 ADD	X21, X21, X12

  (3584) 0x51fa24 LDR	X12, [SP, #104]

  (3584) 0x51fa28 ADD	X27, X27, #1

  (3584) 0x51fa2c CMP	X12, X27

  (3584) 0x51fa30 B.NE	51f640

  (3584) 0x51fa34 LDP	X19, X20, [SP, #16]

  (3584) 0x51fa38 LDP	X21, X22, [SP, #32]

  (3584) 0x51fa3c LDP	X23, X24, [SP, #48]

  (3584) 0x51fa40 LDP	X25, X26, [SP, #64]

  (3584) 0x51fa44 LDP	X27, X28, [SP, #80]

  (3584) 0x51fa48 LDP	X29, X30, [SP], #336

  (3584) 0x51fa4c RET

  (3584) 0x51fa50 LDR	X10, [SP, #152]

  (3584) 0x51fa54 CMP	X10, #0

  (3584) 0x51fa58 B.LE	51fa20

  (3584) 0x51fa5c LDP	X2, X0, [SP, #160]

  (3584) 0x51fa60 ADD	X15, X28, X12,LSL #3

  (3584) 0x51fa64 MOVZ	X14, #0

  (3584) 0x51fa68 B	51fa78

    (3585) 0x51fa6c ADD	X2, X2, #16

    (3585) 0x51fa70 CMP	X4, X2

    (3585) 0x51fa74 B.EQ	51fa20

    (3585) 0x51fa78 LDP	X13, X16, [X2]

    (3585) 0x51fa7c ORR	X6, XZR, X14

    (3585) 0x51fa80 ADD	X14, X14, X16

    (3585) 0x51fa84 CMP	X25, X13

    (3585) 0x51fa88 B.NE	51fa6c

    (3585) 0x51fa8c CMP	X12, #0

    (3585) 0x51fa90 B.LE	51fa6c

    (3585) 0x51fa94 CMP	X16, #0

    (3585) 0x51fa98 B.LE	51fa6c

    (3585) 0x51fa9c ADD	X10, X0, X6,LSL #3

    (3585) 0x51faa0 ORR	X3, XZR, X28

    (3585) 0x51faa4 ADD	X6, X0, X14,LSL #3

      (3587) 0x51faa8 SUB	X30, X6, X10

      (3587) 0x51faac ORR	X1, XZR, X10

      (3587) 0x51fab0 SUB	X13, X30, #8

      (3587) 0x51fab4 UBFM	X16, X13, #3, #63

      (3587) 0x51fab8 ADD	X17, X16, #1

      (3587) 0x51fabc ANDS	X30, X17, #4224

      (3587) 0x51fac0 B.EQ	51fb98

      (3587) 0x51fac4 CMP	X30, #1

      (3587) 0x51fac8 B.EQ	51fb6c

      (3587) 0x51facc CMP	X30, #2

      (3587) 0x51fad0 B.EQ	51fb58

      (3587) 0x51fad4 CMP	X30, #3

      (3587) 0x51fad8 B.EQ	51fb44

      (3587) 0x51fadc CMP	X30, #4

      (3587) 0x51fae0 B.EQ	51fb30

      (3587) 0x51fae4 CMP	X30, #5

      (3587) 0x51fae8 B.EQ	51fb1c

      (3587) 0x51faec CMP	X30, #6

      (3587) 0x51faf0 B.EQ	51fb08

      (3587) 0x51faf4 LDR	X13, [X3]

      (3587) 0x51faf8 LDR	X1, [X10]

      (3587) 0x51fafc CMP	X13, X1

      (3587) 0x51fb00 B.EQ	51fd1c

      (3587) 0x51fb04 ADD	X1, X10, #8

      (3587) 0x51fb08 LDR	X30, [X1]

      (3587) 0x51fb0c LDR	X13, [X3]

      (3587) 0x51fb10 CMP	X13, X30

      (3587) 0x51fb14 B.EQ	51fd08

      (3587) 0x51fb18 ADD	X1, X1, #8

      (3587) 0x51fb1c LDR	X30, [X1]

      (3587) 0x51fb20 LDR	X13, [X3]

      (3587) 0x51fb24 CMP	X13, X30

      (3587) 0x51fb28 B.EQ	51fcf4

      (3587) 0x51fb2c ADD	X1, X1, #8

      (3587) 0x51fb30 LDR	X30, [X1]

      (3587) 0x51fb34 LDR	X13, [X3]

      (3587) 0x51fb38 CMP	X13, X30

      (3587) 0x51fb3c B.EQ	51fce0

      (3587) 0x51fb40 ADD	X1, X1, #8

      (3587) 0x51fb44 LDR	X30, [X1]

      (3587) 0x51fb48 LDR	X13, [X3]

      (3587) 0x51fb4c CMP	X13, X30

      (3587) 0x51fb50 B.EQ	51fccc

      (3587) 0x51fb54 ADD	X1, X1, #8

      (3587) 0x51fb58 LDR	X30, [X1]

      (3587) 0x51fb5c LDR	X13, [X3]

      (3587) 0x51fb60 CMP	X13, X30

      (3587) 0x51fb64 B.EQ	51fcb8

      (3587) 0x51fb68 ADD	X1, X1, #8

      (3587) 0x51fb6c LDR	X30, [X1]

      (3587) 0x51fb70 LDR	X13, [X3]

      (3587) 0x51fb74 CMP	X13, X30

      (3587) 0x51fb78 B.NE	51fb8c

      (3587) 0x51fb7c STR	X22, [X1]

      (3587) 0x51fb80 LDR	X16, [X20, X19]

      (3587) 0x51fb84 ADD	X17, X16, #1

      (3587) 0x51fb88 STR	X17, [X20, X19]

      (3587) 0x51fb8c ADD	X1, X1, #8

      (3587) 0x51fb90 CMP	X1, X6

      (3587) 0x51fb94 B.EQ	51fca8

        (3586) 0x51fb98 LDR	X30, [X1]

        (3586) 0x51fb9c LDR	X13, [X3]

        (3586) 0x51fba0 CMP	X13, X30

        (3586) 0x51fba4 B.NE	51fbb8

        (3586) 0x51fba8 STR	X22, [X1]

        (3586) 0x51fbac LDR	X16, [X20, X19]

        (3586) 0x51fbb0 ADD	X17, X16, #1

        (3586) 0x51fbb4 STR	X17, [X20, X19]

        (3586) 0x51fbb8 LDR	X16, [X3]

        (3586) 0x51fbbc ADD	X30, X1, #8

        (3586) 0x51fbc0 LDR	X13, [X1, #8]

        (3586) 0x51fbc4 CMP	X16, X13

        (3586) 0x51fbc8 B.NE	51fbdc

        (3586) 0x51fbcc STR	X22, [X1, #8]

        (3586) 0x51fbd0 LDR	X1, [X20, X19]

        (3586) 0x51fbd4 ADD	X17, X1, #1

        (3586) 0x51fbd8 STR	X17, [X20, X19]

        (3586) 0x51fbdc LDR	X13, [X3]

        (3586) 0x51fbe0 LDR	X16, [X30, #8]

        (3586) 0x51fbe4 CMP	X13, X16

        (3586) 0x51fbe8 B.NE	51fbfc

        (3586) 0x51fbec STR	X22, [X30, #8]

        (3586) 0x51fbf0 LDR	X1, [X20, X19]

        (3586) 0x51fbf4 ADD	X17, X1, #1

        (3586) 0x51fbf8 STR	X17, [X20, X19]

        (3586) 0x51fbfc LDR	X13, [X3]

        (3586) 0x51fc00 LDR	X16, [X30, #16]

        (3586) 0x51fc04 CMP	X13, X16

        (3586) 0x51fc08 B.NE	51fc1c

        (3586) 0x51fc0c STR	X22, [X30, #16]

        (3586) 0x51fc10 LDR	X1, [X20, X19]

        (3586) 0x51fc14 ADD	X17, X1, #1

        (3586) 0x51fc18 STR	X17, [X20, X19]

        (3586) 0x51fc1c LDR	X13, [X3]

        (3586) 0x51fc20 LDR	X16, [X30, #24]

        (3586) 0x51fc24 CMP	X13, X16

        (3586) 0x51fc28 B.NE	51fc3c

        (3586) 0x51fc2c STR	X22, [X30, #24]

        (3586) 0x51fc30 LDR	X1, [X20, X19]

        (3586) 0x51fc34 ADD	X17, X1, #1

        (3586) 0x51fc38 STR	X17, [X20, X19]

        (3586) 0x51fc3c LDR	X13, [X3]

        (3586) 0x51fc40 LDR	X16, [X30, #32]

        (3586) 0x51fc44 CMP	X13, X16

        (3586) 0x51fc48 B.NE	51fc5c

        (3586) 0x51fc4c STR	X22, [X30, #32]

        (3586) 0x51fc50 LDR	X1, [X20, X19]

        (3586) 0x51fc54 ADD	X17, X1, #1

        (3586) 0x51fc58 STR	X17, [X20, X19]

        (3586) 0x51fc5c LDR	X13, [X3]

        (3586) 0x51fc60 LDR	X16, [X30, #40]

        (3586) 0x51fc64 CMP	X13, X16

        (3586) 0x51fc68 B.NE	51fc7c

        (3586) 0x51fc6c STR	X22, [X30, #40]

        (3586) 0x51fc70 LDR	X1, [X20, X19]

        (3586) 0x51fc74 ADD	X17, X1, #1

        (3586) 0x51fc78 STR	X17, [X20, X19]

        (3586) 0x51fc7c LDR	X13, [X3]

        (3586) 0x51fc80 LDR	X16, [X30, #48]

        (3586) 0x51fc84 CMP	X13, X16

        (3586) 0x51fc88 B.NE	51fc9c

        (3586) 0x51fc8c STR	X22, [X30, #48]

        (3586) 0x51fc90 LDR	X1, [X20, X19]

        (3586) 0x51fc94 ADD	X17, X1, #1

        (3586) 0x51fc98 STR	X17, [X20, X19]

        (3586) 0x51fc9c ADD	X1, X30, #56

        (3586) 0x51fca0 CMP	X1, X6

        (3586) 0x51fca4 B.NE	51fb98

      (3587) 0x51fca8 ADD	X3, X3, #8

      (3587) 0x51fcac CMP	X3, X15

      (3587) 0x51fcb0 B.NE	51faa8

    (3585) 0x51fcb4 B	51fa6c

      (3587) 0x51fcb8 STR	X22, [X1]

      (3587) 0x51fcbc LDR	X16, [X20, X19]

      (3587) 0x51fcc0 ADD	X17, X16, #1

      (3587) 0x51fcc4 STR	X17, [X20, X19]

      (3587) 0x51fcc8 B	51fb68

      (3587) 0x51fccc STR	X22, [X1]

      (3587) 0x51fcd0 LDR	X16, [X20, X19]

      (3587) 0x51fcd4 ADD	X17, X16, #1

      (3587) 0x51fcd8 STR	X17, [X20, X19]

      (3587) 0x51fcdc B	51fb54

      (3587) 0x51fce0 STR	X22, [X1]

      (3587) 0x51fce4 LDR	X16, [X20, X19]

      (3587) 0x51fce8 ADD	X17, X16, #1

      (3587) 0x51fcec STR	X17, [X20, X19]

      (3587) 0x51fcf0 B	51fb40

      (3587) 0x51fcf4 STR	X22, [X1]

      (3587) 0x51fcf8 LDR	X16, [X20, X19]

      (3587) 0x51fcfc ADD	X17, X16, #1

      (3587) 0x51fd00 STR	X17, [X20, X19]

      (3587) 0x51fd04 B	51fb2c

      (3587) 0x51fd08 STR	X22, [X1]

      (3587) 0x51fd0c LDR	X16, [X20, X19]

      (3587) 0x51fd10 ADD	X17, X16, #1

      (3587) 0x51fd14 STR	X17, [X20, X19]

      (3587) 0x51fd18 B	51fb18

      (3587) 0x51fd1c STR	X22, [X10]

      (3587) 0x51fd20 LDR	X16, [X20, X19]

      (3587) 0x51fd24 ADD	X17, X16, #1

      (3587) 0x51fd28 STR	X17, [X20, X19]

      (3587) 0x51fd2c B	51fb04

0x51fd58 LDR	X2, [SP, #184]

0x51fd5c LDR	X15, [SP, #216]

0x51fd60 LDR	X14, [SP, #200]

0x51fd64 LDR	X2, [X2, X13]

0x51fd68 LDR	X10, [X15, X13]

0x51fd6c LDR	X16, [SP, #208]

0x51fd70 LDR	X6, [X14, X13]

0x51fd74 SUB	X3, X10, X2

0x51fd78 LDR	X25, [X16, X13]

0x51fd7c CMP	X12, X3

0x51fd80 B.GT	52026c

0x51fd84 CMP	X12, #0

0x51fd88 B.LE	51fa24

0x51fd8c MOVZ	X3, #0

0x51fd90 MOVZ	X14, #0

0x51fd94 ADD	X12, X12, X21

0x51fd98 ORR	X15, XZR, X2

0x51fd9c HINT	#0

  (3588) 0x51fda0 LDR	X1, [X28, X21,LSL #3]

  (3588) 0x51fda4 CMP	X2, #0

  (3588) 0x51fda8 B.LE	51feec

    (3591) 0x51fdac ANDS	X17, X2, #4224

    (3591) 0x51fdb0 MOVZ	X0, #0

    (3591) 0x51fdb4 B.EQ	51fe60

    (3591) 0x51fdb8 CMP	X17, #1

    (3591) 0x51fdbc B.EQ	51fe48

    (3591) 0x51fdc0 CMP	X17, #2

    (3591) 0x51fdc4 B.EQ	51fe38

    (3591) 0x51fdc8 CMP	X17, #3

    (3591) 0x51fdcc B.EQ	51fe28

    (3591) 0x51fdd0 CMP	X17, #4

    (3591) 0x51fdd4 B.EQ	51fe18

    (3591) 0x51fdd8 CMP	X17, #5

    (3591) 0x51fddc B.EQ	51fe08

    (3591) 0x51fde0 CMP	X17, #6

    (3591) 0x51fde4 B.EQ	51fdf8

    (3591) 0x51fde8 LDR	X30, [X25]

    (3591) 0x51fdec CMP	X30, X1

    (3591) 0x51fdf0 B.EQ	51ff68

    (3591) 0x51fdf4 MOVZ	X0, #1

    (3591) 0x51fdf8 LDR	X16, [X25, X0,LSL #3]

    (3591) 0x51fdfc CMP	X16, X1

    (3591) 0x51fe00 B.EQ	51ff68

    (3591) 0x51fe04 ADD	X0, X0, #1

    (3591) 0x51fe08 LDR	X17, [X25, X0,LSL #3]

    (3591) 0x51fe0c CMP	X17, X1

    (3591) 0x51fe10 B.EQ	51ff68

    (3591) 0x51fe14 ADD	X0, X0, #1

    (3591) 0x51fe18 LDR	X30, [X25, X0,LSL #3]

    (3591) 0x51fe1c CMP	X30, X1

    (3591) 0x51fe20 B.EQ	51ff68

    (3591) 0x51fe24 ADD	X0, X0, #1

    (3591) 0x51fe28 LDR	X16, [X25, X0,LSL #3]

    (3591) 0x51fe2c CMP	X16, X1

    (3591) 0x51fe30 B.EQ	51ff68

    (3591) 0x51fe34 ADD	X0, X0, #1

    (3591) 0x51fe38 LDR	X17, [X25, X0,LSL #3]

    (3591) 0x51fe3c CMP	X17, X1

    (3591) 0x51fe40 B.EQ	51ff68

    (3591) 0x51fe44 ADD	X0, X0, #1

    (3591) 0x51fe48 LDR	X30, [X25, X0,LSL #3]

    (3591) 0x51fe4c CMP	X30, X1

    (3591) 0x51fe50 B.EQ	51ff68

    (3591) 0x51fe54 ADD	X0, X0, #1

    (3591) 0x51fe58 CMP	X2, X0

    (3591) 0x51fe5c B.EQ	51feec

      (3592) 0x51fe60 LDR	X16, [X25, X0,LSL #3]

      (3592) 0x51fe64 CMP	X16, X1

      (3592) 0x51fe68 B.EQ	51ff68

      (3592) 0x51fe6c ADD	X0, X0, #1

      (3592) 0x51fe70 LDR	X17, [X25, X0,LSL #3]

      (3592) 0x51fe74 ORR	X30, XZR, X0

      (3592) 0x51fe78 CMP	X17, X1

      (3592) 0x51fe7c B.EQ	51ff68

      (3592) 0x51fe80 ADD	X0, X0, #1

      (3592) 0x51fe84 LDR	X16, [X25, X0,LSL #3]

      (3592) 0x51fe88 CMP	X16, X1

      (3592) 0x51fe8c B.EQ	51ff68

      (3592) 0x51fe90 ADD	X0, X30, #2

      (3592) 0x51fe94 LDR	X17, [X25, X0,LSL #3]

      (3592) 0x51fe98 CMP	X17, X1

      (3592) 0x51fe9c B.EQ	51ff68

      (3592) 0x51fea0 ADD	X0, X30, #3

      (3592) 0x51fea4 LDR	X16, [X25, X0,LSL #3]

      (3592) 0x51fea8 CMP	X16, X1

      (3592) 0x51feac B.EQ	51ff68

      (3592) 0x51feb0 ADD	X0, X30, #4

      (3592) 0x51feb4 LDR	X17, [X25, X0,LSL #3]

      (3592) 0x51feb8 CMP	X17, X1

      (3592) 0x51febc B.EQ	51ff68

      (3592) 0x51fec0 ADD	X0, X30, #5

      (3592) 0x51fec4 LDR	X16, [X25, X0,LSL #3]

      (3592) 0x51fec8 CMP	X16, X1

      (3592) 0x51fecc B.EQ	51ff68

      (3592) 0x51fed0 ADD	X0, X30, #6

      (3592) 0x51fed4 LDR	X17, [X25, X0,LSL #3]

      (3592) 0x51fed8 CMP	X17, X1

      (3592) 0x51fedc B.EQ	51ff68

      (3592) 0x51fee0 ADD	X0, X30, #7

      (3592) 0x51fee4 CMP	X2, X0

      (3592) 0x51fee8 B.NE	51fe60

  (3588) 0x51feec LDR	D3, [X26, X21,LSL #3]

  (3588) 0x51fef0 CMP	X10, X15

  (3588) 0x51fef4 B.LE	51ff84

  (3588) 0x51fef8 UBFM	X16, X15, #61, #60

  (3588) 0x51fefc ADD	X15, X15, #1

  (3588) 0x51ff00 STR	X1, [X25, X16]

  (3588) 0x51ff04 STR	D3, [X6, X16]

  (3588) 0x51ff08 ADD	X21, X21, #1

  (3588) 0x51ff0c CMP	X21, X12

  (3588) 0x51ff10 B.NE	51fda0

0x51ff14 LDR	X6, [SP, #184]

0x51ff18 ADD	X21, X15, X14

0x51ff1c STR	X21, [X6, X13]

0x51ff20 CBNZ	X14, 51ff98

0x51ff24 ORR	X21, XZR, X12

0x51ff28 CBZ	X3, 51fa24

0x51ff2c ORR	X0, XZR, X3

0x51ff30 STR	X9, [SP, #112]

0x51ff34 STP	X5, X11, [SP, #240]

0x51ff38 STP	X7, X8, [SP, #256]

0x51ff3c STR	X18, [SP, #272]

0x51ff40 STR	X4, [SP, #288]

0x51ff44 BL	546e20

0x51ff48 LDR	X0, [SP, #112]

0x51ff4c BL	546e20

0x51ff50 LDR	X18, [SP, #272]

0x51ff54 MOVZ	X9, #0

0x51ff58 LDP	X5, X11, [SP, #240]

0x51ff5c LDP	X7, X8, [SP, #256]

0x51ff60 LDR	X4, [SP, #288]

0x51ff64 B	51fa24

    (3591) 0x51ff68 LDR	D4, [X26, X21,LSL #3]

    (3591) 0x51ff6c ADD	X21, X21, #1

    (3591) 0x51ff70 STR	D4, [X6, X0,LSL #3]

    (3591) 0x51ff74 CMP	X21, X12

    (3591) 0x51ff78 B.EQ	51ff14

    (3591) 0x51ff7c LDR	X1, [X28, X21,LSL #3]

    (3591) 0x51ff80 B	51fdac

  (3588) 0x51ff84 UBFM	X30, X14, #61, #60

  (3588) 0x51ff88 ADD	X14, X14, #1

  (3588) 0x51ff8c STR	X1, [X3, X30]

  (3588) 0x51ff90 STR	D3, [X9, X30]

  (3588) 0x51ff94 B	51ff08

0x51ff98 LDR	X10, [SP, #208]

0x51ff9c UBFM	X25, X21, #61, #60

0x51ffa0 ORR	X1, XZR, X25

0x51ffa4 STR	X13, [SP, #112]

0x51ffa8 STR	X9, [SP, #272]

0x51ffac LDR	X0, [X10, X13]

0x51ffb0 STP	X3, X15, [SP, #240]

0x51ffb4 STP	X14, X12, [SP, #256]

0x51ffb8 STP	X5, X11, [SP, #288]

0x51ffbc STP	X7, X8, [SP, #304]

0x51ffc0 STP	X18, X4, [SP, #320]

0x51ffc4 BL	546dc8

0x51ffc8 LDR	X3, [SP, #112]

0x51ffcc ORR	X1, XZR, X25

0x51ffd0 ORR	X9, XZR, X0

0x51ffd4 LDP	X2, X25, [SP, #200]

0x51ffd8 LDR	X0, [X2, X3]

0x51ffdc STR	X9, [X25, X3]

0x51ffe0 BL	546dc8

0x51ffe4 LDR	X13, [SP, #112]

0x51ffe8 ORR	X16, XZR, X0

0x51ffec LDP	X3, X15, [SP, #240]

0x51fff0 LDP	X14, X12, [SP, #256]

0x51fff4 UBFM	X17, X15, #61, #60

0x51fff8 LDP	X5, X11, [SP, #288]

0x51fffc CMP	X14, #1

0x520000 LDP	X7, X8, [SP, #304]

0x520004 LDP	X18, X4, [SP, #320]

0x520008 LDR	X1, [SP, #200]

0x52000c LDR	X30, [X25, X13]

0x520010 LDR	X9, [SP, #272]

0x520014 STR	X0, [X1, X13]

0x520018 LDR	X0, [SP, #216]

0x52001c STR	X21, [X0, X13]

0x520020 B.EQ	5203e8

0x520024 ADD	X2, X30, X15,LSL #3

0x520028 UBFM	X17, X15, #61, #60

0x52002c ADD	X1, X16, X15,LSL #3

0x520030 WHILEWR	P15.D, X2, X1

0x520034 CSINC	W21, WZR, WZR, #2

0x520038 WHILEWR	P15.D, X9, X1

0x52003c CSINC	W6, WZR, WZR, #2

0x520040 CMP	W21, #0

0x520044 CCMP	W6, #0, #4, #1

0x520048 CSINC	W10, WZR, WZR, #0

0x52004c WHILEWR	P15.D, X3, X2

0x520050 CCMP	W10, #0, #4, #3

0x520054 B.EQ	5203e8

0x520058 UBFM	X25, X14, #1, #63

0x52005c MOVZ	X0, #0

0x520060 UBFM	X21, X25, #60, #59

0x520064 SUB	X13, X21, #16

0x520068 UBFM	X6, X13, #4, #63

0x52006c ADD	X10, X6, #1

0x520070 ANDS	X25, X10, #4224

0x520074 B.EQ	520128

0x520078 CMP	X25, #1

0x52007c B.EQ	52010c

0x520080 CMP	X25, #2

0x520084 B.EQ	5200f8

0x520088 CMP	X25, #3

0x52008c B.EQ	5200e4

0x520090 CMP	X25, #4

0x520094 B.EQ	5200d0

0x520098 CMP	X25, #5

0x52009c B.EQ	5200bc

0x5200a0 CMP	X25, #6

0x5200a4 B.NE	5205f8

0x5200a8 LDR	Q7, [X3, X0]

0x5200ac LDR	Q6, [X9, X0]

0x5200b0 STR	Q7, [X2, X0]

0x5200b4 STR	Q6, [X1, X0]

0x5200b8 ADD	X0, X0, #16

0x5200bc LDR	Q17, [X3, X0]

0x5200c0 LDR	Q16, [X9, X0]

0x5200c4 STR	Q17, [X2, X0]

0x5200c8 STR	Q16, [X1, X0]

0x5200cc ADD	X0, X0, #16

0x5200d0 LDR	Q19, [X3, X0]

0x5200d4 LDR	Q18, [X9, X0]

0x5200d8 STR	Q19, [X2, X0]

0x5200dc STR	Q18, [X1, X0]

0x5200e0 ADD	X0, X0, #16

0x5200e4 LDR	Q21, [X3, X0]

0x5200e8 LDR	Q20, [X9, X0]

0x5200ec STR	Q21, [X2, X0]

0x5200f0 STR	Q20, [X1, X0]

0x5200f4 ADD	X0, X0, #16

0x5200f8 LDR	Q23, [X3, X0]

0x5200fc LDR	Q22, [X9, X0]

0x520100 STR	Q23, [X2, X0]

0x520104 STR	Q22, [X1, X0]

0x520108 ADD	X0, X0, #16

0x52010c LDR	Q25, [X3, X0]

0x520110 LDR	Q24, [X9, X0]

0x520114 STR	Q25, [X2, X0]

0x520118 STR	Q24, [X1, X0]

0x52011c ADD	X0, X0, #16

0x520120 CMP	X0, X21

0x520124 B.EQ	5201d4

0x520128 ORR	X25, XZR, X21

  (3590) 0x52012c LDR	Q27, [X3, X0]

  (3590) 0x520130 ADD	X6, X0, #16

  (3590) 0x520134 ADD	X21, X0, #32

  (3590) 0x520138 ADD	X17, X0, #48

  (3590) 0x52013c ADD	X13, X0, #64

  (3590) 0x520140 LDR	Q26, [X9, X0]

  (3590) 0x520144 ADD	X10, X0, #80

  (3590) 0x520148 STR	Q27, [X2, X0]

  (3590) 0x52014c LDR	Q28, [X3, X6]

  (3590) 0x520150 STR	Q26, [X1, X0]

  (3590) 0x520154 LDR	Q29, [X9, X6]

  (3590) 0x520158 STR	Q28, [X2, X6]

  (3590) 0x52015c LDR	Q0, [X3, X21]

  (3590) 0x520160 STR	Q29, [X1, X6]

  (3590) 0x520164 ADD	X6, X0, #96

  (3590) 0x520168 LDR	Q31, [X9, X21]

  (3590) 0x52016c STR	Q0, [X2, X21]

  (3590) 0x520170 LDR	Q1, [X3, X17]

  (3590) 0x520174 STR	Q31, [X1, X21]

  (3590) 0x520178 ADD	X21, X0, #112

  (3590) 0x52017c ADD	X0, X0, #128

  (3590) 0x520180 LDR	Q2, [X9, X17]

  (3590) 0x520184 STR	Q1, [X2, X17]

  (3590) 0x520188 LDR	Q3, [X3, X13]

  (3590) 0x52018c STR	Q2, [X1, X17]

  (3590) 0x520190 LDR	Q4, [X9, X13]

  (3590) 0x520194 STR	Q3, [X2, X13]

  (3590) 0x520198 LDR	Q30, [X3, X10]

  (3590) 0x52019c STR	Q4, [X1, X13]

  (3590) 0x5201a0 LDR	Q5, [X9, X10]

  (3590) 0x5201a4 STR	Q30, [X2, X10]

  (3590) 0x5201a8 LDR	Q6, [X3, X6]

  (3590) 0x5201ac STR	Q5, [X1, X10]

  (3590) 0x5201b0 LDR	Q7, [X9, X6]

  (3590) 0x5201b4 STR	Q6, [X2, X6]

  (3590) 0x5201b8 LDR	Q16, [X3, X21]

  (3590) 0x5201bc STR	Q7, [X1, X6]

  (3590) 0x5201c0 LDR	Q17, [X9, X21]

  (3590) 0x5201c4 STR	Q16, [X2, X21]

  (3590) 0x5201c8 STR	Q17, [X1, X21]

  (3590) 0x5201cc CMP	X0, X25

  (3590) 0x5201d0 B.NE	52012c

0x5201d4 AND	X2, X14, #8127

0x5201d8 ADD	X15, X2, X15

0x5201dc TBZ	W14, #0, 520568

0x5201e0 UBFM	X14, X2, #61, #60

0x5201e4 UBFM	X1, X15, #61, #60

0x5201e8 LDR	X0, [X3, X14]

0x5201ec ORR	X21, XZR, X12

0x5201f0 LDR	D18, [X9, X14]

0x5201f4 STR	X0, [X30, X1]

0x5201f8 STR	D18, [X16, X1]

0x5201fc B	51ff28

0x52026c SUB	X9, X12, X3

0x520270 MOVZ	X1, #8

0x520274 STP	X12, X6, [SP, #240]

0x520278 ORR	X0, XZR, X9

0x52027c STR	X9, [SP, #112]

0x520280 STP	X10, X2, [SP, #256]

0x520284 STR	X13, [SP, #272]

0x520288 STP	X5, X11, [SP, #288]

0x52028c STP	X7, X8, [SP, #304]

0x520290 STP	X18, X4, [SP, #320]

0x520294 BL	546d88

0x520298 ORR	X7, XZR, X0

0x52029c LDR	X0, [SP, #112]

0x5202a0 MOVZ	X1, #8

0x5202a4 STR	X7, [SP, #112]

0x5202a8 BL	546d88

0x5202ac LDP	X12, X6, [SP, #240]

0x5202b0 ORR	X9, XZR, X0

0x5202b4 LDP	X10, X2, [SP, #256]

0x5202b8 LDP	X5, X11, [SP, #288]

0x5202bc LDP	X7, X8, [SP, #304]

0x5202c0 LDP	X18, X4, [SP, #320]

0x5202c4 LDR	X3, [SP, #112]

0x5202c8 LDR	X13, [SP, #272]

0x5202cc CMP	X12, #0

0x5202d0 B.GT	51fd90

0x5202d4 LDR	X1, [SP, #184]

0x5202d8 STR	X2, [X1, X13]

0x5202dc B	51ff28

0x5203e8 ANDS	X13, X14, #4224

0x5203ec ADD	X21, X30, X17

0x5203f0 MOVZ	X0, #0

0x5203f4 ADD	X25, X16, X17

0x5203f8 B.EQ	5204c0

0x5203fc CMP	X13, #1

0x520400 B.EQ	5204a4

0x520404 CMP	X13, #2

0x520408 B.EQ	520490

0x52040c CMP	X13, #3

0x520410 B.EQ	52047c

0x520414 CMP	X13, #4

0x520418 B.EQ	520468

0x52041c CMP	X13, #5

0x520420 B.EQ	520454

0x520424 CMP	X13, #6

0x520428 B.EQ	520440

0x52042c LDR	D19, [X9]

0x520430 MOVZ	X0, #1

0x520434 LDR	X10, [X3]

0x520438 STR	X10, [X30, X17]

0x52043c STR	D19, [X16, X17]

0x520440 LDR	D20, [X9, X0,LSL #3]

0x520444 LDR	X16, [X3, X0,LSL #3]

0x520448 STR	X16, [X21, X0,LSL #3]

0x52044c STR	D20, [X25, X0,LSL #3]

0x520450 ADD	X0, X0, #1

0x520454 LDR	D21, [X9, X0,LSL #3]

0x520458 LDR	X30, [X3, X0,LSL #3]

0x52045c STR	X30, [X21, X0,LSL #3]

0x520460 STR	D21, [X25, X0,LSL #3]

0x520464 ADD	X0, X0, #1

0x520468 LDR	D22, [X9, X0,LSL #3]

0x52046c LDR	X17, [X3, X0,LSL #3]

0x520470 STR	X17, [X21, X0,LSL #3]

0x520474 STR	D22, [X25, X0,LSL #3]

0x520478 ADD	X0, X0, #1

0x52047c LDR	D23, [X9, X0,LSL #3]

0x520480 LDR	X6, [X3, X0,LSL #3]

0x520484 STR	X6, [X21, X0,LSL #3]

0x520488 STR	D23, [X25, X0,LSL #3]

0x52048c ADD	X0, X0, #1

0x520490 LDR	D24, [X9, X0,LSL #3]

0x520494 LDR	X2, [X3, X0,LSL #3]

0x520498 STR	X2, [X21, X0,LSL #3]

0x52049c STR	D24, [X25, X0,LSL #3]

0x5204a0 ADD	X0, X0, #1

0x5204a4 LDR	D25, [X9, X0,LSL #3]

0x5204a8 LDR	X15, [X3, X0,LSL #3]

0x5204ac STR	X15, [X21, X0,LSL #3]

0x5204b0 STR	D25, [X25, X0,LSL #3]

0x5204b4 ADD	X0, X0, #1

0x5204b8 CMP	X0, X14

0x5204bc B.EQ	520568

  (3589) 0x5204c0 LDR	X16, [X3, X0,LSL #3]

  (3589) 0x5204c4 ADD	X1, X0, #1

  (3589) 0x5204c8 ADD	X30, X0, #2

  (3589) 0x5204cc ADD	X13, X0, #3

  (3589) 0x5204d0 ADD	X10, X0, #4

  (3589) 0x5204d4 LDR	D26, [X9, X0,LSL #3]

  (3589) 0x5204d8 ADD	X2, X0, #6

  (3589) 0x5204dc STR	X16, [X21, X0,LSL #3]

  (3589) 0x5204e0 ADD	X16, X0, #5

  (3589) 0x5204e4 LDR	X17, [X3, X1,LSL #3]

  (3589) 0x5204e8 STR	D26, [X25, X0,LSL #3]

  (3589) 0x5204ec LDR	D27, [X9, X1,LSL #3]

  (3589) 0x5204f0 STR	X17, [X21, X1,LSL #3]

  (3589) 0x5204f4 LDR	X6, [X3, X30,LSL #3]

  (3589) 0x5204f8 STR	D27, [X25, X1,LSL #3]

  (3589) 0x5204fc ADD	X1, X0, #7

  (3589) 0x520500 ADD	X0, X0, #8

  (3589) 0x520504 LDR	D28, [X9, X30,LSL #3]

  (3589) 0x520508 STR	X6, [X21, X30,LSL #3]

  (3589) 0x52050c LDR	X15, [X3, X13,LSL #3]

  (3589) 0x520510 STR	D28, [X25, X30,LSL #3]

  (3589) 0x520514 LDR	D29, [X9, X13,LSL #3]

  (3589) 0x520518 STR	X15, [X21, X13,LSL #3]

  (3589) 0x52051c LDR	X30, [X3, X10,LSL #3]

  (3589) 0x520520 STR	D29, [X25, X13,LSL #3]

  (3589) 0x520524 LDR	D0, [X9, X10,LSL #3]

  (3589) 0x520528 STR	X30, [X21, X10,LSL #3]

  (3589) 0x52052c LDR	X13, [X3, X16,LSL #3]

  (3589) 0x520530 STR	D0, [X25, X10,LSL #3]

  (3589) 0x520534 LDR	D31, [X9, X16,LSL #3]

  (3589) 0x520538 STR	X13, [X21, X16,LSL #3]

  (3589) 0x52053c LDR	X10, [X3, X2,LSL #3]

  (3589) 0x520540 STR	D31, [X25, X16,LSL #3]

  (3589) 0x520544 LDR	D1, [X9, X2,LSL #3]

  (3589) 0x520548 STR	X10, [X21, X2,LSL #3]

  (3589) 0x52054c LDR	X17, [X3, X1,LSL #3]

  (3589) 0x520550 STR	D1, [X25, X2,LSL #3]

  (3589) 0x520554 LDR	D2, [X9, X1,LSL #3]

  (3589) 0x520558 STR	X17, [X21, X1,LSL #3]

  (3589) 0x52055c STR	D2, [X25, X1,LSL #3]

  (3589) 0x520560 CMP	X0, X14

  (3589) 0x520564 B.NE	5204c0

0x520568 ORR	X21, XZR, X12

0x52056c B	51ff2c

0x5205f8 LDR	Q30, [X3]

0x5205fc MOVZ	X0, #16

0x520600 LDR	Q5, [X9]

0x520604 STR	Q30, [X30, X17]

0x520608 STR	Q5, [X16, X17]

0x52060c B	5200a8

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c: 3240 - 3500

--------------------------------------------------------------------------------

3240: #pragma omp parallel

[...]

3291:          for (ii=ns; ii < ne; ii++)

3292:          {

3293:             row = rows[ii];

3294:             n = ncols[ii];

3295:             /* processor owns the row */

3296:             if (row >= row_partitioning[pstart] && row < row_partitioning[pstart+1])

3297:             {

3298:                row_local = row - row_partitioning[pstart];

3299:                /* compute local row number */

3300:                if (need_aux)

3301:                {

3302:                   local_j = aux_j[row_local];

3303:                   local_data = aux_data[row_local];

3304:    	          space = row_space[row_local];

3305:    	          old_size = row_length[row_local];

3306:    	          size = space - old_size;

3307:    	          if (size < n)

3308:       	          {

3309:       	             size = n - size;

3310:       	             tmp_j = hypre_CTAlloc(HYPRE_Int,size);

3311:       	             tmp_data = hypre_CTAlloc(HYPRE_Complex,size);

3312:       	          }

3313:       	          tmp_indx = 0;

3314:       	          not_found = 1;

3315:       	          size = old_size;

3316:                   for (i=0; i < n; i++)

3317:       	          {

3318:       	             for (j=0; j < old_size; j++)

3319:       	             {

3320:       	                if (local_j[j] == cols[indx])

3321:       	                {

3322:                            local_data[j] = values[indx];

[...]

3329:       	                if (size < space)

3330:       	                {

3331:       	                   local_j[size] = cols[indx];

3332:       	                   local_data[size++] = values[indx];

3333:       	                }

3334:       	                else

3335:       	                {

3336:       	                   tmp_j[tmp_indx] = cols[indx];

3337:       	                   tmp_data[tmp_indx++] = values[indx];

3338:       	                }

3339:       	             }

3340:       	             not_found = 1;

3341:         	     indx++;

3342:       	          }

3343:

3344:                   row_length[row_local] = size+tmp_indx;

3345:

3346:                   if (tmp_indx)

3347:                   {

3348:    	             aux_j[row_local] = hypre_TReAlloc(aux_j[row_local],HYPRE_Int,

3349:                                                     size+tmp_indx);

3350:    	             aux_data[row_local] = hypre_TReAlloc(aux_data[row_local],

3351:                                                        HYPRE_Complex,size+tmp_indx);

3352:                      row_space[row_local] = size+tmp_indx;

3353:                      local_j = aux_j[row_local];

[...]

3359:    	          for (i=0; i < tmp_indx; i++)

3360:    	          {

3361:    	             local_j[cnt] = tmp_j[i];

3362:    	             local_data[cnt++] = tmp_data[i];

3363: 	          }

3364:

3365: 	          if (tmp_j)

3366: 	          {

3367: 	             hypre_TFree(tmp_j);

3368: 	             hypre_TFree(tmp_data);

[...]

3376: 	          offd_indx = hypre_AuxParCSRMatrixIndxOffd(aux_matrix)[row_local];

[...]

3458:                   hypre_AuxParCSRMatrixIndxOffd(aux_matrix)[row_local] = cnt_offd;

[...]

3466:                indx +=  n;

3467:    	       if (aux_matrix)

3468:                {

3469:                   col_indx = 0;

3470:                   for (i=0; i < off_proc_i_indx; i=i+2)

3471:                   {

3472: 	             row_len = off_proc_i[i+1];

3473: 	             if (off_proc_i[i] == row)

3474: 		     {

3475: 		        for (j=0; j < n; j++)

3476: 		        {

3477: 			   cnt1 = col_indx;

3478: 			   for (k=0; k < row_len; k++)

3479: 			   {

3480: 			      if (off_proc_j[cnt1] == cols[j])

3481: 			      {

3482:                                  off_proc_j[cnt1++] = -1;

3483:                		         /*cancel_indx++;*/

3484: 	                         offproc_cnt[my_thread_num]++;

[...]

3500: 		        col_indx += row_len;

Coverage (%)	Name	Source Location	Module
►100.00+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.53
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.18
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.00
Bottlenecks	P12,
Function	hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1
Source	IJMatrix_parcsr.c:3293-3316,IJMatrix_parcsr.c:3344-3353,IJMatrix_parcsr.c:3359-3362,IJMatrix_parcsr.c:3365-3368,IJMatrix_parcsr.c:3376-3376,IJMatrix_parcsr.c:3458-3458,IJMatrix_parcsr.c:3467-3467
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	43.83
CQA cycles if no scalar integer	17.33
CQA cycles if FP arith vectorized	43.83
CQA cycles if fully vectorized	37.25
Front-end cycles	32.13
P0 cycles	19.50
P1 cycles	19.50
P2 cycles	15.50
P3 cycles	15.50
P4 cycles	15.50
P5 cycles	15.50
P6 cycles	15.50
P7 cycles	15.50
P8 cycles	11.00
P9 cycles	11.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	43.83
P13 cycles	43.50
P14 cycles	43.67
P15 cycles	16.50
P16 cycles	16.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	258.00
Nb uops	257.00
Nb loads	NA
Nb stores	55.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	33.76
Bytes prefetched	0.00
Bytes loaded	832.00
Bytes stored	648.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	25.69
Vectorization ratio load	46.67
Vectorization ratio store	25.45
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	70.41
Vector-efficiency ratio load	83.33
Vector-efficiency ratio store	73.64
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	46.74

Metric	Value
CQA speedup if no scalar integer	2.53
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.18
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.00
Bottlenecks	P12,
Function	hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1
Source	IJMatrix_parcsr.c:3293-3316,IJMatrix_parcsr.c:3344-3353,IJMatrix_parcsr.c:3359-3362,IJMatrix_parcsr.c:3365-3368,IJMatrix_parcsr.c:3376-3376,IJMatrix_parcsr.c:3458-3458,IJMatrix_parcsr.c:3467-3467
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	43.83
CQA cycles if no scalar integer	17.33
CQA cycles if FP arith vectorized	43.83
CQA cycles if fully vectorized	37.25
Front-end cycles	32.13
P0 cycles	19.50
P1 cycles	19.50
P2 cycles	15.50
P3 cycles	15.50
P4 cycles	15.50
P5 cycles	15.50
P6 cycles	15.50
P7 cycles	15.50
P8 cycles	11.00
P9 cycles	11.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	43.83
P13 cycles	43.50
P14 cycles	43.67
P15 cycles	16.50
P16 cycles	16.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	258.00
Nb uops	257.00
Nb loads	NA
Nb stores	55.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	33.76
Bytes prefetched	0.00
Bytes loaded	832.00
Bytes stored	648.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	25.69
Vectorization ratio load	46.67
Vectorization ratio store	25.45
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	70.41
Vector-efficiency ratio load	83.33
Vector-efficiency ratio store	73.64
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	46.74

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1
Source file and lines	IJMatrix_parcsr.c:3240-3500
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3240,3291-3322,3329-3353,3359-3368,3376,3458,3466-3484,3500.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3293-3316,3344-3353,3359-3362,3365-3368,3376,3458,3467.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 43.83 to 17.33 cycles (2.53x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 70% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 43.83 to 37.25 cycles (1.18x speedup).

Details

25% of VPU instructions are used in vector version (process two or more data elements in vector registers):

46% of VPU loads are used in vector version.
25% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 43.83 to 3.00 cycles (14.61x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 832 bytes. The binary loop is storing 648 bytes.

General properties

nb instructions	258
loop length	1032
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

32.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	19.50	19.50	15.50	15.50	15.50	15.50	15.50	15.50	11.00	11.00	0.00	0.00	43.83	43.50	43.67	16.50	16.50
cycles	19.50	19.50	15.50	15.50	15.50	15.50	15.50	15.50	11.00	11.00	0.00	0.00	43.83	43.50	43.67	16.50	16.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	32.13
Overall L1	43.83

Vectorization ratios

all	25%
load	46%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 43.83 cycles. At this rate:

19% of peak load performance is reached (18.98 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
30% of peak store performance is reached (14.78 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 51f640

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR X30, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X16, X17, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X3, [X30]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X17, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X16, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X25, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 51fa18 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x798>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [X18]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X25, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 51fa18 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x798>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X30, X25, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X13, X30, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CBNZ X16, 51fd58 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xad8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X2, 51fa50 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x7d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X2, X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X15, X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X14, X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X3, X10, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X25, [X16, X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X12, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 52026c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xfec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X12, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 51fa24 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x7a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X3, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ X14, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X12, X12, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X15, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
LDR X6, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X21, X15, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X21, [X6, X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBNZ X14, 51ff98 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xd18>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CBZ X3, 51fa24 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x7a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X9, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X5, X11, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X7, X8, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X18, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X4, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 546e20 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 546e20 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X5, X11, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X7, X8, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X4, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 51fa24 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x7a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X25, X21, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X1, XZR, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X13, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X9, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X10, X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X3, X15, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X14, X12, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X5, X11, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X7, X8, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X18, X4, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
BL 546dc8 <hypre_ReAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X1, XZR, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X9, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X2, X25, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X0, [X2, X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X9, [X25, X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 546dc8 <hypre_ReAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X16, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X3, X15, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X14, X12, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
UBFM X17, X15, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X5, X11, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
CMP X14, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
LDP X7, X8, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X18, X4, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X1, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X30, [X25, X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X1, X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X21, [X0, X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B.EQ 5203e8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x1168>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X30, X15,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X17, X15, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, X16, X15,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
WHILEWR P15.D, X2, X1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	3	1	N/A
CSINC W21, WZR, WZR, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
WHILEWR P15.D, X9, X1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	3	1	N/A
CSINC W6, WZR, WZR, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W21, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP W6, #0, #4, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (25.0%)
CSINC W10, WZR, WZR, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
WHILEWR P15.D, X3, X2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	3	1	N/A
CCMP W10, #0, #4, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (25.0%)
B.EQ 5203e8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x1168>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X25, X14, #1, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ X0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X21, X25, #60, #59	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X13, X21, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X6, X13, #4, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X6, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ANDS X25, X10, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 520128 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xea8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 52010c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xe8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 5200f8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xe78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 5200e4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xe64>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 5200d0 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xe50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 5200bc <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xe3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 5205f8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x1378>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q7, [X3, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Q6, [X9, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STR Q7, [X2, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Q6, [X1, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ADD X0, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q17, [X3, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Q16, [X9, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STR Q17, [X2, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Q16, [X1, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ADD X0, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q19, [X3, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Q18, [X9, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STR Q19, [X2, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Q18, [X1, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ADD X0, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q21, [X3, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Q20, [X9, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STR Q21, [X2, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Q20, [X1, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ADD X0, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q23, [X3, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Q22, [X9, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STR Q23, [X2, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Q22, [X1, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ADD X0, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q25, [X3, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Q24, [X9, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STR Q25, [X2, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Q24, [X1, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ADD X0, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X0, X21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 5201d4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xf54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X25, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND X2, X14, #8127	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X15, X2, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TBZ W14, #0, 520568 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x12e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X14, X2, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X1, X15, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X0, [X3, X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X21, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D18, [X9, X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR X0, [X30, X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR D18, [X16, X1]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
B 51ff28 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xca8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X9, X12, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X12, X6, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X0, XZR, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X9, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X10, X2, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X13, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X5, X11, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X7, X8, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X18, X4, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
BL 546d88 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X7, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X7, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 546d88 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X12, X6, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ORR X9, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X10, X2, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X5, X11, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X7, X8, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X18, X4, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X3, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X12, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 51fd90 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [X1, X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 51ff28 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xca8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ANDS X13, X14, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
ADD X21, X30, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ X0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X25, X16, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B.EQ 5204c0 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x1240>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 5204a4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x1224>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 520490 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x1210>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 52047c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x11fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 520468 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x11e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 520454 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x11d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 520440 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x11c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D19, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
MOVZ X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X10, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [X30, X17]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR D19, [X16, X17]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D20, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X16, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X16, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR D20, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D21, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X30, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X30, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR D21, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D22, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X17, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X17, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR D22, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D23, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X6, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X6, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR D23, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D24, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X2, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR D24, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D25, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X15, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X15, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR D25, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X0, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 520568 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x12e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 51ff2c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xcac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q30, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
MOVZ X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q5, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STR Q30, [X30, X17]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Q5, [X16, X17]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
B 5200a8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xe28>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1
Source file and lines	IJMatrix_parcsr.c:3240-3500
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

25% of VPU instructions are used in vector version (process two or more data elements in vector registers):

46% of VPU loads are used in vector version.
25% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 43.83 to 3.00 cycles (14.61x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 832 bytes. The binary loop is storing 648 bytes.

General properties

nb instructions	258
loop length	1032
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

32.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	19.50	19.50	15.50	15.50	15.50	15.50	15.50	15.50	11.00	11.00	0.00	0.00	43.83	43.50	43.67	16.50	16.50
cycles	19.50	19.50	15.50	15.50	15.50	15.50	15.50	15.50	11.00	11.00	0.00	0.00	43.83	43.50	43.67	16.50	16.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	32.13
Overall L1	43.83

Vectorization ratios

all	25%
load	46%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 43.83 cycles. At this rate:

19% of peak load performance is reached (18.98 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
30% of peak store performance is reached (14.78 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 51f640

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR X30, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X16, X17, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X3, [X30]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X17, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X16, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X25, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 51fa18 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x798>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [X18]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X25, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 51fa18 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x798>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X30, X25, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X13, X30, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CBNZ X16, 51fd58 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xad8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X2, 51fa50 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x7d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X2, X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X15, X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X14, X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X3, X10, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X25, [X16, X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X12, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 52026c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xfec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X12, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 51fa24 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x7a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X3, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ X14, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X12, X12, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X15, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
LDR X6, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X21, X15, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X21, [X6, X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBNZ X14, 51ff98 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xd18>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CBZ X3, 51fa24 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x7a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X9, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X5, X11, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X7, X8, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X18, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X4, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 546e20 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 546e20 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X5, X11, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X7, X8, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X4, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 51fa24 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x7a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X25, X21, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X1, XZR, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X13, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X9, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X10, X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X3, X15, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X14, X12, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X5, X11, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X7, X8, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X18, X4, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
BL 546dc8 <hypre_ReAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X1, XZR, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X9, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X2, X25, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X0, [X2, X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X9, [X25, X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 546dc8 <hypre_ReAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X16, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X3, X15, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X14, X12, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
UBFM X17, X15, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X5, X11, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
CMP X14, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
LDP X7, X8, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X18, X4, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X1, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X30, [X25, X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X1, X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X21, [X0, X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B.EQ 5203e8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x1168>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X30, X15,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X17, X15, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, X16, X15,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
WHILEWR P15.D, X2, X1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	3	1	N/A
CSINC W21, WZR, WZR, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
WHILEWR P15.D, X9, X1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	3	1	N/A
CSINC W6, WZR, WZR, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W21, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP W6, #0, #4, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (25.0%)
CSINC W10, WZR, WZR, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
WHILEWR P15.D, X3, X2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	3	1	N/A
CCMP W10, #0, #4, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (25.0%)
B.EQ 5203e8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x1168>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X25, X14, #1, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ X0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X21, X25, #60, #59	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X13, X21, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X6, X13, #4, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X6, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ANDS X25, X10, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 520128 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xea8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 52010c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xe8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 5200f8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xe78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 5200e4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xe64>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 5200d0 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xe50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 5200bc <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xe3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 5205f8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x1378>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q7, [X3, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Q6, [X9, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STR Q7, [X2, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Q6, [X1, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ADD X0, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q17, [X3, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Q16, [X9, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STR Q17, [X2, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Q16, [X1, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ADD X0, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q19, [X3, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Q18, [X9, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STR Q19, [X2, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Q18, [X1, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ADD X0, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q21, [X3, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Q20, [X9, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STR Q21, [X2, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Q20, [X1, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ADD X0, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q23, [X3, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Q22, [X9, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STR Q23, [X2, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Q22, [X1, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ADD X0, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q25, [X3, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Q24, [X9, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STR Q25, [X2, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Q24, [X1, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ADD X0, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X0, X21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 5201d4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xf54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X25, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND X2, X14, #8127	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X15, X2, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TBZ W14, #0, 520568 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x12e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X14, X2, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X1, X15, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X0, [X3, X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X21, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D18, [X9, X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR X0, [X30, X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR D18, [X16, X1]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
B 51ff28 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xca8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X9, X12, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X12, X6, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X0, XZR, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X9, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X10, X2, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X13, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X5, X11, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X7, X8, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X18, X4, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
BL 546d88 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X7, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X7, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 546d88 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X12, X6, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ORR X9, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X10, X2, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X5, X11, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X7, X8, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X18, X4, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X3, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X12, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 51fd90 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [X1, X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 51ff28 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xca8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ANDS X13, X14, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
ADD X21, X30, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ X0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X25, X16, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B.EQ 5204c0 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x1240>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 5204a4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x1224>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 520490 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x1210>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 52047c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x11fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 520468 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x11e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 520454 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x11d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 520440 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x11c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D19, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
MOVZ X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X10, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [X30, X17]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR D19, [X16, X17]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D20, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X16, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X16, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR D20, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D21, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X30, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X30, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR D21, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D22, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X17, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X17, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR D22, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D23, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X6, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X6, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR D23, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D24, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X2, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR D24, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D25, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X15, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X15, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR D25, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X0, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 520568 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x12e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 51ff2c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xcac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q30, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
MOVZ X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q5, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STR Q30, [X30, X17]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Q5, [X16, X17]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
B 5200a8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xe28>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code