OV - exec - Loop 3131

	Loop Id: 3131	Module: exec	Source: par_csr_matop.c:865-989 [...]	Coverage: 0.02%

0x500424 LDR	X18, [SP, #168]

0x500428 ORR	X2, XZR, X20

0x50042c ORR	X9, XZR, X25

0x500430 CBNZ	X18, 500514

0x500434 LDP	X12, X4, [X10]

0x500438 CMP	X12, X4

0x50043c B.GE	5004c4

0x500440 LDP	X17, X18, [SP, #176]

0x500444 LDP	X13, X11, [SP, #192]

0x500448 STR	X8, [SP, #120]

  (3136) 0x50044c LDR	X23, [X16, X12,LSL #3]

  (3136) 0x500450 LDR	D28, [X13, X12,LSL #3]

  (3136) 0x500454 UBFM	X5, X23, #61, #60

  (3136) 0x500458 ADD	X8, X5, #8

  (3136) 0x50045c LDR	X1, [X27, X5]

  (3136) 0x500460 ADD	X15, X27, X8

  (3136) 0x500464 LDR	X14, [X27, X8]

  (3136) 0x500468 CMP	X1, X14

  (3136) 0x50046c B.GE	5004ac

    (3138) 0x500470 LDR	X4, [X21, X1,LSL #3]

    (3138) 0x500474 UBFM	X28, X2, #61, #60

    (3138) 0x500478 LDR	D6, [X22, X1,LSL #3]

    (3138) 0x50047c UBFM	X23, X4, #61, #60

    (3138) 0x500480 LDR	X3, [X0, X23]

    (3138) 0x500484 FMUL	D7, D28, D6

    (3138) 0x500488 UBFM	X30, X3, #61, #60

    (3138) 0x50048c CMP	X20, X3

    (3138) 0x500490 B.GT	500644

    (3138) 0x500494 LDR	D16, [X19, X30]

    (3138) 0x500498 ADD	X1, X1, #1

    (3138) 0x50049c FADD	D17, D16, D7

    (3138) 0x5004a0 STR	D17, [X19, X30]

    (3138) 0x5004a4 CMP	X1, X14

    (3138) 0x5004a8 B.LT	500470

  (3136) 0x5004ac CBNZ	X17, 500668

  (3136) 0x5004b0 LDR	X4, [X10, #8]

  (3136) 0x5004b4 ADD	X12, X12, #1

  (3136) 0x5004b8 CMP	X4, X12

  (3136) 0x5004bc B.GT	50044c

0x5004c0 LDR	X8, [SP, #120]

0x5004c4 ADD	X8, X8, #1

0x5004c8 ADD	X10, X10, #8

0x5004cc LDR	X20, [SP, #144]

0x5004d0 LDR	X17, [SP, #160]

0x5004d4 ADD	X25, X20, #8

0x5004d8 STR	X25, [SP, #144]

0x5004dc CMP	X17, X8

0x5004e0 B.EQ	500748

0x5004e4 LDR	X23, [SP, #152]

0x5004e8 ORR	X25, XZR, X9

0x5004ec ORR	X20, XZR, X2

0x5004f0 CBZ	X23, 500424

0x500514 LDR	X5, [SP, #144]

0x500518 LDP	X13, X3, [X5]

0x50051c CMP	X13, X3

0x500520 B.GE	500434

0x500524 LDR	X4, [SP, #112]

0x500528 LDP	X14, X15, [SP, #272]

0x50052c LDP	X18, X28, [SP, #296]

0x500530 STP	X22, X16, [SP, #240]

0x500534 ORR	X22, XZR, X10

0x500538 LDR	X23, [SP, #136]

0x50053c STP	X21, X27, [SP, #224]

0x500540 ORR	X21, XZR, X5

0x500544 ORR	X27, XZR, X8

0x500548 LDR	X17, [SP, #256]

0x50054c STP	X6, X7, [SP, #208]

0x500550 LDR	X10, [SP, #264]

0x500554 LDR	X16, [SP, #288]

0x500558 LDR	X3, [SP, #312]

0x50055c HINT	#0

  (3132) 0x500560 LDR	X6, [X15, X13,LSL #3]

  (3132) 0x500564 LDR	D31, [X16, X13,LSL #3]

  (3132) 0x500568 UBFM	X7, X6, #61, #60

  (3132) 0x50056c ADD	X8, X7, #8

  (3132) 0x500570 LDR	X1, [X10, X7]

  (3132) 0x500574 ADD	X12, X10, X8

  (3132) 0x500578 LDR	X11, [X10, X8]

  (3132) 0x50057c CMP	X1, X11

  (3132) 0x500580 B.GE	5005cc

  (3132) 0x500584 STP	X10, X28, [SP, #120]

    (3134) 0x500588 UBFM	X28, X9, #61, #60

    (3134) 0x50058c LDR	X10, [X17, X1,LSL #3]

    (3134) 0x500590 LDR	D1, [X18, X1,LSL #3]

    (3134) 0x500594 ADD	X30, X26, X10

    (3134) 0x500598 UBFM	X5, X30, #61, #60

    (3134) 0x50059c LDR	X6, [X0, X5]

    (3134) 0x5005a0 FMUL	D2, D31, D1

    (3134) 0x5005a4 UBFM	X30, X6, #61, #60

    (3134) 0x5005a8 CMP	X25, X6

    (3134) 0x5005ac B.GT	500724

    (3134) 0x5005b0 LDR	D0, [X23, X30]

    (3134) 0x5005b4 ADD	X1, X1, #1

    (3134) 0x5005b8 FADD	D3, D0, D2

    (3134) 0x5005bc STR	D3, [X23, X30]

    (3134) 0x5005c0 CMP	X1, X11

    (3134) 0x5005c4 B.LT	500588

  (3132) 0x5005c8 LDP	X10, X28, [SP, #120]

  (3132) 0x5005cc ADD	X12, X14, X8

  (3132) 0x5005d0 LDR	X1, [X14, X7]

  (3132) 0x5005d4 LDR	X30, [X14, X8]

  (3132) 0x5005d8 CMP	X1, X30

  (3132) 0x5005dc B.GE	50061c

    (3133) 0x5005e0 LDR	X6, [X28, X1,LSL #3]

    (3133) 0x5005e4 UBFM	X8, X2, #61, #60

    (3133) 0x5005e8 LDR	D30, [X3, X1,LSL #3]

    (3133) 0x5005ec UBFM	X7, X6, #61, #60

    (3133) 0x5005f0 LDR	X5, [X0, X7]

    (3133) 0x5005f4 FMUL	D4, D31, D30

    (3133) 0x5005f8 UBFM	X11, X5, #61, #60

    (3133) 0x5005fc CMP	X20, X5

    (3133) 0x500600 B.GT	5006f0

    (3133) 0x500604 LDR	D29, [X19, X11]

    (3133) 0x500608 ADD	X1, X1, #1

    (3133) 0x50060c FADD	D5, D29, D4

    (3133) 0x500610 STR	D5, [X19, X11]

    (3133) 0x500614 CMP	X1, X30

    (3133) 0x500618 B.LT	5005e0

  (3132) 0x50061c LDR	X12, [X21, #8]

  (3132) 0x500620 ADD	X13, X13, #1

  (3132) 0x500624 CMP	X12, X13

  (3132) 0x500628 B.GT	500560

0x50062c ORR	X8, XZR, X27

0x500630 ORR	X10, XZR, X22

0x500634 LDP	X6, X7, [SP, #208]

0x500638 LDP	X21, X27, [SP, #224]

0x50063c LDP	X22, X16, [SP, #240]

0x500640 B	500434

    (3138) 0x500644 STR	X2, [X0, X23]

    (3138) 0x500648 ADD	X1, X1, #1

    (3138) 0x50064c ADD	X2, X2, #1

    (3138) 0x500650 STR	D7, [X19, X28]

    (3138) 0x500654 STR	X4, [X24, X28]

    (3138) 0x500658 LDR	X14, [X15]

    (3138) 0x50065c CMP	X14, X1

    (3138) 0x500660 B.GT	500470

  (3136) 0x500664 CBZ	X17, 5004b0

  (3136) 0x500668 LDR	X1, [X18, X5]

  (3136) 0x50066c ADD	X4, X18, X8

  (3136) 0x500670 LDR	X30, [X18, X8]

  (3136) 0x500674 CMP	X1, X30

  (3136) 0x500678 B.GE	5004b0

  (3136) 0x50067c LDR	X28, [SP, #136]

    (3137) 0x500680 UBFM	X23, X9, #61, #60

    (3137) 0x500684 LDR	X5, [X6, X1,LSL #3]

    (3137) 0x500688 LDR	D27, [X7, X1,LSL #3]

    (3137) 0x50068c LDR	X8, [X11, X5,LSL #3]

    (3137) 0x500690 FMUL	D18, D28, D27

    (3137) 0x500694 ADD	X15, X26, X8

    (3137) 0x500698 UBFM	X3, X15, #61, #60

    (3137) 0x50069c LDR	X14, [X0, X3]

    (3137) 0x5006a0 UBFM	X5, X14, #61, #60

    (3137) 0x5006a4 CMP	X25, X14

    (3137) 0x5006a8 B.GT	5006c8

    (3137) 0x5006ac LDR	D26, [X28, X5]

    (3137) 0x5006b0 ADD	X1, X1, #1

    (3137) 0x5006b4 FADD	D19, D26, D18

    (3137) 0x5006b8 STR	D19, [X28, X5]

    (3137) 0x5006bc CMP	X1, X30

    (3137) 0x5006c0 B.LT	500680

  (3136) 0x5006c4 B	5004b0

    (3137) 0x5006c8 LDR	X30, [SP, #112]

    (3137) 0x5006cc ADD	X1, X1, #1

    (3137) 0x5006d0 STR	X9, [X0, X3]

    (3137) 0x5006d4 ADD	X9, X9, #1

    (3137) 0x5006d8 STR	D18, [X28, X23]

    (3137) 0x5006dc STR	X8, [X30, X23]

    (3137) 0x5006e0 LDR	X30, [X4]

    (3137) 0x5006e4 CMP	X30, X1

    (3137) 0x5006e8 B.GT	500680

  (3136) 0x5006ec B	5004b0

    (3133) 0x5006f0 STR	X2, [X0, X7]

    (3133) 0x5006f4 ADD	X1, X1, #1

    (3133) 0x5006f8 ADD	X2, X2, #1

    (3133) 0x5006fc STR	D4, [X19, X8]

    (3133) 0x500700 STR	X6, [X24, X8]

    (3133) 0x500704 LDR	X30, [X12]

    (3133) 0x500708 CMP	X30, X1

    (3133) 0x50070c B.GT	5005e0

  (3132) 0x500710 LDR	X12, [X21, #8]

  (3132) 0x500714 ADD	X13, X13, #1

  (3132) 0x500718 CMP	X12, X13

  (3132) 0x50071c B.GT	500560

0x500720 B	50062c

    (3134) 0x500724 STR	X9, [X0, X5]

    (3134) 0x500728 ADD	X1, X1, #1

    (3134) 0x50072c ADD	X9, X9, #1

    (3134) 0x500730 STR	D2, [X23, X28]

    (3134) 0x500734 STR	X10, [X4, X28]

    (3134) 0x500738 LDR	X11, [X12]

    (3134) 0x50073c CMP	X11, X1

    (3134) 0x500740 B.GT	500588

  (3132) 0x500744 B	5005c8

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 865 - 989

--------------------------------------------------------------------------------

865:     for (i1 = ns; i1 < ne; i1++)

[...]

874:       if ( allsquare )

[...]

886:       if (num_cols_offd_A)

887:       {

888:          for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++)

889:          {

890:             i2 = A_offd_j[jj2];

891:             a_entry = A_offd_data[jj2];

[...]

897:             for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++)

898:             {

899:                i3 = num_cols_diag_B+B_ext_offd_j[jj3];

[...]

907:                if (B_marker[i3] < jj_row_begin_offd)

908:                {

909:                   B_marker[i3] = jj_count_offd;

910:                   C_offd_data[jj_count_offd] = a_entry*B_ext_offd_data[jj3];

911:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

912:                   jj_count_offd++;

913:                }

914:                else

915:                   C_offd_data[B_marker[i3]] += a_entry*B_ext_offd_data[jj3];

916:             }

917:             for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++)

918:             {

919:                i3 = B_ext_diag_j[jj3];

920:                if (B_marker[i3] < jj_row_begin_diag)

921:                {

922:                   B_marker[i3] = jj_count_diag;

923:                   C_diag_data[jj_count_diag] = a_entry*B_ext_diag_data[jj3];

924:                   C_diag_j[jj_count_diag] = i3;

925:                   jj_count_diag++;

926:                }

927:                else

928:                   C_diag_data[B_marker[i3]] += a_entry*B_ext_diag_data[jj3];

[...]

937:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

938:       {

939:          i2 = A_diag_j[jj2];

940:          a_entry = A_diag_data[jj2];

[...]

946:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

947:          {

948:             i3 = B_diag_j[jj3];

[...]

956:             if (B_marker[i3] < jj_row_begin_diag)

957:             {

958:                B_marker[i3] = jj_count_diag;

959:                C_diag_data[jj_count_diag] = a_entry*B_diag_data[jj3];

960:                C_diag_j[jj_count_diag] = i3;

961:                jj_count_diag++;

962:             }

963:             else

964:             {

965:                C_diag_data[B_marker[i3]] += a_entry*B_diag_data[jj3];

966:             }

967:          }

968:          if (num_cols_offd_B)

969:          {

970:             for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++)

971:             {

972:                i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]];

[...]

980:                if (B_marker[i3] < jj_row_begin_offd)

981:                {

982:                   B_marker[i3] = jj_count_offd;

983:                   C_offd_data[jj_count_offd] = a_entry*B_offd_data[jj3];

984:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

985:                   jj_count_offd++;

986:                }

987:                else

988:                {

989:                   C_offd_data[B_marker[i3]] += a_entry*B_offd_data[jj3];

Coverage (%)	Name	Source Location	Module
►100.00+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.29
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P12,
Function	hypre_ParMatmul._omp_fn.3
Source	par_csr_matop.c:865-865,par_csr_matop.c:874-874,par_csr_matop.c:886-888,par_csr_matop.c:937-937
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.83
CQA cycles if no scalar integer	8.83
CQA cycles if FP arith vectorized	8.83
CQA cycles if fully vectorized	6.83
Front-end cycles	6.00
P0 cycles	3.50
P1 cycles	3.50
P2 cycles	2.58
P3 cycles	2.58
P4 cycles	2.50
P5 cycles	2.50
P6 cycles	2.42
P7 cycles	2.42
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	8.83
P13 cycles	8.50
P14 cycles	8.67
P15 cycles	2.50
P16 cycles	2.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	49.00
Nb uops	48.00
Nb loads	NA
Nb stores	5.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	34.42
Bytes prefetched	0.00
Bytes loaded	240.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	65.15
Vector-efficiency ratio load	71.88
Vector-efficiency ratio store	80.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.29
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P12,
Function	hypre_ParMatmul._omp_fn.3
Source	par_csr_matop.c:865-865,par_csr_matop.c:874-874,par_csr_matop.c:886-888,par_csr_matop.c:937-937
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.83
CQA cycles if no scalar integer	8.83
CQA cycles if FP arith vectorized	8.83
CQA cycles if fully vectorized	6.83
Front-end cycles	6.00
P0 cycles	3.50
P1 cycles	3.50
P2 cycles	2.58
P3 cycles	2.58
P4 cycles	2.50
P5 cycles	2.50
P6 cycles	2.42
P7 cycles	2.42
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	8.83
P13 cycles	8.50
P14 cycles	8.67
P15 cycles	2.50
P16 cycles	2.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	49.00
Nb uops	48.00
Nb loads	NA
Nb stores	5.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	34.42
Bytes prefetched	0.00
Bytes loaded	240.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	65.15
Vector-efficiency ratio load	71.88
Vector-efficiency ratio store	80.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParMatmul._omp_fn.3
Source file and lines	par_csr_matop.c:865-989
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:865,874,886-891,897-899,907-928,937-940,946-948,956-972,980-989.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:865,874,886-888,937.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 65% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 8.83 to 6.83 cycles (1.29x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 240 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	49
loop length	196
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	2.58	2.58	2.50	2.50	2.42	2.42	0.00	0.00	0.00	0.00	8.83	8.50	8.67	2.50	2.50
cycles	3.50	3.50	2.58	2.58	2.50	2.50	2.42	2.42	0.00	0.00	0.00	0.00	8.83	8.50	8.67	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.00
Overall L1	8.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.83 cycles. At this rate:

28% of peak load performance is reached (27.17 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
15% of peak store performance is reached (7.25 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 500434

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR X18, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X2, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X9, XZR, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CBNZ X18, 500514 <hypre_ParMatmul._omp_fn.3+0x254>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X12, X4, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
CMP X12, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 5004c4 <hypre_ParMatmul._omp_fn.3+0x204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X17, X18, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X13, X11, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X8, X8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X10, X10, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X20, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X17, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X25, X20, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X25, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X17, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 500748 <hypre_ParMatmul._omp_fn.3+0x488>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X23, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X25, XZR, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X20, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CBZ X23, 500424 <hypre_ParMatmul._omp_fn.3+0x164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X13, X3, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
CMP X13, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.GE 500434 <hypre_ParMatmul._omp_fn.3+0x174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X14, X15, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X18, X28, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STP X22, X16, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X22, XZR, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X23, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STP X21, X27, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X21, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X27, XZR, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X17, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STP X6, X7, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X10, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X3, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
HINT #0																					N/A
ORR X8, XZR, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X10, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X6, X7, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X21, X27, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X22, X16, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
B 500434 <hypre_ParMatmul._omp_fn.3+0x174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 50062c <hypre_ParMatmul._omp_fn.3+0x36c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_ParMatmul._omp_fn.3
Source file and lines	par_csr_matop.c:865-989
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 240 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	49
loop length	196
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	2.58	2.58	2.50	2.50	2.42	2.42	0.00	0.00	0.00	0.00	8.83	8.50	8.67	2.50	2.50
cycles	3.50	3.50	2.58	2.58	2.50	2.50	2.42	2.42	0.00	0.00	0.00	0.00	8.83	8.50	8.67	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.00
Overall L1	8.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.83 cycles. At this rate:

28% of peak load performance is reached (27.17 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
15% of peak store performance is reached (7.25 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 500434

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR X18, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X2, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X9, XZR, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CBNZ X18, 500514 <hypre_ParMatmul._omp_fn.3+0x254>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X12, X4, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
CMP X12, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 5004c4 <hypre_ParMatmul._omp_fn.3+0x204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X17, X18, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X13, X11, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X8, X8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X10, X10, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X20, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X17, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X25, X20, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X25, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X17, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 500748 <hypre_ParMatmul._omp_fn.3+0x488>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X23, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X25, XZR, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X20, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CBZ X23, 500424 <hypre_ParMatmul._omp_fn.3+0x164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X13, X3, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
CMP X13, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.GE 500434 <hypre_ParMatmul._omp_fn.3+0x174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X14, X15, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X18, X28, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STP X22, X16, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X22, XZR, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X23, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STP X21, X27, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X21, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X27, XZR, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X17, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STP X6, X7, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X10, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X3, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
HINT #0																					N/A
ORR X8, XZR, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X10, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X6, X7, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X21, X27, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X22, X16, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
B 500434 <hypre_ParMatmul._omp_fn.3+0x174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 50062c <hypre_ParMatmul._omp_fn.3+0x36c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code