OV - exec - Loop 3121

	Loop Id: 3121	Module: exec	Source: par_csr_matop.c:127-242 [...]	Coverage: 0.02%

0x4ff2d4 ORR	X3, XZR, X20

0x4ff2d8 LDR	X18, [SP, #112]

0x4ff2dc CBNZ	X18, 4ff3b0

0x4ff2e4 LDR	X17, [X28, X2,LSL #3]

0x4ff2e8 ORR	X7, XZR, X25

0x4ff2ec LDR	X12, [X28, X15]

0x4ff2f0 CMP	X17, X12

0x4ff2f4 B.GE	4ff374

0x4ff2f8 HINT	#0

0x4ff2fc HINT	#0

  (3125) 0x4ff300 LDR	X25, [X6, X17,LSL #3]

  (3125) 0x4ff304 UBFM	X18, X25, #61, #60

  (3125) 0x4ff308 ADD	X30, X18, #8

  (3125) 0x4ff30c LDR	X12, [X23, X18]

  (3125) 0x4ff310 ADD	X25, X23, X30

  (3125) 0x4ff314 LDR	X16, [X23, X30]

  (3125) 0x4ff318 CMP	X12, X16

  (3125) 0x4ff31c B.GE	4ff35c

  (3125) 0x4ff320 ORR	X13, XZR, X5

  (3125) 0x4ff324 STR	X0, [SP, #104]

    (3128) 0x4ff328 LDR	X0, [X21, X12,LSL #3]

    (3128) 0x4ff32c UBFM	X5, X0, #61, #60

    (3128) 0x4ff330 LDR	X0, [X19, X5]

    (3128) 0x4ff334 CMP	X20, X0

    (3128) 0x4ff338 B.LE	4ff484

    (3128) 0x4ff33c STR	X3, [X19, X5]

    (3128) 0x4ff340 ADD	X12, X12, #1

    (3128) 0x4ff344 ADD	X3, X3, #1

    (3128) 0x4ff348 LDR	X16, [X25]

    (3128) 0x4ff34c CMP	X16, X12

    (3128) 0x4ff350 B.GT	4ff328

  (3125) 0x4ff354 LDR	X0, [SP, #104]

  (3125) 0x4ff358 ORR	X5, XZR, X13

  (3125) 0x4ff35c CBNZ	X5, 4ff4cc

  (3125) 0x4ff360 LDR	X18, [X28, X15]

  (3125) 0x4ff364 ADD	X17, X17, #1

  (3125) 0x4ff368 CMP	X18, X17

  (3125) 0x4ff36c B.GT	4ff300

0x4ff370 ORR	X25, XZR, X7

0x4ff374 STR	X20, [X0, X2,LSL #3]

0x4ff378 ADD	X15, X15, #8

0x4ff37c LDR	X20, [SP, #120]

0x4ff380 STR	X14, [X1, X2,LSL #3]

0x4ff384 ADD	X2, X2, #1

0x4ff388 CMP	X20, X2

0x4ff38c B.EQ	4ff540

0x4ff390 LDR	X13, [SP, #128]

0x4ff394 ORR	X14, XZR, X11

0x4ff398 ORR	X20, XZR, X3

0x4ff39c CBZ	X13, 4ff2d4

0x4ff3b0 LDR	X30, [X10, X2,LSL #3]

0x4ff3b4 LDR	X12, [X10, X15]

0x4ff3b8 CMP	X30, X12

0x4ff3bc B.GE	4ff2e0

0x4ff3c0 LDR	X7, [SP, #184]

0x4ff3c4 ORR	X11, XZR, X14

0x4ff3c8 STP	X5, X24, [SP, #144]

  (3120) 0x4ff3cc LDR	X24, [X4, X30,LSL #3]

  (3120) 0x4ff3d0 UBFM	X5, X24, #61, #60

  (3120) 0x4ff3d4 ADD	X24, X5, #8

  (3120) 0x4ff3d8 LDR	X12, [X7, X5]

  (3120) 0x4ff3dc ADD	X17, X7, X24

  (3120) 0x4ff3e0 LDR	X16, [X7, X24]

  (3120) 0x4ff3e4 CMP	X12, X16

  (3120) 0x4ff3e8 B.GE	4ff424

  (3120) 0x4ff3ec STR	X0, [SP, #104]

    (3123) 0x4ff3f0 LDR	X0, [X25, X12,LSL #3]

    (3123) 0x4ff3f4 ADD	X13, X22, X0

    (3123) 0x4ff3f8 UBFM	X18, X13, #61, #60

    (3123) 0x4ff3fc LDR	X0, [X19, X18]

    (3123) 0x4ff400 CMP	X14, X0

    (3123) 0x4ff404 B.LE	4ff49c

    (3123) 0x4ff408 STR	X11, [X19, X18]

    (3123) 0x4ff40c ADD	X12, X12, #1

    (3123) 0x4ff410 ADD	X11, X11, #1

    (3123) 0x4ff414 LDR	X16, [X17]

    (3123) 0x4ff418 CMP	X12, X16

    (3123) 0x4ff41c B.LT	4ff3f0

  (3120) 0x4ff420 LDR	X0, [SP, #104]

  (3120) 0x4ff424 LDR	X13, [X8, X5]

  (3120) 0x4ff428 ADD	X5, X8, X24

  (3120) 0x4ff42c LDR	X18, [X8, X24]

  (3120) 0x4ff430 CMP	X13, X18

  (3120) 0x4ff434 B.GE	4ff46c

  (3120) 0x4ff438 HINT	#0

  (3120) 0x4ff43c HINT	#0

    (3122) 0x4ff440 LDR	X24, [X26, X13,LSL #3]

    (3122) 0x4ff444 UBFM	X17, X24, #61, #60

    (3122) 0x4ff448 LDR	X12, [X19, X17]

    (3122) 0x4ff44c CMP	X20, X12

    (3122) 0x4ff450 B.LE	4ff4ac

    (3122) 0x4ff454 STR	X3, [X19, X17]

    (3122) 0x4ff458 ADD	X13, X13, #1

    (3122) 0x4ff45c ADD	X3, X3, #1

    (3122) 0x4ff460 LDR	X18, [X5]

    (3122) 0x4ff464 CMP	X18, X13

    (3122) 0x4ff468 B.GT	4ff440

  (3120) 0x4ff46c LDR	X16, [X10, X15]

  (3120) 0x4ff470 ADD	X30, X30, #1

  (3120) 0x4ff474 CMP	X16, X30

  (3120) 0x4ff478 B.GT	4ff3cc

0x4ff47c LDP	X5, X24, [SP, #144]

0x4ff480 B	4ff2e4

    (3128) 0x4ff484 ADD	X12, X12, #1

    (3128) 0x4ff488 CMP	X12, X16

    (3128) 0x4ff48c B.LT	4ff328

  (3125) 0x4ff490 LDR	X0, [SP, #104]

  (3125) 0x4ff494 ORR	X5, XZR, X13

  (3125) 0x4ff498 B	4ff35c

    (3123) 0x4ff49c ADD	X12, X12, #1

    (3123) 0x4ff4a0 CMP	X12, X16

    (3123) 0x4ff4a4 B.LT	4ff3f0

  (3120) 0x4ff4a8 B	4ff420

    (3122) 0x4ff4ac ADD	X13, X13, #1

    (3122) 0x4ff4b0 CMP	X13, X18

    (3122) 0x4ff4b4 B.LT	4ff440

  (3120) 0x4ff4b8 LDR	X16, [X10, X15]

  (3120) 0x4ff4bc ADD	X30, X30, #1

  (3120) 0x4ff4c0 CMP	X16, X30

  (3120) 0x4ff4c4 B.GT	4ff3cc

0x4ff4c8 B	4ff47c

  (3125) 0x4ff4cc LDR	X13, [X9, X18]

  (3125) 0x4ff4d0 ADD	X18, X9, X30

  (3125) 0x4ff4d4 LDR	X25, [X9, X30]

  (3125) 0x4ff4d8 CMP	X13, X25

  (3125) 0x4ff4dc B.GE	4ff360

    (3126) 0x4ff4e0 LDR	X30, [X27, X13,LSL #3]

    (3126) 0x4ff4e4 LDR	X12, [X24, X30,LSL #3]

    (3126) 0x4ff4e8 ADD	X16, X22, X12

    (3126) 0x4ff4ec UBFM	X30, X16, #61, #60

    (3126) 0x4ff4f0 LDR	X12, [X19, X30]

    (3126) 0x4ff4f4 CMP	X14, X12

    (3126) 0x4ff4f8 B.LE	4ff530

    (3127) 0x4ff4fc STR	X11, [X19, X30]

    (3127) 0x4ff500 ADD	X13, X13, #1

    (3127) 0x4ff504 ADD	X11, X11, #1

    (3127) 0x4ff508 LDR	X25, [X18]

    (3127) 0x4ff50c CMP	X25, X13

    (3127) 0x4ff510 B.LE	4ff360

    (3127) 0x4ff514 LDR	X30, [X27, X13,LSL #3]

    (3127) 0x4ff518 LDR	X12, [X24, X30,LSL #3]

    (3127) 0x4ff51c ADD	X16, X22, X12

    (3127) 0x4ff520 UBFM	X30, X16, #61, #60

    (3127) 0x4ff524 LDR	X12, [X19, X30]

    (3127) 0x4ff528 CMP	X14, X12

    (3127) 0x4ff52c B.GT	4ff4fc

    (3126) 0x4ff530 ADD	X13, X13, #1

    (3126) 0x4ff534 CMP	X25, X13

    (3126) 0x4ff538 B.GT	4ff4e0

  (3125) 0x4ff53c B	4ff360

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 127 - 242

--------------------------------------------------------------------------------

127:     for (i1 = ns; i1 < ne; i1++)

[...]

135:       if ( allsquare ) {

[...]

144:       if (num_cols_offd_A)

145:       {

146:          for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++)

[...]

154:             for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++)

155:             {

156:                i3 = num_cols_diag_B+B_ext_offd_j[jj3];

[...]

164:                if (B_marker[i3] < jj_row_begin_offd)

165:                {

166:                   B_marker[i3] = jj_count_offd;

167:                   jj_count_offd++;

168:                }

169:             }

170:             for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++)

171:             {

172:                i3 = B_ext_diag_j[jj3];

173:

174:                if (B_marker[i3] < jj_row_begin_diag)

175:                {

176:                   B_marker[i3] = jj_count_diag;

177:                   jj_count_diag++;

[...]

187:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

[...]

195:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

[...]

205:             if (B_marker[i3] < jj_row_begin_diag)

206:             {

207:                B_marker[i3] = jj_count_diag;

208:                jj_count_diag++;

[...]

216:          if (num_cols_offd_B)

217:          {

218:             for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++)

219:             {

220:                i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]];

[...]

228:                if (B_marker[i3] < jj_row_begin_offd)

229:                {

230:                   B_marker[i3] = jj_count_offd;

231:                   jj_count_offd++;

[...]

241:       (*C_diag_i)[i1] = jj_row_begin_diag;

242:       (*C_offd_i)[i1] = jj_row_begin_offd;

Coverage (%)	Name	Source Location	Module
►100.00+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.19
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	P12,
Function	hypre_ParMatmul_RowSizes._omp_fn.0
Source	par_csr_matop.c:127-127,par_csr_matop.c:135-135,par_csr_matop.c:144-146,par_csr_matop.c:187-187,par_csr_matop.c:241-242
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.17
CQA cycles if no scalar integer	4.17
CQA cycles if FP arith vectorized	4.17
CQA cycles if fully vectorized	3.50
Front-end cycles	3.75
P0 cycles	3.50
P1 cycles	3.50
P2 cycles	1.92
P3 cycles	1.92
P4 cycles	1.83
P5 cycles	1.83
P6 cycles	1.75
P7 cycles	1.75
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	4.17
P13 cycles	3.83
P14 cycles	4.00
P15 cycles	1.50
P16 cycles	1.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	32.00
Nb uops	30.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	26.88
Bytes prefetched	0.00
Bytes loaded	80.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	55.88
Vector-efficiency ratio load	58.33
Vector-efficiency ratio store	66.67
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.19
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	P12,
Function	hypre_ParMatmul_RowSizes._omp_fn.0
Source	par_csr_matop.c:127-127,par_csr_matop.c:135-135,par_csr_matop.c:144-146,par_csr_matop.c:187-187,par_csr_matop.c:241-242
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.17
CQA cycles if no scalar integer	4.17
CQA cycles if FP arith vectorized	4.17
CQA cycles if fully vectorized	3.50
Front-end cycles	3.75
P0 cycles	3.50
P1 cycles	3.50
P2 cycles	1.92
P3 cycles	1.92
P4 cycles	1.83
P5 cycles	1.83
P6 cycles	1.75
P7 cycles	1.75
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	4.17
P13 cycles	3.83
P14 cycles	4.00
P15 cycles	1.50
P16 cycles	1.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	32.00
Nb uops	30.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	26.88
Bytes prefetched	0.00
Bytes loaded	80.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	55.88
Vector-efficiency ratio load	58.33
Vector-efficiency ratio store	66.67
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParMatmul_RowSizes._omp_fn.0
Source file and lines	par_csr_matop.c:127-242
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:127,135,144-146,154-156,164-177,187,195,205-208,216-220,228-231,241-242.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:127,135,144-146,187,241-242.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 55% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 4.17 to 3.50 cycles (1.19x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 80 bytes. The binary loop is storing 32 bytes.

General properties

nb instructions	32
loop length	128
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	1.92	1.92	1.83	1.83	1.75	1.75	0.00	0.00	0.00	0.00	4.17	3.83	4.00	1.50	1.50
cycles	3.50	3.50	1.92	1.92	1.83	1.83	1.75	1.75	0.00	0.00	0.00	0.00	4.17	3.83	4.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.75
Overall L1	4.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.17 cycles. At this rate:

20% of peak load performance is reached (19.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (7.68 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4ff2e4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
ORR X3, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X18, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CBNZ X18, 4ff3b0 <hypre_ParMatmul_RowSizes._omp_fn.0+0x1f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [X28, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X7, XZR, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X12, [X28, X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X17, X12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4ff374 <hypre_ParMatmul_RowSizes._omp_fn.0+0x1b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
ORR X25, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X20, [X0, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X15, X15, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X20, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X14, [X1, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X20, X2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4ff540 <hypre_ParMatmul_RowSizes._omp_fn.0+0x380>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X14, XZR, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X20, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CBZ X13, 4ff2d4 <hypre_ParMatmul_RowSizes._omp_fn.0+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [X10, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X10, X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X30, X12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.GE 4ff2e0 <hypre_ParMatmul_RowSizes._omp_fn.0+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X7, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X11, XZR, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X5, X24, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X5, X24, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
B 4ff2e4 <hypre_ParMatmul_RowSizes._omp_fn.0+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4ff47c <hypre_ParMatmul_RowSizes._omp_fn.0+0x2bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_ParMatmul_RowSizes._omp_fn.0
Source file and lines	par_csr_matop.c:127-242
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 80 bytes. The binary loop is storing 32 bytes.

General properties

nb instructions	32
loop length	128
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	1.92	1.92	1.83	1.83	1.75	1.75	0.00	0.00	0.00	0.00	4.17	3.83	4.00	1.50	1.50
cycles	3.50	3.50	1.92	1.92	1.83	1.83	1.75	1.75	0.00	0.00	0.00	0.00	4.17	3.83	4.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.75
Overall L1	4.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.17 cycles. At this rate:

20% of peak load performance is reached (19.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (7.68 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4ff2e4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
ORR X3, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X18, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CBNZ X18, 4ff3b0 <hypre_ParMatmul_RowSizes._omp_fn.0+0x1f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [X28, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X7, XZR, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X12, [X28, X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X17, X12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4ff374 <hypre_ParMatmul_RowSizes._omp_fn.0+0x1b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
ORR X25, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X20, [X0, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X15, X15, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X20, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X14, [X1, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X20, X2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4ff540 <hypre_ParMatmul_RowSizes._omp_fn.0+0x380>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X14, XZR, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X20, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CBZ X13, 4ff2d4 <hypre_ParMatmul_RowSizes._omp_fn.0+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [X10, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X10, X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X30, X12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.GE 4ff2e0 <hypre_ParMatmul_RowSizes._omp_fn.0+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X7, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X11, XZR, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X5, X24, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X5, X24, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
B 4ff2e4 <hypre_ParMatmul_RowSizes._omp_fn.0+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4ff47c <hypre_ParMatmul_RowSizes._omp_fn.0+0x2bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code