OV - exec - Loop 2687

	Loop Id: 2687	Module: exec	Source: ams.c:3662-3682 [...]	Coverage: 23.47%

0x4ddd98 ADD	X1, X1, #1

0x4ddd9c CMP	X8, X1

0x4ddda0 B.EQ	4de1e8

0x4ddda4 LDR	X5, [X9, X1,LSL #3]

0x4ddda8 UBFM	X0, X5, #61, #60

0x4dddac ADD	X30, X6, X5,LSL #3

0x4dddb0 LDR	D6, [X6, X0]

0x4dddb4 FCMP	D31, D6

0x4dddb8 B.EQ	4ddd98

0x4dddbc LDR	X21, [X18, X1,LSL #3]

0x4dddc0 LDR	D0, [X15, X1,LSL #3]

0x4dddc4 CMP	X5, X21

0x4dddc8 B.GE	4ddfc0

0x4dddcc SUB	X20, X21, X5

0x4dddd0 SUB	X2, X20, #1

0x4dddd4 CMP	X2, #3

0x4dddd8 B.LS	4ddf50

0x4ddddc UBFM	X19, X20, #2, #63

0x4ddde0 ADD	X0, X12, X0

0x4ddde4 DUP	Z27.D, #0

0x4ddde8 ORR	Z18.D, Z27.D, Z27.D

0x4dddec UBFM	X7, X19, #59, #58

0x4dddf0 ORR	X2, XZR, X30

0x4dddf4 ADD	X19, X0, X19,LSL #5

0x4dddf8 SUB	X7, X7, #32

0x4dddfc UBFM	X7, X7, #5, #63

0x4dde00 ADD	X7, X7, #1

0x4dde04 ANDS	X7, X7, #4160

0x4dde08 B.EQ	4ddea0

0x4dde0c CMP	X7, #1

0x4dde10 B.EQ	4dde70

0x4dde14 CMP	X7, #2

0x4dde18 B.EQ	4dde48

0x4dde1c LD1D	{Z23.D}, P7/Z, [X0, MUL VL]

0x4dde20 LD1D	{Z4.D}, P7/Z, [X0, #1, MUL VL]

0x4dde24 ADD	X2, X30, #32

0x4dde28 ADD	X0, X0, #32

0x4dde2c LD1D	{Z22.D}, P7/Z, [X3, Z23.D,LSL #3]

0x4dde30 LD1D	{Z5.D}, P7/Z, [X30, MUL VL]

0x4dde34 LD1D	{Z20.D}, P7/Z, [X3, Z4.D,LSL #3]

0x4dde38 MOVPRFX	Z18, Z27

0x4dde3c FMLS	Z18.D, P7/M, Z5.D, Z22.D

0x4dde40 LD1D	{Z24.D}, P7/Z, [X30, #1, MUL VL]

0x4dde44 FMLS	Z27.D, P7/M, Z24.D, Z20.D

0x4dde48 LD1D	{Z2.D}, P7/Z, [X0, MUL VL]

0x4dde4c LD1D	{Z16.D}, P7/Z, [X2, MUL VL]

0x4dde50 LD1D	{Z19.D}, P7/Z, [X0, #1, MUL VL]

0x4dde54 LD1D	{Z3.D}, P7/Z, [X2, #1, MUL VL]

0x4dde58 ADD	X0, X0, #32

0x4dde5c ADD	X2, X2, #32

0x4dde60 LD1D	{Z1.D}, P7/Z, [X3, Z2.D,LSL #3]

0x4dde64 LD1D	{Z17.D}, P7/Z, [X3, Z19.D,LSL #3]

0x4dde68 FMLS	Z18.D, P7/M, Z16.D, Z1.D

0x4dde6c FMLS	Z27.D, P7/M, Z3.D, Z17.D

0x4dde70 LD1D	{Z25.D}, P7/Z, [X0, MUL VL]

0x4dde74 LD1D	{Z21.D}, P7/Z, [X0, #1, MUL VL]

0x4dde78 ADD	X0, X0, #32

0x4dde7c LD1D	{Z7.D}, P7/Z, [X2, MUL VL]

0x4dde80 LD1D	{Z29.D}, P7/Z, [X2, #1, MUL VL]

0x4dde84 LD1D	{Z26.D}, P7/Z, [X3, Z25.D,LSL #3]

0x4dde88 LD1D	{Z28.D}, P7/Z, [X3, Z21.D,LSL #3]

0x4dde8c ADD	X2, X2, #32

0x4dde90 FMLS	Z18.D, P7/M, Z7.D, Z26.D

0x4dde94 FMLS	Z27.D, P7/M, Z29.D, Z28.D

0x4dde98 CMP	X19, X0

0x4dde9c B.EQ	4ddf30

  (2689) 0x4ddea0 LD1D	{Z6.D}, P7/Z, [X2, MUL VL]

  (2689) 0x4ddea4 LD1D	{Z5.D}, P7/Z, [X2, #3, MUL VL]

  (2689) 0x4ddea8 LD1D	{Z23.D}, P7/Z, [X0, MUL VL]

  (2689) 0x4ddeac LD1D	{Z4.D}, P7/Z, [X0, #2, MUL VL]

  (2689) 0x4ddeb0 LD1D	{Z22.D}, P7/Z, [X3, Z23.D,LSL #3]

  (2689) 0x4ddeb4 LD1D	{Z24.D}, P7/Z, [X0, #1, MUL VL]

  (2689) 0x4ddeb8 LD1D	{Z3.D}, P7/Z, [X0, #4, MUL VL]

  (2689) 0x4ddebc LD1D	{Z1.D}, P7/Z, [X0, #3, MUL VL]

  (2689) 0x4ddec0 LD1D	{Z17.D}, P7/Z, [X0, #6, MUL VL]

  (2689) 0x4ddec4 LD1D	{Z21.D}, P7/Z, [X0, #5, MUL VL]

  (2689) 0x4ddec8 LD1D	{Z26.D}, P7/Z, [X0, #7, MUL VL]

  (2689) 0x4ddecc ADD	X0, X0, #128

  (2689) 0x4dded0 FMLS	Z18.D, P7/M, Z6.D, Z22.D

  (2689) 0x4dded4 LD1D	{Z20.D}, P7/Z, [X3, Z4.D,LSL #3]

  (2689) 0x4dded8 LD1D	{Z2.D}, P7/Z, [X2, #2, MUL VL]

  (2689) 0x4ddedc LD1D	{Z16.D}, P7/Z, [X2, #1, MUL VL]

  (2689) 0x4ddee0 LD1D	{Z28.D}, P7/Z, [X2, #4, MUL VL]

  (2689) 0x4ddee4 LD1D	{Z6.D}, P7/Z, [X2, #6, MUL VL]

  (2689) 0x4ddee8 LD1D	{Z22.D}, P7/Z, [X2, #7, MUL VL]

  (2689) 0x4ddeec LD1D	{Z19.D}, P7/Z, [X3, Z24.D,LSL #3]

  (2689) 0x4ddef0 LD1D	{Z25.D}, P7/Z, [X3, Z1.D,LSL #3]

  (2689) 0x4ddef4 FMLS	Z27.D, P7/M, Z16.D, Z19.D

  (2689) 0x4ddef8 FMLS	Z18.D, P7/M, Z2.D, Z20.D

  (2689) 0x4ddefc FMLS	Z27.D, P7/M, Z5.D, Z25.D

  (2689) 0x4ddf00 LD1D	{Z7.D}, P7/Z, [X3, Z3.D,LSL #3]

  (2689) 0x4ddf04 LD1D	{Z5.D}, P7/Z, [X2, #5, MUL VL]

  (2689) 0x4ddf08 LD1D	{Z29.D}, P7/Z, [X3, Z17.D,LSL #3]

  (2689) 0x4ddf0c FMLS	Z18.D, P7/M, Z28.D, Z7.D

  (2689) 0x4ddf10 LD1D	{Z23.D}, P7/Z, [X3, Z21.D,LSL #3]

  (2689) 0x4ddf14 LD1D	{Z4.D}, P7/Z, [X3, Z26.D,LSL #3]

  (2689) 0x4ddf18 FMLS	Z27.D, P7/M, Z5.D, Z23.D

  (2689) 0x4ddf1c ADD	X2, X2, #128

  (2689) 0x4ddf20 FMLS	Z18.D, P7/M, Z6.D, Z29.D

  (2689) 0x4ddf24 FMLS	Z27.D, P7/M, Z22.D, Z4.D

  (2689) 0x4ddf28 CMP	X19, X0

  (2689) 0x4ddf2c B.NE	4ddea0

0x4ddf30 FADD	Z27.D, Z18.D, Z27.D

0x4ddf34 FADDV	D18, P7, Z27.D

0x4ddf38 FADD	D0, D0, D18

0x4ddf3c ANDS	XZR, X20, #4160

0x4ddf40 B.EQ	4ddfc0

0x4ddf44 AND	X30, X20, #8062

0x4ddf48 ADD	X5, X5, X30

0x4ddf4c UBFM	X0, X5, #61, #60

0x4ddf50 LDR	X20, [X12, X0]

0x4ddf54 ADD	X19, X5, #1

0x4ddf58 LDR	D20, [X6, X0]

0x4ddf5c LDR	D2, [X3, X20,LSL #3]

0x4ddf60 FMSUB	D0, D20, D2, D0

0x4ddf64 CMP	X21, X19

0x4ddf68 B.LE	4ddfc0

0x4ddf6c ADD	X2, X0, #8

0x4ddf70 ADD	X7, X5, #2

0x4ddf74 LDR	X30, [X12, X2]

0x4ddf78 LDR	D24, [X6, X2]

0x4ddf7c LDR	D16, [X3, X30,LSL #3]

0x4ddf80 FMSUB	D0, D24, D16, D0

0x4ddf84 CMP	X21, X7

0x4ddf88 B.LE	4ddfc0

0x4ddf8c ADD	X20, X0, #16

0x4ddf90 ADD	X5, X5, #3

0x4ddf94 LDR	X19, [X12, X20]

0x4ddf98 LDR	D19, [X6, X20]

0x4ddf9c LDR	D3, [X3, X19,LSL #3]

0x4ddfa0 FMSUB	D0, D19, D3, D0

0x4ddfa4 CMP	X21, X5

0x4ddfa8 B.LE	4ddfc0

0x4ddfac ADD	X21, X0, #24

0x4ddfb0 LDR	X0, [X12, X21]

0x4ddfb4 LDR	D1, [X6, X21]

0x4ddfb8 LDR	D17, [X3, X0,LSL #3]

0x4ddfbc FMSUB	D0, D17, D1, D0

0x4ddfc0 LDR	X7, [X14, X1,LSL #3]

0x4ddfc4 LDR	X30, [X17, X1,LSL #3]

0x4ddfc8 CMP	X7, X30

0x4ddfcc B.GE	4de1c4

0x4ddfd0 SUB	X20, X30, X7

0x4ddfd4 SUB	X2, X20, #1

0x4ddfd8 CMP	X2, #3

0x4ddfdc B.LS	4de150

0x4ddfe0 UBFM	X19, X20, #2, #63

0x4ddfe4 ADD	X0, X10, X7,LSL #3

0x4ddfe8 DUP	Z25.D, #0

0x4ddfec ORR	Z27.D, Z25.D, Z25.D

0x4ddff0 UBFM	X5, X19, #59, #58

0x4ddff4 ADD	X2, X11, X7,LSL #3

0x4ddff8 SUB	X21, X5, #32

0x4ddffc ADD	X19, X0, X19,LSL #5

0x4de000 UBFM	X5, X21, #5, #63

0x4de004 ADD	X21, X5, #1

0x4de008 ANDS	X5, X21, #4160

0x4de00c B.EQ	4de0a4

0x4de010 CMP	X5, #1

0x4de014 B.EQ	4de074

0x4de018 CMP	X5, #2

0x4de01c B.EQ	4de04c

0x4de020 LD1D	{Z21.D}, P7/Z, [X2, MUL VL]

0x4de024 LD1D	{Z7.D}, P7/Z, [X0, MUL VL]

0x4de028 LD1D	{Z28.D}, P7/Z, [X2, #1, MUL VL]

0x4de02c LD1D	{Z29.D}, P7/Z, [X0, #1, MUL VL]

0x4de030 ADD	X2, X2, #32

0x4de034 ADD	X0, X0, #32

0x4de038 LD1D	{Z6.D}, P7/Z, [X4, Z21.D,LSL #3]

0x4de03c LD1D	{Z26.D}, P7/Z, [X4, Z28.D,LSL #3]

0x4de040 MOVPRFX	Z27, Z25

0x4de044 FMLS	Z27.D, P7/M, Z6.D, Z7.D

0x4de048 FMLS	Z25.D, P7/M, Z26.D, Z29.D

0x4de04c LD1D	{Z23.D}, P7/Z, [X2, MUL VL]

0x4de050 LD1D	{Z5.D}, P7/Z, [X0, MUL VL]

0x4de054 LD1D	{Z4.D}, P7/Z, [X2, #1, MUL VL]

0x4de058 LD1D	{Z22.D}, P7/Z, [X0, #1, MUL VL]

0x4de05c ADD	X2, X2, #32

0x4de060 ADD	X0, X0, #32

0x4de064 LD1D	{Z18.D}, P7/Z, [X4, Z23.D,LSL #3]

0x4de068 LD1D	{Z20.D}, P7/Z, [X4, Z4.D,LSL #3]

0x4de06c FMLS	Z27.D, P7/M, Z18.D, Z5.D

0x4de070 FMLS	Z25.D, P7/M, Z20.D, Z22.D

0x4de074 LD1D	{Z24.D}, P7/Z, [X0, MUL VL]

0x4de078 LD1D	{Z16.D}, P7/Z, [X0, #1, MUL VL]

0x4de07c ADD	X0, X0, #32

0x4de080 LD1D	{Z2.D}, P7/Z, [X2, MUL VL]

0x4de084 LD1D	{Z19.D}, P7/Z, [X2, #1, MUL VL]

0x4de088 LD1D	{Z3.D}, P7/Z, [X4, Z2.D,LSL #3]

0x4de08c LD1D	{Z1.D}, P7/Z, [X4, Z19.D,LSL #3]

0x4de090 ADD	X2, X2, #32

0x4de094 FMLS	Z27.D, P7/M, Z3.D, Z24.D

0x4de098 FMLS	Z25.D, P7/M, Z1.D, Z16.D

0x4de09c CMP	X19, X0

0x4de0a0 B.EQ	4de134

  (2688) 0x4de0a4 LD1D	{Z17.D}, P7/Z, [X2, MUL VL]

  (2688) 0x4de0a8 LD1D	{Z21.D}, P7/Z, [X0, #1, MUL VL]

  (2688) 0x4de0ac LD1D	{Z7.D}, P7/Z, [X4, Z17.D,LSL #3]

  (2688) 0x4de0b0 LD1D	{Z28.D}, P7/Z, [X0, MUL VL]

  (2688) 0x4de0b4 LD1D	{Z5.D}, P7/Z, [X0, #2, MUL VL]

  (2688) 0x4de0b8 LD1D	{Z23.D}, P7/Z, [X0, #4, MUL VL]

  (2688) 0x4de0bc LD1D	{Z24.D}, P7/Z, [X0, #3, MUL VL]

  (2688) 0x4de0c0 LD1D	{Z16.D}, P7/Z, [X0, #5, MUL VL]

  (2688) 0x4de0c4 LD1D	{Z3.D}, P7/Z, [X0, #7, MUL VL]

  (2688) 0x4de0c8 LD1D	{Z26.D}, P7/Z, [X0, #6, MUL VL]

  (2688) 0x4de0cc ADD	X0, X0, #128

  (2688) 0x4de0d0 FMLS	Z27.D, P7/M, Z7.D, Z28.D

  (2688) 0x4de0d4 LD1D	{Z29.D}, P7/Z, [X2, #1, MUL VL]

  (2688) 0x4de0d8 LD1D	{Z4.D}, P7/Z, [X2, #2, MUL VL]

  (2688) 0x4de0dc LD1D	{Z22.D}, P7/Z, [X2, #4, MUL VL]

  (2688) 0x4de0e0 LD1D	{Z2.D}, P7/Z, [X2, #3, MUL VL]

  (2688) 0x4de0e4 LD1D	{Z19.D}, P7/Z, [X2, #6, MUL VL]

  (2688) 0x4de0e8 LD1D	{Z7.D}, P7/Z, [X2, #7, MUL VL]

  (2688) 0x4de0ec LD1D	{Z6.D}, P7/Z, [X4, Z29.D,LSL #3]

  (2688) 0x4de0f0 LD1D	{Z18.D}, P7/Z, [X4, Z4.D,LSL #3]

  (2688) 0x4de0f4 FMLS	Z25.D, P7/M, Z6.D, Z21.D

  (2688) 0x4de0f8 FMLS	Z27.D, P7/M, Z18.D, Z5.D

  (2688) 0x4de0fc LD1D	{Z21.D}, P7/Z, [X2, #5, MUL VL]

  (2688) 0x4de100 LD1D	{Z20.D}, P7/Z, [X4, Z22.D,LSL #3]

  (2688) 0x4de104 LD1D	{Z1.D}, P7/Z, [X4, Z2.D,LSL #3]

  (2688) 0x4de108 FMLS	Z27.D, P7/M, Z20.D, Z23.D

  (2688) 0x4de10c LD1D	{Z17.D}, P7/Z, [X4, Z19.D,LSL #3]

  (2688) 0x4de110 FMLS	Z25.D, P7/M, Z1.D, Z24.D

  (2688) 0x4de114 LD1D	{Z28.D}, P7/Z, [X4, Z21.D,LSL #3]

  (2688) 0x4de118 LD1D	{Z5.D}, P7/Z, [X4, Z7.D,LSL #3]

  (2688) 0x4de11c FMLS	Z25.D, P7/M, Z28.D, Z16.D

  (2688) 0x4de120 ADD	X2, X2, #128

  (2688) 0x4de124 FMLS	Z27.D, P7/M, Z17.D, Z26.D

  (2688) 0x4de128 FMLS	Z25.D, P7/M, Z5.D, Z3.D

  (2688) 0x4de12c CMP	X19, X0

  (2688) 0x4de130 B.NE	4de0a4

0x4de134 FADD	Z25.D, Z25.D, Z27.D

0x4de138 FADDV	D27, P7, Z25.D

0x4de13c FADD	D0, D0, D27

0x4de140 ANDS	XZR, X20, #4160

0x4de144 B.EQ	4de1c4

0x4de148 AND	X20, X20, #8062

0x4de14c ADD	X7, X7, X20

0x4de150 UBFM	X21, X7, #61, #60

0x4de154 ADD	X19, X7, #1

0x4de158 LDR	X5, [X11, X21]

0x4de15c LDR	D23, [X10, X21]

0x4de160 LDR	D29, [X4, X5,LSL #3]

0x4de164 FMSUB	D0, D23, D29, D0

0x4de168 CMP	X19, X30

0x4de16c B.GE	4de1c4

0x4de170 ADD	X0, X21, #8

0x4de174 ADD	X2, X7, #2

0x4de178 LDR	X20, [X11, X0]

0x4de17c LDR	D24, [X10, X0]

0x4de180 LDR	D6, [X4, X20,LSL #3]

0x4de184 FMSUB	D0, D24, D6, D0

0x4de188 CMP	X2, X30

0x4de18c B.GE	4de1c4

0x4de190 ADD	X19, X21, #16

0x4de194 ADD	X7, X7, #3

0x4de198 LDR	X5, [X11, X19]

0x4de19c LDR	D16, [X10, X19]

0x4de1a0 LDR	D3, [X4, X5,LSL #3]

0x4de1a4 FMSUB	D0, D3, D16, D0

0x4de1a8 CMP	X30, X7

0x4de1ac B.LE	4de1c4

0x4de1b0 ADD	X30, X21, #24

0x4de1b4 LDR	X21, [X11, X30]

0x4de1b8 LDR	D26, [X10, X30]

0x4de1bc LDR	D4, [X4, X21,LSL #3]

0x4de1c0 FMSUB	D0, D4, D26, D0

0x4de1c4 LDR	D22, [X16, X1,LSL #3]

0x4de1c8 FMUL	D0, D30, D0

0x4de1cc LDR	D18, [X13, X1,LSL #3]

0x4de1d0 FDIV	D20, D0, D22

0x4de1d4 FADD	D2, D18, D20

0x4de1d8 STR	D2, [X13, X1,LSL #3]

0x4de1dc ADD	X1, X1, #1

0x4de1e0 CMP	X8, X1

0x4de1e4 B.NE	4ddda4

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3662 - 3682

--------------------------------------------------------------------------------

3662: #pragma omp parallel for private(i,ii,jj,res) HYPRE_SMP_SCHEDULE

[...]

3669:          if (A_diag_data[A_diag_i[i]] != zero)

3670:          {

3671:             res = f_data[i];

3672:             for (jj = A_diag_i[i]; jj < A_diag_i[i+1]; jj++)

3673:             {

3674:                ii = A_diag_j[jj];

3675:                res -= A_diag_data[jj] * Vtemp_data[ii];

3676:             }

3677:             for (jj = A_offd_i[i]; jj < A_offd_i[i+1]; jj++)

3678:             {

3679:                ii = A_offd_j[jj];

3680:                res -= A_offd_data[jj] * Vext_data[ii];

3681:             }

3682:             u_data[i] += (relax_weight*res)/l1_norms[i];

Coverage (%)	Name	Source Location	Module
►99.05+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.33
CQA speedup if FP arith vectorized	1.03
CQA speedup if fully vectorized	1.20
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.10
Bottlenecks	micro-operation queue,
Function	hypre_ParCSRRelaxThreads._omp_fn.1
Source	ams.c:3662-3662,ams.c:3669-3682
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	25.50
CQA cycles if no scalar integer	19.17
CQA cycles if FP arith vectorized	24.69
CQA cycles if fully vectorized	21.33
Front-end cycles	25.50
P0 cycles	11.50
P1 cycles	11.50
P2 cycles	12.67
P3 cycles	12.67
P4 cycles	12.67
P5 cycles	12.67
P6 cycles	12.67
P7 cycles	12.67
P8 cycles	9.25
P9 cycles	9.25
P10 cycles	9.25
P11 cycles	9.25
P12 cycles	23.17
P13 cycles	22.83
P14 cycles	23.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	1.75 - 3.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	204.00
Nb uops	204.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	3.02
Nb FLOP add-sub	11.00
Nb FLOP mul	1.00
Nb FLOP fma	32.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.94
Bytes prefetched	0.00
Bytes loaded	832.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	44.63
Vectorization ratio load	63.16
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	33.33
Vectorization ratio fma	60.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	6.90
Vector-efficiency ratio all	72.42
Vector-efficiency ratio load	81.58
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	66.67
Vector-efficiency ratio fma	80.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	53.88

Metric	Value
CQA speedup if no scalar integer	1.33
CQA speedup if FP arith vectorized	1.03
CQA speedup if fully vectorized	1.20
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.10
Bottlenecks	micro-operation queue,
Function	hypre_ParCSRRelaxThreads._omp_fn.1
Source	ams.c:3662-3662,ams.c:3669-3682
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	25.50
CQA cycles if no scalar integer	19.17
CQA cycles if FP arith vectorized	24.69
CQA cycles if fully vectorized	21.33
Front-end cycles	25.50
P0 cycles	11.50
P1 cycles	11.50
P2 cycles	12.67
P3 cycles	12.67
P4 cycles	12.67
P5 cycles	12.67
P6 cycles	12.67
P7 cycles	12.67
P8 cycles	9.25
P9 cycles	9.25
P10 cycles	9.25
P11 cycles	9.25
P12 cycles	23.17
P13 cycles	22.83
P14 cycles	23.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	1.75 - 3.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	204.00
Nb uops	204.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	3.02
Nb FLOP add-sub	11.00
Nb FLOP mul	1.00
Nb FLOP fma	32.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.94
Bytes prefetched	0.00
Bytes loaded	832.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	44.63
Vectorization ratio load	63.16
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	33.33
Vectorization ratio fma	60.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	6.90
Vector-efficiency ratio all	72.42
Vector-efficiency ratio load	81.58
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	66.67
Vector-efficiency ratio fma	80.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	53.88

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParCSRRelaxThreads._omp_fn.1
Source file and lines	ams.c:3662-3682
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662,3669-3682.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 1601 paths individually, rerun with max-paths=1601
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 1601 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 25.50 to 19.17 cycles (1.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 72% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 25.50 to 21.33 cycles (1.20x speedup).

Details

44% of VPU instructions are used in vector version (process two or more data elements in vector registers):

63% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
33% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
60% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
6% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 32 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 77 FP arithmetical operations:

43: addition or subtraction (32 inside FMA instructions)
33: multiply (32 inside FMA instructions)
1: divide

The binary loop is loading 832 bytes. The binary loop is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.09 FP operations per loaded or stored byte.

General properties

nb instructions	204
loop length	816
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

25.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	11.50	11.50	12.67	12.67	12.67	12.67	12.67	12.67	9.25	9.25	9.25	9.25	23.17	22.83	23.00	0.00	0.00
cycles	11.50	11.50	12.67	12.67	12.67	12.67	12.67	12.67	9.25	9.25	9.25	9.25	23.17	22.83	23.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

1.75-3.50

Cycles summary

Front-end	25.50
Overall L1	25.50

Vectorization ratios

INT

all	41%
load	63%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	53%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	57%
fma	60%
div/sqrt	0%
other	0%

INT+FP

all	44%
load	63%
store	0%
mul	0%
add-sub	33%
fma	60%
div/sqrt	0%
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 25.50 cycles. At this rate:

33% of peak load performance is reached (32.63 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.31 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4ddda4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP X8, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4de1e8 <hypre_ParCSRRelaxThreads._omp_fn.1+0x4c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
UBFM X0, X5, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X30, X6, X5,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D6, [X6, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FCMP D31, D6	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
B.EQ 4ddd98 <hypre_ParCSRRelaxThreads._omp_fn.1+0x78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X21, [X18, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D0, [X15, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
CMP X5, X21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4ddfc0 <hypre_ParCSRRelaxThreads._omp_fn.1+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X20, X21, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SUB X2, X20, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP X2, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LS 4ddf50 <hypre_ParCSRRelaxThreads._omp_fn.1+0x230>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X19, X20, #2, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, X12, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
DUP Z27.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (6.3%)
ORR Z18.D, Z27.D, Z27.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
UBFM X7, X19, #59, #58	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X2, XZR, X30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X19, X0, X19,LSL #5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
SUB X7, X7, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X7, X7, #5, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X7, X7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS X7, X7, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4ddea0 <hypre_ParCSRRelaxThreads._omp_fn.1+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X7, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4dde70 <hypre_ParCSRRelaxThreads._omp_fn.1+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X7, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4dde48 <hypre_ParCSRRelaxThreads._omp_fn.1+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LD1D {Z23.D}, P7/Z, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z4.D}, P7/Z, [X0, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X2, X30, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, X0, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z22.D}, P7/Z, [X3, Z23.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z5.D}, P7/Z, [X30, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z20.D}, P7/Z, [X3, Z4.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
MOVPRFX Z18, Z27	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FMLS Z18.D, P7/M, Z5.D, Z22.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LD1D {Z24.D}, P7/Z, [X30, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLS Z27.D, P7/M, Z24.D, Z20.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LD1D {Z2.D}, P7/Z, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z16.D}, P7/Z, [X2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z19.D}, P7/Z, [X0, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z3.D}, P7/Z, [X2, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X2, X2, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z1.D}, P7/Z, [X3, Z2.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z17.D}, P7/Z, [X3, Z19.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLS Z18.D, P7/M, Z16.D, Z1.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLS Z27.D, P7/M, Z3.D, Z17.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LD1D {Z25.D}, P7/Z, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z21.D}, P7/Z, [X0, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z7.D}, P7/Z, [X2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z29.D}, P7/Z, [X2, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z26.D}, P7/Z, [X3, Z25.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z28.D}, P7/Z, [X3, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X2, X2, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMLS Z18.D, P7/M, Z7.D, Z26.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLS Z27.D, P7/M, Z29.D, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
CMP X19, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4ddf30 <hypre_ParCSRRelaxThreads._omp_fn.1+0x210>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FADD Z27.D, Z18.D, Z27.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FADDV D18, P7, Z27.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	vect (100.0%)
FADD D0, D0, D18	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
ANDS XZR, X20, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4ddfc0 <hypre_ParCSRRelaxThreads._omp_fn.1+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X30, X20, #8062	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, X5, X30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X0, X5, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X20, [X12, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X19, X5, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D20, [X6, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D2, [X3, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMSUB D0, D20, D2, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
CMP X21, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4ddfc0 <hypre_ParCSRRelaxThreads._omp_fn.1+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X0, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X7, X5, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X30, [X12, X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D24, [X6, X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D16, [X3, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMSUB D0, D24, D16, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
CMP X21, X7	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4ddfc0 <hypre_ParCSRRelaxThreads._omp_fn.1+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X20, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, X5, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X19, [X12, X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D19, [X6, X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D3, [X3, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMSUB D0, D19, D3, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
CMP X21, X5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4ddfc0 <hypre_ParCSRRelaxThreads._omp_fn.1+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X21, X0, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X0, [X12, X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D1, [X6, X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D17, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMSUB D0, D17, D1, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
LDR X7, [X14, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
LDR X30, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X7, X30	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4de1c4 <hypre_ParCSRRelaxThreads._omp_fn.1+0x4a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X20, X30, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SUB X2, X20, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP X2, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LS 4de150 <hypre_ParCSRRelaxThreads._omp_fn.1+0x430>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X19, X20, #2, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, X10, X7,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
DUP Z25.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (6.3%)
ORR Z27.D, Z25.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
UBFM X5, X19, #59, #58	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X2, X11, X7,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SUB X21, X5, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X19, X0, X19,LSL #5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
UBFM X5, X21, #5, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X21, X5, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ANDS X5, X21, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 4de0a4 <hypre_ParCSRRelaxThreads._omp_fn.1+0x384>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4de074 <hypre_ParCSRRelaxThreads._omp_fn.1+0x354>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4de04c <hypre_ParCSRRelaxThreads._omp_fn.1+0x32c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LD1D {Z21.D}, P7/Z, [X2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z7.D}, P7/Z, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z28.D}, P7/Z, [X2, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z29.D}, P7/Z, [X0, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X2, X2, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, X0, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z6.D}, P7/Z, [X4, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z26.D}, P7/Z, [X4, Z28.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
MOVPRFX Z27, Z25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FMLS Z27.D, P7/M, Z6.D, Z7.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLS Z25.D, P7/M, Z26.D, Z29.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LD1D {Z23.D}, P7/Z, [X2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z5.D}, P7/Z, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z4.D}, P7/Z, [X2, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z22.D}, P7/Z, [X0, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X2, X2, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, X0, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z18.D}, P7/Z, [X4, Z23.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z20.D}, P7/Z, [X4, Z4.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLS Z27.D, P7/M, Z18.D, Z5.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLS Z25.D, P7/M, Z20.D, Z22.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LD1D {Z24.D}, P7/Z, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z16.D}, P7/Z, [X0, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z2.D}, P7/Z, [X2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z19.D}, P7/Z, [X2, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z3.D}, P7/Z, [X4, Z2.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z1.D}, P7/Z, [X4, Z19.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X2, X2, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMLS Z27.D, P7/M, Z3.D, Z24.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLS Z25.D, P7/M, Z1.D, Z16.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
CMP X19, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4de134 <hypre_ParCSRRelaxThreads._omp_fn.1+0x414>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FADD Z25.D, Z25.D, Z27.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FADDV D27, P7, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	vect (100.0%)
FADD D0, D0, D27	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
ANDS XZR, X20, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4de1c4 <hypre_ParCSRRelaxThreads._omp_fn.1+0x4a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X20, X20, #8062	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X7, X7, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X21, X7, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X19, X7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X5, [X11, X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D23, [X10, X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D29, [X4, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMSUB D0, D23, D29, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
CMP X19, X30	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4de1c4 <hypre_ParCSRRelaxThreads._omp_fn.1+0x4a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X21, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X2, X7, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X20, [X11, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D24, [X10, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D6, [X4, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMSUB D0, D24, D6, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
CMP X2, X30	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4de1c4 <hypre_ParCSRRelaxThreads._omp_fn.1+0x4a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X19, X21, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X7, X7, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X5, [X11, X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D16, [X10, X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D3, [X4, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMSUB D0, D3, D16, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
CMP X30, X7	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4de1c4 <hypre_ParCSRRelaxThreads._omp_fn.1+0x4a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X30, X21, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X21, [X11, X30]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D26, [X10, X30]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D4, [X4, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMSUB D0, D4, D26, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
LDR D22, [X16, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL D0, D30, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
LDR D18, [X13, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FDIV D20, D0, D22	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
FADD D2, D18, D20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
STR D2, [X13, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP X8, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 4ddda4 <hypre_ParCSRRelaxThreads._omp_fn.1+0x84>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_ParCSRRelaxThreads._omp_fn.1
Source file and lines	ams.c:3662-3682
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662,3669-3682.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 1601 paths individually, rerun with max-paths=1601
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

44% of VPU instructions are used in vector version (process two or more data elements in vector registers):

63% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
33% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
60% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
6% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 32 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 77 FP arithmetical operations:

43: addition or subtraction (32 inside FMA instructions)
33: multiply (32 inside FMA instructions)
1: divide

The binary loop is loading 832 bytes. The binary loop is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.09 FP operations per loaded or stored byte.

General properties

nb instructions	204
loop length	816
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

25.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	11.50	11.50	12.67	12.67	12.67	12.67	12.67	12.67	9.25	9.25	9.25	9.25	23.17	22.83	23.00	0.00	0.00
cycles	11.50	11.50	12.67	12.67	12.67	12.67	12.67	12.67	9.25	9.25	9.25	9.25	23.17	22.83	23.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

1.75-3.50

Cycles summary

Front-end	25.50
Overall L1	25.50

Vectorization ratios

INT

all	41%
load	63%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	53%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	57%
fma	60%
div/sqrt	0%
other	0%

INT+FP

all	44%
load	63%
store	0%
mul	0%
add-sub	33%
fma	60%
div/sqrt	0%
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 25.50 cycles. At this rate:

33% of peak load performance is reached (32.63 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.31 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4ddda4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP X8, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4de1e8 <hypre_ParCSRRelaxThreads._omp_fn.1+0x4c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
UBFM X0, X5, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X30, X6, X5,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D6, [X6, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FCMP D31, D6	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
B.EQ 4ddd98 <hypre_ParCSRRelaxThreads._omp_fn.1+0x78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X21, [X18, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D0, [X15, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
CMP X5, X21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4ddfc0 <hypre_ParCSRRelaxThreads._omp_fn.1+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X20, X21, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SUB X2, X20, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP X2, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LS 4ddf50 <hypre_ParCSRRelaxThreads._omp_fn.1+0x230>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X19, X20, #2, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, X12, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
DUP Z27.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (6.3%)
ORR Z18.D, Z27.D, Z27.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
UBFM X7, X19, #59, #58	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X2, XZR, X30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X19, X0, X19,LSL #5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
SUB X7, X7, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X7, X7, #5, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X7, X7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS X7, X7, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4ddea0 <hypre_ParCSRRelaxThreads._omp_fn.1+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X7, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4dde70 <hypre_ParCSRRelaxThreads._omp_fn.1+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X7, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4dde48 <hypre_ParCSRRelaxThreads._omp_fn.1+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LD1D {Z23.D}, P7/Z, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z4.D}, P7/Z, [X0, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X2, X30, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, X0, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z22.D}, P7/Z, [X3, Z23.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z5.D}, P7/Z, [X30, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z20.D}, P7/Z, [X3, Z4.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
MOVPRFX Z18, Z27	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FMLS Z18.D, P7/M, Z5.D, Z22.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LD1D {Z24.D}, P7/Z, [X30, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLS Z27.D, P7/M, Z24.D, Z20.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LD1D {Z2.D}, P7/Z, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z16.D}, P7/Z, [X2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z19.D}, P7/Z, [X0, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z3.D}, P7/Z, [X2, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X2, X2, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z1.D}, P7/Z, [X3, Z2.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z17.D}, P7/Z, [X3, Z19.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLS Z18.D, P7/M, Z16.D, Z1.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLS Z27.D, P7/M, Z3.D, Z17.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LD1D {Z25.D}, P7/Z, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z21.D}, P7/Z, [X0, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z7.D}, P7/Z, [X2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z29.D}, P7/Z, [X2, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z26.D}, P7/Z, [X3, Z25.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z28.D}, P7/Z, [X3, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X2, X2, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMLS Z18.D, P7/M, Z7.D, Z26.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLS Z27.D, P7/M, Z29.D, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
CMP X19, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4ddf30 <hypre_ParCSRRelaxThreads._omp_fn.1+0x210>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FADD Z27.D, Z18.D, Z27.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FADDV D18, P7, Z27.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	vect (100.0%)
FADD D0, D0, D18	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
ANDS XZR, X20, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4ddfc0 <hypre_ParCSRRelaxThreads._omp_fn.1+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X30, X20, #8062	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, X5, X30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X0, X5, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X20, [X12, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X19, X5, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D20, [X6, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D2, [X3, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMSUB D0, D20, D2, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
CMP X21, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4ddfc0 <hypre_ParCSRRelaxThreads._omp_fn.1+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X0, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X7, X5, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X30, [X12, X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D24, [X6, X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D16, [X3, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMSUB D0, D24, D16, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
CMP X21, X7	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4ddfc0 <hypre_ParCSRRelaxThreads._omp_fn.1+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X20, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, X5, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X19, [X12, X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D19, [X6, X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D3, [X3, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMSUB D0, D19, D3, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
CMP X21, X5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4ddfc0 <hypre_ParCSRRelaxThreads._omp_fn.1+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X21, X0, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X0, [X12, X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D1, [X6, X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D17, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMSUB D0, D17, D1, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
LDR X7, [X14, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
LDR X30, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X7, X30	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4de1c4 <hypre_ParCSRRelaxThreads._omp_fn.1+0x4a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X20, X30, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SUB X2, X20, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP X2, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LS 4de150 <hypre_ParCSRRelaxThreads._omp_fn.1+0x430>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X19, X20, #2, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, X10, X7,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
DUP Z25.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (6.3%)
ORR Z27.D, Z25.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
UBFM X5, X19, #59, #58	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X2, X11, X7,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SUB X21, X5, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X19, X0, X19,LSL #5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
UBFM X5, X21, #5, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X21, X5, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ANDS X5, X21, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 4de0a4 <hypre_ParCSRRelaxThreads._omp_fn.1+0x384>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4de074 <hypre_ParCSRRelaxThreads._omp_fn.1+0x354>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4de04c <hypre_ParCSRRelaxThreads._omp_fn.1+0x32c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LD1D {Z21.D}, P7/Z, [X2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z7.D}, P7/Z, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z28.D}, P7/Z, [X2, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z29.D}, P7/Z, [X0, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X2, X2, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, X0, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z6.D}, P7/Z, [X4, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z26.D}, P7/Z, [X4, Z28.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
MOVPRFX Z27, Z25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FMLS Z27.D, P7/M, Z6.D, Z7.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLS Z25.D, P7/M, Z26.D, Z29.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LD1D {Z23.D}, P7/Z, [X2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z5.D}, P7/Z, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z4.D}, P7/Z, [X2, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z22.D}, P7/Z, [X0, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X2, X2, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, X0, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z18.D}, P7/Z, [X4, Z23.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z20.D}, P7/Z, [X4, Z4.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLS Z27.D, P7/M, Z18.D, Z5.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLS Z25.D, P7/M, Z20.D, Z22.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LD1D {Z24.D}, P7/Z, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z16.D}, P7/Z, [X0, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1D {Z2.D}, P7/Z, [X2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z19.D}, P7/Z, [X2, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z3.D}, P7/Z, [X4, Z2.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z1.D}, P7/Z, [X4, Z19.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X2, X2, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMLS Z27.D, P7/M, Z3.D, Z24.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLS Z25.D, P7/M, Z1.D, Z16.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
CMP X19, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4de134 <hypre_ParCSRRelaxThreads._omp_fn.1+0x414>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FADD Z25.D, Z25.D, Z27.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FADDV D27, P7, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	vect (100.0%)
FADD D0, D0, D27	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
ANDS XZR, X20, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4de1c4 <hypre_ParCSRRelaxThreads._omp_fn.1+0x4a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X20, X20, #8062	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X7, X7, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X21, X7, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X19, X7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X5, [X11, X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D23, [X10, X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D29, [X4, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMSUB D0, D23, D29, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
CMP X19, X30	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4de1c4 <hypre_ParCSRRelaxThreads._omp_fn.1+0x4a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X21, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X2, X7, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X20, [X11, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D24, [X10, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D6, [X4, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMSUB D0, D24, D6, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
CMP X2, X30	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4de1c4 <hypre_ParCSRRelaxThreads._omp_fn.1+0x4a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X19, X21, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X7, X7, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X5, [X11, X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D16, [X10, X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D3, [X4, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMSUB D0, D3, D16, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
CMP X30, X7	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4de1c4 <hypre_ParCSRRelaxThreads._omp_fn.1+0x4a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X30, X21, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X21, [X11, X30]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D26, [X10, X30]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D4, [X4, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMSUB D0, D4, D26, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
LDR D22, [X16, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL D0, D30, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
LDR D18, [X13, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FDIV D20, D0, D22	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
FADD D2, D18, D20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
STR D2, [X13, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP X8, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 4ddda4 <hypre_ParCSRRelaxThreads._omp_fn.1+0x84>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code