OV - exec - Loop 2645

	Loop Id: 2645	Module: exec	Source: ams.c:3382-3401 [...]	Coverage: 0.01%

0x4d9784 MOVI	D31, #0

0x4d9788 CBNZ	X4, 4d9914

0x4d978c ADD	X12, X12, #1

0x4d9790 CMP	X26, X12

0x4d9794 B.EQ	4d9d20

0x4d9798 LDR	X14, [X7, X12,LSL #3]

0x4d979c ORR	X3, XZR, X12

0x4d97a0 LDR	X0, [X24, X12,LSL #3]

0x4d97a4 STR	XZR, [X19, X12,LSL #3]

0x4d97a8 CMP	X0, X14

0x4d97ac B.GE	4d9784

0x4d97b0 ADD	X18, X21, X14,LSL #3

0x4d97b4 UBFM	X14, X0, #61, #60

0x4d97b8 MOVI	D31, #0

0x4d97bc ADD	X0, X21, X0,LSL #3

0x4d97c0 SUB	X16, X18, X0

0x4d97c4 SUB	X11, X16, #8

0x4d97c8 UBFM	X2, X11, #3, #63

0x4d97cc ADD	X30, X2, #1

0x4d97d0 ANDS	X17, X30, #4224

0x4d97d4 B.EQ	4d9880

0x4d97d8 CMP	X17, #1

0x4d97dc B.EQ	4d9868

0x4d97e0 CMP	X17, #2

0x4d97e4 B.EQ	4d9858

0x4d97e8 CMP	X17, #3

0x4d97ec B.EQ	4d9848

0x4d97f0 CMP	X17, #4

0x4d97f4 B.EQ	4d9838

0x4d97f8 CMP	X17, #5

0x4d97fc B.EQ	4d9828

0x4d9800 CMP	X17, #6

0x4d9804 B.EQ	4d9818

0x4d9808 LDR	D25, [X21, X14]

0x4d980c ADD	X0, X0, #8

0x4d9810 FABS	D31, D25

0x4d9814 STR	D31, [X19, X3,LSL #3]

0x4d9818 LDR	D26, [X0], #8

0x4d981c FABS	D27, D26

0x4d9820 FADD	D31, D31, D27

0x4d9824 STR	D31, [X19, X3,LSL #3]

0x4d9828 LDR	D6, [X0], #8

0x4d982c FABS	D0, D6

0x4d9830 FADD	D31, D31, D0

0x4d9834 STR	D31, [X19, X3,LSL #3]

0x4d9838 LDR	D1, [X0], #8

0x4d983c FABS	D2, D1

0x4d9840 FADD	D31, D31, D2

0x4d9844 STR	D31, [X19, X3,LSL #3]

0x4d9848 LDR	D3, [X0], #8

0x4d984c FABS	D4, D3

0x4d9850 FADD	D31, D31, D4

0x4d9854 STR	D31, [X19, X3,LSL #3]

0x4d9858 LDR	D5, [X0], #8

0x4d985c FABS	D7, D5

0x4d9860 FADD	D31, D31, D7

0x4d9864 STR	D31, [X19, X3,LSL #3]

0x4d9868 LDR	D16, [X0], #8

0x4d986c FABS	D17, D16

0x4d9870 FADD	D31, D31, D17

0x4d9874 STR	D31, [X19, X3,LSL #3]

0x4d9878 CMP	X18, X0

0x4d987c B.EQ	4d9788

  (2647) 0x4d9880 ORR	X16, XZR, X0

  (2647) 0x4d9884 ADD	X0, X0, #64

  (2647) 0x4d9888 LDR	D17, [X16], #8

  (2647) 0x4d988c FABS	D18, D17

  (2647) 0x4d9890 FADD	D31, D31, D18

  (2647) 0x4d9894 STR	D31, [X19, X3,LSL #3]

  (2647) 0x4d9898 LDUR	D19, [X0, #456]

  (2647) 0x4d989c FABS	D20, D19

  (2647) 0x4d98a0 FADD	D28, D31, D20

  (2647) 0x4d98a4 STR	D28, [X19, X3,LSL #3]

  (2647) 0x4d98a8 LDR	D29, [X16, #8]

  (2647) 0x4d98ac FABS	D24, D29

  (2647) 0x4d98b0 FADD	D21, D28, D24

  (2647) 0x4d98b4 STR	D21, [X19, X3,LSL #3]

  (2647) 0x4d98b8 LDUR	D22, [X0, #472]

  (2647) 0x4d98bc FABS	D30, D22

  (2647) 0x4d98c0 FADD	D23, D21, D30

  (2647) 0x4d98c4 STR	D23, [X19, X3,LSL #3]

  (2647) 0x4d98c8 LDUR	D25, [X0, #480]

  (2647) 0x4d98cc FABS	D26, D25

  (2647) 0x4d98d0 FADD	D27, D23, D26

  (2647) 0x4d98d4 STR	D27, [X19, X3,LSL #3]

  (2647) 0x4d98d8 LDUR	D6, [X0, #488]

  (2647) 0x4d98dc FABS	D0, D6

  (2647) 0x4d98e0 FADD	D1, D27, D0

  (2647) 0x4d98e4 STR	D1, [X19, X3,LSL #3]

  (2647) 0x4d98e8 LDUR	D2, [X0, #496]

  (2647) 0x4d98ec FABS	D3, D2

  (2647) 0x4d98f0 FADD	D31, D1, D3

  (2647) 0x4d98f4 STR	D31, [X19, X3,LSL #3]

  (2647) 0x4d98f8 LDUR	D16, [X0, #504]

  (2647) 0x4d98fc FABS	D17, D16

  (2647) 0x4d9900 FADD	D31, D31, D17

  (2647) 0x4d9904 STR	D31, [X19, X3,LSL #3]

  (2647) 0x4d9908 CMP	X18, X0

  (2647) 0x4d990c B.NE	4d9880

0x4d9910 CBZ	X4, 4d978c

0x4d9914 LDR	X18, [X10, X3,LSL #3]

0x4d9918 LDR	X14, [X15, X3,LSL #3]

0x4d991c CMP	X14, X18

0x4d9920 B.LE	4d978c

0x4d9924 ADD	X16, X6, X14,LSL #3

0x4d9928 UBFM	X11, X18, #61, #60

0x4d992c ADD	X0, X6, X18,LSL #3

0x4d9930 SUB	X2, X16, X0

0x4d9934 SUB	X30, X2, #8

0x4d9938 UBFM	X17, X30, #3, #63

0x4d993c ADD	X18, X17, #1

0x4d9940 ANDS	X14, X18, #4224

0x4d9944 B.EQ	4d99e0

0x4d9948 CMP	X14, #1

0x4d994c B.EQ	4d99c8

0x4d9950 CMP	X14, #2

0x4d9954 B.EQ	4d99b8

0x4d9958 CMP	X14, #3

0x4d995c B.EQ	4d99a8

0x4d9960 CMP	X14, #4

0x4d9964 B.EQ	4d9998

0x4d9968 CMP	X14, #5

0x4d996c B.EQ	4d9988

0x4d9970 CMP	X14, #6

0x4d9974 B.NE	4dcb70

0x4d9978 LDR	D20, [X0], #8

0x4d997c FABS	D28, D20

0x4d9980 FADD	D31, D31, D28

0x4d9984 STR	D31, [X19, X3,LSL #3]

0x4d9988 LDR	D29, [X0], #8

0x4d998c FABS	D24, D29

0x4d9990 FADD	D31, D31, D24

0x4d9994 STR	D31, [X19, X3,LSL #3]

0x4d9998 LDR	D21, [X0], #8

0x4d999c FABS	D22, D21

0x4d99a0 FADD	D31, D31, D22

0x4d99a4 STR	D31, [X19, X3,LSL #3]

0x4d99a8 LDR	D30, [X0], #8

0x4d99ac FABS	D23, D30

0x4d99b0 FADD	D31, D31, D23

0x4d99b4 STR	D31, [X19, X3,LSL #3]

0x4d99b8 LDR	D25, [X0], #8

0x4d99bc FABS	D26, D25

0x4d99c0 FADD	D31, D31, D26

0x4d99c4 STR	D31, [X19, X3,LSL #3]

0x4d99c8 LDR	D27, [X0], #8

0x4d99cc FABS	D6, D27

0x4d99d0 FADD	D31, D31, D6

0x4d99d4 STR	D31, [X19, X3,LSL #3]

0x4d99d8 CMP	X0, X16

0x4d99dc B.EQ	4d978c

  (2646) 0x4d99e0 ORR	X2, XZR, X0

  (2646) 0x4d99e4 ADD	X0, X0, #64

  (2646) 0x4d99e8 LDR	D20, [X2], #8

  (2646) 0x4d99ec FABS	D28, D20

  (2646) 0x4d99f0 FADD	D29, D31, D28

  (2646) 0x4d99f4 STR	D29, [X19, X3,LSL #3]

  (2646) 0x4d99f8 LDUR	D24, [X0, #456]

  (2646) 0x4d99fc FABS	D21, D24

  (2646) 0x4d9a00 FADD	D22, D29, D21

  (2646) 0x4d9a04 STR	D22, [X19, X3,LSL #3]

  (2646) 0x4d9a08 LDR	D30, [X2, #8]

  (2646) 0x4d9a0c FABS	D23, D30

  (2646) 0x4d9a10 FADD	D25, D22, D23

  (2646) 0x4d9a14 STR	D25, [X19, X3,LSL #3]

  (2646) 0x4d9a18 LDUR	D26, [X0, #472]

  (2646) 0x4d9a1c FABS	D27, D26

  (2646) 0x4d9a20 FADD	D6, D25, D27

  (2646) 0x4d9a24 STR	D6, [X19, X3,LSL #3]

  (2646) 0x4d9a28 LDUR	D0, [X0, #480]

  (2646) 0x4d9a2c FABS	D1, D0

  (2646) 0x4d9a30 FADD	D2, D6, D1

  (2646) 0x4d9a34 STR	D2, [X19, X3,LSL #3]

  (2646) 0x4d9a38 LDUR	D3, [X0, #488]

  (2646) 0x4d9a3c FABS	D4, D3

  (2646) 0x4d9a40 FADD	D5, D2, D4

  (2646) 0x4d9a44 STR	D5, [X19, X3,LSL #3]

  (2646) 0x4d9a48 LDUR	D7, [X0, #496]

  (2646) 0x4d9a4c FABS	D16, D7

  (2646) 0x4d9a50 FADD	D31, D5, D16

  (2646) 0x4d9a54 STR	D31, [X19, X3,LSL #3]

  (2646) 0x4d9a58 LDUR	D27, [X0, #504]

  (2646) 0x4d9a5c FABS	D6, D27

  (2646) 0x4d9a60 FADD	D31, D31, D6

  (2646) 0x4d9a64 STR	D31, [X19, X3,LSL #3]

  (2646) 0x4d9a68 CMP	X0, X16

  (2646) 0x4d9a6c B.NE	4d99e0

0x4d9a70 B	4d978c

0x4dcb70 LDR	D18, [X6, X11]

0x4dcb74 ADD	X0, X0, #8

0x4dcb78 FABS	D19, D18

0x4dcb7c FADD	D31, D31, D19

0x4dcb80 STR	D31, [X19, X3,LSL #3]

0x4dcb84 B	4d9978

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3382 - 3401

--------------------------------------------------------------------------------

3382:          for (i = ns; i < ne; i++)

3383:          {

3384:             l1_norm[i] = 0.0;

3385:             if (cf_marker == NULL)

3386:             {

3387:                /* Add the l1 norm of the diag part of the ith row */

3388:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

3389:                   l1_norm[i] += fabs(A_diag_data[j]);

3390:                /* Add the l1 norm of the offd part of the ith row */

3391:                if (num_cols_offd)

3392:                {

3393:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

3394:                      l1_norm[i] += fabs(A_offd_data[j]);

[...]

3401:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

Coverage (%)	Name	Source Location	Module
►100.00+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.63
CQA speedup if FP arith vectorized	1.26
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	micro-operation queue,
Function	hypre_ParCSRComputeL1NormsThreads._omp_fn.0
Source	ams.c:3382-3384,ams.c:3388-3394,ams.c:3401-3401
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	15.25
CQA cycles if no scalar integer	9.33
CQA cycles if FP arith vectorized	12.06
CQA cycles if fully vectorized	7.63
Front-end cycles	15.25
P0 cycles	11.50
P1 cycles	11.50
P2 cycles	8.25
P3 cycles	8.25
P4 cycles	8.17
P5 cycles	8.17
P6 cycles	8.08
P7 cycles	8.08
P8 cycles	10.75
P9 cycles	10.75
P10 cycles	10.75
P11 cycles	10.75
P12 cycles	11.17
P13 cycles	10.83
P14 cycles	11.00
P15 cycles	0.50
P16 cycles	0.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	122.00
Nb uops	122.00
Nb loads	NA
Nb stores	15.00
Nb stack references	0.00
FLOP/cycle	0.85
Nb FLOP add-sub	13.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.31
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	120.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	1.63
CQA speedup if FP arith vectorized	1.26
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	micro-operation queue,
Function	hypre_ParCSRComputeL1NormsThreads._omp_fn.0
Source	ams.c:3382-3384,ams.c:3388-3394,ams.c:3401-3401
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	15.25
CQA cycles if no scalar integer	9.33
CQA cycles if FP arith vectorized	12.06
CQA cycles if fully vectorized	7.63
Front-end cycles	15.25
P0 cycles	11.50
P1 cycles	11.50
P2 cycles	8.25
P3 cycles	8.25
P4 cycles	8.17
P5 cycles	8.17
P6 cycles	8.08
P7 cycles	8.08
P8 cycles	10.75
P9 cycles	10.75
P10 cycles	10.75
P11 cycles	10.75
P12 cycles	11.17
P13 cycles	10.83
P14 cycles	11.00
P15 cycles	0.50
P16 cycles	0.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	122.00
Nb uops	122.00
Nb loads	NA
Nb stores	15.00
Nb stack references	0.00
FLOP/cycle	0.85
Nb FLOP add-sub	13.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.31
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	120.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParCSRComputeL1NormsThreads._omp_fn.0
Source file and lines	ams.c:3382-3401
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3382-3394,3401.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3382-3384,3388-3394,3401.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 272 paths individually, rerun with max-paths=272
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 272 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.25 to 9.33 cycles (1.63x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 15.25 to 7.62 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 13 FP arithmetical operations:

13: addition or subtraction

The binary loop is loading 144 bytes. The binary loop is storing 120 bytes.

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	122
loop length	488
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

15.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	11.50	11.50	8.25	8.25	8.17	8.17	8.08	8.08	10.75	10.75	10.75	10.75	11.17	10.83	11.00	0.50	0.50
cycles	11.50	11.50	8.25	8.25	8.17	8.17	8.08	8.08	10.75	10.75	10.75	10.75	11.17	10.83	11.00	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.25
Overall L1	15.25

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 15.25 cycles. At this rate:

9% of peak load performance is reached (9.44 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (7.87 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4d97a8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
MOVI D31, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	N/A
CBNZ X4, 4d9914 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1294>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X12, X12, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X26, X12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4d9d20 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x16a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X7, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X3, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X0, [X24, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X19, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X0, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4d9784 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1104>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X18, X21, X14,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X14, X0, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVI D31, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	N/A
ADD X0, X21, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X16, X18, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X11, X16, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X2, X11, #3, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X30, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS X17, X30, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4d9880 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X17, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4d9868 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x11e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X17, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4d9858 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x11d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X17, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4d9848 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x11c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X17, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4d9838 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x11b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X17, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4d9828 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x11a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X17, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4d9818 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1198>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D25, [X21, X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X0, X0, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FABS D31, D25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D26, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D27, D26	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D27	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D6, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D0, D6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D1, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D2, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D3, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D4, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D5, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D7, D5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D7	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D16, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D17, D16	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D17	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X18, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4d9788 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ X4, 4d978c <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x110c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [X10, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X14, [X15, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X14, X18	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4d978c <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x110c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X16, X6, X14,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X11, X18, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, X6, X18,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X2, X16, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X30, X2, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X17, X30, #3, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X18, X17, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS X14, X18, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 4d99e0 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1360>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4d99c8 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1348>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4d99b8 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1338>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4d99a8 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1328>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4d9998 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1318>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4d9988 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 4dcb70 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x44f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D20, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D28, D20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D29, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D24, D29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D21, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D22, D21	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D30, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D23, D30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D23	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D25, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D26, D25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D26	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D27, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D6, D27	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X0, X16	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4d978c <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x110c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4d978c <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x110c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D18, [X6, X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X0, X0, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FABS D19, D18	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D19	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
B 4d9978 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x12f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_ParCSRComputeL1NormsThreads._omp_fn.0
Source file and lines	ams.c:3382-3401
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 272 paths individually, rerun with max-paths=272
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.25 to 9.33 cycles (1.63x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 13 FP arithmetical operations:

13: addition or subtraction

The binary loop is loading 144 bytes. The binary loop is storing 120 bytes.

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	122
loop length	488
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

15.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	11.50	11.50	8.25	8.25	8.17	8.17	8.08	8.08	10.75	10.75	10.75	10.75	11.17	10.83	11.00	0.50	0.50
cycles	11.50	11.50	8.25	8.25	8.17	8.17	8.08	8.08	10.75	10.75	10.75	10.75	11.17	10.83	11.00	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.25
Overall L1	15.25

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 15.25 cycles. At this rate:

9% of peak load performance is reached (9.44 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (7.87 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4d97a8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
MOVI D31, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	N/A
CBNZ X4, 4d9914 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1294>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X12, X12, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X26, X12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4d9d20 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x16a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X7, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X3, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X0, [X24, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X19, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X0, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4d9784 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1104>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X18, X21, X14,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X14, X0, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVI D31, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	N/A
ADD X0, X21, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X16, X18, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X11, X16, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X2, X11, #3, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X30, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS X17, X30, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4d9880 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X17, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4d9868 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x11e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X17, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4d9858 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x11d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X17, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4d9848 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x11c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X17, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4d9838 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x11b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X17, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4d9828 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x11a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X17, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4d9818 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1198>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D25, [X21, X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X0, X0, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FABS D31, D25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D26, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D27, D26	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D27	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D6, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D0, D6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D1, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D2, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D3, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D4, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D5, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D7, D5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D7	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D16, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D17, D16	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D17	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X18, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4d9788 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ X4, 4d978c <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x110c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [X10, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X14, [X15, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X14, X18	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4d978c <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x110c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X16, X6, X14,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X11, X18, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, X6, X18,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X2, X16, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X30, X2, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X17, X30, #3, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X18, X17, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS X14, X18, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 4d99e0 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1360>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4d99c8 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1348>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4d99b8 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1338>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4d99a8 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1328>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4d9998 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1318>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4d9988 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 4dcb70 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x44f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D20, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D28, D20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D29, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D24, D29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D21, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D22, D21	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D30, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D23, D30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D23	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D25, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D26, D25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D26	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D27, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D6, D27	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X0, X16	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4d978c <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x110c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4d978c <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x110c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D18, [X6, X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X0, X0, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FABS D19, D18	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D19	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
B 4d9978 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x12f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code