OV - exec - Function hypre_SeqVectorInnerProd._omp

	Function: hypre_SeqVectorInnerProd._omp_fn.0	Module: exec	Source: vector.c:483-486	Coverage (incl. loops): 0.98% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/vector.c: 483 - 486

--------------------------------------------------------------------------------

483: #pragma omp parallel for private(i) reduction(+:result) HYPRE_SMP_SCHEDULE

484: #endif

485:    for (i = 0; i < size; i++)

486:       result += hypre_conj(y_data[i]) * x_data[i];

0x53f3e0 STP	X29, X30, [SP, #976]!

0x53f3e4 ADD	X29, SP, #0

0x53f3e8 STP	X19, X20, [SP, #16]

0x53f3ec ORR	X20, XZR, X0

0x53f3f0 STR	X21, [SP, #32]

0x53f3f4 LDR	X21, [X0, #16]

0x53f3f8 BL	410930

0x53f3fc SBFM	X19, X0, #0, #31

0x53f400 BL	410940

0x53f404 SBFM	X4, X0, #0, #31

0x53f408 SDIV	X3, X21, X19

0x53f40c MSUB	X1, X3, X19, X21

0x53f410 CMP	X4, X1

0x53f414 B.LT	53f648

(4028) 0x53f418 MADD	X13, X3, X4, X1

(4028) 0x53f41c MOVI	D31, #0

(4028) 0x53f420 ADD	X0, X3, X13

(4028) 0x53f424 CMP	X13, X0

(4028) 0x53f428 B.GE	53f614

(4028) 0x53f42c SUB	X2, X3, #1

(4028) 0x53f430 LDP	X12, X11, [X20]

(4028) 0x53f434 CMP	X2, #6

(4028) 0x53f438 B.LS	53f67c

(4028) 0x53f43c UBFM	X7, X3, #3, #63

(4028) 0x53f440 MOVI	V29.2D, #0

(4028) 0x53f444 ADD	X4, X11, X13,LSL #3

(4028) 0x53f448 UBFM	X6, X7, #58, #57

(4028) 0x53f44c ADD	X1, X12, X13,LSL #3

(4028) 0x53f450 SUB	X8, X6, #64

(4028) 0x53f454 ADD	X14, X4, X7,LSL #6

(4028) 0x53f458 UBFM	X9, X8, #6, #63

(4028) 0x53f45c ADD	X10, X9, #1

(4028) 0x53f460 ORR	V1.16B, V29.16B, V29.16B

(4028) 0x53f464 ORR	V28.16B, V29.16B, V29.16B

(4028) 0x53f468 ANDS	X15, X10, #4160

(4028) 0x53f46c ORR	V2.16B, V29.16B, V29.16B

(4028) 0x53f470 B.EQ	53f4d4

(4028) 0x53f474 CMP	X15, #1

(4028) 0x53f478 B.EQ	53f4a8

(4028) 0x53f47c CMP	X15, #2

(4028) 0x53f480 B.NE	53f654

(4028) 0x53f484 LDP	Q5, Q6, [X1, #16]

(4028) 0x53f488 LDP	Q23, Q7, [X4, #32]

(4028) 0x53f48c LDP	Q16, Q22, [X4], #64

(4028) 0x53f490 LDR	Q17, [X1, #48]

(4028) 0x53f494 LDR	Q18, [X1], #64

(4028) 0x53f498 FMLA	V1.2D, V23.2D, V6.2D

(4028) 0x53f49c FMLA	V28.2D, V22.2D, V5.2D

(4028) 0x53f4a0 FMLA	V29.2D, V7.2D, V17.2D

(4028) 0x53f4a4 FMLA	V2.2D, V16.2D, V18.2D

(4028) 0x53f4a8 LDP	Q19, Q20, [X1, #16]

(4028) 0x53f4ac LDP	Q21, Q31, [X4, #32]

(4028) 0x53f4b0 LDP	Q30, Q0, [X4], #64

(4028) 0x53f4b4 LDR	Q25, [X1, #48]

(4028) 0x53f4b8 LDR	Q26, [X1], #64

(4028) 0x53f4bc FMLA	V1.2D, V21.2D, V20.2D

(4028) 0x53f4c0 FMLA	V28.2D, V0.2D, V19.2D

(4028) 0x53f4c4 FMLA	V29.2D, V31.2D, V25.2D

(4028) 0x53f4c8 FMLA	V2.2D, V30.2D, V26.2D

(4028) 0x53f4cc CMP	X4, X14

(4028) 0x53f4d0 B.EQ	53f58c

  (4029) 0x53f4d4 ORR	X16, XZR, X4

  (4029) 0x53f4d8 ORR	X17, XZR, X1

  (4029) 0x53f4dc LDP	Q24, Q5, [X4, #16]

  (4029) 0x53f4e0 ADD	X18, X4, #192

  (4029) 0x53f4e4 ADD	X30, X1, #192

  (4029) 0x53f4e8 LDR	Q3, [X16], #64

  (4029) 0x53f4ec LDR	Q4, [X17], #64

  (4029) 0x53f4f0 LDP	Q6, Q27, [X1, #16]

  (4029) 0x53f4f4 LDP	Q23, Q17, [X4, #48]

  (4029) 0x53f4f8 ADD	X21, X16, #64

  (4029) 0x53f4fc ADD	X4, X4, #256

  (4029) 0x53f500 LDP	Q22, Q18, [X1, #48]

  (4029) 0x53f504 ADD	X19, X17, #64

  (4029) 0x53f508 ADD	X1, X1, #256

  (4029) 0x53f50c FMLA	V2.2D, V3.2D, V4.2D

  (4029) 0x53f510 LDP	Q7, Q16, [X16, #16]

  (4029) 0x53f514 LDP	Q19, Q20, [X17, #16]

  (4029) 0x53f518 FMLA	V28.2D, V24.2D, V6.2D

  (4029) 0x53f51c LDP	Q21, Q31, [X16, #48]

  (4029) 0x53f520 LDP	Q30, Q0, [X17, #48]

  (4029) 0x53f524 FMLA	V1.2D, V5.2D, V27.2D

  (4029) 0x53f528 LDP	Q26, Q3, [X21, #16]

  (4029) 0x53f52c FMLA	V29.2D, V23.2D, V22.2D

  (4029) 0x53f530 LDR	Q27, [X19, #48]

  (4029) 0x53f534 LDP	Q25, Q4, [X19, #16]

  (4029) 0x53f538 FMLA	V2.2D, V17.2D, V18.2D

  (4029) 0x53f53c LDR	Q24, [X21, #48]

  (4029) 0x53f540 FMLA	V28.2D, V7.2D, V19.2D

  (4029) 0x53f544 LDUR	Q17, [X4, #448]

  (4029) 0x53f548 LDP	Q5, Q6, [X30, #16]

  (4029) 0x53f54c FMLA	V1.2D, V16.2D, V20.2D

  (4029) 0x53f550 LDP	Q7, Q16, [X18, #16]

  (4029) 0x53f554 FMLA	V29.2D, V21.2D, V30.2D

  (4029) 0x53f558 LDUR	Q22, [X1, #448]

  (4029) 0x53f55c LDR	Q23, [X30, #48]

  (4029) 0x53f560 FMLA	V28.2D, V26.2D, V25.2D

  (4029) 0x53f564 LDR	Q18, [X18, #48]

  (4029) 0x53f568 FMLA	V1.2D, V3.2D, V4.2D

  (4029) 0x53f56c FMLA	V2.2D, V31.2D, V0.2D

  (4029) 0x53f570 FMLA	V29.2D, V24.2D, V27.2D

  (4029) 0x53f574 FMLA	V28.2D, V7.2D, V5.2D

  (4029) 0x53f578 FMLA	V1.2D, V16.2D, V6.2D

  (4029) 0x53f57c FMLA	V2.2D, V17.2D, V22.2D

  (4029) 0x53f580 FMLA	V29.2D, V18.2D, V23.2D

  (4029) 0x53f584 CMP	X4, X14

  (4029) 0x53f588 B.NE	53f4d4

(4028) 0x53f58c AND	X5, X3, #7997

(4028) 0x53f590 FADD	V29.2D, V1.2D, V29.2D

(4028) 0x53f594 FADD	V28.2D, V2.2D, V28.2D

(4028) 0x53f598 FADD	V31.2D, V29.2D, V28.2D

(4028) 0x53f59c CMP	X5, X3

(4028) 0x53f5a0 B.EQ	53f60c

(4028) 0x53f5a4 ADD	X13, X5, X13

(4028) 0x53f5a8 SUB	X3, X3, X5

(4028) 0x53f5ac WHILELO	P7.D, XZR, X3

(4028) 0x53f5b0 LD1D	{Z2.D}, P7/Z, [X12, X13,LSL #3]

(4028) 0x53f5b4 LD1D	{Z1.D}, P7/Z, [X11, X13,LSL #3]

(4028) 0x53f5b8 MOVZ	X0, #2

(4028) 0x53f5bc ADD	X2, X11, X13,LSL #3

(4028) 0x53f5c0 FMLA	Z31.D, P7/M, Z2.D, Z1.D

(4028) 0x53f5c4 WHILELO	P0.D, X0, X3

(4028) 0x53f5c8 ADD	X12, X12, X13,LSL #3

(4028) 0x53f5cc B.EQ	53f60c

(4028) 0x53f5d0 MOVZ	X11, #4

(4028) 0x53f5d4 LD1D	{Z19.D}, P0/Z, [X2, #1, MUL VL]

(4028) 0x53f5d8 LD1D	{Z20.D}, P0/Z, [X12, #1, MUL VL]

(4028) 0x53f5dc WHILELO	P1.D, X11, X3

(4028) 0x53f5e0 FMLA	Z31.D, P0/M, Z20.D, Z19.D

(4028) 0x53f5e4 B.EQ	53f60c

(4028) 0x53f5e8 MOVZ	X5, #6

(4028) 0x53f5ec LD1D	{Z21.D}, P1/Z, [X2, #2, MUL VL]

(4028) 0x53f5f0 LD1D	{Z30.D}, P1/Z, [X12, #2, MUL VL]

(4028) 0x53f5f4 WHILELO	P2.D, X5, X3

(4028) 0x53f5f8 FMLA	Z31.D, P1/M, Z21.D, Z30.D

(4028) 0x53f5fc B.EQ	53f60c

(4028) 0x53f600 LD1D	{Z0.D}, P2/Z, [X2, #3, MUL VL]

(4028) 0x53f604 LD1D	{Z26.D}, P2/Z, [X12, #3, MUL VL]

(4028) 0x53f608 FMLA	Z31.D, P2/M, Z0.D, Z26.D

(4028) 0x53f60c PTRUE	P3.B, VL16

(4028) 0x53f610 FADDV	D31, P3, Z31.D

(4028) 0x53f614 ADD	X20, X20, #24

(4028) 0x53f618 LDR	X1, [X20]

  (4027) 0x53f61c FMOV	D3, X1

  (4027) 0x53f620 ORR	X7, XZR, X1

  (4027) 0x53f624 FADD	D25, D31, D3

  (4027) 0x53f628 FMOV	X6, D25

  (4027) 0x53f62c CAS	X7, X6, [X20]

  (4027) 0x53f630 CMP	X1, X7

  (4027) 0x53f634 B.NE	53f688

(4028) 0x53f638 LDR	X21, [SP, #32]

(4028) 0x53f63c LDP	X19, X20, [SP, #16]

(4028) 0x53f640 LDP	X29, X30, [SP], #48

(4028) 0x53f644 RET

(4028) 0x53f648 ADD	X3, X3, #1

(4028) 0x53f64c MOVZ	X1, #0

(4028) 0x53f650 B	53f418

(4028) 0x53f654 LDP	Q30, Q0, [X1, #16]

(4028) 0x53f658 LDP	Q25, Q26, [X4, #32]

(4028) 0x53f65c LDP	Q24, Q27, [X4], #64

(4028) 0x53f660 LDR	Q3, [X1, #48]

(4028) 0x53f664 LDR	Q4, [X1], #64

(4028) 0x53f668 FMLA	V1.2D, V25.2D, V0.2D

(4028) 0x53f66c FMLA	V28.2D, V27.2D, V30.2D

(4028) 0x53f670 FMLA	V2.2D, V24.2D, V4.2D

(4028) 0x53f674 FMLA	V29.2D, V26.2D, V3.2D

(4028) 0x53f678 B	53f484

(4028) 0x53f67c MOVZ	X5, #0

(4028) 0x53f680 DUP	Z31.D, #0

(4028) 0x53f684 B	53f5a4

  (4027) 0x53f688 ORR	X1, XZR, X7

  (4027) 0x53f68c B	53f61c

Coverage (%)	Name	Source Location	Module
►98.67+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	vector.c:483-486
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/vector.c:483-486.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 68% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 20.00 to 10.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	14
loop length	56
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.75
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 53f3e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X21, [X0, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 410930 <@plt_start@+0x1b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X19, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (100.0%)
BL 410940 <@plt_start@+0x1c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X4, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SDIV X3, X21, X19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
MSUB X1, X3, X19, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP X4, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.LT 53f648 <hypre_SeqVectorInnerProd._omp_fn.0+0x268>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	vector.c:483-486
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/vector.c:483-486.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	14
loop length	56
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.75
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 53f3e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X21, [X0, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 410930 <@plt_start@+0x1b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X19, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (100.0%)
BL 410940 <@plt_start@+0x1c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X4, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SDIV X3, X21, X19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
MSUB X1, X3, X19, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP X4, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.LT 53f648 <hypre_SeqVectorInnerProd._omp_fn.0+0x268>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼hypre_SeqVectorInnerProd._omp_fn.0–	0.98	0.16
▼Loop 4028 - vector.c:483-486 - exec–	0.00	0.00
○Loop 4029 - vector.c:486-486 - exec	0.98	0.12
○Loop 4027 - vector.c:483-483 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code