OV - exec - Function hypre_SeqVectorAxpy._omp

	Function: hypre_SeqVectorAxpy._omp_fn.0	Module: exec	Source: vector.c:449-452	Coverage (incl. loops): 1.89% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/vector.c: 449 - 452

--------------------------------------------------------------------------------

449: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

450: #endif

451:    for (i = 0; i < size; i++)

452:       y_data[i] += alpha * x_data[i];

0x53f020 STP	X29, X30, [SP, #976]!

0x53f024 ADD	X29, SP, #0

0x53f028 STP	X19, X20, [SP, #16]

0x53f02c ORR	X20, XZR, X0

0x53f030 STR	X21, [SP, #32]

0x53f034 LDR	X21, [X0, #24]

0x53f038 BL	410930

0x53f03c SBFM	X19, X0, #0, #31

0x53f040 BL	410940

0x53f044 SBFM	X1, X0, #0, #31

0x53f048 SDIV	X4, X21, X19

0x53f04c MSUB	X2, X4, X19, X21

0x53f050 CMP	X1, X2

0x53f054 B.LT	53f24c

(4024) 0x53f058 MADD	X1, X4, X1, X2

(4024) 0x53f05c ADD	X0, X4, X1

(4024) 0x53f060 CMP	X1, X0

(4024) 0x53f064 B.GE	53f23c

(4024) 0x53f068 SUB	X3, X4, #1

(4024) 0x53f06c LDR	D30, [X20]

(4024) 0x53f070 LDP	X8, X6, [X20, #8]

(4024) 0x53f074 CMP	X3, #1

(4024) 0x53f078 B.LS	53f258

(4024) 0x53f07c ADD	X15, X8, X1,LSL #3

(4024) 0x53f080 ADD	X16, X6, X1,LSL #3

(4024) 0x53f084 WHILEWR	P15.D, X15, X16

(4024) 0x53f088 B.CS	53f258

(4024) 0x53f08c UBFM	X7, X4, #1, #63

(4024) 0x53f090 DUP	V31.2D, V30.D[0]

(4024) 0x53f094 MOVZ	X18, #0

(4024) 0x53f098 UBFM	X17, X7, #60, #59

(4024) 0x53f09c SUB	X5, X17, #16

(4024) 0x53f0a0 UBFM	X9, X5, #4, #63

(4024) 0x53f0a4 ADD	X10, X9, #1

(4024) 0x53f0a8 ANDS	X11, X10, #4224

(4024) 0x53f0ac B.EQ	53f174

(4024) 0x53f0b0 CMP	X11, #1

(4024) 0x53f0b4 B.EQ	53f158

(4024) 0x53f0b8 CMP	X11, #2

(4024) 0x53f0bc B.EQ	53f144

(4024) 0x53f0c0 CMP	X11, #3

(4024) 0x53f0c4 B.EQ	53f130

(4024) 0x53f0c8 CMP	X11, #4

(4024) 0x53f0cc B.EQ	53f11c

(4024) 0x53f0d0 CMP	X11, #5

(4024) 0x53f0d4 B.EQ	53f108

(4024) 0x53f0d8 CMP	X11, #6

(4024) 0x53f0dc B.EQ	53f0f4

(4024) 0x53f0e0 LDR	Q29, [X16]

(4024) 0x53f0e4 MOVZ	X18, #16

(4024) 0x53f0e8 LDR	Q28, [X15]

(4024) 0x53f0ec FMLA	V29.2D, V28.2D, V31.2D

(4024) 0x53f0f0 STR	Q29, [X16]

(4024) 0x53f0f4 LDR	Q0, [X15, X18]

(4024) 0x53f0f8 LDR	Q1, [X16, X18]

(4024) 0x53f0fc FMLA	V1.2D, V0.2D, V31.2D

(4024) 0x53f100 STR	Q1, [X16, X18]

(4024) 0x53f104 ADD	X18, X18, #16

(4024) 0x53f108 LDR	Q2, [X15, X18]

(4024) 0x53f10c LDR	Q3, [X16, X18]

(4024) 0x53f110 FMLA	V3.2D, V2.2D, V31.2D

(4024) 0x53f114 STR	Q3, [X16, X18]

(4024) 0x53f118 ADD	X18, X18, #16

(4024) 0x53f11c LDR	Q4, [X15, X18]

(4024) 0x53f120 LDR	Q5, [X16, X18]

(4024) 0x53f124 FMLA	V5.2D, V4.2D, V31.2D

(4024) 0x53f128 STR	Q5, [X16, X18]

(4024) 0x53f12c ADD	X18, X18, #16

(4024) 0x53f130 LDR	Q6, [X15, X18]

(4024) 0x53f134 LDR	Q7, [X16, X18]

(4024) 0x53f138 FMLA	V7.2D, V6.2D, V31.2D

(4024) 0x53f13c STR	Q7, [X16, X18]

(4024) 0x53f140 ADD	X18, X18, #16

(4024) 0x53f144 LDR	Q16, [X15, X18]

(4024) 0x53f148 LDR	Q17, [X16, X18]

(4024) 0x53f14c FMLA	V17.2D, V16.2D, V31.2D

(4024) 0x53f150 STR	Q17, [X16, X18]

(4024) 0x53f154 ADD	X18, X18, #16

(4024) 0x53f158 LDR	Q18, [X15, X18]

(4024) 0x53f15c LDR	Q19, [X16, X18]

(4024) 0x53f160 FMLA	V19.2D, V18.2D, V31.2D

(4024) 0x53f164 STR	Q19, [X16, X18]

(4024) 0x53f168 ADD	X18, X18, #16

(4024) 0x53f16c CMP	X17, X18

(4024) 0x53f170 B.EQ	53f21c

  (4026) 0x53f174 LDR	Q20, [X15, X18]

  (4026) 0x53f178 ADD	X30, X18, #16

  (4026) 0x53f17c ADD	X14, X18, #32

  (4026) 0x53f180 ADD	X13, X18, #48

  (4026) 0x53f184 ADD	X12, X18, #64

  (4026) 0x53f188 LDR	Q21, [X16, X18]

  (4026) 0x53f18c ADD	X20, X18, #80

  (4026) 0x53f190 ADD	X21, X18, #96

  (4026) 0x53f194 ADD	X19, X18, #112

  (4026) 0x53f198 FMLA	V21.2D, V20.2D, V31.2D

  (4026) 0x53f19c STR	Q21, [X16, X18]

  (4026) 0x53f1a0 ADD	X18, X18, #128

  (4026) 0x53f1a4 LDR	Q22, [X15, X30]

  (4026) 0x53f1a8 LDR	Q23, [X16, X30]

  (4026) 0x53f1ac FMLA	V23.2D, V22.2D, V31.2D

  (4026) 0x53f1b0 STR	Q23, [X16, X30]

  (4026) 0x53f1b4 LDR	Q24, [X15, X14]

  (4026) 0x53f1b8 LDR	Q25, [X16, X14]

  (4026) 0x53f1bc FMLA	V25.2D, V24.2D, V31.2D

  (4026) 0x53f1c0 STR	Q25, [X16, X14]

  (4026) 0x53f1c4 LDR	Q26, [X15, X13]

  (4026) 0x53f1c8 LDR	Q27, [X16, X13]

  (4026) 0x53f1cc FMLA	V27.2D, V26.2D, V31.2D

  (4026) 0x53f1d0 STR	Q27, [X16, X13]

  (4026) 0x53f1d4 LDR	Q28, [X15, X12]

  (4026) 0x53f1d8 LDR	Q29, [X16, X12]

  (4026) 0x53f1dc FMLA	V29.2D, V28.2D, V31.2D

  (4026) 0x53f1e0 STR	Q29, [X16, X12]

  (4026) 0x53f1e4 LDR	Q0, [X15, X20]

  (4026) 0x53f1e8 LDR	Q1, [X16, X20]

  (4026) 0x53f1ec FMLA	V1.2D, V0.2D, V31.2D

  (4026) 0x53f1f0 STR	Q1, [X16, X20]

  (4026) 0x53f1f4 LDR	Q2, [X15, X21]

  (4026) 0x53f1f8 LDR	Q3, [X16, X21]

  (4026) 0x53f1fc FMLA	V3.2D, V2.2D, V31.2D

  (4026) 0x53f200 STR	Q3, [X16, X21]

  (4026) 0x53f204 LDR	Q4, [X15, X19]

  (4026) 0x53f208 LDR	Q5, [X16, X19]

  (4026) 0x53f20c FMLA	V5.2D, V4.2D, V31.2D

  (4026) 0x53f210 STR	Q5, [X16, X19]

  (4026) 0x53f214 CMP	X17, X18

  (4026) 0x53f218 B.NE	53f174

(4024) 0x53f21c AND	X2, X4, #8127

(4024) 0x53f220 TBZ	W4, #0, 53f23c

(4024) 0x53f224 ADD	X1, X1, X2

(4024) 0x53f228 UBFM	X4, X1, #61, #60

(4024) 0x53f22c LDR	D6, [X8, X4]

(4024) 0x53f230 LDR	D31, [X6, X4]

(4024) 0x53f234 FMADD	D30, D30, D6, D31

(4024) 0x53f238 STR	D30, [X6, X4]

(4024) 0x53f23c LDR	X21, [SP, #32]

(4024) 0x53f240 LDP	X19, X20, [SP, #16]

(4024) 0x53f244 LDP	X29, X30, [SP], #48

(4024) 0x53f248 RET

(4024) 0x53f24c ADD	X4, X4, #1

(4024) 0x53f250 MOVZ	X2, #0

(4024) 0x53f254 B	53f058

(4024) 0x53f258 SUB	X3, X0, X1

(4024) 0x53f25c ANDS	X15, X3, #4224

(4024) 0x53f260 B.EQ	53f328

(4024) 0x53f264 CMP	X15, #1

(4024) 0x53f268 B.EQ	53f30c

(4024) 0x53f26c CMP	X15, #2

(4024) 0x53f270 B.EQ	53f2f8

(4024) 0x53f274 CMP	X15, #3

(4024) 0x53f278 B.EQ	53f2e4

(4024) 0x53f27c CMP	X15, #4

(4024) 0x53f280 B.EQ	53f2d0

(4024) 0x53f284 CMP	X15, #5

(4024) 0x53f288 B.EQ	53f2bc

(4024) 0x53f28c CMP	X15, #6

(4024) 0x53f290 B.EQ	53f2a8

(4024) 0x53f294 LDR	D7, [X8, X1,LSL #3]

(4024) 0x53f298 LDR	D16, [X6, X1,LSL #3]

(4024) 0x53f29c FMADD	D17, D30, D7, D16

(4024) 0x53f2a0 STR	D17, [X6, X1,LSL #3]

(4024) 0x53f2a4 ADD	X1, X1, #1

(4024) 0x53f2a8 LDR	D18, [X8, X1,LSL #3]

(4024) 0x53f2ac LDR	D19, [X6, X1,LSL #3]

(4024) 0x53f2b0 FMADD	D20, D30, D18, D19

(4024) 0x53f2b4 STR	D20, [X6, X1,LSL #3]

(4024) 0x53f2b8 ADD	X1, X1, #1

(4024) 0x53f2bc LDR	D21, [X8, X1,LSL #3]

(4024) 0x53f2c0 LDR	D22, [X6, X1,LSL #3]

(4024) 0x53f2c4 FMADD	D23, D30, D21, D22

(4024) 0x53f2c8 STR	D23, [X6, X1,LSL #3]

(4024) 0x53f2cc ADD	X1, X1, #1

(4024) 0x53f2d0 LDR	D24, [X8, X1,LSL #3]

(4024) 0x53f2d4 LDR	D25, [X6, X1,LSL #3]

(4024) 0x53f2d8 FMADD	D26, D30, D24, D25

(4024) 0x53f2dc STR	D26, [X6, X1,LSL #3]

(4024) 0x53f2e0 ADD	X1, X1, #1

(4024) 0x53f2e4 LDR	D27, [X8, X1,LSL #3]

(4024) 0x53f2e8 LDR	D28, [X6, X1,LSL #3]

(4024) 0x53f2ec FMADD	D29, D30, D27, D28

(4024) 0x53f2f0 STR	D29, [X6, X1,LSL #3]

(4024) 0x53f2f4 ADD	X1, X1, #1

(4024) 0x53f2f8 LDR	D0, [X8, X1,LSL #3]

(4024) 0x53f2fc LDR	D1, [X6, X1,LSL #3]

(4024) 0x53f300 FMADD	D2, D30, D0, D1

(4024) 0x53f304 STR	D2, [X6, X1,LSL #3]

(4024) 0x53f308 ADD	X1, X1, #1

(4024) 0x53f30c LDR	D3, [X8, X1,LSL #3]

(4024) 0x53f310 LDR	D4, [X6, X1,LSL #3]

(4024) 0x53f314 FMADD	D5, D30, D3, D4

(4024) 0x53f318 STR	D5, [X6, X1,LSL #3]

(4024) 0x53f31c ADD	X1, X1, #1

(4024) 0x53f320 CMP	X0, X1

(4024) 0x53f324 B.EQ	53f23c

  (4025) 0x53f328 LDR	D6, [X8, X1,LSL #3]

  (4025) 0x53f32c ADD	X16, X1, #1

  (4025) 0x53f330 ADD	X9, X1, #2

  (4025) 0x53f334 ADD	X17, X1, #3

  (4025) 0x53f338 ADD	X7, X1, #4

  (4025) 0x53f33c LDR	D31, [X6, X1,LSL #3]

  (4025) 0x53f340 ADD	X5, X1, #5

  (4025) 0x53f344 ADD	X10, X1, #6

  (4025) 0x53f348 ADD	X11, X1, #7

  (4025) 0x53f34c FMADD	D7, D30, D6, D31

  (4025) 0x53f350 STR	D7, [X6, X1,LSL #3]

  (4025) 0x53f354 ADD	X1, X1, #8

  (4025) 0x53f358 LDR	D16, [X8, X16,LSL #3]

  (4025) 0x53f35c LDR	D17, [X6, X16,LSL #3]

  (4025) 0x53f360 FMADD	D18, D30, D16, D17

  (4025) 0x53f364 STR	D18, [X6, X16,LSL #3]

  (4025) 0x53f368 LDR	D19, [X8, X9,LSL #3]

  (4025) 0x53f36c LDR	D20, [X6, X9,LSL #3]

  (4025) 0x53f370 FMADD	D21, D30, D19, D20

  (4025) 0x53f374 STR	D21, [X6, X9,LSL #3]

  (4025) 0x53f378 LDR	D22, [X8, X17,LSL #3]

  (4025) 0x53f37c LDR	D23, [X6, X17,LSL #3]

  (4025) 0x53f380 FMADD	D24, D30, D22, D23

  (4025) 0x53f384 STR	D24, [X6, X17,LSL #3]

  (4025) 0x53f388 LDR	D25, [X8, X7,LSL #3]

  (4025) 0x53f38c LDR	D26, [X6, X7,LSL #3]

  (4025) 0x53f390 FMADD	D27, D30, D25, D26

  (4025) 0x53f394 STR	D27, [X6, X7,LSL #3]

  (4025) 0x53f398 LDR	D28, [X8, X5,LSL #3]

  (4025) 0x53f39c LDR	D29, [X6, X5,LSL #3]

  (4025) 0x53f3a0 FMADD	D0, D30, D28, D29

  (4025) 0x53f3a4 STR	D0, [X6, X5,LSL #3]

  (4025) 0x53f3a8 LDR	D1, [X8, X10,LSL #3]

  (4025) 0x53f3ac LDR	D2, [X6, X10,LSL #3]

  (4025) 0x53f3b0 FMADD	D3, D30, D1, D2

  (4025) 0x53f3b4 STR	D3, [X6, X10,LSL #3]

  (4025) 0x53f3b8 LDR	D4, [X8, X11,LSL #3]

  (4025) 0x53f3bc LDR	D5, [X6, X11,LSL #3]

  (4025) 0x53f3c0 FMADD	D6, D30, D4, D5

  (4025) 0x53f3c4 STR	D6, [X6, X11,LSL #3]

  (4025) 0x53f3c8 CMP	X0, X1

  (4025) 0x53f3cc B.NE	53f328

(4024) 0x53f3d0 B	53f23c

0x53f3d4 HINT	#0

0x53f3d8 HINT	#0

0x53f3dc HINT	#0

Coverage (%)	Name	Source Location	Module
►99.00+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	vector.c:449-452
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/vector.c:449-452.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 68% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 20.00 to 10.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	17
loop length	68
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.75
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 53f020

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X21, [X0, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 410930 <@plt_start@+0x1b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X19, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
BL 410940 <@plt_start@+0x1c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X1, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SDIV X4, X21, X19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
MSUB X2, X4, X19, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP X1, X2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 53f24c <hypre_SeqVectorAxpy._omp_fn.0+0x22c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	vector.c:449-452
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/vector.c:449-452.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	17
loop length	68
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.75
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 53f020

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X21, [X0, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 410930 <@plt_start@+0x1b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X19, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
BL 410940 <@plt_start@+0x1c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X1, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SDIV X4, X21, X19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
MSUB X2, X4, X19, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP X1, X2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 53f24c <hypre_SeqVectorAxpy._omp_fn.0+0x22c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼hypre_SeqVectorAxpy._omp_fn.0–	1.89	0.30
▼Loop 4024 - vector.c:449-452 - exec–	0.00	0.00
○Loop 4026 - vector.c:452-452 - exec	1.89	0.23
○Loop 4025 - vector.c:452-452 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code