OV - exec - Function hypre_SeqVectorScale._omp

	Function: hypre_SeqVectorScale._omp_fn.0	Module: exec	Source: vector.c:413-416	Coverage (incl. loops): 0.34% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/vector.c: 413 - 416

--------------------------------------------------------------------------------

413: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

414: #endif

415:    for (i = 0; i < size; i++)

416:       y_data[i] *= alpha;

0x53edec STP	X29, X30, [SP, #976]!

0x53edf0 ADD	X29, SP, #0

0x53edf4 STP	X19, X20, [SP, #16]

0x53edf8 ORR	X20, XZR, X0

0x53edfc STR	X21, [SP, #32]

0x53ee00 LDR	X21, [X0, #16]

0x53ee04 BL	410930

0x53ee08 SBFM	X19, X0, #0, #31

0x53ee0c BL	410940

0x53ee10 SBFM	X2, X0, #0, #31

0x53ee14 SDIV	X3, X21, X19

0x53ee18 MSUB	X1, X3, X19, X21

0x53ee1c CMP	X2, X1

0x53ee20 B.LT	53f014

(4022) 0x53ee24 MADD	X16, X3, X2, X1

(4022) 0x53ee28 ADD	X5, X3, X16

(4022) 0x53ee2c CMP	X16, X5

(4022) 0x53ee30 B.GE	53f004

(4022) 0x53ee34 SUB	X0, X3, #1

(4022) 0x53ee38 LDR	D31, [X20]

(4022) 0x53ee3c LDR	X6, [X20, #8]

(4022) 0x53ee40 CMP	X0, #2

(4022) 0x53ee44 B.LS	53efbc

(4022) 0x53ee48 UBFM	X4, X3, #2, #63

(4022) 0x53ee4c ADD	X14, X6, X16,LSL #3

(4022) 0x53ee50 DUP	V30.2D, V31.D[0]

(4022) 0x53ee54 UBFM	X7, X4, #59, #58

(4022) 0x53ee58 SUB	X8, X7, #32

(4022) 0x53ee5c ADD	X9, X14, X4,LSL #5

(4022) 0x53ee60 UBFM	X10, X8, #5, #63

(4022) 0x53ee64 ADD	X11, X10, #1

(4022) 0x53ee68 ANDS	X12, X11, #4224

(4022) 0x53ee6c B.EQ	53ef18

(4022) 0x53ee70 CMP	X12, #1

(4022) 0x53ee74 B.EQ	53ef00

(4022) 0x53ee78 CMP	X12, #2

(4022) 0x53ee7c B.EQ	53eef0

(4022) 0x53ee80 CMP	X12, #3

(4022) 0x53ee84 B.EQ	53eee0

(4022) 0x53ee88 CMP	X12, #4

(4022) 0x53ee8c B.EQ	53eed0

(4022) 0x53ee90 CMP	X12, #5

(4022) 0x53ee94 B.EQ	53eec0

(4022) 0x53ee98 CMP	X12, #6

(4022) 0x53ee9c B.EQ	53eeb0

(4022) 0x53eea0 LDP	Q7, Q16, [X14]

(4022) 0x53eea4 FMUL	V0.2D, V7.2D, V30.2D

(4022) 0x53eea8 FMUL	V1.2D, V16.2D, V30.2D

(4022) 0x53eeac STP	Q0, Q1, [X14], #32

(4022) 0x53eeb0 LDP	Q5, Q6, [X14]

(4022) 0x53eeb4 FMUL	V2.2D, V5.2D, V30.2D

(4022) 0x53eeb8 FMUL	V3.2D, V6.2D, V30.2D

(4022) 0x53eebc STP	Q2, Q3, [X14], #32

(4022) 0x53eec0 LDP	Q17, Q4, [X14]

(4022) 0x53eec4 FMUL	V18.2D, V17.2D, V30.2D

(4022) 0x53eec8 FMUL	V19.2D, V4.2D, V30.2D

(4022) 0x53eecc STP	Q18, Q19, [X14], #32

(4022) 0x53eed0 LDP	Q20, Q29, [X14]

(4022) 0x53eed4 FMUL	V21.2D, V20.2D, V30.2D

(4022) 0x53eed8 FMUL	V22.2D, V29.2D, V30.2D

(4022) 0x53eedc STP	Q21, Q22, [X14], #32

(4022) 0x53eee0 LDP	Q28, Q23, [X14]

(4022) 0x53eee4 FMUL	V24.2D, V28.2D, V30.2D

(4022) 0x53eee8 FMUL	V25.2D, V23.2D, V30.2D

(4022) 0x53eeec STP	Q24, Q25, [X14], #32

(4022) 0x53eef0 LDP	Q27, Q26, [X14]

(4022) 0x53eef4 FMUL	V7.2D, V27.2D, V30.2D

(4022) 0x53eef8 FMUL	V16.2D, V26.2D, V30.2D

(4022) 0x53eefc STP	Q7, Q16, [X14], #32

(4022) 0x53ef00 LDP	Q0, Q1, [X14]

(4022) 0x53ef04 FMUL	V5.2D, V0.2D, V30.2D

(4022) 0x53ef08 FMUL	V6.2D, V1.2D, V30.2D

(4022) 0x53ef0c STP	Q5, Q6, [X14], #32

(4022) 0x53ef10 CMP	X14, X9

(4022) 0x53ef14 B.EQ	53efac

  (4023) 0x53ef18 LDP	Q2, Q3, [X14]

  (4023) 0x53ef1c ORR	X13, XZR, X14

  (4023) 0x53ef20 LDP	Q28, Q18, [X14, #96]

  (4023) 0x53ef24 LDP	Q21, Q22, [X14, #32]

  (4023) 0x53ef28 LDP	Q19, Q20, [X14, #64]

  (4023) 0x53ef2c LDP	Q23, Q24, [X14, #128]

  (4023) 0x53ef30 FMUL	V17.2D, V2.2D, V30.2D

  (4023) 0x53ef34 LDP	Q25, Q27, [X14, #160]

  (4023) 0x53ef38 FMUL	V4.2D, V3.2D, V30.2D

  (4023) 0x53ef3c LDP	Q26, Q0, [X14, #192]

  (4023) 0x53ef40 FMUL	V21.2D, V21.2D, V30.2D

  (4023) 0x53ef44 LDP	Q1, Q29, [X14, #224]

  (4023) 0x53ef48 ADD	X14, X14, #256

  (4023) 0x53ef4c FMUL	V22.2D, V22.2D, V30.2D

  (4023) 0x53ef50 FMUL	V19.2D, V19.2D, V30.2D

  (4023) 0x53ef54 FMUL	V20.2D, V20.2D, V30.2D

  (4023) 0x53ef58 FMUL	V7.2D, V23.2D, V30.2D

  (4023) 0x53ef5c FMUL	V16.2D, V24.2D, V30.2D

  (4023) 0x53ef60 FMUL	V5.2D, V25.2D, V30.2D

  (4023) 0x53ef64 FMUL	V6.2D, V27.2D, V30.2D

  (4023) 0x53ef68 FMUL	V3.2D, V26.2D, V30.2D

  (4023) 0x53ef6c FMUL	V2.2D, V1.2D, V30.2D

  (4023) 0x53ef70 STP	Q17, Q4, [X14, #1792]

  (4023) 0x53ef74 FMUL	V17.2D, V28.2D, V30.2D

  (4023) 0x53ef78 FMUL	V4.2D, V0.2D, V30.2D

  (4023) 0x53ef7c FMUL	V28.2D, V18.2D, V30.2D

  (4023) 0x53ef80 STUR	Q2, [X14, #480]

  (4023) 0x53ef84 FMUL	V18.2D, V29.2D, V30.2D

  (4023) 0x53ef88 STP	Q21, Q22, [X14, #1824]

  (4023) 0x53ef8c STP	Q19, Q20, [X14, #1856]

  (4023) 0x53ef90 STP	Q17, Q28, [X14, #1888]

  (4023) 0x53ef94 STP	Q7, Q16, [X14, #1920]

  (4023) 0x53ef98 STP	Q5, Q6, [X14, #1952]

  (4023) 0x53ef9c STP	Q3, Q4, [X14, #1984]

  (4023) 0x53efa0 STR	Q18, [X13, #240]

  (4023) 0x53efa4 CMP	X14, X9

  (4023) 0x53efa8 B.NE	53ef18

(4022) 0x53efac AND	X15, X3, #8062

(4022) 0x53efb0 ADD	X16, X16, X15

(4022) 0x53efb4 CMP	X3, X15

(4022) 0x53efb8 B.EQ	53f004

(4022) 0x53efbc UBFM	X17, X16, #61, #60

(4022) 0x53efc0 ADD	X18, X16, #1

(4022) 0x53efc4 LDR	D30, [X6, X17]

(4022) 0x53efc8 FMUL	D23, D30, D31

(4022) 0x53efcc STR	D23, [X6, X17]

(4022) 0x53efd0 CMP	X5, X18

(4022) 0x53efd4 B.LE	53f004

(4022) 0x53efd8 ADD	X30, X17, #8

(4022) 0x53efdc ADD	X20, X16, #2

(4022) 0x53efe0 LDR	D24, [X6, X30]

(4022) 0x53efe4 FMUL	D25, D24, D31

(4022) 0x53efe8 STR	D25, [X6, X30]

(4022) 0x53efec CMP	X5, X20

(4022) 0x53eff0 B.LE	53f004

(4022) 0x53eff4 ADD	X21, X17, #16

(4022) 0x53eff8 LDR	D27, [X6, X21]

(4022) 0x53effc FMUL	D31, D27, D31

(4022) 0x53f000 STR	D31, [X6, X21]

(4022) 0x53f004 LDR	X21, [SP, #32]

(4022) 0x53f008 LDP	X19, X20, [SP, #16]

(4022) 0x53f00c LDP	X29, X30, [SP], #48

(4022) 0x53f010 RET

(4022) 0x53f014 ADD	X3, X3, #1

(4022) 0x53f018 MOVZ	X1, #0

(4022) 0x53f01c B	53ee24

Coverage (%)	Name	Source Location	Module
►99.63+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	vector.c:413-416
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/vector.c:413-416.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 68% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 20.00 to 10.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	14
loop length	56
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.75
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 53edec

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X21, [X0, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 410930 <@plt_start@+0x1b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X19, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (100.0%)
BL 410940 <@plt_start@+0x1c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X2, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SDIV X3, X21, X19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
MSUB X1, X3, X19, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP X2, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.LT 53f014 <hypre_SeqVectorScale._omp_fn.0+0x228>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	vector.c:413-416
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/vector.c:413-416.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	14
loop length	56
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.75
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 53edec

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X21, [X0, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 410930 <@plt_start@+0x1b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X19, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (100.0%)
BL 410940 <@plt_start@+0x1c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X2, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SDIV X3, X21, X19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
MSUB X1, X3, X19, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP X2, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.LT 53f014 <hypre_SeqVectorScale._omp_fn.0+0x228>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼hypre_SeqVectorScale._omp_fn.0–	0.34	0.05
▼Loop 4022 - vector.c:413-416 - exec–	0.00	0.00
○Loop 4023 - vector.c:416-416 - exec	0.34	0.04

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code