OV - exec - Function hypre_SeqVectorSetConstantValues._omp

	Function: hypre_SeqVectorSetConstantValues._omp_fn.0	Module: exec	Source: vector.c:268-271	Coverage (incl. loops): 0.20% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/vector.c: 268 - 271

--------------------------------------------------------------------------------

268: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

269: #endif

270:    for (i = 0; i < size; i++)

271:       vector_data[i] = value;

0x53e8a0 STP	X29, X30, [SP, #976]!

0x53e8a4 ADD	X29, SP, #0

0x53e8a8 STP	X19, X20, [SP, #16]

0x53e8ac ORR	X20, XZR, X0

0x53e8b0 STR	X21, [SP, #32]

0x53e8b4 LDR	X21, [X0, #16]

0x53e8b8 BL	410930

0x53e8bc SBFM	X19, X0, #0, #31

0x53e8c0 BL	410940

0x53e8c4 SBFM	X1, X0, #0, #31

0x53e8c8 SDIV	X3, X21, X19

0x53e8cc MSUB	X2, X3, X19, X21

0x53e8d0 CMP	X1, X2

0x53e8d4 B.LT	53ea48

(4017) 0x53e8d8 MADD	X16, X3, X1, X2

(4017) 0x53e8dc ADD	X4, X3, X16

(4017) 0x53e8e0 CMP	X16, X4

(4017) 0x53e8e4 B.GE	53ea38

(4017) 0x53e8e8 SUB	X0, X3, #1

(4017) 0x53e8ec LDR	D30, [X20]

(4017) 0x53e8f0 LDR	X5, [X20, #8]

(4017) 0x53e8f4 CMP	X0, #7

(4017) 0x53e8f8 B.LS	53e9bc

(4017) 0x53e8fc UBFM	X6, X3, #2, #63

(4017) 0x53e900 ADD	X14, X5, X16,LSL #3

(4017) 0x53e904 DUP	V31.2D, V30.D[0]

(4017) 0x53e908 UBFM	X7, X6, #59, #58

(4017) 0x53e90c SUB	X8, X7, #32

(4017) 0x53e910 ADD	X9, X14, X6,LSL #5

(4017) 0x53e914 UBFM	X10, X8, #5, #63

(4017) 0x53e918 ADD	X11, X10, #1

(4017) 0x53e91c ANDS	X12, X11, #4224

(4017) 0x53e920 B.EQ	53e978

(4017) 0x53e924 CMP	X12, #1

(4017) 0x53e928 B.EQ	53e96c

(4017) 0x53e92c CMP	X12, #2

(4017) 0x53e930 B.EQ	53e968

(4017) 0x53e934 CMP	X12, #3

(4017) 0x53e938 B.EQ	53e964

(4017) 0x53e93c CMP	X12, #4

(4017) 0x53e940 B.EQ	53e960

(4017) 0x53e944 CMP	X12, #5

(4017) 0x53e948 B.EQ	53e95c

(4017) 0x53e94c CMP	X12, #6

(4017) 0x53e950 B.EQ	53e958

(4017) 0x53e954 STP	Q31, Q31, [X14], #32

(4017) 0x53e958 STP	Q31, Q31, [X14], #32

(4017) 0x53e95c STP	Q31, Q31, [X14], #32

(4017) 0x53e960 STP	Q31, Q31, [X14], #32

(4017) 0x53e964 STP	Q31, Q31, [X14], #32

(4017) 0x53e968 STP	Q31, Q31, [X14], #32

(4017) 0x53e96c STP	Q31, Q31, [X14], #32

(4017) 0x53e970 CMP	X9, X14

(4017) 0x53e974 B.EQ	53e9ac

  (4018) 0x53e978 ADD	X13, X14, #32

  (4018) 0x53e97c STR	Q31, [X14, #32]

  (4018) 0x53e980 ADD	X14, X14, #256

  (4018) 0x53e984 STP	Q31, Q31, [X14, #1792]

  (4018) 0x53e988 STP	Q31, Q31, [X13, #16]

  (4018) 0x53e98c STUR	Q31, [X14, #336]

  (4018) 0x53e990 STP	Q31, Q31, [X14, #1888]

  (4018) 0x53e994 STP	Q31, Q31, [X14, #1920]

  (4018) 0x53e998 STP	Q31, Q31, [X14, #1952]

  (4018) 0x53e99c STP	Q31, Q31, [X14, #1984]

  (4018) 0x53e9a0 STP	Q31, Q31, [X14, #2016]

  (4018) 0x53e9a4 CMP	X9, X14

  (4018) 0x53e9a8 B.NE	53e978

(4017) 0x53e9ac AND	X15, X3, #8062

(4017) 0x53e9b0 ADD	X16, X16, X15

(4017) 0x53e9b4 CMP	X3, X15

(4017) 0x53e9b8 B.EQ	53ea38

(4017) 0x53e9bc UBFM	X17, X16, #61, #60

(4017) 0x53e9c0 ADD	X18, X16, #1

(4017) 0x53e9c4 STR	D30, [X5, X17]

(4017) 0x53e9c8 CMP	X4, X18

(4017) 0x53e9cc B.LE	53ea38

(4017) 0x53e9d0 ADD	X30, X5, X17

(4017) 0x53e9d4 ADD	X20, X16, #2

(4017) 0x53e9d8 STR	D30, [X30, #8]

(4017) 0x53e9dc CMP	X4, X20

(4017) 0x53e9e0 B.LE	53ea38

(4017) 0x53e9e4 ADD	X21, X16, #3

(4017) 0x53e9e8 STR	D30, [X30, #16]

(4017) 0x53e9ec CMP	X4, X21

(4017) 0x53e9f0 B.LE	53ea38

(4017) 0x53e9f4 ADD	X19, X16, #4

(4017) 0x53e9f8 STR	D30, [X30, #24]

(4017) 0x53e9fc CMP	X4, X19

(4017) 0x53ea00 B.LE	53ea38

(4017) 0x53ea04 ADD	X1, X16, #5

(4017) 0x53ea08 STR	D30, [X30, #32]

(4017) 0x53ea0c CMP	X4, X1

(4017) 0x53ea10 B.LE	53ea38

(4017) 0x53ea14 ADD	X3, X16, #6

(4017) 0x53ea18 STR	D30, [X30, #40]

(4017) 0x53ea1c CMP	X4, X3

(4017) 0x53ea20 B.LE	53ea38

(4017) 0x53ea24 ADD	X2, X16, #7

(4017) 0x53ea28 STR	D30, [X30, #48]

(4017) 0x53ea2c CMP	X4, X2

(4017) 0x53ea30 B.LE	53ea38

(4017) 0x53ea34 STR	D30, [X30, #56]

(4017) 0x53ea38 LDR	X21, [SP, #32]

(4017) 0x53ea3c LDP	X19, X20, [SP, #16]

(4017) 0x53ea40 LDP	X29, X30, [SP], #48

(4017) 0x53ea44 RET

(4017) 0x53ea48 ADD	X3, X3, #1

(4017) 0x53ea4c MOVZ	X2, #0

(4017) 0x53ea50 B	53e8d8

0x53ea54 HINT	#0

0x53ea58 HINT	#0

0x53ea5c HINT	#0

Coverage (%)	Name	Source Location	Module
►97.71+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►2.29+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	hypre_SeqVectorSetConstantValu[...]	vector.c:278	exec
○	hypre_PCGSolve	pcg.c:542	exec
○	main	amg.c:419	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	vector.c:268-271
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/vector.c:268-271.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 68% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 20.00 to 10.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	17
loop length	68
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.75
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 53e8a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X21, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 410930 <@plt_start@+0x1b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X19, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
BL 410940 <@plt_start@+0x1c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X1, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SDIV X3, X21, X19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
MSUB X2, X3, X19, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP X1, X2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 53ea48 <hypre_SeqVectorSetConstantValues._omp_fn.0+0x1a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	vector.c:268-271
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/vector.c:268-271.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	17
loop length	68
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.75
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 53e8a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X21, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 410930 <@plt_start@+0x1b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X19, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
BL 410940 <@plt_start@+0x1c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X1, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SDIV X3, X21, X19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
MSUB X2, X3, X19, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP X1, X2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 53ea48 <hypre_SeqVectorSetConstantValues._omp_fn.0+0x1a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼hypre_SeqVectorSetConstantValues._omp_fn.0–	0.20	0.03
▼Loop 4017 - vector.c:268-271 - exec–	0.00	0.00
○Loop 4018 - vector.c:271-271 - exec	0.20	0.02

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code