OV - exec - Function hypre_CSRMatrixMatvecT._omp

	Function: hypre_CSRMatrixMatvecT._omp_fn.3	Module: exec	Source: csr_matvec.c:554-579 [...]	Coverage (incl. loops): 1.29% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 554 - 579

--------------------------------------------------------------------------------

554: #pragma omp parallel private(i,jj,j,my_thread_num,offset)

555: #endif

556:          {

557:             my_thread_num = hypre_GetThreadNum();

558:             offset =  y_size*my_thread_num;

[...]

564:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

565:                {

566:                   j = A_j[jj];

567:                   y_data_expand[offset + j] += A_data[jj] * x_data[i];

[...]

577:                for (j = 0; j < num_threads; j++)

578:                {

579:                   y_data[i] += y_data_expand[j*y_size + i];

0x53bbe4 STP	X29, X30, [SP, #912]!

0x53bbe8 ADD	X29, SP, #0

0x53bbec STP	X19, X20, [SP, #16]

0x53bbf0 STP	X21, X22, [SP, #32]

0x53bbf4 STP	X23, X24, [SP, #48]

0x53bbf8 STP	X25, X26, [SP, #64]

0x53bbfc STP	X27, X28, [SP, #80]

0x53bc00 LDP	X28, X7, [X0]

0x53bc04 LDR	X26, [X0, #64]

0x53bc08 STR	X7, [SP, #104]

0x53bc0c LDP	X27, X20, [X0, #16]

0x53bc10 LDP	X25, X23, [X0, #32]

0x53bc14 LDP	X22, X19, [X0, #48]

0x53bc18 BL	5499c0

0x53bc1c ORR	X24, XZR, X0

0x53bc20 BL	410930

0x53bc24 SBFM	X21, X0, #0, #31

0x53bc28 BL	410940

0x53bc2c SDIV	X12, X20, X21

0x53bc30 SBFM	X0, X0, #0, #31

0x53bc34 LDR	X14, [SP, #104]

0x53bc38 MSUB	X2, X12, X21, X20

0x53bc3c CMP	X0, X2

0x53bc40 B.LT	53bf78

0x53bc44 MADD	X2, X12, X0, X2

0x53bc48 ADD	X15, X12, X2

0x53bc4c CMP	X2, X15

0x53bc50 B.GE	53bda4

0x53bc54 MADD	X16, X22, X24, XZR

0x53bc58 ADD	X13, X14, #8

0x53bc5c HINT	#0

(3974) 0x53bc60 LDR	X1, [X14, X2,LSL #3]

(3974) 0x53bc64 LDR	X11, [X13, X2,LSL #3]

(3974) 0x53bc68 CMP	X1, X11

(3974) 0x53bc6c B.GE	53bd98

(3974) 0x53bc70 SUB	X3, X11, X1

(3974) 0x53bc74 ANDS	X4, X3, #4160

(3974) 0x53bc78 B.EQ	53bd00

(3974) 0x53bc7c CMP	X4, #1

(3974) 0x53bc80 B.EQ	53bcd4

(3974) 0x53bc84 CMP	X4, #2

(3974) 0x53bc88 B.EQ	53bcb0

(3974) 0x53bc8c LDR	X5, [X27, X1,LSL #3]

(3974) 0x53bc90 LDR	D31, [X28, X1,LSL #3]

(3974) 0x53bc94 ADD	X1, X1, #1

(3974) 0x53bc98 LDR	D30, [X25, X2,LSL #3]

(3974) 0x53bc9c ADD	X6, X16, X5

(3974) 0x53bca0 UBFM	X8, X6, #61, #60

(3974) 0x53bca4 LDR	D29, [X19, X8]

(3974) 0x53bca8 FMADD	D0, D31, D30, D29

(3974) 0x53bcac STR	D0, [X19, X8]

(3974) 0x53bcb0 LDR	X9, [X27, X1,LSL #3]

(3974) 0x53bcb4 LDR	D28, [X28, X1,LSL #3]

(3974) 0x53bcb8 ADD	X1, X1, #1

(3974) 0x53bcbc LDR	D27, [X25, X2,LSL #3]

(3974) 0x53bcc0 ADD	X10, X16, X9

(3974) 0x53bcc4 UBFM	X17, X10, #61, #60

(3974) 0x53bcc8 LDR	D26, [X19, X17]

(3974) 0x53bccc FMADD	D1, D28, D27, D26

(3974) 0x53bcd0 STR	D1, [X19, X17]

(3974) 0x53bcd4 LDR	X18, [X27, X1,LSL #3]

(3974) 0x53bcd8 LDR	D25, [X28, X1,LSL #3]

(3974) 0x53bcdc ADD	X1, X1, #1

(3974) 0x53bce0 LDR	D24, [X25, X2,LSL #3]

(3974) 0x53bce4 ADD	X30, X16, X18

(3974) 0x53bce8 UBFM	X7, X30, #61, #60

(3974) 0x53bcec LDR	D23, [X19, X7]

(3974) 0x53bcf0 FMADD	D2, D25, D24, D23

(3974) 0x53bcf4 STR	D2, [X19, X7]

(3974) 0x53bcf8 CMP	X1, X11

(3974) 0x53bcfc B.EQ	53bd98

  (3975) 0x53bd00 LDR	X20, [X27, X1,LSL #3]

  (3975) 0x53bd04 ADD	X24, X1, #1

  (3975) 0x53bd08 ADD	X12, X1, #3

  (3975) 0x53bd0c ADD	X8, X1, #2

  (3975) 0x53bd10 LDR	D5, [X28, X1,LSL #3]

  (3975) 0x53bd14 ADD	X1, X1, #4

  (3975) 0x53bd18 LDR	D4, [X25, X2,LSL #3]

  (3975) 0x53bd1c ADD	X3, X16, X20

  (3975) 0x53bd20 UBFM	X6, X3, #61, #60

  (3975) 0x53bd24 LDR	X5, [X27, X24,LSL #3]

  (3975) 0x53bd28 LDR	D3, [X19, X6]

  (3975) 0x53bd2c LDR	X4, [X27, X8,LSL #3]

  (3975) 0x53bd30 ADD	X9, X16, X5

  (3975) 0x53bd34 UBFM	X10, X9, #61, #60

  (3975) 0x53bd38 LDR	X17, [X27, X12,LSL #3]

  (3975) 0x53bd3c FMADD	D6, D5, D4, D3

  (3975) 0x53bd40 ADD	X18, X16, X4

  (3975) 0x53bd44 UBFM	X30, X18, #61, #60

  (3975) 0x53bd48 ADD	X7, X16, X17

  (3975) 0x53bd4c UBFM	X20, X7, #61, #60

  (3975) 0x53bd50 STR	D6, [X19, X6]

  (3975) 0x53bd54 LDR	D16, [X28, X24,LSL #3]

  (3975) 0x53bd58 LDR	D7, [X25, X2,LSL #3]

  (3975) 0x53bd5c LDR	D17, [X19, X10]

  (3975) 0x53bd60 FMADD	D18, D16, D7, D17

  (3975) 0x53bd64 STR	D18, [X19, X10]

  (3975) 0x53bd68 LDR	D19, [X28, X8,LSL #3]

  (3975) 0x53bd6c LDR	D20, [X25, X2,LSL #3]

  (3975) 0x53bd70 LDR	D21, [X19, X30]

  (3975) 0x53bd74 FMADD	D22, D19, D20, D21

  (3975) 0x53bd78 STR	D22, [X19, X30]

  (3975) 0x53bd7c LDR	D31, [X28, X12,LSL #3]

  (3975) 0x53bd80 LDR	D30, [X25, X2,LSL #3]

  (3975) 0x53bd84 LDR	D29, [X19, X20]

  (3975) 0x53bd88 FMADD	D0, D31, D30, D29

  (3975) 0x53bd8c STR	D0, [X19, X20]

  (3975) 0x53bd90 CMP	X1, X11

  (3975) 0x53bd94 B.NE	53bd00

(3974) 0x53bd98 ADD	X2, X2, #1

(3974) 0x53bd9c CMP	X15, X2

(3974) 0x53bda0 B.NE	53bc60

0x53bda4 STR	X0, [SP, #104]

0x53bda8 BL	410880

0x53bdac SDIV	X27, X22, X21

0x53bdb0 LDR	X28, [SP, #104]

0x53bdb4 MSUB	X25, X27, X21, X22

0x53bdb8 CMP	X28, X25

0x53bdbc B.LT	53bf6c

0x53bdc0 MADD	X1, X27, X28, X25

0x53bdc4 ADD	X21, X27, X1

0x53bdc8 CMP	X1, X21

0x53bdcc B.GE	53bf50

0x53bdd0 CMP	X26, #0

0x53bdd4 B.LE	53bf50

0x53bdd8 ADD	X19, X19, X1,LSL #3

0x53bddc UBFM	X22, X22, #61, #60

(3973) 0x53bde0 ANDS	X0, X26, #4224

(3973) 0x53bde4 LDR	D2, [X23, X1,LSL #3]

(3973) 0x53bde8 ORR	X15, XZR, X19

(3973) 0x53bdec MOVZ	X14, #0

(3973) 0x53bdf0 B.EQ	53beb8

(3973) 0x53bdf4 CMP	X0, #1

(3973) 0x53bdf8 B.EQ	53be9c

(3973) 0x53bdfc CMP	X0, #2

(3973) 0x53be00 B.EQ	53be88

(3973) 0x53be04 CMP	X0, #3

(3973) 0x53be08 B.EQ	53be74

(3973) 0x53be0c CMP	X0, #4

(3973) 0x53be10 B.EQ	53be60

(3973) 0x53be14 CMP	X0, #5

(3973) 0x53be18 B.EQ	53be4c

(3973) 0x53be1c CMP	X0, #6

(3973) 0x53be20 B.EQ	53be38

(3973) 0x53be24 LDR	D28, [X19]

(3973) 0x53be28 MOVZ	X14, #1

(3973) 0x53be2c ADD	X15, X19, X22

(3973) 0x53be30 FADD	D2, D2, D28

(3973) 0x53be34 STR	D2, [X23, X1,LSL #3]

(3973) 0x53be38 LDR	D27, [X15]

(3973) 0x53be3c ADD	X14, X14, #1

(3973) 0x53be40 ADD	X15, X15, X22

(3973) 0x53be44 FADD	D2, D2, D27

(3973) 0x53be48 STR	D2, [X23, X1,LSL #3]

(3973) 0x53be4c LDR	D26, [X15]

(3973) 0x53be50 ADD	X14, X14, #1

(3973) 0x53be54 ADD	X15, X15, X22

(3973) 0x53be58 FADD	D2, D2, D26

(3973) 0x53be5c STR	D2, [X23, X1,LSL #3]

(3973) 0x53be60 LDR	D1, [X15]

(3973) 0x53be64 ADD	X14, X14, #1

(3973) 0x53be68 ADD	X15, X15, X22

(3973) 0x53be6c FADD	D2, D2, D1

(3973) 0x53be70 STR	D2, [X23, X1,LSL #3]

(3973) 0x53be74 LDR	D25, [X15]

(3973) 0x53be78 ADD	X14, X14, #1

(3973) 0x53be7c ADD	X15, X15, X22

(3973) 0x53be80 FADD	D2, D2, D25

(3973) 0x53be84 STR	D2, [X23, X1,LSL #3]

(3973) 0x53be88 LDR	D24, [X15]

(3973) 0x53be8c ADD	X14, X14, #1

(3973) 0x53be90 ADD	X15, X15, X22

(3973) 0x53be94 FADD	D2, D2, D24

(3973) 0x53be98 STR	D2, [X23, X1,LSL #3]

(3973) 0x53be9c LDR	D23, [X15]

(3973) 0x53bea0 ADD	X14, X14, #1

(3973) 0x53bea4 ADD	X15, X15, X22

(3973) 0x53bea8 FADD	D2, D2, D23

(3973) 0x53beac STR	D2, [X23, X1,LSL #3]

(3973) 0x53beb0 CMP	X26, X14

(3973) 0x53beb4 B.EQ	53bf40

  (3972) 0x53beb8 LDR	D5, [X15]

  (3972) 0x53bebc ADD	X16, X15, X22

  (3972) 0x53bec0 ADD	X13, X15, X22,LSL #1

  (3972) 0x53bec4 ADD	X14, X14, #8

  (3972) 0x53bec8 ADD	X11, X13, X22

  (3972) 0x53becc ADD	X24, X13, X22,LSL #1

  (3972) 0x53bed0 ADD	X12, X24, X22

  (3972) 0x53bed4 ADD	X8, X24, X22,LSL #1

  (3972) 0x53bed8 FADD	D4, D2, D5

  (3972) 0x53bedc STR	D4, [X23, X1,LSL #3]

  (3972) 0x53bee0 LDR	D3, [X15, X22]

  (3972) 0x53bee4 ADD	X15, X8, X22,LSL #1

  (3972) 0x53bee8 FADD	D6, D4, D3

  (3972) 0x53beec STR	D6, [X23, X1,LSL #3]

  (3972) 0x53bef0 LDR	D16, [X16, X22]

  (3972) 0x53bef4 FADD	D7, D6, D16

  (3972) 0x53bef8 STR	D7, [X23, X1,LSL #3]

  (3972) 0x53befc LDR	D17, [X13, X22]

  (3972) 0x53bf00 FADD	D18, D7, D17

  (3972) 0x53bf04 STR	D18, [X23, X1,LSL #3]

  (3972) 0x53bf08 LDR	D19, [X11, X22]

  (3972) 0x53bf0c FADD	D20, D18, D19

  (3972) 0x53bf10 STR	D20, [X23, X1,LSL #3]

  (3972) 0x53bf14 LDR	D21, [X24, X22]

  (3972) 0x53bf18 FADD	D22, D20, D21

  (3972) 0x53bf1c STR	D22, [X23, X1,LSL #3]

  (3972) 0x53bf20 LDR	D31, [X12, X22]

  (3972) 0x53bf24 FADD	D30, D22, D31

  (3972) 0x53bf28 STR	D30, [X23, X1,LSL #3]

  (3972) 0x53bf2c LDR	D29, [X8, X22]

  (3972) 0x53bf30 FADD	D2, D30, D29

  (3972) 0x53bf34 STR	D2, [X23, X1,LSL #3]

  (3972) 0x53bf38 CMP	X26, X14

  (3972) 0x53bf3c B.NE	53beb8

(3973) 0x53bf40 ADD	X1, X1, #1

(3973) 0x53bf44 ADD	X19, X19, #8

(3973) 0x53bf48 CMP	X21, X1

(3973) 0x53bf4c B.NE	53bde0

0x53bf50 LDP	X19, X20, [SP, #16]

0x53bf54 LDP	X21, X22, [SP, #32]

0x53bf58 LDP	X23, X24, [SP, #48]

0x53bf5c LDP	X25, X26, [SP, #64]

0x53bf60 LDP	X27, X28, [SP, #80]

0x53bf64 LDP	X29, X30, [SP], #112

0x53bf68 B	410880

0x53bf6c ADD	X27, X27, #1

0x53bf70 MOVZ	X25, #0

0x53bf74 B	53bdc0

0x53bf78 ADD	X12, X12, #1

0x53bf7c MOVZ	X2, #0

0x53bf80 B	53bc44

Coverage (%)	Name	Source Location	Module
►98.96+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.04+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	hypre_CSRMatrixMatvecT	csr_matvec.c:554	exec
○	hypre_ParCSRMatrixMatvecT	par_csr_matvec.c:439	exec
○	hypre_BoomerAMGCycle	par_cycle.c:434	exec
○	hypre_BoomerAMGSolve	par_amg_solve.c:235	exec
○	hypre_PCGSolve	pcg.c:545	exec
○	main	amg.c:419	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	csr_matvec.c:554-579
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:554-558,564-567,577-579.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 69% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 40.00 to 30.00 cycles (1.33x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 40.00 to 2.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 184 bytes. The binary function is storing 112 bytes.

General properties

nb instructions	59
loop length	236
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	6.00	6.00	4.67	4.50	4.67	4.67	7.00	4.50	0.00	0.00	0.00	0.00	7.00	7.00	7.00	4.00	4.00
cycles	6.00	6.00	4.67	4.50	4.67	4.67	7.00	4.50	0.00	0.00	0.00	0.00	7.00	7.00	7.00	4.00	4.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-40.00

Cycles summary

Front-end	7.25
Overall L1	10.00-40.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 40.00 cycles. At this rate:

4% of peak load performance is reached (4.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 53bbe4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X28, X7, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X26, [X0, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X7, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X27, X20, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X25, X23, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X22, X19, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
BL 5499c0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 410930 <@plt_start@+0x1b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X21, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
BL 410940 <@plt_start@+0x1c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SDIV X12, X20, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
SBFM X0, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X14, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MSUB X2, X12, X21, X20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
CMP X0, X2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 53bf78 <hypre_CSRMatrixMatvecT._omp_fn.3+0x394>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X2, X12, X0, X2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
ADD X15, X12, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X2, X15	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 53bda4 <hypre_CSRMatrixMatvecT._omp_fn.3+0x1c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X16, X22, X24, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
ADD X13, X14, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
HINT #0																					N/A
STR X0, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410880 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SDIV X27, X22, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
LDR X28, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MSUB X25, X27, X21, X22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
CMP X28, X25	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 53bf6c <hypre_CSRMatrixMatvecT._omp_fn.3+0x388>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X1, X27, X28, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
ADD X21, X27, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X1, X21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 53bf50 <hypre_CSRMatrixMatvecT._omp_fn.3+0x36c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X26, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 53bf50 <hypre_CSRMatrixMatvecT._omp_fn.3+0x36c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X19, X19, X1,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X22, X22, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #112	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
B 410880 <@plt_start@+0x100>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X27, X27, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ X25, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 53bdc0 <hypre_CSRMatrixMatvecT._omp_fn.3+0x1dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X12, X12, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ X2, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 53bc44 <hypre_CSRMatrixMatvecT._omp_fn.3+0x60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	csr_matvec.c:554-579
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:554-558,564-567,577-579.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 40.00 to 2.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 184 bytes. The binary function is storing 112 bytes.

General properties

nb instructions	59
loop length	236
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	6.00	6.00	4.67	4.50	4.67	4.67	7.00	4.50	0.00	0.00	0.00	0.00	7.00	7.00	7.00	4.00	4.00
cycles	6.00	6.00	4.67	4.50	4.67	4.67	7.00	4.50	0.00	0.00	0.00	0.00	7.00	7.00	7.00	4.00	4.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-40.00

Cycles summary

Front-end	7.25
Overall L1	10.00-40.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 40.00 cycles. At this rate:

4% of peak load performance is reached (4.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 53bbe4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X28, X7, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X26, [X0, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X7, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X27, X20, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X25, X23, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X22, X19, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
BL 5499c0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 410930 <@plt_start@+0x1b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X21, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
BL 410940 <@plt_start@+0x1c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SDIV X12, X20, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
SBFM X0, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X14, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MSUB X2, X12, X21, X20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
CMP X0, X2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 53bf78 <hypre_CSRMatrixMatvecT._omp_fn.3+0x394>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X2, X12, X0, X2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
ADD X15, X12, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X2, X15	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 53bda4 <hypre_CSRMatrixMatvecT._omp_fn.3+0x1c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X16, X22, X24, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
ADD X13, X14, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
HINT #0																					N/A
STR X0, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410880 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SDIV X27, X22, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
LDR X28, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MSUB X25, X27, X21, X22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
CMP X28, X25	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 53bf6c <hypre_CSRMatrixMatvecT._omp_fn.3+0x388>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X1, X27, X28, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
ADD X21, X27, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X1, X21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 53bf50 <hypre_CSRMatrixMatvecT._omp_fn.3+0x36c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X26, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 53bf50 <hypre_CSRMatrixMatvecT._omp_fn.3+0x36c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X19, X19, X1,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X22, X22, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #112	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
B 410880 <@plt_start@+0x100>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X27, X27, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ X25, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 53bdc0 <hypre_CSRMatrixMatvecT._omp_fn.3+0x1dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X12, X12, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ X2, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 53bc44 <hypre_CSRMatrixMatvecT._omp_fn.3+0x60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼hypre_CSRMatrixMatvecT._omp_fn.3–	1.29	0.21
▼Loop 3974 - csr_matvec.c:564-567 - exec–	0.85	0.11
○Loop 3975 - csr_matvec.c:564-567 - exec	0.17	0.02
▼Loop 3973 - csr_matvec.c:577-579 - exec–	0.00	0.01
○Loop 3972 - csr_matvec.c:577-579 - exec	0.28	0.03

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Vectorization

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Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

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Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code