OV - exec - Function hypre_CSRMatrixTranspose._omp

	Function: hypre_CSRMatrixTranspose._omp_fn.0	Module: exec	Source: csr_matop.c:380-560 [...]	Coverage (incl. loops): 0.16% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c: 380 - 560

--------------------------------------------------------------------------------

380:   return idx%dim1*dim2 + idx/dim1;

[...]

463: #pragma omp parallel

464: #endif

465:    {

466:    HYPRE_Int num_threads = hypre_NumActiveThreads();

467:    HYPRE_Int my_thread_num = hypre_GetThreadNum();

468:

469:    HYPRE_Int iBegin = hypre_CSRMatrixGetLoadBalancedPartitionBegin(A);

470:    HYPRE_Int iEnd = hypre_CSRMatrixGetLoadBalancedPartitionEnd(A);

471:    hypre_assert(iBegin <= iEnd);

472:    hypre_assert(iBegin >= 0 && iBegin <= num_rowsA);

473:    hypre_assert(iEnd >= 0 && iEnd <= num_rowsA);

474:

475:    HYPRE_Int i, j;

476:    memset(bucket + my_thread_num*num_colsA, 0, sizeof(HYPRE_Int)*num_colsA);

[...]

483:    for (j = A_i[iBegin]; j < A_i[iEnd]; ++j) {

484:      HYPRE_Int idx = A_j[j];

485:      bucket[my_thread_num*num_colsA + idx]++;

[...]

493: #pragma omp barrier

494: #endif

495:

496:    for (i = my_thread_num*num_colsA + 1; i < (my_thread_num + 1)*num_colsA; ++i) {

497:      HYPRE_Int transpose_i = transpose_idx(i, num_threads, num_colsA);

498:      HYPRE_Int transpose_i_minus_1 = transpose_idx(i - 1, num_threads, num_colsA);

499:

500:      bucket[transpose_i] += bucket[transpose_i_minus_1];

501:    }

502:

503: #ifdef HYPRE_USING_OPENMP

504: #pragma omp barrier

505: #pragma omp master

506: #endif

507:    {

508:      for (i = 1; i < num_threads; ++i) {

509:        HYPRE_Int j0 = num_colsA*i - 1, j1 = num_colsA*(i + 1) - 1;

510:        HYPRE_Int transpose_j0 = transpose_idx(j0, num_threads, num_colsA);

511:        HYPRE_Int transpose_j1 = transpose_idx(j1, num_threads, num_colsA);

512:

513:        bucket[transpose_j1] += bucket[transpose_j0];

514:      }

515:    }

516: #ifdef HYPRE_USING_OPENMP

517: #pragma omp barrier

518: #endif

519:

520:    if (my_thread_num > 0) {

521:      HYPRE_Int transpose_i0 = transpose_idx(num_colsA*my_thread_num - 1, num_threads, num_colsA);

522:      HYPRE_Int offset = bucket[transpose_i0];

523:

524:      for (i = my_thread_num*num_colsA; i < (my_thread_num + 1)*num_colsA - 1; ++i) {

525:        HYPRE_Int transpose_i = transpose_idx(i, num_threads, num_colsA);

526:

527:        bucket[transpose_i] += offset;

528:      }

529:    }

530:

531: #ifdef HYPRE_USING_OPENMP

532: #pragma omp barrier

[...]

539:    if (data) {

540:       for (i = iEnd - 1; i >= iBegin; --i) {

541:         for (j = A_i[i + 1] - 1; j >= A_i[i]; --j) {

542:           HYPRE_Int idx = A_j[j];

543:           --bucket[my_thread_num*num_colsA + idx];

544:

545:           HYPRE_Int offset = bucket[my_thread_num*num_colsA + idx];

546:

547:           AT_data[offset] = A_data[j];

548:           AT_j[offset] = i;

549:         }

550:       }

551:    }

552:    else {

553:       for (i = iEnd - 1; i >= iBegin; --i) {

554:         for (j = A_i[i + 1] - 1; j >= A_i[i]; --j) {

555:           HYPRE_Int idx = A_j[j];

556:           --bucket[my_thread_num*num_colsA + idx];

557:

558:           HYPRE_Int offset = bucket[my_thread_num*num_colsA + idx];

559:

560:           AT_j[offset] = i;

0x532028 STP	X29, X30, [SP, #896]!

0x53202c ADD	X29, SP, #0

0x532030 STP	X19, X20, [SP, #16]

0x532034 STP	X21, X22, [SP, #32]

0x532038 STP	X23, X24, [SP, #48]

0x53203c STP	X25, X26, [SP, #64]

0x532040 STP	X27, X28, [SP, #80]

0x532044 LDP	X19, X1, [X0]

0x532048 STR	X1, [SP, #120]

0x53204c LDP	X28, X22, [X0, #16]

0x532050 LDP	X23, X21, [X0, #32]

0x532054 LDP	X27, X26, [X0, #48]

0x532058 LDP	X24, X20, [X0, #64]

0x53205c BL	5499a0

0x532060 ORR	X25, XZR, X0

0x532064 BL	5499c0

0x532068 ORR	X2, XZR, X0

0x53206c ORR	X0, XZR, X19

0x532070 STR	X2, [SP, #104]

0x532074 BL	5378d0

0x532078 ORR	X3, XZR, X0

0x53207c ORR	X0, XZR, X19

0x532080 STR	X3, [SP, #96]

0x532084 BL	537980

0x532088 ORR	X19, XZR, X0

0x53208c LDR	X0, [SP, #96]

0x532090 CMP	X0, X19

0x532094 B.GT	532620

0x532098 LDR	X8, [SP, #96]

0x53209c CMP	X8, #0

0x5320a0 CCMP	X21, X8, #1, #10

0x5320a4 B.LT	532664

(3813) 0x5320a8 CMP	X19, #0

(3813) 0x5320ac CCMP	X21, X19, #1, #10

(3813) 0x5320b0 B.LT	5326a4

(3813) 0x5320b4 LDR	X16, [SP, #104]

(3813) 0x5320b8 UBFM	X2, X27, #61, #60

(3813) 0x5320bc MOVZ	W1, #0

(3813) 0x5320c0 MADD	X21, X27, X16, XZR

(3813) 0x5320c4 ADD	X0, X20, X21,LSL #3

(3813) 0x5320c8 BL	4108c0

(3813) 0x5320cc LDR	X1, [SP, #96]

(3813) 0x5320d0 ADD	X3, X22, X19,LSL #3

(3813) 0x5320d4 LDR	X0, [X22, X19,LSL #3]

(3813) 0x5320d8 LDR	X2, [X22, X1,LSL #3]

(3813) 0x5320dc CMP	X2, X0

(3813) 0x5320e0 B.GE	53210c

  (3822) 0x5320e4 LDR	X17, [X23, X2,LSL #3]

  (3822) 0x5320e8 ADD	X2, X2, #1

  (3822) 0x5320ec ADD	X30, X21, X17

  (3822) 0x5320f0 UBFM	X4, X30, #61, #60

  (3822) 0x5320f4 LDR	X5, [X20, X4]

  (3822) 0x5320f8 ADD	X6, X5, #1

  (3822) 0x5320fc STR	X6, [X20, X4]

  (3822) 0x532100 LDR	X7, [X3]

  (3822) 0x532104 CMP	X7, X2

  (3822) 0x532108 B.GT	5320e4

(3813) 0x53210c BL	410880

(3813) 0x532110 ADD	X8, X27, X21

(3813) 0x532114 ADD	X0, X21, #1

(3813) 0x532118 STR	X8, [SP, #112]

(3813) 0x53211c CMP	X27, #1

(3813) 0x532120 B.LE	5322a0

(3813) 0x532124 SUB	X9, X8, X0

(3813) 0x532128 ANDS	X10, X9, #4160

(3813) 0x53212c B.EQ	5321e4

(3813) 0x532130 CMP	X10, #1

(3813) 0x532134 B.EQ	5321a4

(3813) 0x532138 CMP	X10, #2

(3813) 0x53213c B.EQ	532170

(3813) 0x532140 SDIV	X11, X0, X25

(3813) 0x532144 SDIV	X12, X21, X25

(3813) 0x532148 MSUB	X13, X11, X25, X0

(3813) 0x53214c ADD	X0, X0, #1

(3813) 0x532150 MADD	X14, X13, X27, X11

(3813) 0x532154 MSUB	X15, X12, X25, X21

(3813) 0x532158 ADD	X18, X20, X14,LSL #3

(3813) 0x53215c MADD	X16, X15, X27, X12

(3813) 0x532160 LDR	X1, [X18]

(3813) 0x532164 LDR	X3, [X20, X16,LSL #3]

(3813) 0x532168 ADD	X17, X1, X3

(3813) 0x53216c STR	X17, [X18]

(3813) 0x532170 SDIV	X30, X0, X25

(3813) 0x532174 SUB	X2, X0, #1

(3813) 0x532178 SDIV	X4, X2, X25

(3813) 0x53217c MSUB	X5, X30, X25, X0

(3813) 0x532180 ADD	X0, X0, #1

(3813) 0x532184 MADD	X6, X5, X27, X30

(3813) 0x532188 MSUB	X7, X4, X25, X2

(3813) 0x53218c ADD	X8, X20, X6,LSL #3

(3813) 0x532190 MADD	X9, X7, X27, X4

(3813) 0x532194 LDR	X11, [X8]

(3813) 0x532198 LDR	X10, [X20, X9,LSL #3]

(3813) 0x53219c ADD	X12, X11, X10

(3813) 0x5321a0 STR	X12, [X8]

(3813) 0x5321a4 SDIV	X14, X0, X25

(3813) 0x5321a8 SUB	X13, X0, #1

(3813) 0x5321ac LDR	X5, [SP, #112]

(3813) 0x5321b0 SDIV	X15, X13, X25

(3813) 0x5321b4 MSUB	X18, X14, X25, X0

(3813) 0x5321b8 ADD	X0, X0, #1

(3813) 0x5321bc MADD	X16, X18, X27, X14

(3813) 0x5321c0 MSUB	X3, X15, X25, X13

(3813) 0x5321c4 ADD	X1, X20, X16,LSL #3

(3813) 0x5321c8 MADD	X17, X3, X27, X15

(3813) 0x5321cc LDR	X30, [X1]

(3813) 0x5321d0 LDR	X2, [X20, X17,LSL #3]

(3813) 0x5321d4 ADD	X4, X30, X2

(3813) 0x5321d8 STR	X4, [X1]

(3813) 0x5321dc CMP	X0, X5

(3813) 0x5321e0 B.EQ	5322a0

  (3821) 0x5321e4 SUB	X6, X0, #1

  (3821) 0x5321e8 SDIV	X7, X0, X25

  (3821) 0x5321ec ADD	X15, X0, #1

  (3821) 0x5321f0 ADD	X18, X0, #2

  (3821) 0x5321f4 ADD	X1, X0, #3

  (3821) 0x5321f8 ORR	X3, XZR, X18

  (3821) 0x5321fc SDIV	X8, X6, X25

  (3821) 0x532200 SDIV	X11, X15, X25

  (3821) 0x532204 MSUB	X9, X7, X25, X0

  (3821) 0x532208 ADD	X0, X0, #4

  (3821) 0x53220c SDIV	X12, X18, X25

  (3821) 0x532210 MSUB	X10, X8, X25, X6

  (3821) 0x532214 MADD	X16, X9, X27, X7

  (3821) 0x532218 MSUB	X30, X11, X25, X15

  (3821) 0x53221c MADD	X14, X10, X27, X8

  (3821) 0x532220 UBFM	X13, X16, #61, #60

  (3821) 0x532224 SDIV	X6, X1, X25

  (3821) 0x532228 LDR	X17, [X20, X13]

  (3821) 0x53222c LDR	X2, [X20, X14,LSL #3]

  (3821) 0x532230 MADD	X4, X30, X27, X11

  (3821) 0x532234 ORR	X11, XZR, X12

  (3821) 0x532238 MSUB	X18, X12, X25, X18

  (3821) 0x53223c UBFM	X7, X4, #61, #60

  (3821) 0x532240 ADD	X5, X17, X2

  (3821) 0x532244 MADD	X10, X18, X27, X12

  (3821) 0x532248 MSUB	X2, X11, X25, X3

  (3821) 0x53224c STR	X5, [X20, X13]

  (3821) 0x532250 LDR	X15, [X20, X16,LSL #3]

  (3821) 0x532254 UBFM	X14, X10, #61, #60

  (3821) 0x532258 MSUB	X16, X6, X25, X1

  (3821) 0x53225c MADD	X1, X2, X27, X11

  (3821) 0x532260 LDR	X8, [X20, X7]

  (3821) 0x532264 MADD	X12, X16, X27, X6

  (3821) 0x532268 UBFM	X30, X12, #61, #60

  (3821) 0x53226c ADD	X9, X8, X15

  (3821) 0x532270 STR	X9, [X20, X7]

  (3821) 0x532274 LDR	X13, [X20, X4,LSL #3]

  (3821) 0x532278 LDR	X17, [X20, X14]

  (3821) 0x53227c LDR	X7, [SP, #112]

  (3821) 0x532280 ADD	X3, X17, X13

  (3821) 0x532284 STR	X3, [X20, X14]

  (3821) 0x532288 LDR	X4, [X20, X30]

  (3821) 0x53228c LDR	X5, [X20, X1,LSL #3]

  (3821) 0x532290 ADD	X6, X4, X5

  (3821) 0x532294 STR	X6, [X20, X30]

  (3821) 0x532298 CMP	X0, X7

  (3821) 0x53229c B.NE	5321e4

(3813) 0x5322a0 BL	410880

(3813) 0x5322a4 BL	410940

(3813) 0x5322a8 CBNZ	W0, 5323e0

(3813) 0x5322ac CMP	X25, #1

(3813) 0x5322b0 B.LE	5323e0

(3813) 0x5322b4 SUB	X15, X27, #1

(3813) 0x5322b8 MOVZ	X0, #1

(3813) 0x5322bc SDIV	X18, X15, X25

(3813) 0x5322c0 MSUB	X8, X18, X25, X15

(3813) 0x5322c4 MADD	X11, X8, X27, X18

(3813) 0x5322c8 LDR	X2, [X20, X11,LSL #3]

(3813) 0x5322cc CMP	X27, X0

(3813) 0x5322d0 B.NE	5327f4

(3813) 0x5322d4 SUB	X9, X25, X27

(3813) 0x5322d8 ANDS	X5, X9, #4160

(3813) 0x5322dc B.EQ	532358

(3813) 0x5322e0 CMP	X5, X0

(3813) 0x5322e4 B.EQ	532330

(3813) 0x5322e8 CMP	X5, #2

(3813) 0x5322ec B.EQ	532310

(3813) 0x5322f0 SDIV	X6, X27, X25

(3813) 0x5322f4 MOVZ	X0, #2

(3813) 0x5322f8 MSUB	X3, X6, X25, X27

(3813) 0x5322fc ADD	X7, X6, X3

(3813) 0x532300 ADD	X15, X20, X7,LSL #3

(3813) 0x532304 LDR	X18, [X15]

(3813) 0x532308 ADD	X2, X2, X18

(3813) 0x53230c STR	X2, [X15]

(3813) 0x532310 SDIV	X8, X0, X25

(3813) 0x532314 MSUB	X11, X8, X25, X0

(3813) 0x532318 ADD	X0, X0, #1

(3813) 0x53231c ADD	X10, X8, X11

(3813) 0x532320 ADD	X16, X20, X10,LSL #3

(3813) 0x532324 LDR	X14, [X16]

(3813) 0x532328 ADD	X2, X2, X14

(3813) 0x53232c STR	X2, [X16]

(3813) 0x532330 SDIV	X17, X0, X25

(3813) 0x532334 MSUB	X30, X17, X25, X0

(3813) 0x532338 ADD	X0, X0, #1

(3813) 0x53233c ADD	X12, X17, X30

(3813) 0x532340 ADD	X13, X20, X12,LSL #3

(3813) 0x532344 LDR	X1, [X13]

(3813) 0x532348 ADD	X2, X2, X1

(3813) 0x53234c STR	X2, [X13]

(3813) 0x532350 CMP	X25, X0

(3813) 0x532354 B.EQ	5323e0

  (3820) 0x532358 SDIV	X4, X0, X25

  (3820) 0x53235c ADD	X5, X0, #1

  (3820) 0x532360 ADD	X7, X0, #2

  (3820) 0x532364 ADD	X6, X0, #3

  (3820) 0x532368 SDIV	X15, X5, X25

  (3820) 0x53236c SDIV	X10, X7, X25

  (3820) 0x532370 MSUB	X9, X4, X25, X0

  (3820) 0x532374 ADD	X0, X0, #4

  (3820) 0x532378 MSUB	X8, X15, X25, X5

  (3820) 0x53237c ADD	X3, X4, X9

  (3820) 0x532380 UBFM	X18, X3, #61, #60

  (3820) 0x532384 LDR	X11, [X20, X18]

  (3820) 0x532388 ADD	X16, X15, X8

  (3820) 0x53238c UBFM	X14, X16, #61, #60

  (3820) 0x532390 MSUB	X12, X10, X25, X7

  (3820) 0x532394 ADD	X1, X10, X12

  (3820) 0x532398 ADD	X17, X2, X11

  (3820) 0x53239c SDIV	X2, X6, X25

  (3820) 0x5323a0 UBFM	X4, X1, #61, #60

  (3820) 0x5323a4 STR	X17, [X20, X18]

  (3820) 0x5323a8 LDR	X30, [X20, X14]

  (3820) 0x5323ac ADD	X13, X17, X30

  (3820) 0x5323b0 MSUB	X5, X2, X25, X6

  (3820) 0x5323b4 STR	X13, [X20, X14]

  (3820) 0x5323b8 LDR	X6, [X20, X4]

  (3820) 0x5323bc ADD	X7, X2, X5

  (3820) 0x5323c0 UBFM	X15, X7, #61, #60

  (3820) 0x5323c4 ADD	X9, X13, X6

  (3820) 0x5323c8 STR	X9, [X20, X4]

  (3820) 0x5323cc LDR	X3, [X20, X15]

  (3820) 0x5323d0 ADD	X2, X9, X3

  (3820) 0x5323d4 STR	X2, [X20, X15]

  (3820) 0x5323d8 CMP	X25, X0

  (3820) 0x5323dc B.NE	532358

(3813) 0x5323e0 BL	410880

(3813) 0x5323e4 LDR	X0, [SP, #104]

(3813) 0x5323e8 CMP	X0, #0

(3813) 0x5323ec B.LE	53250c

(3813) 0x5323f0 SUB	X18, X21, #1

(3813) 0x5323f4 LDR	X8, [SP, #112]

(3813) 0x5323f8 SDIV	X11, X18, X25

(3813) 0x5323fc SUB	X16, X8, #1

(3813) 0x532400 MSUB	X10, X11, X25, X18

(3813) 0x532404 MADD	X14, X10, X27, X11

(3813) 0x532408 LDR	X17, [X20, X14,LSL #3]

(3813) 0x53240c CMP	X21, X16

(3813) 0x532410 B.GE	53250c

(3813) 0x532414 ORR	X18, XZR, X21

(3813) 0x532418 CMP	X27, #1

(3813) 0x53241c B.NE	5326dc

(3813) 0x532420 SUB	X27, X16, X21

(3813) 0x532424 ANDS	X1, X27, #4160

(3813) 0x532428 B.EQ	532484

(3813) 0x53242c CMP	X1, #1

(3813) 0x532430 B.EQ	53245c

(3813) 0x532434 CMP	X1, #2

(3813) 0x532438 B.NE	5327d0

(3813) 0x53243c SDIV	X12, X18, X25

(3813) 0x532440 MSUB	X13, X12, X25, X18

(3813) 0x532444 ADD	X18, X18, #1

(3813) 0x532448 ADD	X4, X12, X13

(3813) 0x53244c ADD	X5, X20, X4,LSL #3

(3813) 0x532450 LDR	X6, [X5]

(3813) 0x532454 ADD	X7, X6, X17

(3813) 0x532458 STR	X7, [X5]

(3813) 0x53245c SDIV	X15, X18, X25

(3813) 0x532460 MSUB	X9, X15, X25, X18

(3813) 0x532464 ADD	X18, X18, #1

(3813) 0x532468 ADD	X3, X15, X9

(3813) 0x53246c ADD	X0, X20, X3,LSL #3

(3813) 0x532470 LDR	X27, [X0]

(3813) 0x532474 ADD	X1, X27, X17

(3813) 0x532478 STR	X1, [X0]

(3813) 0x53247c CMP	X16, X18

(3813) 0x532480 B.EQ	53250c

  (3818) 0x532484 SDIV	X8, X18, X25

  (3818) 0x532488 ADD	X14, X18, #1

  (3818) 0x53248c ADD	X11, X18, #2

  (3818) 0x532490 ADD	X10, X18, #3

  (3818) 0x532494 SDIV	X30, X14, X25

  (3818) 0x532498 SDIV	X2, X11, X25

  (3818) 0x53249c MSUB	X12, X8, X25, X18

  (3818) 0x5324a0 ADD	X18, X18, #4

  (3818) 0x5324a4 SDIV	X15, X10, X25

  (3818) 0x5324a8 ADD	X4, X8, X12

  (3818) 0x5324ac UBFM	X5, X4, #61, #60

  (3818) 0x5324b0 LDR	X6, [X20, X5]

  (3818) 0x5324b4 MSUB	X13, X30, X25, X14

  (3818) 0x5324b8 MSUB	X0, X2, X25, X11

  (3818) 0x5324bc ADD	X7, X30, X13

  (3818) 0x5324c0 UBFM	X3, X7, #61, #60

  (3818) 0x5324c4 ADD	X27, X2, X0

  (3818) 0x5324c8 ADD	X9, X6, X17

  (3818) 0x5324cc UBFM	X8, X27, #61, #60

  (3818) 0x5324d0 MSUB	X14, X15, X25, X10

  (3818) 0x5324d4 STR	X9, [X20, X5]

  (3818) 0x5324d8 LDR	X1, [X20, X3]

  (3818) 0x5324dc ADD	X11, X15, X14

  (3818) 0x5324e0 UBFM	X30, X11, #61, #60

  (3818) 0x5324e4 ADD	X10, X1, X17

  (3818) 0x5324e8 STR	X10, [X20, X3]

  (3818) 0x5324ec LDR	X2, [X20, X8]

  (3818) 0x5324f0 ADD	X12, X2, X17

  (3818) 0x5324f4 STR	X12, [X20, X8]

  (3818) 0x5324f8 LDR	X13, [X20, X30]

  (3818) 0x5324fc ADD	X4, X13, X17

  (3818) 0x532500 STR	X4, [X20, X30]

  (3818) 0x532504 CMP	X16, X18

  (3818) 0x532508 B.NE	532484

(3813) 0x53250c BL	410880

(3813) 0x532510 LDR	X25, [SP, #120]

(3813) 0x532514 SUB	X3, X19, #1

(3813) 0x532518 CBNZ	X25, 532598

(3813) 0x53251c LDR	X28, [SP, #96]

(3813) 0x532520 CMP	X28, X3

(3813) 0x532524 B.GT	53257c

(3813) 0x532528 SUB	X26, X28, #1

(3813) 0x53252c ADD	X19, X22, #8

  (3815) 0x532530 LDR	X16, [X19, X3,LSL #3]

  (3815) 0x532534 LDR	X17, [X22, X3,LSL #3]

  (3815) 0x532538 SUB	X5, X16, #1

  (3815) 0x53253c CMP	X5, X17

  (3815) 0x532540 B.LT	532570

    (3816) 0x532544 LDR	X18, [X23, X5,LSL #3]

    (3816) 0x532548 SUB	X5, X5, #1

    (3816) 0x53254c ADD	X6, X21, X18

    (3816) 0x532550 UBFM	X7, X6, #61, #60

    (3816) 0x532554 LDR	X15, [X20, X7]

    (3816) 0x532558 SUB	X0, X15, #1

    (3816) 0x53255c STR	X0, [X20, X7]

    (3816) 0x532560 STR	X3, [X24, X0,LSL #3]

    (3816) 0x532564 LDR	X9, [X22, X3,LSL #3]

    (3816) 0x532568 CMP	X9, X5

    (3816) 0x53256c B.LE	532544

  (3815) 0x532570 SUB	X3, X3, #1

  (3815) 0x532574 CMP	X3, X26

  (3815) 0x532578 B.NE	532530

  (3811) 0x53257c LDP	X19, X20, [SP, #16]

  (3811) 0x532580 LDP	X21, X22, [SP, #32]

  (3811) 0x532584 LDP	X23, X24, [SP, #48]

  (3811) 0x532588 LDP	X25, X26, [SP, #64]

  (3811) 0x53258c LDP	X27, X28, [SP, #80]

  (3811) 0x532590 LDP	X29, X30, [SP], #128

  (3811) 0x532594 RET

  (3811) 0x532598 LDR	X27, [SP, #96]

  (3811) 0x53259c CMP	X27, X3

  (3811) 0x5325a0 B.GT	53257c

(3813) 0x5325a4 SUB	X14, X27, #1

(3813) 0x5325a8 ADD	X8, X22, #8

  (3812) 0x5325ac LDR	X1, [X8, X3,LSL #3]

  (3812) 0x5325b0 LDR	X10, [X22, X3,LSL #3]

  (3812) 0x5325b4 SUB	X30, X1, #1

  (3812) 0x5325b8 CMP	X30, X10

  (3812) 0x5325bc B.LT	5325f8

    (3814) 0x5325c0 LDR	X11, [X23, X30,LSL #3]

    (3814) 0x5325c4 LDR	D31, [X28, X30,LSL #3]

    (3814) 0x5325c8 SUB	X30, X30, #1

    (3814) 0x5325cc ADD	X2, X21, X11

    (3814) 0x5325d0 UBFM	X12, X2, #61, #60

    (3814) 0x5325d4 LDR	X13, [X20, X12]

    (3814) 0x5325d8 SUB	X4, X13, #1

    (3814) 0x5325dc UBFM	X25, X4, #61, #60

    (3814) 0x5325e0 STR	X4, [X20, X12]

    (3814) 0x5325e4 STR	D31, [X26, X25]

    (3814) 0x5325e8 STR	X3, [X24, X25]

    (3814) 0x5325ec LDR	X19, [X22, X3,LSL #3]

    (3814) 0x5325f0 CMP	X19, X30

    (3814) 0x5325f4 B.LE	5325c0

  (3812) 0x5325f8 SUB	X3, X3, #1

  (3812) 0x5325fc CMP	X3, X14

  (3812) 0x532600 B.NE	5325ac

(3813) 0x532604 LDP	X19, X20, [SP, #16]

(3813) 0x532608 LDP	X21, X22, [SP, #32]

(3813) 0x53260c LDP	X23, X24, [SP, #48]

(3813) 0x532610 LDP	X25, X26, [SP, #64]

(3813) 0x532614 LDP	X27, X28, [SP, #80]

(3813) 0x532618 LDP	X29, X30, [SP], #128

(3813) 0x53261c RET

(3813) 0x532620 ADRP	X4,

(3813) 0x532624 ADRP	X5,

(3813) 0x532628 ADRP	X6,

(3813) 0x53262c ADD	X2, X4, #1040

(3813) 0x532630 ADD	X1, X5, #2384

(3813) 0x532634 LDR	X0, [X6, #1784]

(3813) 0x532638 BL	547050

(3813) 0x53263c ADRP	X7,

(3813) 0x532640 MOVZ	X3, #0

(3813) 0x532644 ADD	X0, X7, #912

(3813) 0x532648 MOVZ	X2, #1

(3813) 0x53264c MOVZ	X1, #471

(3813) 0x532650 BL	54a840

(3813) 0x532654 LDR	X8, [SP, #96]

(3813) 0x532658 CMP	X8, #0

(3813) 0x53265c CCMP	X21, X8, #1, #10

(3813) 0x532660 B.GE	5320a8

(3813) 0x532664 ADRP	X9,

(3813) 0x532668 ADRP	X10,

(3813) 0x53266c ADRP	X11,

(3813) 0x532670 ADD	X2, X9, #1000

(3813) 0x532674 ADD	X1, X10, #2384

(3813) 0x532678 LDR	X0, [X11, #1784]

(3813) 0x53267c BL	547050

(3813) 0x532680 ADRP	X12,

(3813) 0x532684 MOVZ	X3, #0

(3813) 0x532688 ADD	X0, X12, #912

(3813) 0x53268c MOVZ	X2, #1

(3813) 0x532690 MOVZ	X1, #472

(3813) 0x532694 BL	54a840

(3813) 0x532698 CMP	X19, #0

(3813) 0x53269c CCMP	X21, X19, #1, #10

(3813) 0x5326a0 B.GE	5320b4

(3813) 0x5326a4 ADRP	X13,

(3813) 0x5326a8 ADRP	X14,

(3813) 0x5326ac ADRP	X15,

(3813) 0x5326b0 ADD	X2, X13, #880

(3813) 0x5326b4 ADD	X1, X14, #2384

(3813) 0x5326b8 LDR	X0, [X15, #1784]

(3813) 0x5326bc BL	547050

(3813) 0x5326c0 ADRP	X18,

(3813) 0x5326c4 MOVZ	X3, #0

(3813) 0x5326c8 ADD	X0, X18, #912

(3813) 0x5326cc MOVZ	X2, #1

(3813) 0x5326d0 MOVZ	X1, #473

(3813) 0x5326d4 BL	54a840

(3813) 0x5326d8 B	5320b4

(3813) 0x5326dc SUB	X2, X16, X21

(3813) 0x5326e0 ORR	X1, XZR, X21

(3813) 0x5326e4 ANDS	X30, X2, #4160

(3813) 0x5326e8 B.EQ	532744

(3813) 0x5326ec CMP	X30, #1

(3813) 0x5326f0 B.EQ	53271c

(3813) 0x5326f4 CMP	X30, #2

(3813) 0x5326f8 B.NE	53291c

(3813) 0x5326fc SDIV	X15, X1, X25

(3813) 0x532700 MSUB	X9, X15, X25, X1

(3813) 0x532704 ADD	X1, X1, #1

(3813) 0x532708 MADD	X3, X9, X27, X15

(3813) 0x53270c ADD	X0, X20, X3,LSL #3

(3813) 0x532710 LDR	X18, [X0]

(3813) 0x532714 ADD	X8, X18, X17

(3813) 0x532718 STR	X8, [X0]

(3813) 0x53271c SDIV	X11, X1, X25

(3813) 0x532720 MSUB	X10, X11, X25, X1

(3813) 0x532724 ADD	X1, X1, #1

(3813) 0x532728 MADD	X14, X10, X27, X11

(3813) 0x53272c ADD	X30, X20, X14,LSL #3

(3813) 0x532730 LDR	X2, [X30]

(3813) 0x532734 ADD	X12, X2, X17

(3813) 0x532738 STR	X12, [X30]

(3813) 0x53273c CMP	X1, X16

(3813) 0x532740 B.EQ	53250c

  (3817) 0x532744 SDIV	X13, X1, X25

  (3817) 0x532748 ADD	X4, X1, #1

  (3817) 0x53274c ADD	X6, X1, #2

  (3817) 0x532750 ADD	X5, X1, #3

  (3817) 0x532754 SDIV	X7, X4, X25

  (3817) 0x532758 SDIV	X15, X6, X25

  (3817) 0x53275c MSUB	X9, X13, X25, X1

  (3817) 0x532760 ADD	X1, X1, #4

  (3817) 0x532764 SDIV	X11, X5, X25

  (3817) 0x532768 MADD	X18, X9, X27, X13

  (3817) 0x53276c MSUB	X3, X7, X25, X4

  (3817) 0x532770 MSUB	X14, X15, X25, X6

  (3817) 0x532774 UBFM	X8, X18, #61, #60

  (3817) 0x532778 LDR	X10, [X20, X8]

  (3817) 0x53277c MADD	X0, X3, X27, X7

  (3817) 0x532780 MADD	X2, X14, X27, X15

  (3817) 0x532784 MSUB	X5, X11, X25, X5

  (3817) 0x532788 UBFM	X30, X0, #61, #60

  (3817) 0x53278c UBFM	X13, X2, #61, #60

  (3817) 0x532790 ADD	X12, X10, X17

  (3817) 0x532794 MADD	X7, X5, X27, X11

  (3817) 0x532798 STR	X12, [X20, X8]

  (3817) 0x53279c LDR	X4, [X20, X30]

  (3817) 0x5327a0 UBFM	X9, X7, #61, #60

  (3817) 0x5327a4 ADD	X6, X4, X17

  (3817) 0x5327a8 STR	X6, [X20, X30]

  (3817) 0x5327ac LDR	X15, [X20, X13]

  (3817) 0x5327b0 ADD	X3, X15, X17

  (3817) 0x5327b4 STR	X3, [X20, X13]

  (3817) 0x5327b8 LDR	X18, [X20, X9]

  (3817) 0x5327bc ADD	X0, X18, X17

  (3817) 0x5327c0 STR	X0, [X20, X9]

  (3817) 0x5327c4 CMP	X1, X16

  (3817) 0x5327c8 B.NE	532744

(3813) 0x5327cc B	53250c

(3813) 0x5327d0 SDIV	X8, X21, X25

(3813) 0x5327d4 ADD	X18, X21, #1

(3813) 0x5327d8 MSUB	X14, X8, X25, X21

(3813) 0x5327dc ADD	X10, X8, X14

(3813) 0x5327e0 ADD	X11, X20, X10,LSL #3

(3813) 0x5327e4 LDR	X30, [X11]

(3813) 0x5327e8 ADD	X2, X30, X17

(3813) 0x5327ec STR	X2, [X11]

(3813) 0x5327f0 B	53243c

(3813) 0x5327f4 SUB	X16, X25, X0

(3813) 0x5327f8 UBFM	X10, X27, #63, #62

(3813) 0x5327fc ANDS	X14, X16, #4160

(3813) 0x532800 SUB	X9, X10, #1

(3813) 0x532804 B.EQ	53288c

(3813) 0x532808 CMP	X14, #1

(3813) 0x53280c B.EQ	532860

(3813) 0x532810 CMP	X14, #2

(3813) 0x532814 B.EQ	53283c

(3813) 0x532818 SDIV	X13, X9, X25

(3813) 0x53281c MOVZ	X0, #2

(3813) 0x532820 MSUB	X12, X13, X25, X9

(3813) 0x532824 ADD	X9, X9, X27

(3813) 0x532828 MADD	X17, X12, X27, X13

(3813) 0x53282c ADD	X30, X20, X17,LSL #3

(3813) 0x532830 LDR	X1, [X30]

(3813) 0x532834 ADD	X2, X2, X1

(3813) 0x532838 STR	X2, [X30]

(3813) 0x53283c SDIV	X3, X9, X25

(3813) 0x532840 ADD	X0, X0, #1

(3813) 0x532844 MSUB	X4, X3, X25, X9

(3813) 0x532848 ADD	X9, X9, X27

(3813) 0x53284c MADD	X5, X4, X27, X3

(3813) 0x532850 ADD	X6, X20, X5,LSL #3

(3813) 0x532854 LDR	X7, [X6]

(3813) 0x532858 ADD	X2, X2, X7

(3813) 0x53285c STR	X2, [X6]

(3813) 0x532860 SDIV	X15, X9, X25

(3813) 0x532864 ADD	X0, X0, #1

(3813) 0x532868 MSUB	X18, X15, X25, X9

(3813) 0x53286c ADD	X9, X9, X27

(3813) 0x532870 MADD	X8, X18, X27, X15

(3813) 0x532874 ADD	X11, X20, X8,LSL #3

(3813) 0x532878 LDR	X10, [X11]

(3813) 0x53287c ADD	X2, X2, X10

(3813) 0x532880 STR	X2, [X11]

(3813) 0x532884 CMP	X25, X0

(3813) 0x532888 B.EQ	5323e0

  (3819) 0x53288c SDIV	X16, X9, X25

  (3819) 0x532890 ADD	X14, X9, X27

  (3819) 0x532894 ADD	X0, X0, #4

  (3819) 0x532898 ADD	X17, X14, X27

  (3819) 0x53289c ADD	X30, X17, X27

  (3819) 0x5328a0 SDIV	X12, X14, X25

  (3819) 0x5328a4 SDIV	X5, X17, X25

  (3819) 0x5328a8 MSUB	X13, X16, X25, X9

  (3819) 0x5328ac ADD	X9, X30, X27

  (3819) 0x5328b0 SDIV	X15, X30, X25

  (3819) 0x5328b4 MADD	X1, X13, X27, X16

  (3819) 0x5328b8 MSUB	X4, X12, X25, X14

  (3819) 0x5328bc MSUB	X10, X5, X25, X17

  (3819) 0x5328c0 UBFM	X6, X1, #61, #60

  (3819) 0x5328c4 LDR	X3, [X20, X6]

  (3819) 0x5328c8 MADD	X7, X4, X27, X12

  (3819) 0x5328cc MSUB	X14, X15, X25, X30

  (3819) 0x5328d0 UBFM	X8, X7, #61, #60

  (3819) 0x5328d4 ADD	X18, X2, X3

  (3819) 0x5328d8 MADD	X2, X10, X27, X5

  (3819) 0x5328dc MADD	X12, X14, X27, X15

  (3819) 0x5328e0 STR	X18, [X20, X6]

  (3819) 0x5328e4 LDR	X11, [X20, X8]

  (3819) 0x5328e8 UBFM	X17, X2, #61, #60

  (3819) 0x5328ec UBFM	X13, X12, #61, #60

  (3819) 0x5328f0 ADD	X16, X18, X11

  (3819) 0x5328f4 STR	X16, [X20, X8]

  (3819) 0x5328f8 LDR	X30, [X20, X17]

  (3819) 0x5328fc ADD	X1, X16, X30

  (3819) 0x532900 STR	X1, [X20, X17]

  (3819) 0x532904 LDR	X4, [X20, X13]

  (3819) 0x532908 ADD	X2, X1, X4

  (3819) 0x53290c STR	X2, [X20, X13]

  (3819) 0x532910 CMP	X25, X0

  (3819) 0x532914 B.NE	53288c

(3813) 0x532918 B	5323e0

(3813) 0x53291c SDIV	X12, X21, X25

(3813) 0x532920 ADD	X1, X21, #1

(3813) 0x532924 MSUB	X13, X12, X25, X21

(3813) 0x532928 MADD	X4, X13, X27, X12

(3813) 0x53292c ADD	X5, X20, X4,LSL #3

(3813) 0x532930 LDR	X6, [X5]

(3813) 0x532934 ADD	X7, X6, X17

(3813) 0x532938 STR	X7, [X5]

(3813) 0x53293c B	5326fc

Coverage (%)	Name	Source Location	Module
►99.47+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	csr_matop.c:380-560
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:380,463-476,483-485,493-532,539-560.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 75% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 5.50 to 5.00 cycles (1.10x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.50 to 2.00 cycles (2.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 96 bytes. The binary function is storing 120 bytes.

General properties

nb instructions	32
loop length	128
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.00	3.00	2.50	2.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	5.50	5.17	5.33	4.50	4.50
cycles	3.00	3.00	2.50	2.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	5.50	5.17	5.33	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.00
Overall L1	5.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.50 cycles. At this rate:

18% of peak load performance is reached (17.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
45% of peak store performance is reached (21.82 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 532028

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #896]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X19, X1, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X1, [SP, #120]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X28, X22, [X0, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X23, X21, [X0, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X27, X26, [X0, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X24, X20, [X0, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
BL 5499a0 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X25, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
BL 5499c0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X2, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR X2, [SP, #104]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 5378d0 <hypre_CSRMatrixGetLoadBalancedPartitionBegin>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X3, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR X3, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 537980 <hypre_CSRMatrixGetLoadBalancedPartitionEnd>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [SP, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 532620 <hypre_CSRMatrixTranspose._omp_fn.0+0x5f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X21, X8, #1, #10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	1	N/A
B.LT 532664 <hypre_CSRMatrixTranspose._omp_fn.0+0x63c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	csr_matop.c:380-560
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:380,463-476,483-485,493-532,539-560.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.50 to 2.00 cycles (2.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 96 bytes. The binary function is storing 120 bytes.

General properties

nb instructions	32
loop length	128
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.00	3.00	2.50	2.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	5.50	5.17	5.33	4.50	4.50
cycles	3.00	3.00	2.50	2.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	5.50	5.17	5.33	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.00
Overall L1	5.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.50 cycles. At this rate:

18% of peak load performance is reached (17.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
45% of peak store performance is reached (21.82 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 532028

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #896]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X19, X1, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X1, [SP, #120]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X28, X22, [X0, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X23, X21, [X0, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X27, X26, [X0, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X24, X20, [X0, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
BL 5499a0 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X25, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
BL 5499c0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X2, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR X2, [SP, #104]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 5378d0 <hypre_CSRMatrixGetLoadBalancedPartitionBegin>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X3, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR X3, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 537980 <hypre_CSRMatrixGetLoadBalancedPartitionEnd>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [SP, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 532620 <hypre_CSRMatrixTranspose._omp_fn.0+0x5f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X21, X8, #1, #10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	1	N/A
B.LT 532664 <hypre_CSRMatrixTranspose._omp_fn.0+0x63c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼hypre_CSRMatrixTranspose._omp_fn.0–	0.16	0.03
▼Loop 3813 - csr_matop.c:380-560 - exec–	0.00	0.00
○Loop 3821 - csr_matop.c:380-500 - exec	0.03	0.01
○Loop 3817 - csr_matop.c:380-527 - exec	0.03	0.01
○Loop 3822 - csr_matop.c:483-485 - exec	0.01	0.01
▼Loop 3812 - csr_matop.c:540-548 - exec–	0.00	0.01
○Loop 3814 - csr_matop.c:541-548 - exec	0.08	0.01
○Loop 3811 - csr_matop.c:463-540 - exec	0.00	0.00
○Loop 3820 - csr_matop.c:380-513 - exec	0.00	0.00
○Loop 3818 - csr_matop.c:380-527 - exec	0.00	0.00
○Loop 3819 - csr_matop.c:380-513 - exec	0.00	0.00
▼Loop 3815 - csr_matop.c:553-560 - exec–	0.00	0.00
○Loop 3816 - csr_matop.c:554-560 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code