OV - exec - Function hypre_ParMatmul_RowSizes._omp

	Function: hypre_ParMatmul_RowSizes._omp_fn.0	Module: exec	Source: par_csr_matop.c:102-276 [...]	Coverage (incl. loops): 1.06% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 102 - 276

--------------------------------------------------------------------------------

102: #pragma omp parallel private(ii, i1, jj_row_begin_diag, jj_row_begin_offd, jj_count_diag, jj_count_offd, jj2, i2, jj3, i3)

103: #endif

104:    /*for (ii=0; ii < num_threads; ii++)*/

105:    {

106:     HYPRE_Int *B_marker = NULL;

107:     HYPRE_Int ns, ne;

108:     ii = hypre_GetThreadNum();

109:     if (ii < rest)

110:     {

111:        ns = ii*size+ii;

112:        ne = (ii+1)*size+ii+1;

113:     }

114:     else

115:     {

116:        ns = ii*size+rest;

117:        ne = (ii+1)*size+rest;

118:     }

119:     jj_count_diag = start_indexing;

120:     jj_count_offd = start_indexing;

121:

122:     if (num_cols_diag_B || num_cols_offd_C)

123:     B_marker = hypre_CTAlloc(HYPRE_Int, num_cols_diag_B+num_cols_offd_C);

124:     for (i1 = 0; i1 < num_cols_diag_B+num_cols_offd_C; i1++)

125:       B_marker[i1] = -1;

126:

127:     for (i1 = ns; i1 < ne; i1++)

[...]

135:       if ( allsquare ) {

136:          B_marker[i1] = jj_count_diag;

137:          jj_count_diag++;

[...]

144:       if (num_cols_offd_A)

145:       {

146:          for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++)

[...]

154:             for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++)

155:             {

156:                i3 = num_cols_diag_B+B_ext_offd_j[jj3];

[...]

164:                if (B_marker[i3] < jj_row_begin_offd)

165:                {

166:                   B_marker[i3] = jj_count_offd;

167:                   jj_count_offd++;

168:                }

169:             }

170:             for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++)

171:             {

172:                i3 = B_ext_diag_j[jj3];

173:

174:                if (B_marker[i3] < jj_row_begin_diag)

175:                {

176:                   B_marker[i3] = jj_count_diag;

177:                   jj_count_diag++;

[...]

187:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

[...]

195:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

[...]

205:             if (B_marker[i3] < jj_row_begin_diag)

206:             {

207:                B_marker[i3] = jj_count_diag;

208:                jj_count_diag++;

[...]

216:          if (num_cols_offd_B)

217:          {

218:             for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++)

219:             {

220:                i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]];

[...]

228:                if (B_marker[i3] < jj_row_begin_offd)

229:                {

230:                   B_marker[i3] = jj_count_offd;

231:                   jj_count_offd++;

[...]

241:       (*C_diag_i)[i1] = jj_row_begin_diag;

242:       (*C_offd_i)[i1] = jj_row_begin_offd;

243:

244:     }

245:     jj_count_diag_array[ii] = jj_count_diag;

246:     jj_count_offd_array[ii] = jj_count_offd;

247:

248:     hypre_TFree(B_marker);

249: #ifdef HYPRE_USING_OPENMP

250: #pragma omp barrier

251: #endif

252:

253:     if (ii)

254:     {

255:        jj_count_diag = jj_count_diag_array[0];

256:        jj_count_offd = jj_count_offd_array[0];

257:        for (i1 = 1; i1 < ii; i1++)

258:        {

259:           jj_count_diag += jj_count_diag_array[i1];

260:           jj_count_offd += jj_count_offd_array[i1];

261:        }

262:

263:        for (i1 = ns; i1 < ne; i1++)

264:        {

265:           (*C_diag_i)[i1] += jj_count_diag;

266:           (*C_offd_i)[i1] += jj_count_offd;

267:        }

268:     }

269:     else

270:     {

271:        (*C_diag_i)[num_rows_diag_A] = 0;

272:        (*C_offd_i)[num_rows_diag_A] = 0;

273:        for (i1 = 0; i1 < num_threads; i1++)

274:        {

275:           (*C_diag_i)[num_rows_diag_A] += jj_count_diag_array[i1];

276:           (*C_offd_i)[num_rows_diag_A] += jj_count_offd_array[i1];

0x4ff1c0 STP	X29, X30, [SP, #768]!

0x4ff1c4 ADD	X29, SP, #0

0x4ff1c8 STP	X19, X20, [SP, #16]

0x4ff1cc STP	X21, X22, [SP, #32]

0x4ff1d0 STP	X23, X24, [SP, #48]

0x4ff1d4 STP	X25, X26, [SP, #64]

0x4ff1d8 STP	X27, X28, [SP, #80]

0x4ff1dc LDP	X1, X2, [X0]

0x4ff1e0 STP	X2, X1, [SP, #168]

0x4ff1e4 LDP	X28, X6, [X0, #16]

0x4ff1e8 STR	X6, [SP, #232]

0x4ff1ec LDP	X10, X3, [X0, #32]

0x4ff1f0 STR	X3, [SP, #104]

0x4ff1f4 STR	X10, [SP, #224]

0x4ff1f8 LDP	X9, X27, [X0, #64]

0x4ff1fc LDP	X23, X21, [X0, #48]

0x4ff200 STR	X9, [SP, #216]

0x4ff204 LDP	X8, X26, [X0, #80]

0x4ff208 STR	X8, [SP, #208]

0x4ff20c LDP	X7, X25, [X0, #96]

0x4ff210 STR	X7, [SP, #200]

0x4ff214 LDP	X24, X4, [X0, #112]

0x4ff218 LDR	X12, [X0, #208]

0x4ff21c STR	X4, [SP, #192]

0x4ff220 LDP	X5, X11, [X0, #128]

0x4ff224 STR	X5, [SP, #112]

0x4ff228 STR	X11, [SP, #128]

0x4ff22c LDP	X22, X13, [X0, #144]

0x4ff230 STR	X13, [SP, #184]

0x4ff234 LDP	X14, X18, [X0, #176]

0x4ff238 LDP	X19, X20, [X0, #160]

0x4ff23c STP	X18, X14, [SP, #152]

0x4ff240 LDP	X0, X15, [X0, #192]

0x4ff244 STR	X12, [SP, #120]

0x4ff248 STP	X0, X15, [SP, #136]

0x4ff24c BL	5499c0

0x4ff250 LDP	X2, X18, [SP, #144]

0x4ff254 ORR	X13, XZR, X0

0x4ff258 LDP	X3, X8, [SP, #200]

0x4ff25c MADD	X7, X2, X0, XZR

0x4ff260 LDP	X9, X10, [SP, #216]

0x4ff264 ADD	X12, X2, X7

0x4ff268 LDR	X1, [SP, #120]

0x4ff26c LDR	X5, [SP, #184]

0x4ff270 LDR	X6, [SP, #232]

0x4ff274 CMP	X1, X0

0x4ff278 B.LE	4ff6e0

0x4ff27c ADD	X16, X0, X12

0x4ff280 ORR	X17, X19, X22

0x4ff284 ADD	X4, X0, X7

0x4ff288 ADD	X7, X16, #1

0x4ff28c CBNZ	X17, 4ff6f0

(3113) 0x4ff290 MOVZ	X19, #0

(3113) 0x4ff294 CMP	X4, X7

(3113) 0x4ff298 B.GE	4ff788

(3113) 0x4ff29c LDP	X1, X0, [SP, #168]

(3113) 0x4ff2a0 ADD	X14, X4, #1

(3113) 0x4ff2a4 ORR	X2, XZR, X4

(3113) 0x4ff2a8 UBFM	X15, X14, #61, #60

(3113) 0x4ff2ac ORR	X14, XZR, X20

(3113) 0x4ff2b0 STR	X7, [SP, #120]

(3113) 0x4ff2b4 STR	X3, [SP, #184]

(3113) 0x4ff2b8 LDR	X0, [X0]

(3113) 0x4ff2bc STR	X13, [SP, #216]

(3113) 0x4ff2c0 LDR	X1, [X1]

(3113) 0x4ff2c4 STP	X4, X18, [SP, #200]

(3113) 0x4ff2c8 LDR	X13, [SP, #128]

(3113) 0x4ff2cc LDR	X4, [SP, #104]

(3113) 0x4ff2d0 CBNZ	X13, 4ff3a0

  (3121) 0x4ff2d4 ORR	X3, XZR, X20

  (3121) 0x4ff2d8 LDR	X18, [SP, #112]

  (3121) 0x4ff2dc CBNZ	X18, 4ff3b0

    (3119) 0x4ff2e0 ORR	X11, XZR, X14

  (3121) 0x4ff2e4 LDR	X17, [X28, X2,LSL #3]

  (3121) 0x4ff2e8 ORR	X7, XZR, X25

  (3121) 0x4ff2ec LDR	X12, [X28, X15]

  (3121) 0x4ff2f0 CMP	X17, X12

  (3121) 0x4ff2f4 B.GE	4ff374

  (3121) 0x4ff2f8 HINT	#0

  (3121) 0x4ff2fc HINT	#0

    (3125) 0x4ff300 LDR	X25, [X6, X17,LSL #3]

    (3125) 0x4ff304 UBFM	X18, X25, #61, #60

    (3125) 0x4ff308 ADD	X30, X18, #8

    (3125) 0x4ff30c LDR	X12, [X23, X18]

    (3125) 0x4ff310 ADD	X25, X23, X30

    (3125) 0x4ff314 LDR	X16, [X23, X30]

    (3125) 0x4ff318 CMP	X12, X16

    (3125) 0x4ff31c B.GE	4ff35c

    (3125) 0x4ff320 ORR	X13, XZR, X5

    (3125) 0x4ff324 STR	X0, [SP, #104]

      (3128) 0x4ff328 LDR	X0, [X21, X12,LSL #3]

      (3128) 0x4ff32c UBFM	X5, X0, #61, #60

      (3128) 0x4ff330 LDR	X0, [X19, X5]

      (3128) 0x4ff334 CMP	X20, X0

      (3128) 0x4ff338 B.LE	4ff484

      (3128) 0x4ff33c STR	X3, [X19, X5]

      (3128) 0x4ff340 ADD	X12, X12, #1

      (3128) 0x4ff344 ADD	X3, X3, #1

      (3128) 0x4ff348 LDR	X16, [X25]

      (3128) 0x4ff34c CMP	X16, X12

      (3128) 0x4ff350 B.GT	4ff328

    (3125) 0x4ff354 LDR	X0, [SP, #104]

    (3125) 0x4ff358 ORR	X5, XZR, X13

    (3125) 0x4ff35c CBNZ	X5, 4ff4cc

    (3125) 0x4ff360 LDR	X18, [X28, X15]

    (3125) 0x4ff364 ADD	X17, X17, #1

    (3125) 0x4ff368 CMP	X18, X17

    (3125) 0x4ff36c B.GT	4ff300

  (3121) 0x4ff370 ORR	X25, XZR, X7

  (3121) 0x4ff374 STR	X20, [X0, X2,LSL #3]

  (3121) 0x4ff378 ADD	X15, X15, #8

  (3121) 0x4ff37c LDR	X20, [SP, #120]

  (3121) 0x4ff380 STR	X14, [X1, X2,LSL #3]

  (3121) 0x4ff384 ADD	X2, X2, #1

  (3121) 0x4ff388 CMP	X20, X2

  (3121) 0x4ff38c B.EQ	4ff540

  (3121) 0x4ff390 LDR	X13, [SP, #128]

  (3121) 0x4ff394 ORR	X14, XZR, X11

  (3121) 0x4ff398 ORR	X20, XZR, X3

  (3121) 0x4ff39c CBZ	X13, 4ff2d4

  (3124) 0x4ff3a0 LDR	X18, [SP, #112]

  (3124) 0x4ff3a4 ADD	X3, X20, #1

  (3124) 0x4ff3a8 STR	X20, [X19, X2,LSL #3]

  (3124) 0x4ff3ac CBZ	X18, 4ff2e0

  (3121) 0x4ff3b0 LDR	X30, [X10, X2,LSL #3]

  (3121) 0x4ff3b4 LDR	X12, [X10, X15]

  (3121) 0x4ff3b8 CMP	X30, X12

  (3121) 0x4ff3bc B.GE	4ff2e0

  (3121) 0x4ff3c0 LDR	X7, [SP, #184]

  (3121) 0x4ff3c4 ORR	X11, XZR, X14

  (3121) 0x4ff3c8 STP	X5, X24, [SP, #144]

    (3120) 0x4ff3cc LDR	X24, [X4, X30,LSL #3]

    (3120) 0x4ff3d0 UBFM	X5, X24, #61, #60

    (3120) 0x4ff3d4 ADD	X24, X5, #8

    (3120) 0x4ff3d8 LDR	X12, [X7, X5]

    (3120) 0x4ff3dc ADD	X17, X7, X24

    (3120) 0x4ff3e0 LDR	X16, [X7, X24]

    (3120) 0x4ff3e4 CMP	X12, X16

    (3120) 0x4ff3e8 B.GE	4ff424

    (3120) 0x4ff3ec STR	X0, [SP, #104]

      (3123) 0x4ff3f0 LDR	X0, [X25, X12,LSL #3]

      (3123) 0x4ff3f4 ADD	X13, X22, X0

      (3123) 0x4ff3f8 UBFM	X18, X13, #61, #60

      (3123) 0x4ff3fc LDR	X0, [X19, X18]

      (3123) 0x4ff400 CMP	X14, X0

      (3123) 0x4ff404 B.LE	4ff49c

      (3123) 0x4ff408 STR	X11, [X19, X18]

      (3123) 0x4ff40c ADD	X12, X12, #1

      (3123) 0x4ff410 ADD	X11, X11, #1

      (3123) 0x4ff414 LDR	X16, [X17]

      (3123) 0x4ff418 CMP	X12, X16

      (3123) 0x4ff41c B.LT	4ff3f0

    (3120) 0x4ff420 LDR	X0, [SP, #104]

    (3120) 0x4ff424 LDR	X13, [X8, X5]

    (3120) 0x4ff428 ADD	X5, X8, X24

    (3120) 0x4ff42c LDR	X18, [X8, X24]

    (3120) 0x4ff430 CMP	X13, X18

    (3120) 0x4ff434 B.GE	4ff46c

    (3120) 0x4ff438 HINT	#0

    (3120) 0x4ff43c HINT	#0

      (3122) 0x4ff440 LDR	X24, [X26, X13,LSL #3]

      (3122) 0x4ff444 UBFM	X17, X24, #61, #60

      (3122) 0x4ff448 LDR	X12, [X19, X17]

      (3122) 0x4ff44c CMP	X20, X12

      (3122) 0x4ff450 B.LE	4ff4ac

      (3122) 0x4ff454 STR	X3, [X19, X17]

      (3122) 0x4ff458 ADD	X13, X13, #1

      (3122) 0x4ff45c ADD	X3, X3, #1

      (3122) 0x4ff460 LDR	X18, [X5]

      (3122) 0x4ff464 CMP	X18, X13

      (3122) 0x4ff468 B.GT	4ff440

    (3120) 0x4ff46c LDR	X16, [X10, X15]

    (3120) 0x4ff470 ADD	X30, X30, #1

    (3120) 0x4ff474 CMP	X16, X30

    (3120) 0x4ff478 B.GT	4ff3cc

  (3121) 0x4ff47c LDP	X5, X24, [SP, #144]

  (3121) 0x4ff480 B	4ff2e4

      (3128) 0x4ff484 ADD	X12, X12, #1

      (3128) 0x4ff488 CMP	X12, X16

      (3128) 0x4ff48c B.LT	4ff328

    (3125) 0x4ff490 LDR	X0, [SP, #104]

    (3125) 0x4ff494 ORR	X5, XZR, X13

    (3125) 0x4ff498 B	4ff35c

      (3123) 0x4ff49c ADD	X12, X12, #1

      (3123) 0x4ff4a0 CMP	X12, X16

      (3123) 0x4ff4a4 B.LT	4ff3f0

    (3120) 0x4ff4a8 B	4ff420

      (3122) 0x4ff4ac ADD	X13, X13, #1

      (3122) 0x4ff4b0 CMP	X13, X18

      (3122) 0x4ff4b4 B.LT	4ff440

    (3120) 0x4ff4b8 LDR	X16, [X10, X15]

    (3120) 0x4ff4bc ADD	X30, X30, #1

    (3120) 0x4ff4c0 CMP	X16, X30

    (3120) 0x4ff4c4 B.GT	4ff3cc

  (3121) 0x4ff4c8 B	4ff47c

    (3125) 0x4ff4cc LDR	X13, [X9, X18]

    (3125) 0x4ff4d0 ADD	X18, X9, X30

    (3125) 0x4ff4d4 LDR	X25, [X9, X30]

    (3125) 0x4ff4d8 CMP	X13, X25

    (3125) 0x4ff4dc B.GE	4ff360

      (3126) 0x4ff4e0 LDR	X30, [X27, X13,LSL #3]

      (3126) 0x4ff4e4 LDR	X12, [X24, X30,LSL #3]

      (3126) 0x4ff4e8 ADD	X16, X22, X12

      (3126) 0x4ff4ec UBFM	X30, X16, #61, #60

      (3126) 0x4ff4f0 LDR	X12, [X19, X30]

      (3126) 0x4ff4f4 CMP	X14, X12

      (3126) 0x4ff4f8 B.LE	4ff530

      (3127) 0x4ff4fc STR	X11, [X19, X30]

      (3127) 0x4ff500 ADD	X13, X13, #1

      (3127) 0x4ff504 ADD	X11, X11, #1

      (3127) 0x4ff508 LDR	X25, [X18]

      (3127) 0x4ff50c CMP	X25, X13

      (3127) 0x4ff510 B.LE	4ff360

      (3127) 0x4ff514 LDR	X30, [X27, X13,LSL #3]

      (3127) 0x4ff518 LDR	X12, [X24, X30,LSL #3]

      (3127) 0x4ff51c ADD	X16, X22, X12

      (3127) 0x4ff520 UBFM	X30, X16, #61, #60

      (3127) 0x4ff524 LDR	X12, [X19, X30]

      (3127) 0x4ff528 CMP	X14, X12

      (3127) 0x4ff52c B.GT	4ff4fc

      (3126) 0x4ff530 ADD	X13, X13, #1

      (3126) 0x4ff534 CMP	X25, X13

      (3126) 0x4ff538 B.GT	4ff4e0

    (3125) 0x4ff53c B	4ff360

(3113) 0x4ff540 LDR	X13, [SP, #216]

(3113) 0x4ff544 ORR	X7, XZR, X20

(3113) 0x4ff548 LDP	X4, X18, [SP, #200]

(3113) 0x4ff54c UBFM	X28, X13, #61, #60

(3113) 0x4ff550 ORR	X0, XZR, X19

(3113) 0x4ff554 STR	X3, [X18, X28]

(3113) 0x4ff558 LDR	X23, [SP, #136]

(3113) 0x4ff55c STR	X11, [X23, X28]

(3113) 0x4ff560 STP	X18, X13, [SP, #104]

(3113) 0x4ff564 STP	X4, X7, [SP, #120]

(3113) 0x4ff568 BL	546e20

(3113) 0x4ff56c BL	410880

(3113) 0x4ff570 LDP	X21, X13, [SP, #104]

(3113) 0x4ff574 LDP	X4, X27, [SP, #120]

(3113) 0x4ff578 CBNZ	X13, 4ff794

(3113) 0x4ff57c LDR	X26, [SP, #176]

(3113) 0x4ff580 LDR	X10, [SP, #168]

(3113) 0x4ff584 LDR	X22, [SP, #192]

(3113) 0x4ff588 LDR	X9, [X26]

(3113) 0x4ff58c LDR	X6, [X10]

(3113) 0x4ff590 UBFM	X8, X22, #61, #60

(3113) 0x4ff594 LDR	X4, [SP, #160]

(3113) 0x4ff598 STR	XZR, [X9, X8]

(3113) 0x4ff59c ADD	X19, X9, X22,LSL #3

(3113) 0x4ff5a0 STR	XZR, [X6, X8]

(3113) 0x4ff5a4 ADD	X14, X6, X8

(3113) 0x4ff5a8 CMP	X4, #0

(3113) 0x4ff5ac B.LE	4ff6c4

(3113) 0x4ff5b0 ANDS	X1, X4, #4160

(3113) 0x4ff5b4 B.EQ	4ff624

(3113) 0x4ff5b8 CMP	X1, #1

(3113) 0x4ff5bc B.EQ	4ff5f0

(3113) 0x4ff5c0 CMP	X1, #2

(3113) 0x4ff5c4 B.NE	4ffce8

(3113) 0x4ff5c8 LDR	X30, [X21, X13,LSL #3]

(3113) 0x4ff5cc LDR	X12, [X19]

(3113) 0x4ff5d0 LDR	X18, [SP, #136]

(3113) 0x4ff5d4 ADD	X25, X12, X30

(3113) 0x4ff5d8 STR	X25, [X19]

(3113) 0x4ff5dc LDR	X17, [X18, X13,LSL #3]

(3113) 0x4ff5e0 ADD	X13, X13, #1

(3113) 0x4ff5e4 LDR	X15, [X14]

(3113) 0x4ff5e8 ADD	X2, X15, X17

(3113) 0x4ff5ec STR	X2, [X14]

(3113) 0x4ff5f0 LDR	X20, [X21, X13,LSL #3]

(3113) 0x4ff5f4 LDR	X28, [X19]

(3113) 0x4ff5f8 LDR	X27, [SP, #136]

(3113) 0x4ff5fc LDR	X9, [SP, #160]

(3113) 0x4ff600 ADD	X23, X28, X20

(3113) 0x4ff604 STR	X23, [X19]

(3113) 0x4ff608 LDR	X26, [X27, X13,LSL #3]

(3113) 0x4ff60c ADD	X13, X13, #1

(3113) 0x4ff610 LDR	X22, [X14]

(3113) 0x4ff614 ADD	X8, X22, X26

(3113) 0x4ff618 STR	X8, [X14]

(3113) 0x4ff61c CMP	X9, X13

(3113) 0x4ff620 B.EQ	4ff6c4

(3113) 0x4ff624 LDR	X10, [SP, #136]

  (3118) 0x4ff628 ADD	X4, X13, #1

  (3118) 0x4ff62c ADD	X6, X13, #2

  (3118) 0x4ff630 LDR	X11, [X21, X13,LSL #3]

  (3118) 0x4ff634 ADD	X1, X13, #3

  (3118) 0x4ff638 LDR	X3, [X19]

  (3118) 0x4ff63c ADD	X24, X3, X11

  (3118) 0x4ff640 STR	X24, [X19]

  (3118) 0x4ff644 LDR	X7, [X10, X13,LSL #3]

  (3118) 0x4ff648 ADD	X13, X13, #4

  (3118) 0x4ff64c LDR	X5, [X14]

  (3118) 0x4ff650 ADD	X0, X5, X7

  (3118) 0x4ff654 STR	X0, [X14]

  (3118) 0x4ff658 LDR	X16, [X21, X4,LSL #3]

  (3118) 0x4ff65c LDR	X30, [X19]

  (3118) 0x4ff660 ADD	X12, X30, X16

  (3118) 0x4ff664 STR	X12, [X19]

  (3118) 0x4ff668 LDR	X25, [X10, X4,LSL #3]

  (3118) 0x4ff66c LDR	X18, [X14]

  (3118) 0x4ff670 ADD	X17, X18, X25

  (3118) 0x4ff674 STR	X17, [X14]

  (3118) 0x4ff678 LDR	X15, [X21, X6,LSL #3]

  (3118) 0x4ff67c LDR	X2, [X19]

  (3118) 0x4ff680 ADD	X20, X2, X15

  (3118) 0x4ff684 STR	X20, [X19]

  (3118) 0x4ff688 LDR	X28, [X10, X6,LSL #3]

  (3118) 0x4ff68c LDR	X23, [X14]

  (3118) 0x4ff690 LDR	X6, [SP, #160]

  (3118) 0x4ff694 ADD	X27, X23, X28

  (3118) 0x4ff698 STR	X27, [X14]

  (3118) 0x4ff69c LDR	X26, [X21, X1,LSL #3]

  (3118) 0x4ff6a0 LDR	X22, [X19]

  (3118) 0x4ff6a4 ADD	X8, X22, X26

  (3118) 0x4ff6a8 STR	X8, [X19]

  (3118) 0x4ff6ac LDR	X9, [X10, X1,LSL #3]

  (3118) 0x4ff6b0 LDR	X4, [X14]

  (3118) 0x4ff6b4 ADD	X1, X4, X9

  (3118) 0x4ff6b8 STR	X1, [X14]

  (3118) 0x4ff6bc CMP	X6, X13

  (3118) 0x4ff6c0 B.NE	4ff628

(3113) 0x4ff6c4 LDP	X19, X20, [SP, #16]

(3113) 0x4ff6c8 LDP	X21, X22, [SP, #32]

(3113) 0x4ff6cc LDP	X23, X24, [SP, #48]

(3113) 0x4ff6d0 LDP	X25, X26, [SP, #64]

(3113) 0x4ff6d4 LDP	X27, X28, [SP, #80]

(3113) 0x4ff6d8 LDP	X29, X30, [SP], #256

(3113) 0x4ff6dc RET

(3113) 0x4ff6e0 ORR	X17, X19, X22

(3113) 0x4ff6e4 ADD	X4, X1, X7

(3113) 0x4ff6e8 ADD	X7, X1, X12

(3113) 0x4ff6ec CBZ	X17, 4ff290

(3113) 0x4ff6f0 ADD	X30, X19, X22

(3113) 0x4ff6f4 MOVZ	X1, #8

(3113) 0x4ff6f8 STP	X4, X7, [SP, #144]

(3113) 0x4ff6fc ORR	X0, XZR, X30

(3113) 0x4ff700 STR	X30, [SP, #120]

(3113) 0x4ff704 STR	X18, [SP, #184]

(3113) 0x4ff708 STP	X5, X3, [SP, #200]

(3113) 0x4ff70c STP	X8, X9, [SP, #216]

(3113) 0x4ff710 STP	X10, X6, [SP, #232]

(3113) 0x4ff714 STR	X13, [SP, #248]

(3113) 0x4ff718 BL	546d88

(3113) 0x4ff71c LDR	X11, [SP, #120]

(3113) 0x4ff720 ORR	X19, XZR, X0

(3113) 0x4ff724 LDP	X4, X7, [SP, #144]

(3113) 0x4ff728 LDP	X5, X3, [SP, #200]

(3113) 0x4ff72c LDP	X8, X9, [SP, #216]

(3113) 0x4ff730 LDP	X10, X6, [SP, #232]

(3113) 0x4ff734 LDR	X18, [SP, #184]

(3113) 0x4ff738 LDR	X13, [SP, #248]

(3113) 0x4ff73c CMP	X11, #0

(3113) 0x4ff740 B.LE	4ff294

(3113) 0x4ff744 UBFM	X2, X11, #61, #60

(3113) 0x4ff748 MOVZ	W1, #255

(3113) 0x4ff74c STR	X4, [SP, #120]

(3113) 0x4ff750 STP	X7, X18, [SP, #144]

(3113) 0x4ff754 STR	X5, [SP, #184]

(3113) 0x4ff758 STP	X3, X8, [SP, #200]

(3113) 0x4ff75c STP	X9, X10, [SP, #216]

(3113) 0x4ff760 STP	X6, X13, [SP, #232]

(3113) 0x4ff764 BL	4108c0

(3113) 0x4ff768 LDR	X4, [SP, #120]

(3113) 0x4ff76c LDP	X7, X18, [SP, #144]

(3113) 0x4ff770 LDP	X3, X8, [SP, #200]

(3113) 0x4ff774 LDP	X9, X10, [SP, #216]

(3113) 0x4ff778 LDP	X6, X13, [SP, #232]

(3113) 0x4ff77c LDR	X5, [SP, #184]

(3113) 0x4ff780 CMP	X4, X7

(3113) 0x4ff784 B.LT	4ff29c

(3113) 0x4ff788 ORR	X11, XZR, X20

(3113) 0x4ff78c ORR	X3, XZR, X20

(3113) 0x4ff790 B	4ff54c

(3113) 0x4ff794 LDR	X19, [SP, #136]

(3113) 0x4ff798 LDR	X5, [X21]

(3113) 0x4ff79c LDR	X3, [X19]

(3113) 0x4ff7a0 CMP	X13, #1

(3113) 0x4ff7a4 B.LE	4ffa5c

(3113) 0x4ff7a8 SUB	X14, X13, #2

(3113) 0x4ff7ac SUB	X24, X13, #1

(3113) 0x4ff7b0 CMP	X14, #6

(3113) 0x4ff7b4 B.LS	4fff28

(3113) 0x4ff7b8 UBFM	X10, X24, #3, #63

(3113) 0x4ff7bc LDR	X25, [SP, #136]

(3113) 0x4ff7c0 MOVI	V20.4S, #0

(3113) 0x4ff7c4 ORR	X2, XZR, X21

(3113) 0x4ff7c8 UBFM	X11, X10, #58, #57

(3113) 0x4ff7cc ADD	X7, X21, X10,LSL #6

(3113) 0x4ff7d0 SUB	X0, X11, #64

(3113) 0x4ff7d4 UBFM	X16, X0, #6, #63

(3113) 0x4ff7d8 ADD	X30, X16, #1

(3113) 0x4ff7dc ORR	V25.16B, V20.16B, V20.16B

(3113) 0x4ff7e0 ORR	V19.16B, V20.16B, V20.16B

(3113) 0x4ff7e4 ANDS	X12, X30, #4160

(3113) 0x4ff7e8 ORR	V6.16B, V20.16B, V20.16B

(3113) 0x4ff7ec ORR	V29.16B, V20.16B, V20.16B

(3113) 0x4ff7f0 ADD	X15, X25, #8

(3113) 0x4ff7f4 ORR	V18.16B, V20.16B, V20.16B

(3113) 0x4ff7f8 ORR	V17.16B, V20.16B, V20.16B

(3113) 0x4ff7fc ORR	V30.16B, V20.16B, V20.16B

(3113) 0x4ff800 B.EQ	4ff89c

(3113) 0x4ff804 CMP	X12, #1

(3113) 0x4ff808 B.EQ	4ff854

(3113) 0x4ff80c CMP	X12, #2

(3113) 0x4ff810 B.NE	4ffcc4

  (3116) 0x4ff814 LDP	Q24, Q27, [X15]

  (3116) 0x4ff818 ADD	X2, X2, #64

  (3116) 0x4ff81c LDP	Q0, Q1, [X15, #32]

  (3116) 0x4ff820 ADD	X15, X15, #64

  (3116) 0x4ff824 LDUR	Q26, [X2, #456]

  (3116) 0x4ff828 LDUR	Q28, [X2, #472]

  (3116) 0x4ff82c LDUR	Q2, [X2, #488]

  (3116) 0x4ff830 ADD	V6.2D, V6.2D, V24.2D

  (3116) 0x4ff834 ADD	V19.2D, V19.2D, V27.2D

  (3116) 0x4ff838 LDUR	Q3, [X2, #504]

  (3116) 0x4ff83c ADD	V30.2D, V30.2D, V26.2D

  (3116) 0x4ff840 ADD	V25.2D, V25.2D, V0.2D

  (3116) 0x4ff844 ADD	V20.2D, V20.2D, V1.2D

  (3116) 0x4ff848 ADD	V17.2D, V17.2D, V28.2D

  (3116) 0x4ff84c ADD	V18.2D, V18.2D, V2.2D

  (3116) 0x4ff850 ADD	V29.2D, V29.2D, V3.2D

  (3116) 0x4ff854 LDP	Q4, Q5, [X15]

  (3116) 0x4ff858 ADD	X2, X2, #64

  (3116) 0x4ff85c LDP	Q7, Q16, [X15, #32]

  (3116) 0x4ff860 ADD	X15, X15, #64

  (3116) 0x4ff864 LDUR	Q21, [X2, #456]

  (3116) 0x4ff868 LDUR	Q22, [X2, #472]

  (3116) 0x4ff86c LDUR	Q23, [X2, #488]

  (3116) 0x4ff870 ADD	V6.2D, V6.2D, V4.2D

  (3116) 0x4ff874 ADD	V19.2D, V19.2D, V5.2D

  (3116) 0x4ff878 LDUR	Q31, [X2, #504]

  (3116) 0x4ff87c ADD	V30.2D, V30.2D, V21.2D

  (3116) 0x4ff880 ADD	V25.2D, V25.2D, V7.2D

  (3116) 0x4ff884 ADD	V20.2D, V20.2D, V16.2D

  (3116) 0x4ff888 ADD	V17.2D, V17.2D, V22.2D

  (3116) 0x4ff88c ADD	V18.2D, V18.2D, V23.2D

  (3116) 0x4ff890 ADD	V29.2D, V29.2D, V31.2D

  (3116) 0x4ff894 CMP	X7, X2

  (3116) 0x4ff898 B.EQ	4ff9a0

    (3117) 0x4ff89c LDP	Q24, Q27, [X15]

    (3117) 0x4ff8a0 ADD	X28, X15, #64

    (3117) 0x4ff8a4 ADD	X8, X2, #8

    (3117) 0x4ff8a8 ADD	X20, X2, #64

    (3117) 0x4ff8ac ADD	X23, X15, #128

    (3117) 0x4ff8b0 LDP	Q26, Q28, [X15, #32]

    (3117) 0x4ff8b4 ADD	X9, X20, #8

    (3117) 0x4ff8b8 ADD	X22, X15, #192

    (3117) 0x4ff8bc ORR	X26, XZR, X2

    (3117) 0x4ff8c0 ADD	X2, X2, #256

    (3117) 0x4ff8c4 LDP	Q4, Q5, [X8]

    (3117) 0x4ff8c8 ADD	X15, X15, #256

    (3117) 0x4ff8cc ADD	V1.2D, V19.2D, V27.2D

    (3117) 0x4ff8d0 ADD	V0.2D, V6.2D, V24.2D

    (3117) 0x4ff8d4 LDP	Q6, Q19, [X8, #32]

    (3117) 0x4ff8d8 ADD	V2.2D, V25.2D, V26.2D

    (3117) 0x4ff8dc ADD	V3.2D, V20.2D, V28.2D

    (3117) 0x4ff8e0 LDP	Q25, Q20, [X28, #16]

    (3117) 0x4ff8e4 ADD	V16.2D, V17.2D, V5.2D

    (3117) 0x4ff8e8 ADD	V7.2D, V30.2D, V4.2D

    (3117) 0x4ff8ec LDP	Q30, Q31, [X9]

    (3117) 0x4ff8f0 LDUR	Q4, [X15, #320]

    (3117) 0x4ff8f4 ADD	V17.2D, V18.2D, V6.2D

    (3117) 0x4ff8f8 ADD	V23.2D, V29.2D, V19.2D

    (3117) 0x4ff8fc LDUR	Q19, [X20, #72]

    (3117) 0x4ff900 LDP	Q18, Q21, [X9, #32]

    (3117) 0x4ff904 ADD	V27.2D, V2.2D, V20.2D

    (3117) 0x4ff908 ADD	V22.2D, V1.2D, V25.2D

    (3117) 0x4ff90c ADD	V0.2D, V0.2D, V4.2D

    (3117) 0x4ff910 LDP	Q29, Q2, [X28, #48]

    (3117) 0x4ff914 ADD	V1.2D, V7.2D, V30.2D

    (3117) 0x4ff918 ADD	V24.2D, V16.2D, V31.2D

    (3117) 0x4ff91c LDP	Q5, Q6, [X23, #16]

    (3117) 0x4ff920 LDUR	Q25, [X20, #104]

    (3117) 0x4ff924 ADD	V30.2D, V1.2D, V19.2D

    (3117) 0x4ff928 LDR	Q4, [X22, #48]

    (3117) 0x4ff92c ADD	V26.2D, V17.2D, V18.2D

    (3117) 0x4ff930 LDUR	Q18, [X15, #448]

    (3117) 0x4ff934 ADD	V28.2D, V3.2D, V29.2D

    (3117) 0x4ff938 ADD	V3.2D, V23.2D, V21.2D

    (3117) 0x4ff93c LDUR	Q21, [X20, #120]

    (3117) 0x4ff940 ADD	V17.2D, V0.2D, V2.2D

    (3117) 0x4ff944 ADD	V7.2D, V22.2D, V5.2D

    (3117) 0x4ff948 ADD	V16.2D, V27.2D, V6.2D

    (3117) 0x4ff94c LDUR	Q23, [X20, #88]

    (3117) 0x4ff950 ADD	V27.2D, V26.2D, V25.2D

    (3117) 0x4ff954 LDP	Q20, Q22, [X22, #16]

    (3117) 0x4ff958 ADD	V6.2D, V17.2D, V18.2D

    (3117) 0x4ff95c ADD	V1.2D, V3.2D, V21.2D

    (3117) 0x4ff960 LDR	Q3, [X23, #48]

    (3117) 0x4ff964 LDUR	Q26, [X26, #216]

    (3117) 0x4ff968 ADD	V31.2D, V24.2D, V23.2D

    (3117) 0x4ff96c LDUR	Q24, [X26, #200]

    (3117) 0x4ff970 LDUR	Q29, [X26, #232]

    (3117) 0x4ff974 ADD	V28.2D, V28.2D, V3.2D

    (3117) 0x4ff978 ADD	V19.2D, V7.2D, V20.2D

    (3117) 0x4ff97c ADD	V25.2D, V16.2D, V22.2D

    (3117) 0x4ff980 LDUR	Q2, [X26, #248]

    (3117) 0x4ff984 ADD	V17.2D, V31.2D, V26.2D

    (3117) 0x4ff988 ADD	V30.2D, V30.2D, V24.2D

    (3117) 0x4ff98c ADD	V20.2D, V28.2D, V4.2D

    (3117) 0x4ff990 ADD	V18.2D, V27.2D, V29.2D

    (3117) 0x4ff994 ADD	V29.2D, V1.2D, V2.2D

    (3117) 0x4ff998 CMP	X7, X2

    (3117) 0x4ff99c B.NE	4ff89c

  (3116) 0x4ff9a0 ADD	V0.2D, V17.2D, V30.2D

  (3116) 0x4ff9a4 ADD	V5.2D, V19.2D, V6.2D

  (3116) 0x4ff9a8 AND	X13, X24, #7997

  (3116) 0x4ff9ac ADD	V6.2D, V0.2D, V18.2D

  (3116) 0x4ff9b0 ADD	V7.2D, V5.2D, V25.2D

  (3116) 0x4ff9b4 ADD	V30.2D, V6.2D, V29.2D

  (3116) 0x4ff9b8 ADD	V31.2D, V7.2D, V20.2D

  (3116) 0x4ff9bc ANDS	XZR, X24, #4224

  (3116) 0x4ff9c0 B.EQ	4ffa40

  (3116) 0x4ff9c4 LDR	X14, [SP, #136]

  (3116) 0x4ff9c8 ADD	X1, X13, #1

  (3116) 0x4ff9cc SUB	X19, X24, X13

  (3116) 0x4ff9d0 WHILELO	P7.D, XZR, X19

  (3116) 0x4ff9d4 LD1D	{Z16.D}, P7/Z, [X21, X1,LSL #3]

  (3116) 0x4ff9d8 MOVZ	X6, #2

  (3116) 0x4ff9dc LD1D	{Z17.D}, P7/Z, [X14, X1,LSL #3]

  (3116) 0x4ff9e0 ADD	X21, X21, X1,LSL #3

  (3116) 0x4ff9e4 ADD	Z30.D, P7/M, Z30.D, Z16.D

  (3116) 0x4ff9e8 ADD	Z31.D, P7/M, Z31.D, Z17.D

  (3116) 0x4ff9ec WHILELO	P0.D, X6, X19

  (3116) 0x4ff9f0 ADD	X24, X14, X1,LSL #3

  (3116) 0x4ff9f4 B.EQ	4ffa40

  (3116) 0x4ff9f8 MOVZ	X13, #4

  (3116) 0x4ff9fc LD1D	{Z19.D}, P0/Z, [X21, #1, MUL VL]

  (3116) 0x4ffa00 LD1D	{Z23.D}, P0/Z, [X24, #1, MUL VL]

  (3116) 0x4ffa04 ADD	Z30.D, P0/M, Z30.D, Z19.D

  (3116) 0x4ffa08 ADD	Z31.D, P0/M, Z31.D, Z23.D

  (3116) 0x4ffa0c WHILELO	P1.D, X13, X19

  (3116) 0x4ffa10 B.EQ	4ffa40

  (3116) 0x4ffa14 MOVZ	X10, #6

  (3116) 0x4ffa18 LD1D	{Z25.D}, P1/Z, [X21, #2, MUL VL]

  (3116) 0x4ffa1c LD1D	{Z27.D}, P1/Z, [X24, #2, MUL VL]

  (3116) 0x4ffa20 ADD	Z30.D, P1/M, Z30.D, Z25.D

  (3116) 0x4ffa24 ADD	Z31.D, P1/M, Z31.D, Z27.D

  (3116) 0x4ffa28 WHILELO	P2.D, X10, X19

  (3116) 0x4ffa2c B.EQ	4ffa40

  (3116) 0x4ffa30 LD1D	{Z20.D}, P2/Z, [X21, #3, MUL VL]

  (3116) 0x4ffa34 LD1D	{Z22.D}, P2/Z, [X24, #3, MUL VL]

  (3116) 0x4ffa38 ADD	Z30.D, P2/M, Z30.D, Z20.D

  (3116) 0x4ffa3c ADD	Z31.D, P2/M, Z31.D, Z22.D

  (3116) 0x4ffa40 PTRUE	P3.B, VL16

  (3116) 0x4ffa44 UADDV	D31, P3, Z31.D

  (3116) 0x4ffa48 UADDV	D30, P3, Z30.D

  (3116) 0x4ffa4c FMOV	X11, D31

  (3116) 0x4ffa50 FMOV	X7, D30

  (3116) 0x4ffa54 ADD	X3, X3, X11

  (3116) 0x4ffa58 ADD	X5, X5, X7

  (3116) 0x4ffa5c CMP	X4, X27

  (3116) 0x4ffa60 B.GE	4ff6c4

  (3116) 0x4ffa64 LDP	X16, X0, [SP, #168]

  (3116) 0x4ffa68 SUB	X30, X27, X4

  (3116) 0x4ffa6c SUB	X12, X30, #1

  (3116) 0x4ffa70 LDR	X25, [X0]

  (3116) 0x4ffa74 LDR	X18, [X16]

  (3116) 0x4ffa78 CMP	X12, #2

  (3116) 0x4ffa7c B.LS	4ffd14

  (3116) 0x4ffa80 ADD	X17, X25, X4,LSL #3

  (3116) 0x4ffa84 ADD	X2, X18, X4,LSL #3

  (3116) 0x4ffa88 WHILERW	P15.D, X17, X2

  (3116) 0x4ffa8c B.CS	4ffd14

  (3116) 0x4ffa90 UBFM	X27, X30, #1, #63

  (3116) 0x4ffa94 DUP	V31.2D, X5

  (3116) 0x4ffa98 MOVZ	X22, #0

  (3116) 0x4ffa9c UBFM	X20, X27, #60, #59

  (3116) 0x4ffaa0 SUB	X15, X20, #16

  (3116) 0x4ffaa4 DUP	V30.2D, X3

  (3116) 0x4ffaa8 UBFM	X28, X15, #4, #63

  (3116) 0x4ffaac ADD	X23, X28, #1

  (3116) 0x4ffab0 ANDS	X26, X23, #4224

  (3116) 0x4ffab4 B.EQ	4ffb98

  (3116) 0x4ffab8 CMP	X26, #1

  (3116) 0x4ffabc B.EQ	4ffb74

  (3116) 0x4ffac0 CMP	X26, #2

  (3116) 0x4ffac4 B.EQ	4ffb58

  (3116) 0x4ffac8 CMP	X26, #3

  (3116) 0x4ffacc B.EQ	4ffb3c

  (3116) 0x4ffad0 CMP	X26, #4

  (3116) 0x4ffad4 B.EQ	4ffb20

  (3116) 0x4ffad8 CMP	X26, #5

  (3116) 0x4ffadc B.EQ	4ffb04

  (3116) 0x4ffae0 CMP	X26, #6

  (3116) 0x4ffae4 B.NE	4fff08

  (3116) 0x4ffae8 LDR	Q26, [X17, X22]

  (3116) 0x4ffaec ADD	V29.2D, V26.2D, V31.2D

  (3116) 0x4ffaf0 STR	Q29, [X17, X22]

  (3116) 0x4ffaf4 LDR	Q2, [X2, X22]

  (3116) 0x4ffaf8 ADD	V3.2D, V2.2D, V30.2D

  (3116) 0x4ffafc STR	Q3, [X2, X22]

  (3116) 0x4ffb00 ADD	X22, X22, #16

  (3116) 0x4ffb04 LDR	Q28, [X17, X22]

  (3116) 0x4ffb08 ADD	V4.2D, V28.2D, V31.2D

  (3116) 0x4ffb0c STR	Q4, [X17, X22]

  (3116) 0x4ffb10 LDR	Q0, [X2, X22]

  (3116) 0x4ffb14 ADD	V5.2D, V0.2D, V30.2D

  (3116) 0x4ffb18 STR	Q5, [X2, X22]

  (3116) 0x4ffb1c ADD	X22, X22, #16

  (3116) 0x4ffb20 LDR	Q6, [X17, X22]

  (3116) 0x4ffb24 ADD	V7.2D, V6.2D, V31.2D

  (3116) 0x4ffb28 STR	Q7, [X17, X22]

  (3116) 0x4ffb2c LDR	Q16, [X2, X22]

  (3116) 0x4ffb30 ADD	V17.2D, V16.2D, V30.2D

  (3116) 0x4ffb34 STR	Q17, [X2, X22]

  (3116) 0x4ffb38 ADD	X22, X22, #16

  (3116) 0x4ffb3c LDR	Q19, [X17, X22]

  (3116) 0x4ffb40 ADD	V23.2D, V19.2D, V31.2D

  (3116) 0x4ffb44 STR	Q23, [X17, X22]

  (3116) 0x4ffb48 LDR	Q25, [X2, X22]

  (3116) 0x4ffb4c ADD	V27.2D, V25.2D, V30.2D

  (3116) 0x4ffb50 STR	Q27, [X2, X22]

  (3116) 0x4ffb54 ADD	X22, X22, #16

  (3116) 0x4ffb58 LDR	Q20, [X17, X22]

  (3116) 0x4ffb5c ADD	V22.2D, V20.2D, V31.2D

  (3116) 0x4ffb60 STR	Q22, [X17, X22]

  (3116) 0x4ffb64 LDR	Q18, [X2, X22]

  (3116) 0x4ffb68 ADD	V21.2D, V18.2D, V30.2D

  (3116) 0x4ffb6c STR	Q21, [X2, X22]

  (3116) 0x4ffb70 ADD	X22, X22, #16

  (3116) 0x4ffb74 LDR	Q1, [X17, X22]

  (3116) 0x4ffb78 ADD	V24.2D, V1.2D, V31.2D

  (3116) 0x4ffb7c STR	Q24, [X17, X22]

  (3116) 0x4ffb80 LDR	Q26, [X2, X22]

  (3116) 0x4ffb84 ADD	V29.2D, V26.2D, V30.2D

  (3116) 0x4ffb88 STR	Q29, [X2, X22]

  (3116) 0x4ffb8c ADD	X22, X22, #16

  (3116) 0x4ffb90 CMP	X22, X20

  (3116) 0x4ffb94 B.EQ	4ffc80

    (3115) 0x4ffb98 LDR	Q2, [X17, X22]

    (3115) 0x4ffb9c ADD	X8, X22, #16

    (3115) 0x4ffba0 ADD	X19, X22, #32

    (3115) 0x4ffba4 ADD	X9, X22, #48

    (3115) 0x4ffba8 ADD	X1, X22, #64

    (3115) 0x4ffbac ADD	X21, X22, #80

    (3115) 0x4ffbb0 ADD	X6, X22, #96

    (3115) 0x4ffbb4 ADD	X14, X22, #112

    (3115) 0x4ffbb8 ADD	V3.2D, V2.2D, V31.2D

    (3115) 0x4ffbbc STR	Q3, [X17, X22]

    (3115) 0x4ffbc0 LDR	Q28, [X2, X22]

    (3115) 0x4ffbc4 ADD	V4.2D, V28.2D, V30.2D

    (3115) 0x4ffbc8 STR	Q4, [X2, X22]

    (3115) 0x4ffbcc ADD	X22, X22, #128

    (3115) 0x4ffbd0 LDR	Q0, [X17, X8]

    (3115) 0x4ffbd4 ADD	V5.2D, V0.2D, V31.2D

    (3115) 0x4ffbd8 STR	Q5, [X17, X8]

    (3115) 0x4ffbdc LDR	Q6, [X2, X8]

    (3115) 0x4ffbe0 ADD	V7.2D, V6.2D, V30.2D

    (3115) 0x4ffbe4 STR	Q7, [X2, X8]

    (3115) 0x4ffbe8 LDR	Q16, [X17, X19]

    (3115) 0x4ffbec ADD	V17.2D, V16.2D, V31.2D

    (3115) 0x4ffbf0 STR	Q17, [X17, X19]

    (3115) 0x4ffbf4 LDR	Q19, [X2, X19]

    (3115) 0x4ffbf8 ADD	V23.2D, V19.2D, V30.2D

    (3115) 0x4ffbfc STR	Q23, [X2, X19]

    (3115) 0x4ffc00 LDR	Q25, [X17, X9]

    (3115) 0x4ffc04 ADD	V27.2D, V25.2D, V31.2D

    (3115) 0x4ffc08 STR	Q27, [X17, X9]

    (3115) 0x4ffc0c LDR	Q20, [X2, X9]

    (3115) 0x4ffc10 ADD	V22.2D, V20.2D, V30.2D

    (3115) 0x4ffc14 STR	Q22, [X2, X9]

    (3115) 0x4ffc18 LDR	Q18, [X17, X1]

    (3115) 0x4ffc1c ADD	V21.2D, V18.2D, V31.2D

    (3115) 0x4ffc20 STR	Q21, [X17, X1]

    (3115) 0x4ffc24 LDR	Q1, [X2, X1]

    (3115) 0x4ffc28 ADD	V24.2D, V1.2D, V30.2D

    (3115) 0x4ffc2c STR	Q24, [X2, X1]

    (3115) 0x4ffc30 LDR	Q26, [X17, X21]

    (3115) 0x4ffc34 ADD	V29.2D, V26.2D, V31.2D

    (3115) 0x4ffc38 STR	Q29, [X17, X21]

    (3115) 0x4ffc3c LDR	Q2, [X2, X21]

    (3115) 0x4ffc40 ADD	V3.2D, V2.2D, V30.2D

    (3115) 0x4ffc44 STR	Q3, [X2, X21]

    (3115) 0x4ffc48 LDR	Q28, [X17, X6]

    (3115) 0x4ffc4c ADD	V4.2D, V28.2D, V31.2D

    (3115) 0x4ffc50 STR	Q4, [X17, X6]

    (3115) 0x4ffc54 LDR	Q0, [X2, X6]

    (3115) 0x4ffc58 ADD	V5.2D, V0.2D, V30.2D

    (3115) 0x4ffc5c STR	Q5, [X2, X6]

    (3115) 0x4ffc60 LDR	Q6, [X17, X14]

    (3115) 0x4ffc64 ADD	V7.2D, V6.2D, V31.2D

    (3115) 0x4ffc68 STR	Q7, [X17, X14]

    (3115) 0x4ffc6c LDR	Q16, [X2, X14]

    (3115) 0x4ffc70 ADD	V17.2D, V16.2D, V30.2D

    (3115) 0x4ffc74 STR	Q17, [X2, X14]

    (3115) 0x4ffc78 CMP	X22, X20

    (3115) 0x4ffc7c B.NE	4ffb98

  (3116) 0x4ffc80 TBZ	W30, #0, 4ff6c4

  (3116) 0x4ffc84 AND	X24, X30, #8127

  (3116) 0x4ffc88 ADD	X4, X24, X4

  (3116) 0x4ffc8c UBFM	X13, X4, #61, #60

  (3116) 0x4ffc90 LDR	X10, [X25, X13]

  (3116) 0x4ffc94 ADD	X11, X10, X5

  (3116) 0x4ffc98 STR	X11, [X25, X13]

  (3116) 0x4ffc9c LDR	X7, [X18, X13]

  (3116) 0x4ffca0 ADD	X3, X7, X3

  (3116) 0x4ffca4 STR	X3, [X18, X13]

  (3116) 0x4ffca8 LDP	X19, X20, [SP, #16]

  (3116) 0x4ffcac LDP	X21, X22, [SP, #32]

  (3116) 0x4ffcb0 LDP	X23, X24, [SP, #48]

  (3116) 0x4ffcb4 LDP	X25, X26, [SP, #64]

  (3116) 0x4ffcb8 LDP	X27, X28, [SP, #80]

  (3116) 0x4ffcbc LDP	X29, X30, [SP], #256

  (3116) 0x4ffcc0 RET

  (3116) 0x4ffcc4 LDR	X17, [SP, #136]

  (3116) 0x4ffcc8 ADD	X18, X21, #8

  (3116) 0x4ffccc ADD	X2, X21, #64

  (3116) 0x4ffcd0 LDP	Q6, Q19, [X15]

  (3116) 0x4ffcd4 LDP	Q25, Q20, [X15, #32]

  (3116) 0x4ffcd8 ADD	X15, X17, #72

  (3116) 0x4ffcdc LDP	Q30, Q17, [X18]

  (3116) 0x4ffce0 LDP	Q18, Q29, [X18, #32]

  (3116) 0x4ffce4 B	4ff814

(3113) 0x4ffce8 LDR	X11, [X19]

(3113) 0x4ffcec MOVZ	X13, #1

(3113) 0x4ffcf0 LDR	X3, [X21]

(3113) 0x4ffcf4 LDR	X7, [SP, #136]

(3113) 0x4ffcf8 ADD	X24, X11, X3

(3113) 0x4ffcfc STR	X24, [X19]

(3113) 0x4ffd00 LDR	X5, [X14]

(3113) 0x4ffd04 LDR	X0, [X7]

(3113) 0x4ffd08 ADD	X16, X5, X0

(3113) 0x4ffd0c STR	X16, [X14]

(3113) 0x4ffd10 B	4ff5c8

(3113) 0x4ffd14 SUB	X30, X27, X4

(3113) 0x4ffd18 ANDS	X16, X30, #4224

(3113) 0x4ffd1c B.EQ	4ffe1c

(3113) 0x4ffd20 CMP	X16, #1

(3113) 0x4ffd24 B.EQ	4ffdf8

(3113) 0x4ffd28 CMP	X16, #2

(3113) 0x4ffd2c B.EQ	4ffddc

(3113) 0x4ffd30 CMP	X16, #3

(3113) 0x4ffd34 B.EQ	4ffdc0

(3113) 0x4ffd38 CMP	X16, #4

(3113) 0x4ffd3c B.EQ	4ffda4

(3113) 0x4ffd40 CMP	X16, #5

(3113) 0x4ffd44 B.EQ	4ffd88

(3113) 0x4ffd48 CMP	X16, #6

(3113) 0x4ffd4c B.EQ	4ffd6c

(3113) 0x4ffd50 LDR	X0, [X25, X4,LSL #3]

(3113) 0x4ffd54 ADD	X12, X0, X5

(3113) 0x4ffd58 STR	X12, [X25, X4,LSL #3]

(3113) 0x4ffd5c LDR	X17, [X18, X4,LSL #3]

(3113) 0x4ffd60 ADD	X2, X17, X3

(3113) 0x4ffd64 STR	X2, [X18, X4,LSL #3]

(3113) 0x4ffd68 ADD	X4, X4, #1

(3113) 0x4ffd6c LDR	X20, [X25, X4,LSL #3]

(3113) 0x4ffd70 ADD	X15, X20, X5

(3113) 0x4ffd74 STR	X15, [X25, X4,LSL #3]

(3113) 0x4ffd78 LDR	X28, [X18, X4,LSL #3]

(3113) 0x4ffd7c ADD	X23, X28, X3

(3113) 0x4ffd80 STR	X23, [X18, X4,LSL #3]

(3113) 0x4ffd84 ADD	X4, X4, #1

(3113) 0x4ffd88 LDR	X26, [X25, X4,LSL #3]

(3113) 0x4ffd8c ADD	X22, X26, X5

(3113) 0x4ffd90 STR	X22, [X25, X4,LSL #3]

(3113) 0x4ffd94 LDR	X8, [X18, X4,LSL #3]

(3113) 0x4ffd98 ADD	X9, X8, X3

(3113) 0x4ffd9c STR	X9, [X18, X4,LSL #3]

(3113) 0x4ffda0 ADD	X4, X4, #1

(3113) 0x4ffda4 LDR	X19, [X25, X4,LSL #3]

(3113) 0x4ffda8 ADD	X1, X19, X5

(3113) 0x4ffdac STR	X1, [X25, X4,LSL #3]

(3113) 0x4ffdb0 LDR	X21, [X18, X4,LSL #3]

(3113) 0x4ffdb4 ADD	X6, X21, X3

(3113) 0x4ffdb8 STR	X6, [X18, X4,LSL #3]

(3113) 0x4ffdbc ADD	X4, X4, #1

(3113) 0x4ffdc0 LDR	X14, [X25, X4,LSL #3]

(3113) 0x4ffdc4 ADD	X24, X14, X5

(3113) 0x4ffdc8 STR	X24, [X25, X4,LSL #3]

(3113) 0x4ffdcc LDR	X13, [X18, X4,LSL #3]

(3113) 0x4ffdd0 ADD	X10, X13, X3

(3113) 0x4ffdd4 STR	X10, [X18, X4,LSL #3]

(3113) 0x4ffdd8 ADD	X4, X4, #1

(3113) 0x4ffddc LDR	X11, [X25, X4,LSL #3]

(3113) 0x4ffde0 ADD	X7, X11, X5

(3113) 0x4ffde4 STR	X7, [X25, X4,LSL #3]

(3113) 0x4ffde8 LDR	X30, [X18, X4,LSL #3]

(3113) 0x4ffdec ADD	X16, X30, X3

(3113) 0x4ffdf0 STR	X16, [X18, X4,LSL #3]

(3113) 0x4ffdf4 ADD	X4, X4, #1

(3113) 0x4ffdf8 LDR	X0, [X25, X4,LSL #3]

(3113) 0x4ffdfc ADD	X12, X0, X5

(3113) 0x4ffe00 STR	X12, [X25, X4,LSL #3]

(3113) 0x4ffe04 LDR	X17, [X18, X4,LSL #3]

(3113) 0x4ffe08 ADD	X2, X17, X3

(3113) 0x4ffe0c STR	X2, [X18, X4,LSL #3]

(3113) 0x4ffe10 ADD	X4, X4, #1

(3113) 0x4ffe14 CMP	X27, X4

(3113) 0x4ffe18 B.EQ	4ff6c4

  (3114) 0x4ffe1c LDR	X20, [X25, X4,LSL #3]

  (3114) 0x4ffe20 ADD	X15, X4, #1

  (3114) 0x4ffe24 ADD	X23, X4, #2

  (3114) 0x4ffe28 ADD	X28, X4, #3

  (3114) 0x4ffe2c ADD	X26, X4, #4

  (3114) 0x4ffe30 ADD	X22, X4, #5

  (3114) 0x4ffe34 ADD	X8, X4, #6

  (3114) 0x4ffe38 ADD	X9, X4, #7

  (3114) 0x4ffe3c ADD	X19, X20, X5

  (3114) 0x4ffe40 STR	X19, [X25, X4,LSL #3]

  (3114) 0x4ffe44 LDR	X1, [X18, X4,LSL #3]

  (3114) 0x4ffe48 ADD	X21, X1, X3

  (3114) 0x4ffe4c STR	X21, [X18, X4,LSL #3]

  (3114) 0x4ffe50 ADD	X4, X4, #8

  (3114) 0x4ffe54 LDR	X6, [X25, X15,LSL #3]

  (3114) 0x4ffe58 ADD	X14, X6, X5

  (3114) 0x4ffe5c STR	X14, [X25, X15,LSL #3]

  (3114) 0x4ffe60 LDR	X24, [X18, X15,LSL #3]

  (3114) 0x4ffe64 ADD	X13, X24, X3

  (3114) 0x4ffe68 STR	X13, [X18, X15,LSL #3]

  (3114) 0x4ffe6c LDR	X10, [X25, X23,LSL #3]

  (3114) 0x4ffe70 ADD	X11, X10, X5

  (3114) 0x4ffe74 STR	X11, [X25, X23,LSL #3]

  (3114) 0x4ffe78 LDR	X7, [X18, X23,LSL #3]

  (3114) 0x4ffe7c ADD	X30, X7, X3

  (3114) 0x4ffe80 STR	X30, [X18, X23,LSL #3]

  (3114) 0x4ffe84 LDR	X16, [X25, X28,LSL #3]

  (3114) 0x4ffe88 ADD	X0, X16, X5

  (3114) 0x4ffe8c STR	X0, [X25, X28,LSL #3]

  (3114) 0x4ffe90 LDR	X12, [X18, X28,LSL #3]

  (3114) 0x4ffe94 ADD	X17, X12, X3

  (3114) 0x4ffe98 STR	X17, [X18, X28,LSL #3]

  (3114) 0x4ffe9c LDR	X2, [X25, X26,LSL #3]

  (3114) 0x4ffea0 ADD	X20, X2, X5

  (3114) 0x4ffea4 STR	X20, [X25, X26,LSL #3]

  (3114) 0x4ffea8 LDR	X15, [X18, X26,LSL #3]

  (3114) 0x4ffeac ADD	X28, X15, X3

  (3114) 0x4ffeb0 STR	X28, [X18, X26,LSL #3]

  (3114) 0x4ffeb4 LDR	X23, [X25, X22,LSL #3]

  (3114) 0x4ffeb8 ADD	X26, X23, X5

  (3114) 0x4ffebc STR	X26, [X25, X22,LSL #3]

  (3114) 0x4ffec0 LDR	X19, [X18, X22,LSL #3]

  (3114) 0x4ffec4 ADD	X1, X19, X3

  (3114) 0x4ffec8 STR	X1, [X18, X22,LSL #3]

  (3114) 0x4ffecc LDR	X22, [X25, X8,LSL #3]

  (3114) 0x4ffed0 ADD	X21, X22, X5

  (3114) 0x4ffed4 STR	X21, [X25, X8,LSL #3]

  (3114) 0x4ffed8 LDR	X6, [X18, X8,LSL #3]

  (3114) 0x4ffedc ADD	X14, X6, X3

  (3114) 0x4ffee0 STR	X14, [X18, X8,LSL #3]

  (3114) 0x4ffee4 LDR	X8, [X25, X9,LSL #3]

  (3114) 0x4ffee8 ADD	X24, X8, X5

  (3114) 0x4ffeec STR	X24, [X25, X9,LSL #3]

  (3114) 0x4ffef0 LDR	X13, [X18, X9,LSL #3]

  (3114) 0x4ffef4 ADD	X10, X13, X3

  (3114) 0x4ffef8 STR	X10, [X18, X9,LSL #3]

  (3114) 0x4ffefc CMP	X27, X4

  (3114) 0x4fff00 B.NE	4ffe1c

(3113) 0x4fff04 B	4ff6c4

  (3116) 0x4fff08 LDR	Q18, [X17]

  (3116) 0x4fff0c MOVZ	X22, #16

  (3116) 0x4fff10 ADD	V21.2D, V18.2D, V31.2D

  (3116) 0x4fff14 STR	Q21, [X17]

  (3116) 0x4fff18 LDR	Q1, [X2]

  (3116) 0x4fff1c ADD	V24.2D, V1.2D, V30.2D

  (3116) 0x4fff20 STR	Q24, [X2]

  (3116) 0x4fff24 B	4ffae8

(3113) 0x4fff28 DUP	Z31.B, #0

(3113) 0x4fff2c MOVZ	X13, #0

(3113) 0x4fff30 ORR	Z30.D, Z31.D, Z31.D

(3113) 0x4fff34 B	4ff9c4

0x4fff38 HINT	#0

0x4fff3c HINT	#0

Coverage (%)	Name	Source Location	Module
►99.17+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	par_csr_matop.c:102-276
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:102-127,135-137,144-146,154-156,164-177,187,195,205-208,216-220,228-231,241-276.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 76% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 13.33 to 10.92 cycles (1.22x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 13.33 to 0.50 cycles (26.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 288 bytes. The binary function is storing 232 bytes.

General properties

nb instructions	54
loop length	216
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.92	1.75	1.83	1.83	1.83	1.83	0.00	0.00	0.00	0.00	13.33	13.33	13.33	10.00	10.00
cycles	1.50	1.50	1.92	1.75	1.83	1.83	1.83	1.83	0.00	0.00	0.00	0.00	13.33	13.33	13.33	10.00	10.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.50
Overall L1	13.33

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.33 cycles. At this rate:

22% of peak load performance is reached (21.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
36% of peak store performance is reached (17.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4ff1c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #768]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X1, X2, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STP X2, X1, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X28, X6, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X6, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X3, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X3, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X10, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X9, X27, [X0, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X23, X21, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X9, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X26, [X0, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X8, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X7, X25, [X0, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X7, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X24, X4, [X0, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X12, [X0, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X4, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X5, X11, [X0, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X5, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X11, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X22, X13, [X0, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X13, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X14, X18, [X0, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X19, X20, [X0, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STP X18, X14, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X0, X15, [X0, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X12, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X0, X15, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
BL 5499c0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X2, X18, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
ORR X13, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X3, X8, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MADD X7, X2, X0, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDP X9, X10, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
ADD X12, X2, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X1, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X5, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X6, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X1, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4ff6e0 <hypre_ParMatmul_RowSizes._omp_fn.0+0x520>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X16, X0, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X17, X19, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X4, X0, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X7, X16, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CBNZ X17, 4ff6f0 <hypre_ParMatmul_RowSizes._omp_fn.0+0x530>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	par_csr_matop.c:102-276
Module	exec

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 13.33 to 0.50 cycles (26.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 288 bytes. The binary function is storing 232 bytes.

General properties

nb instructions	54
loop length	216
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.92	1.75	1.83	1.83	1.83	1.83	0.00	0.00	0.00	0.00	13.33	13.33	13.33	10.00	10.00
cycles	1.50	1.50	1.92	1.75	1.83	1.83	1.83	1.83	0.00	0.00	0.00	0.00	13.33	13.33	13.33	10.00	10.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.50
Overall L1	13.33

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.33 cycles. At this rate:

22% of peak load performance is reached (21.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
36% of peak store performance is reached (17.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4ff1c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #768]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X1, X2, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STP X2, X1, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X28, X6, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X6, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X3, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X3, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X10, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X9, X27, [X0, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X23, X21, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X9, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X26, [X0, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X8, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X7, X25, [X0, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X7, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X24, X4, [X0, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X12, [X0, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X4, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X5, X11, [X0, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X5, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X11, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X22, X13, [X0, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X13, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X14, X18, [X0, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X19, X20, [X0, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STP X18, X14, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X0, X15, [X0, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X12, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X0, X15, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
BL 5499c0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X2, X18, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
ORR X13, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X3, X8, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MADD X7, X2, X0, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDP X9, X10, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
ADD X12, X2, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X1, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X5, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X6, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X1, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4ff6e0 <hypre_ParMatmul_RowSizes._omp_fn.0+0x520>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X16, X0, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X17, X19, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X4, X0, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X7, X16, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CBNZ X17, 4ff6f0 <hypre_ParMatmul_RowSizes._omp_fn.0+0x530>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼hypre_ParMatmul_RowSizes._omp_fn.0–	1.06	0.17
▼Loop 3113 - par_csr_matop.c:102-276 - exec–	0.00	0.00
▼Loop 3121 - par_csr_matop.c:127-242 - exec–	0.02	0.01
▼Loop 3125 - par_csr_matop.c:187-231 - exec–	0.36	0.04
○Loop 3128 - par_csr_matop.c:195-208 - exec	0.65	0.08
○Loop 3127 - par_csr_matop.c:218-231 - exec	0.00	0.00
○Loop 3126 - par_csr_matop.c:218-228 - exec	0.00	0.00
▼Loop 3120 - par_csr_matop.c:146-177 - exec–	0.00	0.00
○Loop 3122 - par_csr_matop.c:170-177 - exec	0.00	0.00
○Loop 3123 - par_csr_matop.c:154-167 - exec	0.00	0.00
▼Loop 3124 - par_csr_matop.c:136-146 - exec–	0.00	0.00
○Loop 3119 - par_csr_matop.c:146-146 - exec	0.00	0.00
○Loop 3118 - par_csr_matop.c:273-276 - exec	0.00	0.00
○Loop 3114 - par_csr_matop.c:263-266 - exec	0.00	0.00
▼Loop 3116 - par_csr_matop.c:102-266 - exec–	0.00	0.00
○Loop 3115 - par_csr_matop.c:263-266 - exec	0.04	0.00
○Loop 3117 - par_csr_matop.c:257-260 - exec	0.00	0.00

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Vectorization

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Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

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ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code