OV - exec - Function hypre_ParCSRRelaxThreads._omp

	Function: hypre_ParCSRRelaxThreads._omp_fn.1	Module: exec	Source: ams.c:3662-3682 [...]	Coverage (incl. loops): 51.99% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3662 - 3682

--------------------------------------------------------------------------------

3662: #pragma omp parallel for private(i,ii,jj,res) HYPRE_SMP_SCHEDULE

[...]

3669:          if (A_diag_data[A_diag_i[i]] != zero)

3670:          {

3671:             res = f_data[i];

3672:             for (jj = A_diag_i[i]; jj < A_diag_i[i+1]; jj++)

3673:             {

3674:                ii = A_diag_j[jj];

3675:                res -= A_diag_data[jj] * Vtemp_data[ii];

3676:             }

3677:             for (jj = A_offd_i[i]; jj < A_offd_i[i+1]; jj++)

3678:             {

3679:                ii = A_offd_j[jj];

3680:                res -= A_offd_data[jj] * Vext_data[ii];

3681:             }

3682:             u_data[i] += (relax_weight*res)/l1_norms[i];

0x4ddd20 STP	X29, X30, [SP, #976]!

0x4ddd24 ADD	X29, SP, #0

0x4ddd28 STP	X19, X20, [SP, #16]

0x4ddd2c ORR	X19, XZR, X0

0x4ddd30 STR	X21, [SP, #32]

0x4ddd34 LDR	X21, [X0, #64]

0x4ddd38 BL	410930

0x4ddd3c SBFM	X20, X0, #0, #31

0x4ddd40 BL	410940

0x4ddd44 SBFM	X1, X0, #0, #31

0x4ddd48 SDIV	X8, X21, X20

0x4ddd4c MSUB	X0, X8, X20, X21

0x4ddd50 CMP	X1, X0

0x4ddd54 B.LT	4de1f8

(2686) 0x4ddd58 MADD	X1, X8, X1, X0

(2686) 0x4ddd5c ADD	X8, X8, X1

(2686) 0x4ddd60 CMP	X1, X8

(2686) 0x4ddd64 B.GE	4de1e8

(2686) 0x4ddd68 LDP	X6, X9, [X19, #16]

(2686) 0x4ddd6c PTRUE	P7.B, VL16

(2686) 0x4ddd70 LDP	X12, X14, [X19, #32]

(2686) 0x4ddd74 ADD	X18, X9, #8

(2686) 0x4ddd78 LDP	X10, X11, [X19, #48]

(2686) 0x4ddd7c ADD	X17, X14, #8

(2686) 0x4ddd80 LDP	X13, X15, [X19, #72]

(2686) 0x4ddd84 LDP	X3, X4, [X19, #88]

(2686) 0x4ddd88 LDR	X16, [X19]

(2686) 0x4ddd8c LDR	D30, [X19, #8]

(2686) 0x4ddd90 LDR	D31, [X19, #104]

(2686) 0x4ddd94 B	4ddda4

  (2687) 0x4ddd98 ADD	X1, X1, #1

  (2687) 0x4ddd9c CMP	X8, X1

  (2687) 0x4ddda0 B.EQ	4de1e8

  (2687) 0x4ddda4 LDR	X5, [X9, X1,LSL #3]

  (2687) 0x4ddda8 UBFM	X0, X5, #61, #60

  (2687) 0x4dddac ADD	X30, X6, X5,LSL #3

  (2687) 0x4dddb0 LDR	D6, [X6, X0]

  (2687) 0x4dddb4 FCMP	D31, D6

  (2687) 0x4dddb8 B.EQ	4ddd98

  (2687) 0x4dddbc LDR	X21, [X18, X1,LSL #3]

  (2687) 0x4dddc0 LDR	D0, [X15, X1,LSL #3]

  (2687) 0x4dddc4 CMP	X5, X21

  (2687) 0x4dddc8 B.GE	4ddfc0

  (2687) 0x4dddcc SUB	X20, X21, X5

  (2687) 0x4dddd0 SUB	X2, X20, #1

  (2687) 0x4dddd4 CMP	X2, #3

  (2687) 0x4dddd8 B.LS	4ddf50

  (2687) 0x4ddddc UBFM	X19, X20, #2, #63

  (2687) 0x4ddde0 ADD	X0, X12, X0

  (2687) 0x4ddde4 DUP	Z27.D, #0

  (2687) 0x4ddde8 ORR	Z18.D, Z27.D, Z27.D

  (2687) 0x4dddec UBFM	X7, X19, #59, #58

  (2687) 0x4dddf0 ORR	X2, XZR, X30

  (2687) 0x4dddf4 ADD	X19, X0, X19,LSL #5

  (2687) 0x4dddf8 SUB	X7, X7, #32

  (2687) 0x4dddfc UBFM	X7, X7, #5, #63

  (2687) 0x4dde00 ADD	X7, X7, #1

  (2687) 0x4dde04 ANDS	X7, X7, #4160

  (2687) 0x4dde08 B.EQ	4ddea0

  (2687) 0x4dde0c CMP	X7, #1

  (2687) 0x4dde10 B.EQ	4dde70

  (2687) 0x4dde14 CMP	X7, #2

  (2687) 0x4dde18 B.EQ	4dde48

  (2687) 0x4dde1c LD1D	{Z23.D}, P7/Z, [X0, MUL VL]

  (2687) 0x4dde20 LD1D	{Z4.D}, P7/Z, [X0, #1, MUL VL]

  (2687) 0x4dde24 ADD	X2, X30, #32

  (2687) 0x4dde28 ADD	X0, X0, #32

  (2687) 0x4dde2c LD1D	{Z22.D}, P7/Z, [X3, Z23.D,LSL #3]

  (2687) 0x4dde30 LD1D	{Z5.D}, P7/Z, [X30, MUL VL]

  (2687) 0x4dde34 LD1D	{Z20.D}, P7/Z, [X3, Z4.D,LSL #3]

  (2687) 0x4dde38 MOVPRFX	Z18, Z27

  (2687) 0x4dde3c FMLS	Z18.D, P7/M, Z5.D, Z22.D

  (2687) 0x4dde40 LD1D	{Z24.D}, P7/Z, [X30, #1, MUL VL]

  (2687) 0x4dde44 FMLS	Z27.D, P7/M, Z24.D, Z20.D

  (2687) 0x4dde48 LD1D	{Z2.D}, P7/Z, [X0, MUL VL]

  (2687) 0x4dde4c LD1D	{Z16.D}, P7/Z, [X2, MUL VL]

  (2687) 0x4dde50 LD1D	{Z19.D}, P7/Z, [X0, #1, MUL VL]

  (2687) 0x4dde54 LD1D	{Z3.D}, P7/Z, [X2, #1, MUL VL]

  (2687) 0x4dde58 ADD	X0, X0, #32

  (2687) 0x4dde5c ADD	X2, X2, #32

  (2687) 0x4dde60 LD1D	{Z1.D}, P7/Z, [X3, Z2.D,LSL #3]

  (2687) 0x4dde64 LD1D	{Z17.D}, P7/Z, [X3, Z19.D,LSL #3]

  (2687) 0x4dde68 FMLS	Z18.D, P7/M, Z16.D, Z1.D

  (2687) 0x4dde6c FMLS	Z27.D, P7/M, Z3.D, Z17.D

  (2687) 0x4dde70 LD1D	{Z25.D}, P7/Z, [X0, MUL VL]

  (2687) 0x4dde74 LD1D	{Z21.D}, P7/Z, [X0, #1, MUL VL]

  (2687) 0x4dde78 ADD	X0, X0, #32

  (2687) 0x4dde7c LD1D	{Z7.D}, P7/Z, [X2, MUL VL]

  (2687) 0x4dde80 LD1D	{Z29.D}, P7/Z, [X2, #1, MUL VL]

  (2687) 0x4dde84 LD1D	{Z26.D}, P7/Z, [X3, Z25.D,LSL #3]

  (2687) 0x4dde88 LD1D	{Z28.D}, P7/Z, [X3, Z21.D,LSL #3]

  (2687) 0x4dde8c ADD	X2, X2, #32

  (2687) 0x4dde90 FMLS	Z18.D, P7/M, Z7.D, Z26.D

  (2687) 0x4dde94 FMLS	Z27.D, P7/M, Z29.D, Z28.D

  (2687) 0x4dde98 CMP	X19, X0

  (2687) 0x4dde9c B.EQ	4ddf30

    (2689) 0x4ddea0 LD1D	{Z6.D}, P7/Z, [X2, MUL VL]

    (2689) 0x4ddea4 LD1D	{Z5.D}, P7/Z, [X2, #3, MUL VL]

    (2689) 0x4ddea8 LD1D	{Z23.D}, P7/Z, [X0, MUL VL]

    (2689) 0x4ddeac LD1D	{Z4.D}, P7/Z, [X0, #2, MUL VL]

    (2689) 0x4ddeb0 LD1D	{Z22.D}, P7/Z, [X3, Z23.D,LSL #3]

    (2689) 0x4ddeb4 LD1D	{Z24.D}, P7/Z, [X0, #1, MUL VL]

    (2689) 0x4ddeb8 LD1D	{Z3.D}, P7/Z, [X0, #4, MUL VL]

    (2689) 0x4ddebc LD1D	{Z1.D}, P7/Z, [X0, #3, MUL VL]

    (2689) 0x4ddec0 LD1D	{Z17.D}, P7/Z, [X0, #6, MUL VL]

    (2689) 0x4ddec4 LD1D	{Z21.D}, P7/Z, [X0, #5, MUL VL]

    (2689) 0x4ddec8 LD1D	{Z26.D}, P7/Z, [X0, #7, MUL VL]

    (2689) 0x4ddecc ADD	X0, X0, #128

    (2689) 0x4dded0 FMLS	Z18.D, P7/M, Z6.D, Z22.D

    (2689) 0x4dded4 LD1D	{Z20.D}, P7/Z, [X3, Z4.D,LSL #3]

    (2689) 0x4dded8 LD1D	{Z2.D}, P7/Z, [X2, #2, MUL VL]

    (2689) 0x4ddedc LD1D	{Z16.D}, P7/Z, [X2, #1, MUL VL]

    (2689) 0x4ddee0 LD1D	{Z28.D}, P7/Z, [X2, #4, MUL VL]

    (2689) 0x4ddee4 LD1D	{Z6.D}, P7/Z, [X2, #6, MUL VL]

    (2689) 0x4ddee8 LD1D	{Z22.D}, P7/Z, [X2, #7, MUL VL]

    (2689) 0x4ddeec LD1D	{Z19.D}, P7/Z, [X3, Z24.D,LSL #3]

    (2689) 0x4ddef0 LD1D	{Z25.D}, P7/Z, [X3, Z1.D,LSL #3]

    (2689) 0x4ddef4 FMLS	Z27.D, P7/M, Z16.D, Z19.D

    (2689) 0x4ddef8 FMLS	Z18.D, P7/M, Z2.D, Z20.D

    (2689) 0x4ddefc FMLS	Z27.D, P7/M, Z5.D, Z25.D

    (2689) 0x4ddf00 LD1D	{Z7.D}, P7/Z, [X3, Z3.D,LSL #3]

    (2689) 0x4ddf04 LD1D	{Z5.D}, P7/Z, [X2, #5, MUL VL]

    (2689) 0x4ddf08 LD1D	{Z29.D}, P7/Z, [X3, Z17.D,LSL #3]

    (2689) 0x4ddf0c FMLS	Z18.D, P7/M, Z28.D, Z7.D

    (2689) 0x4ddf10 LD1D	{Z23.D}, P7/Z, [X3, Z21.D,LSL #3]

    (2689) 0x4ddf14 LD1D	{Z4.D}, P7/Z, [X3, Z26.D,LSL #3]

    (2689) 0x4ddf18 FMLS	Z27.D, P7/M, Z5.D, Z23.D

    (2689) 0x4ddf1c ADD	X2, X2, #128

    (2689) 0x4ddf20 FMLS	Z18.D, P7/M, Z6.D, Z29.D

    (2689) 0x4ddf24 FMLS	Z27.D, P7/M, Z22.D, Z4.D

    (2689) 0x4ddf28 CMP	X19, X0

    (2689) 0x4ddf2c B.NE	4ddea0

  (2687) 0x4ddf30 FADD	Z27.D, Z18.D, Z27.D

  (2687) 0x4ddf34 FADDV	D18, P7, Z27.D

  (2687) 0x4ddf38 FADD	D0, D0, D18

  (2687) 0x4ddf3c ANDS	XZR, X20, #4160

  (2687) 0x4ddf40 B.EQ	4ddfc0

  (2687) 0x4ddf44 AND	X30, X20, #8062

  (2687) 0x4ddf48 ADD	X5, X5, X30

  (2687) 0x4ddf4c UBFM	X0, X5, #61, #60

  (2687) 0x4ddf50 LDR	X20, [X12, X0]

  (2687) 0x4ddf54 ADD	X19, X5, #1

  (2687) 0x4ddf58 LDR	D20, [X6, X0]

  (2687) 0x4ddf5c LDR	D2, [X3, X20,LSL #3]

  (2687) 0x4ddf60 FMSUB	D0, D20, D2, D0

  (2687) 0x4ddf64 CMP	X21, X19

  (2687) 0x4ddf68 B.LE	4ddfc0

  (2687) 0x4ddf6c ADD	X2, X0, #8

  (2687) 0x4ddf70 ADD	X7, X5, #2

  (2687) 0x4ddf74 LDR	X30, [X12, X2]

  (2687) 0x4ddf78 LDR	D24, [X6, X2]

  (2687) 0x4ddf7c LDR	D16, [X3, X30,LSL #3]

  (2687) 0x4ddf80 FMSUB	D0, D24, D16, D0

  (2687) 0x4ddf84 CMP	X21, X7

  (2687) 0x4ddf88 B.LE	4ddfc0

  (2687) 0x4ddf8c ADD	X20, X0, #16

  (2687) 0x4ddf90 ADD	X5, X5, #3

  (2687) 0x4ddf94 LDR	X19, [X12, X20]

  (2687) 0x4ddf98 LDR	D19, [X6, X20]

  (2687) 0x4ddf9c LDR	D3, [X3, X19,LSL #3]

  (2687) 0x4ddfa0 FMSUB	D0, D19, D3, D0

  (2687) 0x4ddfa4 CMP	X21, X5

  (2687) 0x4ddfa8 B.LE	4ddfc0

  (2687) 0x4ddfac ADD	X21, X0, #24

  (2687) 0x4ddfb0 LDR	X0, [X12, X21]

  (2687) 0x4ddfb4 LDR	D1, [X6, X21]

  (2687) 0x4ddfb8 LDR	D17, [X3, X0,LSL #3]

  (2687) 0x4ddfbc FMSUB	D0, D17, D1, D0

  (2687) 0x4ddfc0 LDR	X7, [X14, X1,LSL #3]

  (2687) 0x4ddfc4 LDR	X30, [X17, X1,LSL #3]

  (2687) 0x4ddfc8 CMP	X7, X30

  (2687) 0x4ddfcc B.GE	4de1c4

  (2687) 0x4ddfd0 SUB	X20, X30, X7

  (2687) 0x4ddfd4 SUB	X2, X20, #1

  (2687) 0x4ddfd8 CMP	X2, #3

  (2687) 0x4ddfdc B.LS	4de150

  (2687) 0x4ddfe0 UBFM	X19, X20, #2, #63

  (2687) 0x4ddfe4 ADD	X0, X10, X7,LSL #3

  (2687) 0x4ddfe8 DUP	Z25.D, #0

  (2687) 0x4ddfec ORR	Z27.D, Z25.D, Z25.D

  (2687) 0x4ddff0 UBFM	X5, X19, #59, #58

  (2687) 0x4ddff4 ADD	X2, X11, X7,LSL #3

  (2687) 0x4ddff8 SUB	X21, X5, #32

  (2687) 0x4ddffc ADD	X19, X0, X19,LSL #5

  (2687) 0x4de000 UBFM	X5, X21, #5, #63

  (2687) 0x4de004 ADD	X21, X5, #1

  (2687) 0x4de008 ANDS	X5, X21, #4160

  (2687) 0x4de00c B.EQ	4de0a4

  (2687) 0x4de010 CMP	X5, #1

  (2687) 0x4de014 B.EQ	4de074

  (2687) 0x4de018 CMP	X5, #2

  (2687) 0x4de01c B.EQ	4de04c

  (2687) 0x4de020 LD1D	{Z21.D}, P7/Z, [X2, MUL VL]

  (2687) 0x4de024 LD1D	{Z7.D}, P7/Z, [X0, MUL VL]

  (2687) 0x4de028 LD1D	{Z28.D}, P7/Z, [X2, #1, MUL VL]

  (2687) 0x4de02c LD1D	{Z29.D}, P7/Z, [X0, #1, MUL VL]

  (2687) 0x4de030 ADD	X2, X2, #32

  (2687) 0x4de034 ADD	X0, X0, #32

  (2687) 0x4de038 LD1D	{Z6.D}, P7/Z, [X4, Z21.D,LSL #3]

  (2687) 0x4de03c LD1D	{Z26.D}, P7/Z, [X4, Z28.D,LSL #3]

  (2687) 0x4de040 MOVPRFX	Z27, Z25

  (2687) 0x4de044 FMLS	Z27.D, P7/M, Z6.D, Z7.D

  (2687) 0x4de048 FMLS	Z25.D, P7/M, Z26.D, Z29.D

  (2687) 0x4de04c LD1D	{Z23.D}, P7/Z, [X2, MUL VL]

  (2687) 0x4de050 LD1D	{Z5.D}, P7/Z, [X0, MUL VL]

  (2687) 0x4de054 LD1D	{Z4.D}, P7/Z, [X2, #1, MUL VL]

  (2687) 0x4de058 LD1D	{Z22.D}, P7/Z, [X0, #1, MUL VL]

  (2687) 0x4de05c ADD	X2, X2, #32

  (2687) 0x4de060 ADD	X0, X0, #32

  (2687) 0x4de064 LD1D	{Z18.D}, P7/Z, [X4, Z23.D,LSL #3]

  (2687) 0x4de068 LD1D	{Z20.D}, P7/Z, [X4, Z4.D,LSL #3]

  (2687) 0x4de06c FMLS	Z27.D, P7/M, Z18.D, Z5.D

  (2687) 0x4de070 FMLS	Z25.D, P7/M, Z20.D, Z22.D

  (2687) 0x4de074 LD1D	{Z24.D}, P7/Z, [X0, MUL VL]

  (2687) 0x4de078 LD1D	{Z16.D}, P7/Z, [X0, #1, MUL VL]

  (2687) 0x4de07c ADD	X0, X0, #32

  (2687) 0x4de080 LD1D	{Z2.D}, P7/Z, [X2, MUL VL]

  (2687) 0x4de084 LD1D	{Z19.D}, P7/Z, [X2, #1, MUL VL]

  (2687) 0x4de088 LD1D	{Z3.D}, P7/Z, [X4, Z2.D,LSL #3]

  (2687) 0x4de08c LD1D	{Z1.D}, P7/Z, [X4, Z19.D,LSL #3]

  (2687) 0x4de090 ADD	X2, X2, #32

  (2687) 0x4de094 FMLS	Z27.D, P7/M, Z3.D, Z24.D

  (2687) 0x4de098 FMLS	Z25.D, P7/M, Z1.D, Z16.D

  (2687) 0x4de09c CMP	X19, X0

  (2687) 0x4de0a0 B.EQ	4de134

    (2688) 0x4de0a4 LD1D	{Z17.D}, P7/Z, [X2, MUL VL]

    (2688) 0x4de0a8 LD1D	{Z21.D}, P7/Z, [X0, #1, MUL VL]

    (2688) 0x4de0ac LD1D	{Z7.D}, P7/Z, [X4, Z17.D,LSL #3]

    (2688) 0x4de0b0 LD1D	{Z28.D}, P7/Z, [X0, MUL VL]

    (2688) 0x4de0b4 LD1D	{Z5.D}, P7/Z, [X0, #2, MUL VL]

    (2688) 0x4de0b8 LD1D	{Z23.D}, P7/Z, [X0, #4, MUL VL]

    (2688) 0x4de0bc LD1D	{Z24.D}, P7/Z, [X0, #3, MUL VL]

    (2688) 0x4de0c0 LD1D	{Z16.D}, P7/Z, [X0, #5, MUL VL]

    (2688) 0x4de0c4 LD1D	{Z3.D}, P7/Z, [X0, #7, MUL VL]

    (2688) 0x4de0c8 LD1D	{Z26.D}, P7/Z, [X0, #6, MUL VL]

    (2688) 0x4de0cc ADD	X0, X0, #128

    (2688) 0x4de0d0 FMLS	Z27.D, P7/M, Z7.D, Z28.D

    (2688) 0x4de0d4 LD1D	{Z29.D}, P7/Z, [X2, #1, MUL VL]

    (2688) 0x4de0d8 LD1D	{Z4.D}, P7/Z, [X2, #2, MUL VL]

    (2688) 0x4de0dc LD1D	{Z22.D}, P7/Z, [X2, #4, MUL VL]

    (2688) 0x4de0e0 LD1D	{Z2.D}, P7/Z, [X2, #3, MUL VL]

    (2688) 0x4de0e4 LD1D	{Z19.D}, P7/Z, [X2, #6, MUL VL]

    (2688) 0x4de0e8 LD1D	{Z7.D}, P7/Z, [X2, #7, MUL VL]

    (2688) 0x4de0ec LD1D	{Z6.D}, P7/Z, [X4, Z29.D,LSL #3]

    (2688) 0x4de0f0 LD1D	{Z18.D}, P7/Z, [X4, Z4.D,LSL #3]

    (2688) 0x4de0f4 FMLS	Z25.D, P7/M, Z6.D, Z21.D

    (2688) 0x4de0f8 FMLS	Z27.D, P7/M, Z18.D, Z5.D

    (2688) 0x4de0fc LD1D	{Z21.D}, P7/Z, [X2, #5, MUL VL]

    (2688) 0x4de100 LD1D	{Z20.D}, P7/Z, [X4, Z22.D,LSL #3]

    (2688) 0x4de104 LD1D	{Z1.D}, P7/Z, [X4, Z2.D,LSL #3]

    (2688) 0x4de108 FMLS	Z27.D, P7/M, Z20.D, Z23.D

    (2688) 0x4de10c LD1D	{Z17.D}, P7/Z, [X4, Z19.D,LSL #3]

    (2688) 0x4de110 FMLS	Z25.D, P7/M, Z1.D, Z24.D

    (2688) 0x4de114 LD1D	{Z28.D}, P7/Z, [X4, Z21.D,LSL #3]

    (2688) 0x4de118 LD1D	{Z5.D}, P7/Z, [X4, Z7.D,LSL #3]

    (2688) 0x4de11c FMLS	Z25.D, P7/M, Z28.D, Z16.D

    (2688) 0x4de120 ADD	X2, X2, #128

    (2688) 0x4de124 FMLS	Z27.D, P7/M, Z17.D, Z26.D

    (2688) 0x4de128 FMLS	Z25.D, P7/M, Z5.D, Z3.D

    (2688) 0x4de12c CMP	X19, X0

    (2688) 0x4de130 B.NE	4de0a4

  (2687) 0x4de134 FADD	Z25.D, Z25.D, Z27.D

  (2687) 0x4de138 FADDV	D27, P7, Z25.D

  (2687) 0x4de13c FADD	D0, D0, D27

  (2687) 0x4de140 ANDS	XZR, X20, #4160

  (2687) 0x4de144 B.EQ	4de1c4

  (2687) 0x4de148 AND	X20, X20, #8062

  (2687) 0x4de14c ADD	X7, X7, X20

  (2687) 0x4de150 UBFM	X21, X7, #61, #60

  (2687) 0x4de154 ADD	X19, X7, #1

  (2687) 0x4de158 LDR	X5, [X11, X21]

  (2687) 0x4de15c LDR	D23, [X10, X21]

  (2687) 0x4de160 LDR	D29, [X4, X5,LSL #3]

  (2687) 0x4de164 FMSUB	D0, D23, D29, D0

  (2687) 0x4de168 CMP	X19, X30

  (2687) 0x4de16c B.GE	4de1c4

  (2687) 0x4de170 ADD	X0, X21, #8

  (2687) 0x4de174 ADD	X2, X7, #2

  (2687) 0x4de178 LDR	X20, [X11, X0]

  (2687) 0x4de17c LDR	D24, [X10, X0]

  (2687) 0x4de180 LDR	D6, [X4, X20,LSL #3]

  (2687) 0x4de184 FMSUB	D0, D24, D6, D0

  (2687) 0x4de188 CMP	X2, X30

  (2687) 0x4de18c B.GE	4de1c4

  (2687) 0x4de190 ADD	X19, X21, #16

  (2687) 0x4de194 ADD	X7, X7, #3

  (2687) 0x4de198 LDR	X5, [X11, X19]

  (2687) 0x4de19c LDR	D16, [X10, X19]

  (2687) 0x4de1a0 LDR	D3, [X4, X5,LSL #3]

  (2687) 0x4de1a4 FMSUB	D0, D3, D16, D0

  (2687) 0x4de1a8 CMP	X30, X7

  (2687) 0x4de1ac B.LE	4de1c4

  (2687) 0x4de1b0 ADD	X30, X21, #24

  (2687) 0x4de1b4 LDR	X21, [X11, X30]

  (2687) 0x4de1b8 LDR	D26, [X10, X30]

  (2687) 0x4de1bc LDR	D4, [X4, X21,LSL #3]

  (2687) 0x4de1c0 FMSUB	D0, D4, D26, D0

  (2687) 0x4de1c4 LDR	D22, [X16, X1,LSL #3]

  (2687) 0x4de1c8 FMUL	D0, D30, D0

  (2687) 0x4de1cc LDR	D18, [X13, X1,LSL #3]

  (2687) 0x4de1d0 FDIV	D20, D0, D22

  (2687) 0x4de1d4 FADD	D2, D18, D20

  (2687) 0x4de1d8 STR	D2, [X13, X1,LSL #3]

  (2687) 0x4de1dc ADD	X1, X1, #1

  (2687) 0x4de1e0 CMP	X8, X1

  (2687) 0x4de1e4 B.NE	4ddda4

(2686) 0x4de1e8 LDR	X21, [SP, #32]

(2686) 0x4de1ec LDP	X19, X20, [SP, #16]

(2686) 0x4de1f0 LDP	X29, X30, [SP], #48

(2686) 0x4de1f4 RET

(2686) 0x4de1f8 ADD	X8, X8, #1

(2686) 0x4de1fc MOVZ	X0, #0

(2686) 0x4de200 B	4ddd58

Coverage (%)	Name	Source Location	Module
►99.03+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	ams.c:3662-3682
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662,3669-3682.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 68% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 20.00 to 10.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	14
loop length	56
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.75
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4ddd20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X21, [X0, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 410930 <@plt_start@+0x1b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X20, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (100.0%)
BL 410940 <@plt_start@+0x1c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X1, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SDIV X8, X21, X20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
MSUB X0, X8, X20, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP X1, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.LT 4de1f8 <hypre_ParCSRRelaxThreads._omp_fn.1+0x4d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	ams.c:3662-3682
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662,3669-3682.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	14
loop length	56
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.75
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4ddd20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X21, [X0, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 410930 <@plt_start@+0x1b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X20, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (100.0%)
BL 410940 <@plt_start@+0x1c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X1, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SDIV X8, X21, X20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
MSUB X0, X8, X20, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP X1, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.LT 4de1f8 <hypre_ParCSRRelaxThreads._omp_fn.1+0x4d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼hypre_ParCSRRelaxThreads._omp_fn.1–	51.99	8.36
▼Loop 2686 - ams.c:3662-3682 - exec–	0.00	0.00
▼Loop 2687 - ams.c:3662-3682 - exec–	23.47	2.91
○Loop 2689 - ams.c:3672-3675 - exec	28.52	3.54
○Loop 2688 - ams.c:3677-3680 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code