OV - exec - Function hypre_ParCSRRelaxThreads._omp

	Function: hypre_ParCSRRelaxThreads._omp_fn.0	Module: exec	Source: ams.c:3655-3659	Coverage (incl. loops): 1.71% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3655 - 3659

--------------------------------------------------------------------------------

3655: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

3656: #endif

3657:       for (i = 0; i < n; i++)

3658:       {

3659:          Vtemp_data[i] = u_data[i];

0x4dd988 STP	X29, X30, [SP, #976]!

0x4dd98c ADD	X29, SP, #0

0x4dd990 STP	X19, X20, [SP, #16]

0x4dd994 ORR	X20, XZR, X0

0x4dd998 STR	X21, [SP, #32]

0x4dd99c LDR	X21, [X0]

0x4dd9a0 BL	410930

0x4dd9a4 SBFM	X19, X0, #0, #31

0x4dd9a8 BL	410940

0x4dd9ac SBFM	X1, X0, #0, #31

0x4dd9b0 SDIV	X4, X21, X19

0x4dd9b4 MSUB	X2, X4, X19, X21

0x4dd9b8 CMP	X1, X2

0x4dd9bc B.LT	4ddbcc

(2683) 0x4dd9c0 MADD	X1, X4, X1, X2

(2683) 0x4dd9c4 ADD	X5, X4, X1

(2683) 0x4dd9c8 CMP	X1, X5

(2683) 0x4dd9cc B.GE	4ddbbc

(2683) 0x4dd9d0 LDP	X9, X8, [X20, #8]

(2683) 0x4dd9d4 CMP	X4, #1

(2683) 0x4dd9d8 B.EQ	4ddbf0

(2683) 0x4dd9dc UBFM	X6, X1, #61, #60

(2683) 0x4dd9e0 ADD	X3, X8, X1,LSL #3

(2683) 0x4dd9e4 ADD	X0, X6, #8

(2683) 0x4dd9e8 ADD	X7, X9, X0

(2683) 0x4dd9ec SUB	X10, X3, X7

(2683) 0x4dd9f0 CMP	X10, #16

(2683) 0x4dd9f4 B.LS	4ddbf0

(2683) 0x4dd9f8 SUB	X11, X4, #1

(2683) 0x4dd9fc CMP	X11, #2

(2683) 0x4dda00 B.LS	4ddd0c

(2683) 0x4dda04 UBFM	X13, X4, #2, #63

(2683) 0x4dda08 ADD	X17, X9, X6

(2683) 0x4dda0c UBFM	X18, X13, #59, #58

(2683) 0x4dda10 MOVZ	X19, #0

(2683) 0x4dda14 SUB	X14, X18, #32

(2683) 0x4dda18 ADD	X30, X17, #16

(2683) 0x4dda1c UBFM	X15, X14, #5, #63

(2683) 0x4dda20 ADD	X20, X3, #16

(2683) 0x4dda24 ADD	X16, X15, #1

(2683) 0x4dda28 ANDS	X21, X16, #4224

(2683) 0x4dda2c B.EQ	4ddae0

(2683) 0x4dda30 CMP	X21, #1

(2683) 0x4dda34 B.EQ	4ddac4

(2683) 0x4dda38 CMP	X21, #2

(2683) 0x4dda3c B.EQ	4ddab0

(2683) 0x4dda40 CMP	X21, #3

(2683) 0x4dda44 B.EQ	4dda9c

(2683) 0x4dda48 CMP	X21, #4

(2683) 0x4dda4c B.EQ	4dda88

(2683) 0x4dda50 CMP	X21, #5

(2683) 0x4dda54 B.EQ	4dda74

(2683) 0x4dda58 CMP	X21, #6

(2683) 0x4dda5c B.NE	4ddcf4

(2683) 0x4dda60 LDR	Q1, [X17, X19]

(2683) 0x4dda64 LDR	Q0, [X30, X19]

(2683) 0x4dda68 STR	Q1, [X3, X19]

(2683) 0x4dda6c STR	Q0, [X20, X19]

(2683) 0x4dda70 ADD	X19, X19, #32

(2683) 0x4dda74 LDR	Q3, [X17, X19]

(2683) 0x4dda78 LDR	Q2, [X30, X19]

(2683) 0x4dda7c STR	Q3, [X3, X19]

(2683) 0x4dda80 STR	Q2, [X20, X19]

(2683) 0x4dda84 ADD	X19, X19, #32

(2683) 0x4dda88 LDR	Q5, [X17, X19]

(2683) 0x4dda8c LDR	Q4, [X30, X19]

(2683) 0x4dda90 STR	Q5, [X3, X19]

(2683) 0x4dda94 STR	Q4, [X20, X19]

(2683) 0x4dda98 ADD	X19, X19, #32

(2683) 0x4dda9c LDR	Q7, [X17, X19]

(2683) 0x4ddaa0 LDR	Q6, [X30, X19]

(2683) 0x4ddaa4 STR	Q7, [X3, X19]

(2683) 0x4ddaa8 STR	Q6, [X20, X19]

(2683) 0x4ddaac ADD	X19, X19, #32

(2683) 0x4ddab0 LDR	Q17, [X17, X19]

(2683) 0x4ddab4 LDR	Q16, [X30, X19]

(2683) 0x4ddab8 STR	Q17, [X3, X19]

(2683) 0x4ddabc STR	Q16, [X20, X19]

(2683) 0x4ddac0 ADD	X19, X19, #32

(2683) 0x4ddac4 LDR	Q19, [X17, X19]

(2683) 0x4ddac8 LDR	Q18, [X30, X19]

(2683) 0x4ddacc STR	Q19, [X3, X19]

(2683) 0x4ddad0 STR	Q18, [X20, X19]

(2683) 0x4ddad4 ADD	X19, X19, #32

(2683) 0x4ddad8 CMP	X19, X18

(2683) 0x4ddadc B.EQ	4ddb88

  (2685) 0x4ddae0 LDR	Q21, [X17, X19]

  (2685) 0x4ddae4 ADD	X2, X19, #32

  (2685) 0x4ddae8 ADD	X6, X19, #64

  (2685) 0x4ddaec ADD	X5, X19, #96

  (2685) 0x4ddaf0 ADD	X0, X19, #128

  (2685) 0x4ddaf4 LDR	Q20, [X30, X19]

  (2685) 0x4ddaf8 ADD	X7, X19, #160

  (2685) 0x4ddafc ADD	X10, X19, #192

  (2685) 0x4ddb00 ADD	X11, X19, #224

  (2685) 0x4ddb04 STR	Q21, [X3, X19]

  (2685) 0x4ddb08 STR	Q20, [X20, X19]

  (2685) 0x4ddb0c ADD	X19, X19, #256

  (2685) 0x4ddb10 LDR	Q23, [X17, X2]

  (2685) 0x4ddb14 LDR	Q22, [X30, X2]

  (2685) 0x4ddb18 STR	Q23, [X3, X2]

  (2685) 0x4ddb1c STR	Q22, [X20, X2]

  (2685) 0x4ddb20 LDR	Q25, [X17, X6]

  (2685) 0x4ddb24 LDR	Q24, [X30, X6]

  (2685) 0x4ddb28 STR	Q25, [X3, X6]

  (2685) 0x4ddb2c STR	Q24, [X20, X6]

  (2685) 0x4ddb30 LDR	Q27, [X17, X5]

  (2685) 0x4ddb34 LDR	Q26, [X30, X5]

  (2685) 0x4ddb38 STR	Q27, [X3, X5]

  (2685) 0x4ddb3c STR	Q26, [X20, X5]

  (2685) 0x4ddb40 LDR	Q29, [X17, X0]

  (2685) 0x4ddb44 LDR	Q28, [X30, X0]

  (2685) 0x4ddb48 STR	Q29, [X3, X0]

  (2685) 0x4ddb4c STR	Q28, [X20, X0]

  (2685) 0x4ddb50 LDR	Q30, [X17, X7]

  (2685) 0x4ddb54 LDR	Q31, [X30, X7]

  (2685) 0x4ddb58 STR	Q30, [X3, X7]

  (2685) 0x4ddb5c STR	Q31, [X20, X7]

  (2685) 0x4ddb60 LDR	Q1, [X17, X10]

  (2685) 0x4ddb64 LDR	Q0, [X30, X10]

  (2685) 0x4ddb68 STR	Q1, [X3, X10]

  (2685) 0x4ddb6c STR	Q0, [X20, X10]

  (2685) 0x4ddb70 LDR	Q3, [X17, X11]

  (2685) 0x4ddb74 LDR	Q2, [X30, X11]

  (2685) 0x4ddb78 STR	Q3, [X3, X11]

  (2685) 0x4ddb7c STR	Q2, [X20, X11]

  (2685) 0x4ddb80 CMP	X19, X18

  (2685) 0x4ddb84 B.NE	4ddae0

(2683) 0x4ddb88 AND	X12, X4, #8062

(2683) 0x4ddb8c CMP	X4, X12

(2683) 0x4ddb90 B.EQ	4ddbbc

(2683) 0x4ddb94 ADD	X1, X1, X12

(2683) 0x4ddb98 SUB	X4, X4, X12

(2683) 0x4ddb9c WHILELO	P7.D, XZR, X4

(2683) 0x4ddba0 LD1D	{Z4.D}, P7/Z, [X9, X1,LSL #3]

(2683) 0x4ddba4 ADD	X8, X8, X1,LSL #3

(2683) 0x4ddba8 ST1D	{Z4.D}, P7, [X8, MUL VL]

(2683) 0x4ddbac MOVZ	X3, #2

(2683) 0x4ddbb0 WHILELO	P0.D, X3, X4

(2683) 0x4ddbb4 ADD	X9, X9, X1,LSL #3

(2683) 0x4ddbb8 B.NE	4ddbd8

(2683) 0x4ddbbc LDR	X21, [SP, #32]

(2683) 0x4ddbc0 LDP	X19, X20, [SP, #16]

(2683) 0x4ddbc4 LDP	X29, X30, [SP], #48

(2683) 0x4ddbc8 RET

(2683) 0x4ddbcc ADD	X4, X4, #1

(2683) 0x4ddbd0 MOVZ	X2, #0

(2683) 0x4ddbd4 B	4dd9c0

(2683) 0x4ddbd8 LDR	X21, [SP, #32]

(2683) 0x4ddbdc LD1D	{Z5.D}, P0/Z, [X9, #1, MUL VL]

(2683) 0x4ddbe0 ST1D	{Z5.D}, P0, [X8, #1, MUL VL]

(2683) 0x4ddbe4 LDP	X19, X20, [SP, #16]

(2683) 0x4ddbe8 LDP	X29, X30, [SP], #48

(2683) 0x4ddbec RET

(2683) 0x4ddbf0 SUB	X12, X5, X1

(2683) 0x4ddbf4 ANDS	X13, X12, #4224

(2683) 0x4ddbf8 B.EQ	4ddc88

(2683) 0x4ddbfc CMP	X13, #1

(2683) 0x4ddc00 B.EQ	4ddc74

(2683) 0x4ddc04 CMP	X13, #2

(2683) 0x4ddc08 B.EQ	4ddc68

(2683) 0x4ddc0c CMP	X13, #3

(2683) 0x4ddc10 B.EQ	4ddc5c

(2683) 0x4ddc14 CMP	X13, #4

(2683) 0x4ddc18 B.EQ	4ddc50

(2683) 0x4ddc1c CMP	X13, #5

(2683) 0x4ddc20 B.EQ	4ddc44

(2683) 0x4ddc24 CMP	X13, #6

(2683) 0x4ddc28 B.EQ	4ddc38

(2683) 0x4ddc2c LDR	D6, [X9, X1,LSL #3]

(2683) 0x4ddc30 STR	D6, [X8, X1,LSL #3]

(2683) 0x4ddc34 ADD	X1, X1, #1

(2683) 0x4ddc38 LDR	D7, [X9, X1,LSL #3]

(2683) 0x4ddc3c STR	D7, [X8, X1,LSL #3]

(2683) 0x4ddc40 ADD	X1, X1, #1

(2683) 0x4ddc44 LDR	D16, [X9, X1,LSL #3]

(2683) 0x4ddc48 STR	D16, [X8, X1,LSL #3]

(2683) 0x4ddc4c ADD	X1, X1, #1

(2683) 0x4ddc50 LDR	D17, [X9, X1,LSL #3]

(2683) 0x4ddc54 STR	D17, [X8, X1,LSL #3]

(2683) 0x4ddc58 ADD	X1, X1, #1

(2683) 0x4ddc5c LDR	D18, [X9, X1,LSL #3]

(2683) 0x4ddc60 STR	D18, [X8, X1,LSL #3]

(2683) 0x4ddc64 ADD	X1, X1, #1

(2683) 0x4ddc68 LDR	D19, [X9, X1,LSL #3]

(2683) 0x4ddc6c STR	D19, [X8, X1,LSL #3]

(2683) 0x4ddc70 ADD	X1, X1, #1

(2683) 0x4ddc74 LDR	D20, [X9, X1,LSL #3]

(2683) 0x4ddc78 STR	D20, [X8, X1,LSL #3]

(2683) 0x4ddc7c ADD	X1, X1, #1

(2683) 0x4ddc80 CMP	X5, X1

(2683) 0x4ddc84 B.EQ	4ddbbc

  (2684) 0x4ddc88 LDR	D21, [X9, X1,LSL #3]

  (2684) 0x4ddc8c ADD	X17, X1, #1

  (2684) 0x4ddc90 ADD	X30, X1, #2

  (2684) 0x4ddc94 ADD	X18, X1, #3

  (2684) 0x4ddc98 ADD	X14, X1, #4

  (2684) 0x4ddc9c ADD	X20, X1, #5

  (2684) 0x4ddca0 ADD	X15, X1, #6

  (2684) 0x4ddca4 ADD	X16, X1, #7

  (2684) 0x4ddca8 STR	D21, [X8, X1,LSL #3]

  (2684) 0x4ddcac ADD	X1, X1, #8

  (2684) 0x4ddcb0 LDR	D22, [X9, X17,LSL #3]

  (2684) 0x4ddcb4 STR	D22, [X8, X17,LSL #3]

  (2684) 0x4ddcb8 LDR	D23, [X9, X30,LSL #3]

  (2684) 0x4ddcbc STR	D23, [X8, X30,LSL #3]

  (2684) 0x4ddcc0 LDR	D24, [X9, X18,LSL #3]

  (2684) 0x4ddcc4 STR	D24, [X8, X18,LSL #3]

  (2684) 0x4ddcc8 LDR	D25, [X9, X14,LSL #3]

  (2684) 0x4ddccc STR	D25, [X8, X14,LSL #3]

  (2684) 0x4ddcd0 LDR	D26, [X9, X20,LSL #3]

  (2684) 0x4ddcd4 STR	D26, [X8, X20,LSL #3]

  (2684) 0x4ddcd8 LDR	D27, [X9, X15,LSL #3]

  (2684) 0x4ddcdc STR	D27, [X8, X15,LSL #3]

  (2684) 0x4ddce0 LDR	D28, [X9, X16,LSL #3]

  (2684) 0x4ddce4 STR	D28, [X8, X16,LSL #3]

  (2684) 0x4ddce8 CMP	X5, X1

  (2684) 0x4ddcec B.NE	4ddc88

(2683) 0x4ddcf0 B	4ddbbc

(2683) 0x4ddcf4 LDR	Q30, [X17]

(2683) 0x4ddcf8 MOVZ	X19, #32

(2683) 0x4ddcfc LDR	Q31, [X30]

(2683) 0x4ddd00 STR	Q30, [X3]

(2683) 0x4ddd04 STR	Q31, [X20]

(2683) 0x4ddd08 B	4dda60

(2683) 0x4ddd0c MOVZ	X12, #0

(2683) 0x4ddd10 B	4ddb94

0x4ddd14 HINT	#0

0x4ddd18 HINT	#0

0x4ddd1c HINT	#0

Coverage (%)	Name	Source Location	Module
►98.60+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.38+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	hypre_ParCSRRelaxThreads	ams.c:3662	exec
○	hypre_BoomerAMGCycle	par_cycle.c:394	exec
○	hypre_BoomerAMGSolve	par_amg_solve.c:235	exec
○	hypre_PCGSolve	pcg.c:545	exec
○	main	amg.c:419	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	ams.c:3655-3659
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3655-3659.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 68% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 20.00 to 10.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	17
loop length	68
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.75
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4dd988

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X21, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 410930 <@plt_start@+0x1b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X19, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
BL 410940 <@plt_start@+0x1c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X1, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SDIV X4, X21, X19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
MSUB X2, X4, X19, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP X1, X2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 4ddbcc <hypre_ParCSRRelaxThreads._omp_fn.0+0x244>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	ams.c:3655-3659
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3655-3659.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	17
loop length	68
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.75
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4dd988

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X21, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 410930 <@plt_start@+0x1b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X19, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
BL 410940 <@plt_start@+0x1c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X1, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SDIV X4, X21, X19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
MSUB X2, X4, X19, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP X1, X2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 4ddbcc <hypre_ParCSRRelaxThreads._omp_fn.0+0x244>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼hypre_ParCSRRelaxThreads._omp_fn.0–	1.71	0.27
▼Loop 2683 - ams.c:3655-3659 - exec–	0.00	0.00
○Loop 2685 - ams.c:3659-3659 - exec	1.70	0.21
○Loop 2684 - ams.c:3659-3659 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code