OV - exec - Function hypre_BoomerAMGCreate2ndS._omp

	Function: hypre_BoomerAMGCreate2ndS._omp_fn.0	Module: exec	Source: par_strength.c:1253-1278	Coverage (incl. loops): 0.01% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 1253 - 1278

--------------------------------------------------------------------------------

1253: #pragma omp parallel private(i)

1254: #endif

1255:    {

1256:       HYPRE_Int num_coarse_private = 0;

1257:

1258:       HYPRE_Int i_begin, i_end;

1259:       hypre_GetSimpleThreadPartition(&i_begin, &i_end, num_cols_diag_S);

1260:

1261:       for (i = i_begin; i < i_end; i++)

1262:       {

1263:          if (CF_marker[i] > 0) num_coarse_private++;

1264:       }

1265:

1266:       hypre_prefix_sum(&num_coarse_private, &num_coarse, num_coarse_prefix_sum);

1267:

1268:       for (i = i_begin; i < i_end; i++)

1269:       {

1270:          if (CF_marker[i] > 0)

1271:          {

1272:             fine_to_coarse[i] = num_coarse_private;

1273:             coarse_to_fine[num_coarse_private] = i;

1274:             num_coarse_private++;

1275:          }

1276:          else

1277:          {

1278:             fine_to_coarse[i] = -1;

0x4c99c0 STP	X29, X30, [SP, #928]!

0x4c99c4 ADD	X29, SP, #0

0x4c99c8 ADD	X1, SP, #88

0x4c99cc STP	X21, X22, [SP, #32]

0x4c99d0 ORR	X22, XZR, X0

0x4c99d4 ADD	X0, SP, #80

0x4c99d8 STP	X19, X20, [SP, #16]

0x4c99dc LDR	X21, [X22, #16]

0x4c99e0 STR	X23, [SP, #48]

0x4c99e4 STR	XZR, [SP, #72]

0x4c99e8 LDP	X19, X2, [X22]

0x4c99ec LDP	X20, X23, [X22, #32]

0x4c99f0 BL	5499e0

0x4c99f4 LDP	X1, X4, [SP, #80]

0x4c99f8 CMP	X1, X4

0x4c99fc B.GE	4c9bc0

0x4c9a00 ADD	X18, X19, X1,LSL #3

0x4c9a04 MOVZ	W0, #0

0x4c9a08 ADD	X5, X19, X4,LSL #3

0x4c9a0c SUB	X3, X5, X18

0x4c9a10 SUB	X2, X3, #8

0x4c9a14 UBFM	X6, X2, #3, #63

0x4c9a18 LDR	X2, [SP, #72]

0x4c9a1c ADD	X7, X6, #1

0x4c9a20 ANDS	X8, X7, #4224

0x4c9a24 B.EQ	4c9b08

0x4c9a28 CMP	X8, #1

0x4c9a2c B.EQ	4c9ae8

0x4c9a30 CMP	X8, #2

0x4c9a34 B.EQ	4c9ad0

0x4c9a38 CMP	X8, #3

0x4c9a3c B.EQ	4c9ab8

0x4c9a40 CMP	X8, #4

0x4c9a44 B.EQ	4c9aa0

0x4c9a48 CMP	X8, #5

0x4c9a4c B.EQ	4c9a88

0x4c9a50 CMP	X8, #6

0x4c9a54 B.EQ	4c9a70

0x4c9a58 LDR	X9, [X18]

0x4c9a5c CMP	X9, #0

0x4c9a60 B.LE	4c9a6c

0x4c9a64 ADD	X2, X2, #1

0x4c9a68 MOVZ	W0, #1

0x4c9a6c ADD	X18, X18, #8

0x4c9a70 LDR	X10, [X18]

0x4c9a74 CMP	X10, #0

0x4c9a78 B.LE	4c9a84

0x4c9a7c ADD	X2, X2, #1

0x4c9a80 MOVZ	W0, #1

0x4c9a84 ADD	X18, X18, #8

0x4c9a88 LDR	X11, [X18]

0x4c9a8c CMP	X11, #0

0x4c9a90 B.LE	4c9a9c

0x4c9a94 ADD	X2, X2, #1

0x4c9a98 MOVZ	W0, #1

0x4c9a9c ADD	X18, X18, #8

0x4c9aa0 LDR	X12, [X18]

0x4c9aa4 CMP	X12, #0

0x4c9aa8 B.LE	4c9ab4

0x4c9aac ADD	X2, X2, #1

0x4c9ab0 MOVZ	W0, #1

0x4c9ab4 ADD	X18, X18, #8

0x4c9ab8 LDR	X13, [X18]

0x4c9abc CMP	X13, #0

0x4c9ac0 B.LE	4c9acc

0x4c9ac4 ADD	X2, X2, #1

0x4c9ac8 MOVZ	W0, #1

0x4c9acc ADD	X18, X18, #8

0x4c9ad0 LDR	X14, [X18]

0x4c9ad4 CMP	X14, #0

0x4c9ad8 B.LE	4c9ae4

0x4c9adc ADD	X2, X2, #1

0x4c9ae0 MOVZ	W0, #1

0x4c9ae4 ADD	X18, X18, #8

0x4c9ae8 LDR	X15, [X18]

0x4c9aec CMP	X15, #0

0x4c9af0 B.LE	4c9afc

0x4c9af4 ADD	X2, X2, #1

0x4c9af8 MOVZ	W0, #1

0x4c9afc ADD	X18, X18, #8

0x4c9b00 CMP	X18, X5

0x4c9b04 B.EQ	4c9bb8

(2436) 0x4c9b08 LDR	X16, [X18]

(2436) 0x4c9b0c CMP	X16, #0

(2436) 0x4c9b10 B.LE	4c9b1c

(2436) 0x4c9b14 ADD	X2, X2, #1

(2436) 0x4c9b18 MOVZ	W0, #1

(2436) 0x4c9b1c LDR	X17, [X18, #8]

(2436) 0x4c9b20 ADD	X18, X18, #8

(2436) 0x4c9b24 CMP	X17, #0

(2436) 0x4c9b28 B.LE	4c9b34

(2436) 0x4c9b2c ADD	X2, X2, #1

(2436) 0x4c9b30 MOVZ	W0, #1

(2436) 0x4c9b34 LDR	X30, [X18, #8]

(2436) 0x4c9b38 CMP	X30, #0

(2436) 0x4c9b3c B.LE	4c9b48

(2436) 0x4c9b40 ADD	X2, X2, #1

(2436) 0x4c9b44 MOVZ	W0, #1

(2436) 0x4c9b48 LDR	X1, [X18, #16]

(2436) 0x4c9b4c CMP	X1, #0

(2436) 0x4c9b50 B.LE	4c9b5c

(2436) 0x4c9b54 ADD	X2, X2, #1

(2436) 0x4c9b58 MOVZ	W0, #1

(2436) 0x4c9b5c LDR	X4, [X18, #24]

(2436) 0x4c9b60 CMP	X4, #0

(2436) 0x4c9b64 B.LE	4c9b70

(2436) 0x4c9b68 ADD	X2, X2, #1

(2436) 0x4c9b6c MOVZ	W0, #1

(2436) 0x4c9b70 LDR	X3, [X18, #32]

(2436) 0x4c9b74 CMP	X3, #0

(2436) 0x4c9b78 B.LE	4c9b84

(2436) 0x4c9b7c ADD	X2, X2, #1

(2436) 0x4c9b80 MOVZ	W0, #1

(2436) 0x4c9b84 LDR	X6, [X18, #40]

(2436) 0x4c9b88 CMP	X6, #0

(2436) 0x4c9b8c B.LE	4c9b98

(2436) 0x4c9b90 ADD	X2, X2, #1

(2436) 0x4c9b94 MOVZ	W0, #1

(2436) 0x4c9b98 LDR	X7, [X18, #48]

(2436) 0x4c9b9c CMP	X7, #0

(2436) 0x4c9ba0 B.LE	4c9bac

(2436) 0x4c9ba4 ADD	X2, X2, #1

(2436) 0x4c9ba8 MOVZ	W0, #1

(2436) 0x4c9bac ADD	X18, X18, #56

(2436) 0x4c9bb0 CMP	X18, X5

(2436) 0x4c9bb4 B.NE	4c9b08

0x4c9bb8 CBZ	W0, 4c9bc0

0x4c9bbc STR	X2, [SP, #72]

0x4c9bc0 LDR	X1, [X22, #24]

0x4c9bc4 ORR	X2, XZR, X20

0x4c9bc8 ADD	X0, SP, #72

0x4c9bcc BL	54a980

0x4c9bd0 LDP	X4, X8, [SP, #80]

0x4c9bd4 CMP	X4, X8

0x4c9bd8 B.GE	4c9cec

0x4c9bdc SUB	X5, X8, X4

0x4c9be0 LDR	X1, [SP, #72]

0x4c9be4 MOVN	X9, #0

0x4c9be8 ANDS	X10, X5, #4224

0x4c9bec B.EQ	4c9ddc

0x4c9bf0 CMP	X10, #1

0x4c9bf4 B.EQ	4c9cc8

0x4c9bf8 CMP	X10, #2

0x4c9bfc B.EQ	4c9cac

0x4c9c00 CMP	X10, #3

0x4c9c04 B.EQ	4c9c90

0x4c9c08 CMP	X10, #4

0x4c9c0c B.EQ	4c9c74

0x4c9c10 CMP	X10, #5

0x4c9c14 B.EQ	4c9c58

0x4c9c18 CMP	X10, #6

0x4c9c1c B.EQ	4c9c3c

0x4c9c20 LDR	X11, [X19, X4,LSL #3]

0x4c9c24 CMP	X11, #0

0x4c9c28 B.LE	4c9ec0

0x4c9c2c STR	X1, [X21, X4,LSL #3]

0x4c9c30 STR	X4, [X23, X1,LSL #3]

0x4c9c34 ADD	X1, X1, #1

0x4c9c38 ADD	X4, X4, #1

0x4c9c3c LDR	X12, [X19, X4,LSL #3]

0x4c9c40 CMP	X12, #0

0x4c9c44 B.LE	4c9ea8

0x4c9c48 STR	X1, [X21, X4,LSL #3]

0x4c9c4c STR	X4, [X23, X1,LSL #3]

0x4c9c50 ADD	X1, X1, #1

0x4c9c54 ADD	X4, X4, #1

0x4c9c58 LDR	X13, [X19, X4,LSL #3]

0x4c9c5c CMP	X13, #0

0x4c9c60 B.LE	4c9e9c

0x4c9c64 STR	X1, [X21, X4,LSL #3]

0x4c9c68 STR	X4, [X23, X1,LSL #3]

0x4c9c6c ADD	X1, X1, #1

0x4c9c70 ADD	X4, X4, #1

0x4c9c74 LDR	X14, [X19, X4,LSL #3]

0x4c9c78 CMP	X14, #0

0x4c9c7c B.LE	4c9eb4

0x4c9c80 STR	X1, [X21, X4,LSL #3]

0x4c9c84 STR	X4, [X23, X1,LSL #3]

0x4c9c88 ADD	X1, X1, #1

0x4c9c8c ADD	X4, X4, #1

0x4c9c90 LDR	X15, [X19, X4,LSL #3]

0x4c9c94 CMP	X15, #0

0x4c9c98 B.LE	4c9e90

0x4c9c9c STR	X1, [X21, X4,LSL #3]

0x4c9ca0 STR	X4, [X23, X1,LSL #3]

0x4c9ca4 ADD	X1, X1, #1

0x4c9ca8 ADD	X4, X4, #1

0x4c9cac LDR	X16, [X19, X4,LSL #3]

0x4c9cb0 CMP	X16, #0

0x4c9cb4 B.LE	4c9e84

0x4c9cb8 STR	X1, [X21, X4,LSL #3]

0x4c9cbc STR	X4, [X23, X1,LSL #3]

0x4c9cc0 ADD	X1, X1, #1

0x4c9cc4 ADD	X4, X4, #1

0x4c9cc8 LDR	X17, [X19, X4,LSL #3]

0x4c9ccc CMP	X17, #0

0x4c9cd0 B.LE	4c9e7c

0x4c9cd4 STR	X1, [X21, X4,LSL #3]

0x4c9cd8 STR	X4, [X23, X1,LSL #3]

0x4c9cdc ADD	X1, X1, #1

0x4c9ce0 ADD	X4, X4, #1

0x4c9ce4 CMP	X8, X4

0x4c9ce8 B.NE	4c9ddc

(2426) 0x4c9cec LDR	X23, [SP, #48]

(2426) 0x4c9cf0 LDP	X19, X20, [SP, #16]

(2426) 0x4c9cf4 LDP	X21, X22, [SP, #32]

(2426) 0x4c9cf8 LDP	X29, X30, [SP], #96

(2426) 0x4c9cfc RET

  (2427) 0x4c9d00 STR	X1, [X21, X4,LSL #3]

  (2427) 0x4c9d04 STR	X4, [X23, X1,LSL #3]

  (2427) 0x4c9d08 ADD	X4, X4, #1

  (2427) 0x4c9d0c ADD	X1, X1, #1

  (2427) 0x4c9d10 LDR	X3, [X19, X4,LSL #3]

  (2427) 0x4c9d14 CMP	X3, #0

  (2427) 0x4c9d18 B.LE	4c9dfc

    (2428) 0x4c9d1c ADD	X6, X4, #1

    (2428) 0x4c9d20 STR	X1, [X21, X4,LSL #3]

    (2428) 0x4c9d24 STR	X4, [X23, X1,LSL #3]

    (2428) 0x4c9d28 ADD	X1, X1, #1

    (2428) 0x4c9d2c LDR	X7, [X19, X6,LSL #3]

    (2428) 0x4c9d30 CMP	X7, #0

    (2428) 0x4c9d34 B.LE	4c9e10

  (2434) 0x4c9d38 ADD	X2, X4, #2

  (2434) 0x4c9d3c STR	X1, [X21, X6,LSL #3]

  (2434) 0x4c9d40 STR	X6, [X23, X1,LSL #3]

  (2434) 0x4c9d44 ADD	X1, X1, #1

  (2434) 0x4c9d48 LDR	X0, [X19, X2,LSL #3]

  (2434) 0x4c9d4c CMP	X0, #0

  (2434) 0x4c9d50 B.LE	4c9e24

    (2428) 0x4c9d54 ADD	X18, X4, #3

    (2428) 0x4c9d58 STR	X1, [X21, X2,LSL #3]

    (2428) 0x4c9d5c STR	X2, [X23, X1,LSL #3]

    (2428) 0x4c9d60 ADD	X1, X1, #1

    (2428) 0x4c9d64 LDR	X20, [X19, X18,LSL #3]

    (2428) 0x4c9d68 CMP	X20, #0

    (2428) 0x4c9d6c B.LE	4c9e38

  (2432) 0x4c9d70 ADD	X22, X4, #4

  (2432) 0x4c9d74 STR	X1, [X21, X18,LSL #3]

  (2432) 0x4c9d78 STR	X18, [X23, X1,LSL #3]

  (2432) 0x4c9d7c ADD	X1, X1, #1

  (2432) 0x4c9d80 LDR	X5, [X19, X22,LSL #3]

  (2432) 0x4c9d84 CMP	X5, #0

  (2432) 0x4c9d88 B.LE	4c9e4c

    (2428) 0x4c9d8c ADD	X10, X4, #5

    (2428) 0x4c9d90 STR	X1, [X21, X22,LSL #3]

    (2428) 0x4c9d94 STR	X22, [X23, X1,LSL #3]

    (2428) 0x4c9d98 ADD	X1, X1, #1

    (2428) 0x4c9d9c LDR	X11, [X19, X10,LSL #3]

    (2428) 0x4c9da0 CMP	X11, #0

    (2428) 0x4c9da4 B.LE	4c9e60

  (2430) 0x4c9da8 ADD	X12, X4, #6

  (2430) 0x4c9dac STR	X1, [X21, X10,LSL #3]

  (2430) 0x4c9db0 STR	X10, [X23, X1,LSL #3]

  (2430) 0x4c9db4 ADD	X1, X1, #1

  (2430) 0x4c9db8 LDR	X13, [X19, X12,LSL #3]

  (2430) 0x4c9dbc CMP	X13, #0

  (2430) 0x4c9dc0 B.LE	4c9e74

    (2428) 0x4c9dc4 STR	X1, [X21, X12,LSL #3]

    (2428) 0x4c9dc8 STR	X12, [X23, X1,LSL #3]

    (2428) 0x4c9dcc ADD	X1, X1, #1

    (2428) 0x4c9dd0 ADD	X4, X4, #7

    (2428) 0x4c9dd4 CMP	X8, X4

    (2428) 0x4c9dd8 B.EQ	4c9cec

    (2428) 0x4c9ddc LDR	X30, [X19, X4,LSL #3]

    (2428) 0x4c9de0 CMP	X30, #0

    (2428) 0x4c9de4 B.GT	4c9d00

    (2428) 0x4c9de8 STR	X9, [X21, X4,LSL #3]

    (2428) 0x4c9dec ADD	X4, X4, #1

    (2428) 0x4c9df0 LDR	X3, [X19, X4,LSL #3]

    (2428) 0x4c9df4 CMP	X3, #0

    (2428) 0x4c9df8 B.GT	4c9d1c

  (2435) 0x4c9dfc ADD	X6, X4, #1

  (2435) 0x4c9e00 STR	X9, [X21, X4,LSL #3]

  (2435) 0x4c9e04 LDR	X7, [X19, X6,LSL #3]

  (2435) 0x4c9e08 CMP	X7, #0

  (2435) 0x4c9e0c B.GT	4c9d38

    (2428) 0x4c9e10 ADD	X2, X4, #2

    (2428) 0x4c9e14 STR	X9, [X21, X6,LSL #3]

    (2428) 0x4c9e18 LDR	X0, [X19, X2,LSL #3]

    (2428) 0x4c9e1c CMP	X0, #0

    (2428) 0x4c9e20 B.GT	4c9d54

  (2433) 0x4c9e24 ADD	X18, X4, #3

  (2433) 0x4c9e28 STR	X9, [X21, X2,LSL #3]

  (2433) 0x4c9e2c LDR	X20, [X19, X18,LSL #3]

  (2433) 0x4c9e30 CMP	X20, #0

  (2433) 0x4c9e34 B.GT	4c9d70

    (2428) 0x4c9e38 ADD	X22, X4, #4

    (2428) 0x4c9e3c STR	X9, [X21, X18,LSL #3]

    (2428) 0x4c9e40 LDR	X5, [X19, X22,LSL #3]

    (2428) 0x4c9e44 CMP	X5, #0

    (2428) 0x4c9e48 B.GT	4c9d8c

  (2431) 0x4c9e4c ADD	X10, X4, #5

  (2431) 0x4c9e50 STR	X9, [X21, X22,LSL #3]

  (2431) 0x4c9e54 LDR	X11, [X19, X10,LSL #3]

  (2431) 0x4c9e58 CMP	X11, #0

  (2431) 0x4c9e5c B.GT	4c9da8

    (2428) 0x4c9e60 ADD	X12, X4, #6

    (2428) 0x4c9e64 STR	X9, [X21, X10,LSL #3]

    (2428) 0x4c9e68 LDR	X13, [X19, X12,LSL #3]

    (2428) 0x4c9e6c CMP	X13, #0

    (2428) 0x4c9e70 B.GT	4c9dc4

  (2429) 0x4c9e74 STR	X9, [X21, X12,LSL #3]

  (2429) 0x4c9e78 B	4c9dd0

0x4c9e7c STR	X9, [X21, X4,LSL #3]

0x4c9e80 B	4c9ce0

0x4c9e84 STR	X9, [X21, X4,LSL #3]

0x4c9e88 ADD	X4, X4, #1

0x4c9e8c B	4c9cc8

0x4c9e90 STR	X9, [X21, X4,LSL #3]

0x4c9e94 ADD	X4, X4, #1

0x4c9e98 B	4c9cac

0x4c9e9c STR	X9, [X21, X4,LSL #3]

0x4c9ea0 ADD	X4, X4, #1

0x4c9ea4 B	4c9c74

0x4c9ea8 STR	X9, [X21, X4,LSL #3]

0x4c9eac ADD	X4, X4, #1

0x4c9eb0 B	4c9c58

0x4c9eb4 STR	X9, [X21, X4,LSL #3]

0x4c9eb8 ADD	X4, X4, #1

0x4c9ebc B	4c9c90

0x4c9ec0 STR	X9, [X21, X4,LSL #3]

0x4c9ec4 ADD	X4, X4, #1

0x4c9ec8 B	4c9c3c

Coverage (%)	Name	Source Location	Module
►100.00+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	par_strength.c:1253-1278
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1253-1278.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 49% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 22.38 to 21.00 cycles (1.07x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 22.38 to 1.00 cycles (22.37x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 208 bytes. The binary function is storing 240 bytes.

General properties

nb instructions	179
loop length	716
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

22.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	21.00	21.00	15.17	15.17	15.17	15.17	15.17	15.17	0.00	0.00	0.00	0.00	16.50	16.17	16.33	13.50	13.50
cycles	21.00	21.00	15.17	15.17	15.17	15.17	15.17	15.17	0.00	0.00	0.00	0.00	16.50	16.17	16.33	13.50	13.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	22.38
Overall L1	22.38

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 22.38 cycles. At this rate:

9% of peak load performance is reached (9.30 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
22% of peak store performance is reached (10.73 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4c99c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #928]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X1, SP, #88	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X22, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X0, SP, #80	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X21, [X22, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #72]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X19, X2, [X22]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X20, X23, [X22, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
BL 5499e0 <hypre_GetSimpleThreadPartition>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X1, X4, [SP, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
CMP X1, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4c9bc0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X18, X19, X1,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVZ W0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X5, X19, X4,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X3, X5, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X2, X3, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X6, X2, #3, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X2, [SP, #72]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X7, X6, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS X8, X7, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c9b08 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c9ae8 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c9ad0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c9ab8 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c9aa0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c9a88 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c9a70 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X18]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X9, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4c9a6c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X18, X18, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X10, [X18]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X10, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4c9a84 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X18, X18, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X11, [X18]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X11, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4c9a9c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xdc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X18, X18, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X12, [X18]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X12, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4c9ab4 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X18, X18, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X13, [X18]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X13, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4c9acc <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X18, X18, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X14, [X18]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X14, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4c9ae4 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X18, X18, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X15, [X18]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X15, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4c9afc <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X18, X18, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CMP X18, X5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c9bb8 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x1f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ W0, 4c9bc0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X2, [SP, #72]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X1, [X22, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X2, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, SP, #72	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
BL 54a980 <hypre_prefix_sum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X4, X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
CMP X4, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4c9cec <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x32c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X5, X8, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X1, [SP, #72]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS X10, X5, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c9ddc <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x41c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c9cc8 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c9cac <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c9c90 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c9c74 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c9c58 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x298>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c9c3c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X11, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4c9ec0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x500>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X12, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X12, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4c9ea8 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X13, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X13, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4c9e9c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X14, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X14, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4c9eb4 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X15, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X15, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4c9e90 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X16, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X16, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4c9e84 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X17, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X17, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4c9e7c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CMP X8, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 4c9ddc <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x41c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 4c9ce0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x320>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B 4c9cc8 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B 4c9cac <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B 4c9c74 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B 4c9c58 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x298>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B 4c9c90 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B 4c9c3c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	par_strength.c:1253-1278
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1253-1278.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 22.38 to 1.00 cycles (22.37x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 208 bytes. The binary function is storing 240 bytes.

General properties

nb instructions	179
loop length	716
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

22.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	21.00	21.00	15.17	15.17	15.17	15.17	15.17	15.17	0.00	0.00	0.00	0.00	16.50	16.17	16.33	13.50	13.50
cycles	21.00	21.00	15.17	15.17	15.17	15.17	15.17	15.17	0.00	0.00	0.00	0.00	16.50	16.17	16.33	13.50	13.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	22.38
Overall L1	22.38

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 22.38 cycles. At this rate:

9% of peak load performance is reached (9.30 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
22% of peak store performance is reached (10.73 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4c99c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #928]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X1, SP, #88	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X22, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X0, SP, #80	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X21, [X22, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #72]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X19, X2, [X22]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X20, X23, [X22, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
BL 5499e0 <hypre_GetSimpleThreadPartition>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X1, X4, [SP, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
CMP X1, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4c9bc0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X18, X19, X1,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVZ W0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X5, X19, X4,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X3, X5, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X2, X3, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X6, X2, #3, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X2, [SP, #72]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X7, X6, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS X8, X7, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c9b08 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c9ae8 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c9ad0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c9ab8 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c9aa0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c9a88 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c9a70 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X18]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X9, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4c9a6c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X18, X18, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X10, [X18]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X10, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4c9a84 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X18, X18, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X11, [X18]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X11, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4c9a9c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xdc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X18, X18, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X12, [X18]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X12, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4c9ab4 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X18, X18, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X13, [X18]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X13, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4c9acc <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X18, X18, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X14, [X18]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X14, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4c9ae4 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X18, X18, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X15, [X18]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X15, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4c9afc <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X18, X18, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CMP X18, X5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c9bb8 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x1f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ W0, 4c9bc0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X2, [SP, #72]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X1, [X22, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X2, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, SP, #72	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
BL 54a980 <hypre_prefix_sum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X4, X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
CMP X4, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4c9cec <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x32c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X5, X8, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X1, [SP, #72]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS X10, X5, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c9ddc <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x41c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c9cc8 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c9cac <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c9c90 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c9c74 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c9c58 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x298>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c9c3c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X11, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4c9ec0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x500>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X12, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X12, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4c9ea8 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X13, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X13, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4c9e9c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X14, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X14, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4c9eb4 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X15, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X15, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4c9e90 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X16, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X16, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4c9e84 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X17, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X17, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4c9e7c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CMP X8, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 4c9ddc <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x41c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 4c9ce0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x320>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B 4c9cc8 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B 4c9cac <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B 4c9c74 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B 4c9c58 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x298>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B 4c9c90 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B 4c9c3c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGCreate2ndS._omp_fn.0–	0.01	0.00
○Loop 2436 - par_strength.c:1261-1263 - exec	0.01	0.00
▼Loop 2426 - par_strength.c:1253-1278 - exec–	0.00	0.00
○Loop 2429 - par_strength.c:1278-1278 - exec	0.00	0.00
▼Loop 2427 - par_strength.c:1268-1278 - exec–	0.00	0.00
○Loop 2428 - par_strength.c:1268-1278 - exec	0.00	0.00
○Loop 2430 - par_strength.c:1268-1274 - exec	0.00	0.00
○Loop 2435 - par_strength.c:1268-1278 - exec	0.00	0.00
○Loop 2434 - par_strength.c:1268-1274 - exec	0.00	0.00
○Loop 2432 - par_strength.c:1268-1274 - exec	0.00	0.00
○Loop 2433 - par_strength.c:1268-1278 - exec	0.00	0.00
○Loop 2431 - par_strength.c:1268-1278 - exec	0.00	0.00

Report Configuration

Vectorization

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Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

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Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code