OV - exec - Function hypre_BoomerAMGBuildMultipass._omp

	Function: hypre_BoomerAMGBuildMultipass._omp_fn.10	Module: exec	Source: par_multi_interp.c:1737-1881 [...]	Coverage (incl. loops): 1.28% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1737 - 1881

--------------------------------------------------------------------------------

1737: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa,tmp_array,tmp_array_offd)

[...]

1746:              tmp_marker = NULL;

1747:              if (n_fine)

1748:              {    tmp_marker = hypre_CTAlloc(HYPRE_Int,n_fine); }

1749:              tmp_marker_offd = NULL;

1750:              if (num_cols_offd)

1751:              {    tmp_marker_offd = hypre_CTAlloc(HYPRE_Int,num_cols_offd); }

1752:              tmp_array = NULL;

1753:              if (n_coarse)

1754:              {    tmp_array = hypre_CTAlloc(HYPRE_Int,n_coarse); }

1755:              tmp_array_offd = NULL;

1756:              if (new_num_cols_offd > n_coarse_offd)

1757:              {    tmp_array_offd = hypre_CTAlloc(HYPRE_Int,new_num_cols_offd); }

1758:              else

1759:              {    tmp_array_offd = hypre_CTAlloc(HYPRE_Int,n_coarse_offd);}

1760:              for (i=0; i < n_fine; i++)

1761:              {    tmp_marker[i] = -1; }

1762:              for (i=0; i < num_cols_offd; i++)

1763:              {    tmp_marker_offd[i] = -1; }

1764:

1765:              /* Compute this thread's range of pass_length */

1766:              my_thread_num = hypre_GetThreadNum();

1767:              num_threads = hypre_NumActiveThreads();

1768:              thread_start = pass_pointer[pass] + (pass_length/num_threads)*my_thread_num;

1769:              if (my_thread_num == num_threads-1)

1770:              {  thread_stop = pass_pointer[pass] + pass_length; }

1771:              else

1772:              {  thread_stop = pass_pointer[pass] + (pass_length/num_threads)*(my_thread_num+1); }

1773:

1774:              for (i=thread_start; i < thread_stop; i++)

1775:              {

1776:                 i1 = pass_array[i];

1777:                 sum_C = 0;

1778:                 sum_N = 0;

1779:                 j_start = P_diag_start[i1];

1780:                 j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1];

1781:                 cnt = P_diag_i[i1];

1782:                 for (j=j_start; j < j_end; j++)

1783:                 {

1784:                    k1 = P_diag_pass[pass][j];

1785:                tmp_array[k1] = cnt;

1786:                P_diag_data[cnt] = 0;

1787:                P_diag_j[cnt++] = k1;

1788:                 }

1789:                 j_start = P_offd_start[i1];

1790:                 j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1];

1791:                 cnt_offd = P_offd_i[i1];

1792:                 for (j=j_start; j < j_end; j++)

1793:                 {

1794:                    k1 = P_offd_pass[pass][j];

1795:                tmp_array_offd[k1] = cnt_offd;

1796:                P_offd_data[cnt_offd] = 0;

1797:                P_offd_j[cnt_offd++] = k1;

1798:                 }

1799:                 for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

1800:                 {

1801:                j1 = S_diag_j[j];

1802:                if (assigned[j1] == pass-1)

1803:                   tmp_marker[j1] = i1;

1804:                 }

1805:                 for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

1806:                 {

1807:                j1 = S_offd_j[j];

1808:                if (assigned_offd[j1] == pass-1)

1809:                   tmp_marker_offd[j1] = i1;

1810:                 }

1811:                 for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1812:                 {

1813:                j1 = A_diag_j[j];

1814:                if (tmp_marker[j1] == i1)

1815:                {

1816:                   for (k=P_diag_i[j1]; k < P_diag_i[j1+1]; k++)

1817:                   {

1818:                  k1 = P_diag_j[k];

1819:                      alfa = A_diag_data[j]*P_diag_data[k];

1820:                      P_diag_data[tmp_array[k1]] += alfa;

1821:                      sum_C += alfa;

1822:                      sum_N += alfa;

1823:                       }

1824:                   for (k=P_offd_i[j1]; k < P_offd_i[j1+1]; k++)

1825:                   {

1826:                  k1 = P_offd_j[k];

1827:                      alfa = A_diag_data[j]*P_offd_data[k];

1828:                      P_offd_data[tmp_array_offd[k1]] += alfa;

1829:                      sum_C += alfa;

1830:                      sum_N += alfa;

1831:                       }

1832:                    }

1833:                    else

1834:                    {

1835:                       if (CF_marker[j1] != -3 &&

1836:                 (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1837:                  sum_N += A_diag_data[j];

1838:                    }

1839:                 }

1840:                 for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++)

1841:                 {

1842:                if (col_offd_S_to_A)

1843:                   j1 = map_A_to_S[A_offd_j[j]];

1844:                else

1845:                   j1 = A_offd_j[j];

1846:

1847:                if (j1 > -1 && tmp_marker_offd[j1] == i1)

1848:                {

1849:                   j_start = Pext_start[j1];

1850:                   j_end = j_start+Pext_i[j1+1];

1851:                   for (k=j_start; k < j_end; k++)

1852:                   {

1853:                  k1 = Pext_pass[pass][k];

1854:                      alfa = A_offd_data[j]*Pext_data[k];

1855:                  if (k1 < 0)

1856:                         P_diag_data[tmp_array[-k1-1]] += alfa;

1857:                  else

1858:                         P_offd_data[tmp_array_offd[k1]] += alfa;

1859:                      sum_C += alfa;

1860:                      sum_N += alfa;

1861:                       }

1862:                    }

1863:                    else

1864:                    {

1865:                       if (CF_marker_offd[j1] != -3 &&

1866:                 (num_functions == 1 || dof_func_offd[j1] == dof_func[i1]))

1867:                  sum_N += A_offd_data[j];

1868:                    }

1869:                 }

1870:                 diagonal = A_diag_data[A_diag_i[i1]];

1871:                 if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal);

1872:

1873:                 for (j=P_diag_i[i1]; j < P_diag_i[i1+1]; j++)

1874:                P_diag_data[j] *= alfa;

1875:                 for (j=P_offd_i[i1]; j < P_offd_i[i1+1]; j++)

1876:                P_offd_data[j] *= alfa;

1877:              }

1878:              hypre_TFree(tmp_marker);

1879:              hypre_TFree(tmp_marker_offd);

1880:              hypre_TFree(tmp_array);

1881:              hypre_TFree(tmp_array_offd);

0x45bc60 STP	X29, X30, [SP, #656]!

0x45bc64 ADD	X29, SP, #0

0x45bc68 STP	X19, X20, [SP, #16]

0x45bc6c STP	X21, X22, [SP, #32]

0x45bc70 STP	X23, X24, [SP, #48]

0x45bc74 STP	X25, X26, [SP, #64]

0x45bc78 STP	X27, X28, [SP, #80]

0x45bc7c LDP	X1, X11, [X0, #80]

0x45bc80 STR	X1, [SP, #216]

0x45bc84 LDP	X2, X10, [X0, #96]

0x45bc88 STR	X2, [SP, #208]

0x45bc8c LDP	X3, X20, [X0, #112]

0x45bc90 STR	X3, [SP, #96]

0x45bc94 LDP	X4, X25, [X0, #128]

0x45bc98 STR	X4, [SP, #120]

0x45bc9c LDP	X19, X5, [X0, #144]

0x45bca0 STR	X5, [SP, #112]

0x45bca4 LDP	X24, X6, [X0, #160]

0x45bca8 STR	X6, [SP, #304]

0x45bcac LDP	X6, X7, [X0, #176]

0x45bcb0 STR	X7, [SP, #280]

0x45bcb4 LDP	X8, X9, [X0, #192]

0x45bcb8 STR	X9, [SP, #144]

0x45bcbc STR	X8, [SP, #336]

0x45bcc0 LDP	X12, X13, [X0, #208]

0x45bcc4 STP	X13, X12, [SP, #192]

0x45bcc8 LDP	X14, X15, [X0, #224]

0x45bccc STP	X15, X14, [SP, #264]

0x45bcd0 LDP	X16, X17, [X0, #240]

0x45bcd4 STR	X17, [SP, #296]

0x45bcd8 STR	X16, [SP, #312]

0x45bcdc LDP	X18, X21, [X0, #256]

0x45bce0 STR	X21, [SP, #104]

0x45bce4 STR	X18, [SP, #256]

0x45bce8 LDP	X28, X26, [X0, #304]

0x45bcec LDP	X2, X23, [X0, #272]

0x45bcf0 LDP	X22, X8, [X0, #288]

0x45bcf4 STR	X26, [SP, #248]

0x45bcf8 LDP	X3, X27, [X0, #320]

0x45bcfc STR	X27, [SP, #128]

0x45bd00 LDP	X27, X30, [X0, #16]

0x45bd04 LDP	X7, X12, [X0]

0x45bd08 STR	X30, [SP, #352]

0x45bd0c LDP	X21, X1, [X0, #32]

0x45bd10 STR	X1, [SP, #232]

0x45bd14 LDP	X9, X4, [X0, #48]

0x45bd18 STR	X4, [SP, #344]

0x45bd1c LDP	X0, X5, [X0, #64]

0x45bd20 STR	X0, [SP, #224]

0x45bd24 STR	X5, [SP, #288]

0x45bd28 CBNZ	X2, 45cfac

0x45bd2c MOVZ	X26, #0

0x45bd30 LDR	X0, [SP, #96]

0x45bd34 CBNZ	X0, 45cf6c

0x45bd38 MOVZ	X13, #0

0x45bd3c CBNZ	X23, 45cf20

0x45bd40 CMP	X3, X22

0x45bd44 B.LE	45cf00

0x45bd48 ORR	X0, XZR, X3

0x45bd4c STR	X13, [SP, #136]

0x45bd50 STP	X8, X2, [SP, #152]

0x45bd54 STP	X6, X10, [SP, #168]

0x45bd58 STR	X11, [SP, #184]

0x45bd5c STR	X9, [SP, #240]

0x45bd60 STP	X12, X7, [SP, #320]

0x45bd64 MOVZ	X1, #8

0x45bd68 BL	546d88

0x45bd6c LDP	X15, X1, [SP, #152]

0x45bd70 ORR	X22, XZR, X0

0x45bd74 LDP	X4, X5, [SP, #168]

0x45bd78 LDP	X18, X6, [SP, #320]

0x45bd7c LDR	X14, [SP, #136]

0x45bd80 LDR	X3, [SP, #184]

0x45bd84 LDR	X8, [SP, #240]

0x45bd88 CMP	X1, #0

0x45bd8c B.LE	45bdd0

0x45bd90 UBFM	X2, X1, #61, #60

0x45bd94 ORR	X0, XZR, X26

0x45bd98 STR	X14, [SP, #136]

0x45bd9c MOVZ	W1, #255

0x45bda0 STP	X15, X4, [SP, #152]

0x45bda4 STP	X5, X3, [SP, #168]

0x45bda8 STR	X8, [SP, #184]

0x45bdac STR	X18, [SP, #240]

0x45bdb0 STR	X6, [SP, #320]

0x45bdb4 BL	4108c0

0x45bdb8 LDR	X14, [SP, #136]

0x45bdbc LDP	X15, X4, [SP, #152]

0x45bdc0 LDP	X5, X3, [SP, #168]

0x45bdc4 LDR	X8, [SP, #184]

0x45bdc8 LDR	X18, [SP, #240]

0x45bdcc LDR	X6, [SP, #320]

0x45bdd0 LDR	X16, [SP, #96]

0x45bdd4 CMP	X16, #0

0x45bdd8 B.LE	45be18

0x45bddc ORR	X0, XZR, X14

0x45bde0 UBFM	X2, X16, #61, #60

0x45bde4 STR	X15, [SP, #136]

0x45bde8 MOVZ	W1, #255

0x45bdec STP	X4, X5, [SP, #152]

0x45bdf0 STP	X3, X8, [SP, #168]

0x45bdf4 STR	X18, [SP, #184]

0x45bdf8 STR	X6, [SP, #240]

0x45bdfc BL	4108c0

0x45be00 LDR	X15, [SP, #136]

0x45be04 ORR	X14, XZR, X0

0x45be08 LDP	X4, X5, [SP, #152]

0x45be0c LDP	X3, X8, [SP, #168]

0x45be10 LDR	X18, [SP, #184]

0x45be14 LDR	X6, [SP, #240]

0x45be18 STP	X14, X15, [SP, #152]

0x45be1c STP	X4, X5, [SP, #168]

0x45be20 STR	X3, [SP, #184]

0x45be24 STR	X8, [SP, #240]

0x45be28 STP	X18, X6, [SP, #320]

0x45be2c BL	5499c0

0x45be30 STR	X0, [SP, #96]

0x45be34 BL	5499a0

0x45be38 LDR	X14, [SP, #128]

0x45be3c SUB	X5, X0, #1

0x45be40 LDP	X2, X15, [SP, #144]

0x45be44 LDP	X9, X6, [SP, #160]

0x45be48 SDIV	X3, X14, X0

0x45be4c LDP	X10, X11, [SP, #176]

0x45be50 LDP	X18, X7, [SP, #320]

0x45be54 LDR	X13, [SP, #104]

0x45be58 LDR	X8, [SP, #96]

0x45be5c LDR	X12, [SP, #240]

0x45be60 UBFM	X1, X13, #61, #60

0x45be64 LDR	X4, [X2, X1]

0x45be68 CMP	X8, X5

0x45be6c STR	X1, [SP, #136]

0x45be70 ADD	X13, X14, X4

0x45be74 MADD	X14, X8, X3, XZR

0x45be78 ADD	X0, X3, X14

0x45be7c ADD	X1, X4, X14

0x45be80 ADD	X2, X0, X4

0x45be84 CSEL	X4, X13, X2, #0

0x45be88 CMP	X4, X1

0x45be8c B.LE	45c864

0x45be90 LDR	X5, [SP, #336]

0x45be94 SUB	X30, X24, #8

0x45be98 SUB	X16, X25, #8

0x45be9c LDR	X8, [SP, #104]

0x45bea0 ADD	X17, X5, X1,LSL #3

0x45bea4 ADD	X3, X5, X4,LSL #3

0x45bea8 SUB	X13, X8, #1

0x45beac STR	X17, [SP, #128]

0x45beb0 STP	X13, X30, [SP, #96]

0x45beb4 LDP	X17, X30, [SP, #344]

0x45beb8 STR	X3, [SP, #240]

0x45bebc HINT	#0

(856) 0x45bec0 LDR	X14, [SP, #128]

(856) 0x45bec4 LDR	X1, [SP, #120]

(856) 0x45bec8 LDR	X0, [SP, #200]

(856) 0x45becc LDR	X3, [X14]

(856) 0x45bed0 UBFM	X4, X3, #61, #60

(856) 0x45bed4 ADD	X8, X4, #8

(856) 0x45bed8 LDR	X14, [X0, X4]

(856) 0x45bedc LDR	X2, [X1, X8]

(856) 0x45bee0 LDR	X0, [X1, X4]

(856) 0x45bee4 ADD	X5, X14, X2

(856) 0x45bee8 SUB	X1, X5, X0

(856) 0x45beec CMP	X14, X1

(856) 0x45bef0 B.GE	45c09c

(856) 0x45bef4 SUB	X13, X0, X14

(856) 0x45bef8 ADD	X13, X13, X1

(856) 0x45befc LDR	X1, [SP, #272]

(856) 0x45bf00 SUB	X2, X13, X0

(856) 0x45bf04 ANDS	X5, X2, #4224

(856) 0x45bf08 LDR	X2, [SP, #136]

(856) 0x45bf0c LDR	X2, [X1, X2]

(856) 0x45bf10 SUB	X1, XZR, X0,LSL #3

(856) 0x45bf14 ADD	X14, X1, X14,LSL #3

(856) 0x45bf18 ADD	X1, X2, X14

(856) 0x45bf1c B.EQ	45bfe4

(856) 0x45bf20 CMP	X5, #1

(856) 0x45bf24 B.EQ	45bfc8

(856) 0x45bf28 CMP	X5, #2

(856) 0x45bf2c B.EQ	45bfb4

(856) 0x45bf30 CMP	X5, #3

(856) 0x45bf34 B.EQ	45bfa0

(856) 0x45bf38 CMP	X5, #4

(856) 0x45bf3c B.EQ	45bf8c

(856) 0x45bf40 CMP	X5, #5

(856) 0x45bf44 B.EQ	45bf78

(856) 0x45bf48 CMP	X5, #6

(856) 0x45bf4c B.EQ	45bf64

(856) 0x45bf50 LDR	X5, [X1, X0,LSL #3]

(856) 0x45bf54 STR	X0, [X23, X5,LSL #3]

(856) 0x45bf58 STR	XZR, [X20, X0,LSL #3]

(856) 0x45bf5c ADD	X0, X0, #1

(856) 0x45bf60 STR	X5, [X16, X0,LSL #3]

(856) 0x45bf64 LDR	X2, [X1, X0,LSL #3]

(856) 0x45bf68 STR	X0, [X23, X2,LSL #3]

(856) 0x45bf6c STR	XZR, [X20, X0,LSL #3]

(856) 0x45bf70 ADD	X0, X0, #1

(856) 0x45bf74 STR	X2, [X16, X0,LSL #3]

(856) 0x45bf78 LDR	X14, [X1, X0,LSL #3]

(856) 0x45bf7c STR	X0, [X23, X14,LSL #3]

(856) 0x45bf80 STR	XZR, [X20, X0,LSL #3]

(856) 0x45bf84 ADD	X0, X0, #1

(856) 0x45bf88 STR	X14, [X16, X0,LSL #3]

(856) 0x45bf8c LDR	X5, [X1, X0,LSL #3]

(856) 0x45bf90 STR	X0, [X23, X5,LSL #3]

(856) 0x45bf94 STR	XZR, [X20, X0,LSL #3]

(856) 0x45bf98 ADD	X0, X0, #1

(856) 0x45bf9c STR	X5, [X16, X0,LSL #3]

(856) 0x45bfa0 LDR	X2, [X1, X0,LSL #3]

(856) 0x45bfa4 STR	X0, [X23, X2,LSL #3]

(856) 0x45bfa8 STR	XZR, [X20, X0,LSL #3]

(856) 0x45bfac ADD	X0, X0, #1

(856) 0x45bfb0 STR	X2, [X16, X0,LSL #3]

(856) 0x45bfb4 LDR	X14, [X1, X0,LSL #3]

(856) 0x45bfb8 STR	X0, [X23, X14,LSL #3]

(856) 0x45bfbc STR	XZR, [X20, X0,LSL #3]

(856) 0x45bfc0 ADD	X0, X0, #1

(856) 0x45bfc4 STR	X14, [X16, X0,LSL #3]

(856) 0x45bfc8 LDR	X5, [X1, X0,LSL #3]

(856) 0x45bfcc STR	X0, [X23, X5,LSL #3]

(856) 0x45bfd0 STR	XZR, [X20, X0,LSL #3]

(856) 0x45bfd4 ADD	X0, X0, #1

(856) 0x45bfd8 STR	X5, [X16, X0,LSL #3]

(856) 0x45bfdc CMP	X13, X0

(856) 0x45bfe0 B.EQ	45c09c

(856) 0x45bfe4 STP	X26, X15, [SP, #144]

(856) 0x45bfe8 STP	X22, X28, [SP, #160]

  (867) 0x45bfec ADD	X2, X0, #1

  (867) 0x45bff0 ADD	X26, X0, #2

  (867) 0x45bff4 ADD	X22, X0, #3

  (867) 0x45bff8 ADD	X15, X0, #4

  (867) 0x45bffc LDR	X28, [X1, X0,LSL #3]

  (867) 0x45c000 ADD	X14, X0, #5

  (867) 0x45c004 ADD	X5, X0, #6

  (867) 0x45c008 STR	X0, [X23, X28,LSL #3]

  (867) 0x45c00c STR	XZR, [X20, X0,LSL #3]

  (867) 0x45c010 STR	X28, [X16, X2,LSL #3]

  (867) 0x45c014 LDR	X28, [X1, X2,LSL #3]

  (867) 0x45c018 STR	X2, [X23, X28,LSL #3]

  (867) 0x45c01c STR	XZR, [X20, X2,LSL #3]

  (867) 0x45c020 ADD	X2, X0, #7

  (867) 0x45c024 ADD	X0, X0, #8

  (867) 0x45c028 STR	X28, [X16, X26,LSL #3]

  (867) 0x45c02c LDR	X28, [X1, X26,LSL #3]

  (867) 0x45c030 STR	X26, [X23, X28,LSL #3]

  (867) 0x45c034 STR	XZR, [X20, X26,LSL #3]

  (867) 0x45c038 STR	X28, [X16, X22,LSL #3]

  (867) 0x45c03c LDR	X26, [X1, X22,LSL #3]

  (867) 0x45c040 STR	X22, [X23, X26,LSL #3]

  (867) 0x45c044 STR	XZR, [X20, X22,LSL #3]

  (867) 0x45c048 STR	X26, [X16, X15,LSL #3]

  (867) 0x45c04c LDR	X22, [X1, X15,LSL #3]

  (867) 0x45c050 STR	X15, [X23, X22,LSL #3]

  (867) 0x45c054 STR	XZR, [X20, X15,LSL #3]

  (867) 0x45c058 STR	X22, [X16, X14,LSL #3]

  (867) 0x45c05c LDR	X15, [X1, X14,LSL #3]

  (867) 0x45c060 STR	X14, [X23, X15,LSL #3]

  (867) 0x45c064 STR	XZR, [X20, X14,LSL #3]

  (867) 0x45c068 STR	X15, [X16, X5,LSL #3]

  (867) 0x45c06c LDR	X14, [X1, X5,LSL #3]

  (867) 0x45c070 STR	X5, [X23, X14,LSL #3]

  (867) 0x45c074 STR	XZR, [X20, X5,LSL #3]

  (867) 0x45c078 STR	X14, [X16, X2,LSL #3]

  (867) 0x45c07c LDR	X5, [X1, X2,LSL #3]

  (867) 0x45c080 STR	X2, [X23, X5,LSL #3]

  (867) 0x45c084 STR	XZR, [X20, X2,LSL #3]

  (867) 0x45c088 STR	X5, [X16, X0,LSL #3]

  (867) 0x45c08c CMP	X13, X0

  (867) 0x45c090 B.NE	45bfec

(856) 0x45c094 LDP	X26, X15, [SP, #144]

(856) 0x45c098 LDP	X22, X28, [SP, #160]

(856) 0x45c09c LDR	X0, [SP, #112]

(856) 0x45c0a0 LDR	X13, [SP, #192]

(856) 0x45c0a4 LDR	X2, [X0, X8]

(856) 0x45c0a8 LDR	X1, [X13, X4]

(856) 0x45c0ac LDR	X0, [X0, X4]

(856) 0x45c0b0 ADD	X14, X1, X2

(856) 0x45c0b4 SUB	X5, X14, X0

(856) 0x45c0b8 CMP	X1, X5

(856) 0x45c0bc B.GE	45c28c

(856) 0x45c0c0 LDR	X13, [SP, #136]

(856) 0x45c0c4 LDR	X2, [SP, #264]

(856) 0x45c0c8 LDR	X14, [X2, X13]

(856) 0x45c0cc SUB	X13, X0, X1

(856) 0x45c0d0 UBFM	X1, X1, #61, #60

(856) 0x45c0d4 ADD	X13, X13, X5

(856) 0x45c0d8 SUB	X2, X1, X0,LSL #3

(856) 0x45c0dc SUB	X5, X13, X0

(856) 0x45c0e0 ANDS	X5, X5, #4224

(856) 0x45c0e4 ADD	X1, X14, X2

(856) 0x45c0e8 B.EQ	45ced0

(856) 0x45c0ec CMP	X5, #1

(856) 0x45c0f0 B.EQ	45c1ac

(856) 0x45c0f4 CMP	X5, #2

(856) 0x45c0f8 B.EQ	45c194

(856) 0x45c0fc CMP	X5, #3

(856) 0x45c100 B.EQ	45c17c

(856) 0x45c104 CMP	X5, #4

(856) 0x45c108 B.EQ	45c164

(856) 0x45c10c CMP	X5, #5

(856) 0x45c110 B.EQ	45c14c

(856) 0x45c114 CMP	X5, #6

(856) 0x45c118 B.EQ	45c134

(856) 0x45c11c LDR	X14, [X1, X0,LSL #3]

(856) 0x45c120 LDR	X2, [SP, #104]

(856) 0x45c124 STR	X0, [X22, X14,LSL #3]

(856) 0x45c128 STR	XZR, [X19, X0,LSL #3]

(856) 0x45c12c ADD	X0, X0, #1

(856) 0x45c130 STR	X14, [X2, X0,LSL #3]

(856) 0x45c134 LDR	X5, [X1, X0,LSL #3]

(856) 0x45c138 LDR	X14, [SP, #104]

(856) 0x45c13c STR	X0, [X22, X5,LSL #3]

(856) 0x45c140 STR	XZR, [X19, X0,LSL #3]

(856) 0x45c144 ADD	X0, X0, #1

(856) 0x45c148 STR	X5, [X14, X0,LSL #3]

(856) 0x45c14c LDR	X5, [X1, X0,LSL #3]

(856) 0x45c150 LDR	X2, [SP, #104]

(856) 0x45c154 STR	X0, [X22, X5,LSL #3]

(856) 0x45c158 STR	XZR, [X19, X0,LSL #3]

(856) 0x45c15c ADD	X0, X0, #1

(856) 0x45c160 STR	X5, [X2, X0,LSL #3]

(856) 0x45c164 LDR	X14, [X1, X0,LSL #3]

(856) 0x45c168 LDR	X5, [SP, #104]

(856) 0x45c16c STR	X0, [X22, X14,LSL #3]

(856) 0x45c170 STR	XZR, [X19, X0,LSL #3]

(856) 0x45c174 ADD	X0, X0, #1

(856) 0x45c178 STR	X14, [X5, X0,LSL #3]

(856) 0x45c17c LDR	X14, [X1, X0,LSL #3]

(856) 0x45c180 LDR	X2, [SP, #104]

(856) 0x45c184 STR	X0, [X22, X14,LSL #3]

(856) 0x45c188 STR	XZR, [X19, X0,LSL #3]

(856) 0x45c18c ADD	X0, X0, #1

(856) 0x45c190 STR	X14, [X2, X0,LSL #3]

(856) 0x45c194 LDR	X5, [X1, X0,LSL #3]

(856) 0x45c198 LDR	X14, [SP, #104]

(856) 0x45c19c STR	X0, [X22, X5,LSL #3]

(856) 0x45c1a0 STR	XZR, [X19, X0,LSL #3]

(856) 0x45c1a4 ADD	X0, X0, #1

(856) 0x45c1a8 STR	X5, [X14, X0,LSL #3]

(856) 0x45c1ac LDR	X5, [X1, X0,LSL #3]

(856) 0x45c1b0 LDR	X2, [SP, #104]

(856) 0x45c1b4 STR	X0, [X22, X5,LSL #3]

(856) 0x45c1b8 STR	XZR, [X19, X0,LSL #3]

(856) 0x45c1bc ADD	X0, X0, #1

(856) 0x45c1c0 STR	X5, [X2, X0,LSL #3]

(856) 0x45c1c4 CMP	X0, X13

(856) 0x45c1c8 B.EQ	45c28c

(856) 0x45c1cc STP	X26, X15, [SP, #144]

(856) 0x45c1d0 STP	X23, X28, [SP, #160]

(856) 0x45c1d4 STR	X9, [SP, #176]

  (866) 0x45c1d8 LDR	X9, [X1, X0,LSL #3]

  (866) 0x45c1dc ADD	X5, X0, #1

  (866) 0x45c1e0 ADD	X26, X0, #2

  (866) 0x45c1e4 ADD	X23, X0, #3

  (866) 0x45c1e8 ADD	X15, X0, #4

  (866) 0x45c1ec ADD	X14, X0, #5

  (866) 0x45c1f0 STR	X0, [X22, X9,LSL #3]

  (866) 0x45c1f4 STR	XZR, [X19, X0,LSL #3]

  (866) 0x45c1f8 STR	X9, [X2, X5,LSL #3]

  (866) 0x45c1fc ADD	X9, X0, #6

  (866) 0x45c200 LDR	X28, [X1, X5,LSL #3]

  (866) 0x45c204 STR	X5, [X22, X28,LSL #3]

  (866) 0x45c208 STR	XZR, [X19, X5,LSL #3]

  (866) 0x45c20c ADD	X5, X0, #7

  (866) 0x45c210 ADD	X0, X0, #8

  (866) 0x45c214 STR	X28, [X2, X26,LSL #3]

  (866) 0x45c218 LDR	X28, [X1, X26,LSL #3]

  (866) 0x45c21c STR	X26, [X22, X28,LSL #3]

  (866) 0x45c220 STR	XZR, [X19, X26,LSL #3]

  (866) 0x45c224 STR	X28, [X2, X23,LSL #3]

  (866) 0x45c228 LDR	X26, [X1, X23,LSL #3]

  (866) 0x45c22c STR	X23, [X22, X26,LSL #3]

  (866) 0x45c230 STR	XZR, [X19, X23,LSL #3]

  (866) 0x45c234 STR	X26, [X2, X15,LSL #3]

  (866) 0x45c238 LDR	X23, [X1, X15,LSL #3]

  (866) 0x45c23c STR	X15, [X22, X23,LSL #3]

  (866) 0x45c240 STR	XZR, [X19, X15,LSL #3]

  (866) 0x45c244 STR	X23, [X2, X14,LSL #3]

  (866) 0x45c248 LDR	X15, [X1, X14,LSL #3]

  (866) 0x45c24c STR	X14, [X22, X15,LSL #3]

  (866) 0x45c250 STR	XZR, [X19, X14,LSL #3]

  (866) 0x45c254 STR	X15, [X2, X9,LSL #3]

  (866) 0x45c258 LDR	X14, [X1, X9,LSL #3]

  (866) 0x45c25c STR	X9, [X22, X14,LSL #3]

  (866) 0x45c260 STR	XZR, [X19, X9,LSL #3]

  (866) 0x45c264 STR	X14, [X2, X5,LSL #3]

  (866) 0x45c268 LDR	X9, [X1, X5,LSL #3]

  (866) 0x45c26c STR	X5, [X22, X9,LSL #3]

  (866) 0x45c270 STR	XZR, [X19, X5,LSL #3]

  (866) 0x45c274 STR	X9, [X2, X0,LSL #3]

  (866) 0x45c278 CMP	X0, X13

  (866) 0x45c27c B.NE	45c1d8

(856) 0x45c280 LDR	X9, [SP, #176]

(856) 0x45c284 LDP	X26, X15, [SP, #144]

(856) 0x45c288 LDP	X23, X28, [SP, #160]

(856) 0x45c28c LDR	X0, [SP, #216]

(856) 0x45c290 LDR	X1, [X0, X4]

(856) 0x45c294 ADD	X14, X0, X8

(856) 0x45c298 LDR	X13, [X0, X8]

(856) 0x45c29c CMP	X1, X13

(856) 0x45c2a0 B.GE	45c2c8

  (865) 0x45c2a4 LDR	X2, [X11, X1,LSL #3]

  (865) 0x45c2a8 LDR	X5, [SP, #96]

  (865) 0x45c2ac UBFM	X0, X2, #61, #60

  (865) 0x45c2b0 LDR	X2, [X9, X0]

  (865) 0x45c2b4 CMP	X5, X2

  (865) 0x45c2b8 B.EQ	45c8b8

  (865) 0x45c2bc ADD	X1, X1, #1

  (865) 0x45c2c0 CMP	X1, X13

  (865) 0x45c2c4 B.LT	45c2a4

(856) 0x45c2c8 LDR	X0, [SP, #208]

(856) 0x45c2cc LDR	X1, [X0, X4]

(856) 0x45c2d0 ADD	X14, X0, X8

(856) 0x45c2d4 LDR	X13, [X0, X8]

(856) 0x45c2d8 CMP	X1, X13

(856) 0x45c2dc B.GE	45c304

  (864) 0x45c2e0 LDR	X2, [X10, X1,LSL #3]

  (864) 0x45c2e4 LDR	X5, [SP, #96]

  (864) 0x45c2e8 UBFM	X0, X2, #61, #60

  (864) 0x45c2ec LDR	X2, [X28, X0]

  (864) 0x45c2f0 CMP	X5, X2

  (864) 0x45c2f4 B.EQ	45c8a0

  (864) 0x45c2f8 ADD	X1, X1, #1

  (864) 0x45c2fc CMP	X1, X13

  (864) 0x45c300 B.LT	45c2e0

(856) 0x45c304 LDR	X14, [SP, #232]

(856) 0x45c308 MOVI	D20, #0

(856) 0x45c30c FMOV	D29, D20

(856) 0x45c310 LDR	X1, [X14, X4]

(856) 0x45c314 LDR	X14, [X14, X8]

(856) 0x45c318 ADD	X0, X1, #1

(856) 0x45c31c CMP	X0, X14

(856) 0x45c320 B.GE	45c3a0

(856) 0x45c324 ORR	X13, XZR, X6

(856) 0x45c328 ORR	X6, XZR, X9

(856) 0x45c32c STP	X15, X28, [SP, #144]

(856) 0x45c330 ORR	X9, XZR, X11

(856) 0x45c334 B	45c354

  (861) 0x45c338 LDR	X11, [X27, X2]

  (861) 0x45c33c LDR	X5, [X27, X4]

  (861) 0x45c340 CMP	X5, X11

  (861) 0x45c344 B.EQ	45c37c

  (861) 0x45c348 ADD	X0, X0, #1

  (861) 0x45c34c CMP	X0, X14

  (861) 0x45c350 B.EQ	45c390

  (861) 0x45c354 LDR	X11, [X12, X0,LSL #3]

  (861) 0x45c358 UBFM	X2, X11, #61, #60

  (861) 0x45c35c LDR	X28, [X26, X2]

  (861) 0x45c360 CMP	X3, X28

  (861) 0x45c364 B.EQ	45c8d0

  (861) 0x45c368 LDR	X15, [X7, X2]

  (861) 0x45c36c CMN	X15, #3

  (861) 0x45c370 B.EQ	45c348

  (861) 0x45c374 CMP	X18, #1

  (861) 0x45c378 B.NE	45c338

  (861) 0x45c37c LDR	D28, [X21, X0,LSL #3]

  (861) 0x45c380 ADD	X0, X0, #1

  (861) 0x45c384 FADD	D20, D20, D28

  (861) 0x45c388 CMP	X0, X14

  (861) 0x45c38c B.NE	45c354

(856) 0x45c390 LDP	X15, X28, [SP, #144]

(856) 0x45c394 ORR	X11, XZR, X9

(856) 0x45c398 ORR	X9, XZR, X6

(856) 0x45c39c ORR	X6, XZR, X13

(856) 0x45c3a0 LDR	X13, [SP, #224]

(856) 0x45c3a4 LDR	X0, [X13, X4]

(856) 0x45c3a8 LDR	X5, [X13, X8]

(856) 0x45c3ac CMP	X0, X5

(856) 0x45c3b0 B.GE	45c43c

(856) 0x45c3b4 STP	X26, X28, [SP, #144]

(856) 0x45c3b8 STP	X9, X24, [SP, #160]

(856) 0x45c3bc LDP	X14, X24, [SP, #248]

(856) 0x45c3c0 STR	X1, [SP, #176]

(856) 0x45c3c4 LDP	X1, X9, [SP, #280]

(856) 0x45c3c8 B	45c3e8

  (859) 0x45c3cc LDR	X28, [X1, X2]

  (859) 0x45c3d0 LDR	X2, [X27, X4]

  (859) 0x45c3d4 CMP	X28, X2

  (859) 0x45c3d8 B.EQ	45c41c

  (859) 0x45c3dc ADD	X0, X0, #1

  (859) 0x45c3e0 CMP	X0, X5

  (859) 0x45c3e4 B.EQ	45c430

  (859) 0x45c3e8 LDR	X28, [X9, X0,LSL #3]

  (859) 0x45c3ec CBZ	X30, 45c3f4

  (859) 0x45c3f0 LDR	X28, [X24, X28,LSL #3]

  (859) 0x45c3f4 UBFM	X2, X28, #61, #60

  (859) 0x45c3f8 TBNZ	X28, #63, 45c408

  (859) 0x45c3fc LDR	X26, [X15, X2]

  (859) 0x45c400 CMP	X3, X26

  (859) 0x45c404 B.EQ	45cc10

  (859) 0x45c408 LDR	X13, [X6, X2]

  (859) 0x45c40c CMN	X13, #3

  (859) 0x45c410 B.EQ	45c3dc

  (859) 0x45c414 CMP	X18, #1

  (859) 0x45c418 B.NE	45c3cc

  (859) 0x45c41c LDR	D7, [X17, X0,LSL #3]

  (859) 0x45c420 ADD	X0, X0, #1

  (859) 0x45c424 FADD	D20, D20, D7

  (859) 0x45c428 CMP	X0, X5

  (859) 0x45c42c B.NE	45c3e8

(856) 0x45c430 LDR	X1, [SP, #176]

(856) 0x45c434 LDP	X26, X28, [SP, #144]

(856) 0x45c438 LDP	X9, X24, [SP, #160]

(856) 0x45c43c LDR	D21, [X21, X1,LSL #3]

(856) 0x45c440 FMUL	D22, D29, D21

(856) 0x45c444 FCMP	D22, #0

(856) 0x45c448 B.EQ	45c454

(856) 0x45c44c FNEG	D20, D20

(856) 0x45c450 FDIV	D31, D20, D22

(856) 0x45c454 LDR	X3, [SP, #120]

(856) 0x45c458 LDR	X1, [X3, X4]

(856) 0x45c45c LDR	X14, [X3, X8]

(856) 0x45c460 CMP	X1, X14

(856) 0x45c464 B.GE	45c654

(856) 0x45c468 SUB	X13, X14, X1

(856) 0x45c46c SUB	X2, X13, #1

(856) 0x45c470 CMP	X2, #2

(856) 0x45c474 B.LS	45c60c

(856) 0x45c478 UBFM	X3, X13, #2, #63

(856) 0x45c47c ADD	X0, X20, X1,LSL #3

(856) 0x45c480 DUP	V23.2D, V31.D[0]

(856) 0x45c484 UBFM	X2, X1, #61, #60

(856) 0x45c488 UBFM	X5, X3, #59, #58

(856) 0x45c48c SUB	X5, X5, #32

(856) 0x45c490 ADD	X3, X0, X3,LSL #5

(856) 0x45c494 UBFM	X5, X5, #5, #63

(856) 0x45c498 ADD	X5, X5, #1

(856) 0x45c49c ANDS	X5, X5, #4224

(856) 0x45c4a0 B.EQ	45c558

(856) 0x45c4a4 CMP	X5, #1

(856) 0x45c4a8 B.EQ	45c540

(856) 0x45c4ac CMP	X5, #2

(856) 0x45c4b0 B.EQ	45c530

(856) 0x45c4b4 CMP	X5, #3

(856) 0x45c4b8 B.EQ	45c520

(856) 0x45c4bc CMP	X5, #4

(856) 0x45c4c0 B.EQ	45c510

(856) 0x45c4c4 CMP	X5, #5

(856) 0x45c4c8 B.EQ	45c500

(856) 0x45c4cc CMP	X5, #6

(856) 0x45c4d0 B.EQ	45c4f0

(856) 0x45c4d4 LDR	Q27, [X20, X2]

(856) 0x45c4d8 ADD	X0, X0, #32

(856) 0x45c4dc LDUR	Q17, [X0, #496]

(856) 0x45c4e0 FMUL	V30.2D, V27.2D, V23.2D

(856) 0x45c4e4 FMUL	V18.2D, V17.2D, V23.2D

(856) 0x45c4e8 STR	Q30, [X20, X2]

(856) 0x45c4ec STUR	Q18, [X0, #496]

(856) 0x45c4f0 LDP	Q0, Q28, [X0]

(856) 0x45c4f4 FMUL	V26.2D, V0.2D, V23.2D

(856) 0x45c4f8 FMUL	V1.2D, V28.2D, V23.2D

(856) 0x45c4fc STP	Q26, Q1, [X0], #32

(856) 0x45c500 LDP	Q25, Q24, [X0]

(856) 0x45c504 FMUL	V2.2D, V25.2D, V23.2D

(856) 0x45c508 FMUL	V7.2D, V24.2D, V23.2D

(856) 0x45c50c STP	Q2, Q7, [X0], #32

(856) 0x45c510 LDP	Q3, Q6, [X0]

(856) 0x45c514 FMUL	V16.2D, V3.2D, V23.2D

(856) 0x45c518 FMUL	V5.2D, V6.2D, V23.2D

(856) 0x45c51c STP	Q16, Q5, [X0], #32

(856) 0x45c520 LDP	Q19, Q4, [X0]

(856) 0x45c524 FMUL	V29.2D, V19.2D, V23.2D

(856) 0x45c528 FMUL	V21.2D, V4.2D, V23.2D

(856) 0x45c52c STP	Q29, Q21, [X0], #32

(856) 0x45c530 LDP	Q22, Q20, [X0]

(856) 0x45c534 FMUL	V27.2D, V22.2D, V23.2D

(856) 0x45c538 FMUL	V30.2D, V20.2D, V23.2D

(856) 0x45c53c STP	Q27, Q30, [X0], #32

(856) 0x45c540 LDP	Q17, Q18, [X0]

(856) 0x45c544 FMUL	V0.2D, V17.2D, V23.2D

(856) 0x45c548 FMUL	V28.2D, V18.2D, V23.2D

(856) 0x45c54c STP	Q0, Q28, [X0], #32

(856) 0x45c550 CMP	X3, X0

(856) 0x45c554 B.EQ	45c5fc

(856) 0x45c558 STP	X26, X15, [SP, #144]

(856) 0x45c55c STP	X23, X22, [SP, #160]

  (858) 0x45c560 ORR	X22, XZR, X0

  (858) 0x45c564 LDP	Q26, Q1, [X0]

  (858) 0x45c568 LDP	Q29, Q21, [X0, #32]

  (858) 0x45c56c LDP	Q22, Q19, [X0, #64]

  (858) 0x45c570 LDP	Q16, Q27, [X0, #96]

  (858) 0x45c574 LDP	Q6, Q7, [X0, #128]

  (858) 0x45c578 FMUL	V25.2D, V26.2D, V23.2D

  (858) 0x45c57c LDP	Q0, Q5, [X0, #160]

  (858) 0x45c580 FMUL	V24.2D, V1.2D, V23.2D

  (858) 0x45c584 LDP	Q3, Q4, [X0, #192]

  (858) 0x45c588 FMUL	V20.2D, V29.2D, V23.2D

  (858) 0x45c58c LDP	Q30, Q2, [X0, #224]

  (858) 0x45c590 ADD	X0, X0, #256

  (858) 0x45c594 FMUL	V28.2D, V21.2D, V23.2D

  (858) 0x45c598 FMUL	V18.2D, V22.2D, V23.2D

  (858) 0x45c59c FMUL	V26.2D, V19.2D, V23.2D

  (858) 0x45c5a0 FMUL	V1.2D, V16.2D, V23.2D

  (858) 0x45c5a4 FMUL	V17.2D, V27.2D, V23.2D

  (858) 0x45c5a8 FMUL	V29.2D, V7.2D, V23.2D

  (858) 0x45c5ac FMUL	V21.2D, V5.2D, V23.2D

  (858) 0x45c5b0 FMUL	V22.2D, V3.2D, V23.2D

  (858) 0x45c5b4 FMUL	V19.2D, V4.2D, V23.2D

  (858) 0x45c5b8 FMUL	V16.2D, V30.2D, V23.2D

  (858) 0x45c5bc STP	Q25, Q24, [X0, #1792]

  (858) 0x45c5c0 FMUL	V25.2D, V6.2D, V23.2D

  (858) 0x45c5c4 FMUL	V24.2D, V0.2D, V23.2D

  (858) 0x45c5c8 FMUL	V27.2D, V2.2D, V23.2D

  (858) 0x45c5cc STUR	Q16, [X0, #480]

  (858) 0x45c5d0 STP	Q20, Q28, [X0, #1824]

  (858) 0x45c5d4 STP	Q18, Q26, [X0, #1856]

  (858) 0x45c5d8 STP	Q1, Q17, [X0, #1888]

  (858) 0x45c5dc STP	Q25, Q29, [X0, #1920]

  (858) 0x45c5e0 STP	Q24, Q21, [X0, #1952]

  (858) 0x45c5e4 STP	Q22, Q19, [X0, #1984]

  (858) 0x45c5e8 STR	Q27, [X22, #240]

  (858) 0x45c5ec CMP	X3, X0

  (858) 0x45c5f0 B.NE	45c560

(856) 0x45c5f4 LDP	X26, X15, [SP, #144]

(856) 0x45c5f8 LDP	X23, X22, [SP, #160]

(856) 0x45c5fc AND	X2, X13, #8062

(856) 0x45c600 ADD	X1, X1, X2

(856) 0x45c604 ANDS	XZR, X13, #4160

(856) 0x45c608 B.EQ	45c654

(856) 0x45c60c UBFM	X13, X1, #61, #60

(856) 0x45c610 ADD	X3, X1, #1

(856) 0x45c614 LDR	D23, [X20, X13]

(856) 0x45c618 FMUL	D6, D23, D31

(856) 0x45c61c STR	D6, [X20, X13]

(856) 0x45c620 CMP	X14, X3

(856) 0x45c624 B.LE	45c654

(856) 0x45c628 ADD	X5, X13, #8

(856) 0x45c62c ADD	X0, X1, #2

(856) 0x45c630 LDR	D7, [X20, X5]

(856) 0x45c634 FMUL	D0, D7, D31

(856) 0x45c638 STR	D0, [X20, X5]

(856) 0x45c63c CMP	X0, X14

(856) 0x45c640 B.GE	45c654

(856) 0x45c644 ADD	X14, X13, #16

(856) 0x45c648 LDR	D5, [X20, X14]

(856) 0x45c64c FMUL	D3, D5, D31

(856) 0x45c650 STR	D3, [X20, X14]

(856) 0x45c654 LDR	X2, [SP, #112]

(856) 0x45c658 LDR	X1, [X2, X4]

(856) 0x45c65c LDR	X8, [X2, X8]

(856) 0x45c660 CMP	X1, X8

(856) 0x45c664 B.GE	45c84c

(856) 0x45c668 SUB	X5, X8, X1

(856) 0x45c66c SUB	X4, X5, #1

(856) 0x45c670 CMP	X4, #2

(856) 0x45c674 B.LS	45c804

(856) 0x45c678 UBFM	X3, X5, #2, #63

(856) 0x45c67c ADD	X0, X19, X1,LSL #3

(856) 0x45c680 DUP	V28.2D, V31.D[0]

(856) 0x45c684 UBFM	X13, X1, #61, #60

(856) 0x45c688 UBFM	X14, X3, #59, #58

(856) 0x45c68c SUB	X2, X14, #32

(856) 0x45c690 ADD	X3, X0, X3,LSL #5

(856) 0x45c694 UBFM	X4, X2, #5, #63

(856) 0x45c698 ADD	X14, X4, #1

(856) 0x45c69c ANDS	X2, X14, #4224

(856) 0x45c6a0 B.EQ	45c758

(856) 0x45c6a4 CMP	X2, #1

(856) 0x45c6a8 B.EQ	45c740

(856) 0x45c6ac CMP	X2, #2

(856) 0x45c6b0 B.EQ	45c730

(856) 0x45c6b4 CMP	X2, #3

(856) 0x45c6b8 B.EQ	45c720

(856) 0x45c6bc CMP	X2, #4

(856) 0x45c6c0 B.EQ	45c710

(856) 0x45c6c4 CMP	X2, #5

(856) 0x45c6c8 B.EQ	45c700

(856) 0x45c6cc CMP	X2, #6

(856) 0x45c6d0 B.EQ	45c6f0

(856) 0x45c6d4 LDR	Q4, [X19, X13]

(856) 0x45c6d8 ADD	X0, X0, #32

(856) 0x45c6dc LDUR	Q2, [X0, #496]

(856) 0x45c6e0 FMUL	V30.2D, V4.2D, V28.2D

(856) 0x45c6e4 FMUL	V20.2D, V2.2D, V28.2D

(856) 0x45c6e8 STR	Q30, [X19, X13]

(856) 0x45c6ec STUR	Q20, [X0, #496]

(856) 0x45c6f0 LDP	Q18, Q26, [X0]

(856) 0x45c6f4 FMUL	V1.2D, V18.2D, V28.2D

(856) 0x45c6f8 FMUL	V17.2D, V26.2D, V28.2D

(856) 0x45c6fc STP	Q1, Q17, [X0], #32

(856) 0x45c700 LDP	Q25, Q29, [X0]

(856) 0x45c704 FMUL	V24.2D, V25.2D, V28.2D

(856) 0x45c708 FMUL	V21.2D, V29.2D, V28.2D

(856) 0x45c70c STP	Q24, Q21, [X0], #32

(856) 0x45c710 LDP	Q22, Q19, [X0]

(856) 0x45c714 FMUL	V16.2D, V22.2D, V28.2D

(856) 0x45c718 FMUL	V27.2D, V19.2D, V28.2D

(856) 0x45c71c STP	Q16, Q27, [X0], #32

(856) 0x45c720 LDP	Q23, Q6, [X0]

(856) 0x45c724 FMUL	V7.2D, V23.2D, V28.2D

(856) 0x45c728 FMUL	V0.2D, V6.2D, V28.2D

(856) 0x45c72c STP	Q7, Q0, [X0], #32

(856) 0x45c730 LDP	Q5, Q4, [X0]

(856) 0x45c734 FMUL	V3.2D, V5.2D, V28.2D

(856) 0x45c738 FMUL	V30.2D, V4.2D, V28.2D

(856) 0x45c73c STP	Q3, Q30, [X0], #32

(856) 0x45c740 LDP	Q20, Q2, [X0]

(856) 0x45c744 FMUL	V18.2D, V20.2D, V28.2D

(856) 0x45c748 FMUL	V26.2D, V2.2D, V28.2D

(856) 0x45c74c STP	Q18, Q26, [X0], #32

(856) 0x45c750 CMP	X3, X0

(856) 0x45c754 B.EQ	45c7f4

(856) 0x45c758 STP	X26, X15, [SP, #144]

  (857) 0x45c75c ORR	X15, XZR, X0

  (857) 0x45c760 LDP	Q1, Q17, [X0]

  (857) 0x45c764 LDP	Q21, Q22, [X0, #32]

  (857) 0x45c768 LDP	Q19, Q27, [X0, #64]

  (857) 0x45c76c LDP	Q23, Q0, [X0, #96]

  (857) 0x45c770 LDP	Q7, Q16, [X0, #128]

  (857) 0x45c774 FMUL	V25.2D, V1.2D, V28.2D

  (857) 0x45c778 LDP	Q5, Q6, [X0, #160]

  (857) 0x45c77c FMUL	V29.2D, V17.2D, V28.2D

  (857) 0x45c780 LDP	Q3, Q4, [X0, #192]

  (857) 0x45c784 FMUL	V26.2D, V21.2D, V28.2D

  (857) 0x45c788 LDP	Q30, Q24, [X0, #224]

  (857) 0x45c78c ADD	X0, X0, #256

  (857) 0x45c790 FMUL	V1.2D, V22.2D, V28.2D

  (857) 0x45c794 FMUL	V20.2D, V27.2D, V28.2D

  (857) 0x45c798 FMUL	V17.2D, V23.2D, V28.2D

  (857) 0x45c79c FMUL	V18.2D, V0.2D, V28.2D

  (857) 0x45c7a0 FMUL	V21.2D, V16.2D, V28.2D

  (857) 0x45c7a4 FMUL	V22.2D, V5.2D, V28.2D

  (857) 0x45c7a8 FMUL	V27.2D, V3.2D, V28.2D

  (857) 0x45c7ac FMUL	V23.2D, V4.2D, V28.2D

  (857) 0x45c7b0 FMUL	V2.2D, V30.2D, V28.2D

  (857) 0x45c7b4 STP	Q25, Q29, [X0, #1792]

  (857) 0x45c7b8 FMUL	V25.2D, V19.2D, V28.2D

  (857) 0x45c7bc FMUL	V29.2D, V7.2D, V28.2D

  (857) 0x45c7c0 FMUL	V19.2D, V6.2D, V28.2D

  (857) 0x45c7c4 STUR	Q2, [X0, #480]

  (857) 0x45c7c8 FMUL	V0.2D, V24.2D, V28.2D

  (857) 0x45c7cc STP	Q26, Q1, [X0, #1824]

  (857) 0x45c7d0 STP	Q25, Q20, [X0, #1856]

  (857) 0x45c7d4 STP	Q17, Q18, [X0, #1888]

  (857) 0x45c7d8 STP	Q29, Q21, [X0, #1920]

  (857) 0x45c7dc STP	Q22, Q19, [X0, #1952]

  (857) 0x45c7e0 STP	Q27, Q23, [X0, #1984]

  (857) 0x45c7e4 STR	Q0, [X15, #240]

  (857) 0x45c7e8 CMP	X3, X0

  (857) 0x45c7ec B.NE	45c75c

(856) 0x45c7f0 LDP	X26, X15, [SP, #144]

(856) 0x45c7f4 AND	X13, X5, #8062

(856) 0x45c7f8 ADD	X1, X1, X13

(856) 0x45c7fc ANDS	XZR, X5, #4160

(856) 0x45c800 B.EQ	45c84c

(856) 0x45c804 UBFM	X5, X1, #61, #60

(856) 0x45c808 ADD	X3, X1, #1

(856) 0x45c80c LDR	D28, [X19, X5]

(856) 0x45c810 FMUL	D7, D28, D31

(856) 0x45c814 STR	D7, [X19, X5]

(856) 0x45c818 CMP	X3, X8

(856) 0x45c81c B.GE	45c84c

(856) 0x45c820 ADD	X4, X5, #8

(856) 0x45c824 ADD	X14, X1, #2

(856) 0x45c828 LDR	D16, [X19, X4]

(856) 0x45c82c FMUL	D5, D16, D31

(856) 0x45c830 STR	D5, [X19, X4]

(856) 0x45c834 CMP	X8, X14

(856) 0x45c838 B.LE	45c84c

(856) 0x45c83c ADD	X8, X5, #16

(856) 0x45c840 LDR	D6, [X19, X8]

(856) 0x45c844 FMUL	D3, D6, D31

(856) 0x45c848 STR	D3, [X19, X8]

(856) 0x45c84c LDR	X2, [SP, #128]

(856) 0x45c850 LDR	X13, [SP, #240]

(856) 0x45c854 ADD	X0, X2, #8

(856) 0x45c858 STR	X0, [SP, #128]

(856) 0x45c85c CMP	X13, X0

(856) 0x45c860 B.NE	45bec0

0x45c864 ORR	X0, XZR, X26

0x45c868 STR	X15, [SP, #96]

0x45c86c BL	546e20

0x45c870 LDR	X0, [SP, #96]

0x45c874 BL	546e20

0x45c878 ORR	X0, XZR, X23

0x45c87c BL	546e20

0x45c880 ORR	X0, XZR, X22

0x45c884 LDP	X19, X20, [SP, #16]

0x45c888 LDP	X21, X22, [SP, #32]

0x45c88c LDP	X23, X24, [SP, #48]

0x45c890 LDP	X25, X26, [SP, #64]

0x45c894 LDP	X27, X28, [SP, #80]

0x45c898 LDP	X29, X30, [SP], #368

0x45c89c B	546e20

  (864) 0x45c8a0 STR	X3, [X15, X0]

  (864) 0x45c8a4 ADD	X1, X1, #1

  (864) 0x45c8a8 LDR	X13, [X14]

  (864) 0x45c8ac CMP	X13, X1

  (864) 0x45c8b0 B.GT	45c2e0

(856) 0x45c8b4 B	45c304

  (865) 0x45c8b8 STR	X3, [X26, X0]

  (865) 0x45c8bc ADD	X1, X1, #1

  (865) 0x45c8c0 LDR	X13, [X14]

  (865) 0x45c8c4 CMP	X13, X1

  (865) 0x45c8c8 B.GT	45c2a4

(856) 0x45c8cc B	45c2c8

  (861) 0x45c8d0 LDR	X28, [SP, #120]

  (861) 0x45c8d4 ADD	X11, X2, #8

  (861) 0x45c8d8 LDR	X5, [X28, X2]

  (861) 0x45c8dc LDR	X15, [X28, X11]

  (861) 0x45c8e0 CMP	X5, X15

  (861) 0x45c8e4 B.GE	45ca74

  (861) 0x45c8e8 SUB	X28, X15, X5

  (861) 0x45c8ec ANDS	X28, X28, #4160

  (861) 0x45c8f0 B.EQ	45c99c

  (861) 0x45c8f4 CMP	X28, #1

  (861) 0x45c8f8 B.EQ	45c964

  (861) 0x45c8fc CMP	X28, #2

  (861) 0x45c900 B.EQ	45c934

  (861) 0x45c904 LDR	X28, [X25, X5,LSL #3]

  (861) 0x45c908 LDR	D17, [X20, X5,LSL #3]

  (861) 0x45c90c ADD	X5, X5, #1

  (861) 0x45c910 LDR	D18, [X21, X0,LSL #3]

  (861) 0x45c914 LDR	X28, [X23, X28,LSL #3]

  (861) 0x45c918 FMUL	D0, D18, D17

  (861) 0x45c91c UBFM	X28, X28, #61, #60

  (861) 0x45c920 LDR	D26, [X20, X28]

  (861) 0x45c924 FADD	D29, D29, D0

  (861) 0x45c928 FADD	D20, D20, D0

  (861) 0x45c92c FADD	D1, D26, D0

  (861) 0x45c930 STR	D1, [X20, X28]

  (861) 0x45c934 LDR	X28, [X25, X5,LSL #3]

  (861) 0x45c938 LDR	D24, [X20, X5,LSL #3]

  (861) 0x45c93c ADD	X5, X5, #1

  (861) 0x45c940 LDR	D25, [X21, X0,LSL #3]

  (861) 0x45c944 LDR	X28, [X23, X28,LSL #3]

  (861) 0x45c948 FMUL	D2, D25, D24

  (861) 0x45c94c UBFM	X28, X28, #61, #60

  (861) 0x45c950 LDR	D7, [X20, X28]

  (861) 0x45c954 FADD	D29, D29, D2

  (861) 0x45c958 FADD	D20, D20, D2

  (861) 0x45c95c FADD	D3, D7, D2

  (861) 0x45c960 STR	D3, [X20, X28]

  (861) 0x45c964 LDR	X28, [X25, X5,LSL #3]

  (861) 0x45c968 LDR	D5, [X20, X5,LSL #3]

  (861) 0x45c96c ADD	X5, X5, #1

  (861) 0x45c970 LDR	D6, [X21, X0,LSL #3]

  (861) 0x45c974 LDR	X28, [X23, X28,LSL #3]

  (861) 0x45c978 FMUL	D31, D6, D5

  (861) 0x45c97c UBFM	X28, X28, #61, #60

  (861) 0x45c980 LDR	D4, [X20, X28]

  (861) 0x45c984 FADD	D29, D29, D31

  (861) 0x45c988 FADD	D20, D20, D31

  (861) 0x45c98c FADD	D16, D4, D31

  (861) 0x45c990 STR	D16, [X20, X28]

  (861) 0x45c994 CMP	X5, X15

  (861) 0x45c998 B.EQ	45ca74

  (861) 0x45c99c STP	X26, X22, [SP, #160]

  (861) 0x45c9a0 STP	X6, X13, [SP, #176]

    (863) 0x45c9a4 ADD	X13, X5, #1

    (863) 0x45c9a8 ADD	X26, X5, #3

    (863) 0x45c9ac ADD	X28, X13, #1

    (863) 0x45c9b0 LDR	X22, [X25, X5,LSL #3]

    (863) 0x45c9b4 LDR	D19, [X21, X0,LSL #3]

    (863) 0x45c9b8 LDR	D21, [X20, X5,LSL #3]

    (863) 0x45c9bc ADD	X5, X5, #4

    (863) 0x45c9c0 LDR	X6, [X23, X22,LSL #3]

    (863) 0x45c9c4 LDR	X22, [X25, X13,LSL #3]

    (863) 0x45c9c8 FMUL	D22, D19, D21

    (863) 0x45c9cc UBFM	X6, X6, #61, #60

    (863) 0x45c9d0 LDR	D23, [X20, X6]

    (863) 0x45c9d4 LDR	X22, [X23, X22,LSL #3]

    (863) 0x45c9d8 FADD	D27, D29, D22

    (863) 0x45c9dc FADD	D30, D20, D22

    (863) 0x45c9e0 FADD	D31, D23, D22

    (863) 0x45c9e4 UBFM	X22, X22, #61, #60

    (863) 0x45c9e8 STR	D31, [X20, X6]

    (863) 0x45c9ec LDR	D18, [X20, X13,LSL #3]

    (863) 0x45c9f0 LDR	D28, [X21, X0,LSL #3]

    (863) 0x45c9f4 LDR	D17, [X20, X22]

    (863) 0x45c9f8 LDR	X13, [X25, X28,LSL #3]

    (863) 0x45c9fc FMUL	D0, D28, D18

    (863) 0x45ca00 LDR	X6, [X25, X26,LSL #3]

    (863) 0x45ca04 LDR	X13, [X23, X13,LSL #3]

    (863) 0x45ca08 LDR	X6, [X23, X6,LSL #3]

    (863) 0x45ca0c FADD	D26, D17, D0

    (863) 0x45ca10 FADD	D1, D27, D0

    (863) 0x45ca14 FADD	D25, D30, D0

    (863) 0x45ca18 UBFM	X13, X13, #61, #60

    (863) 0x45ca1c UBFM	X6, X6, #61, #60

    (863) 0x45ca20 STR	D26, [X20, X22]

    (863) 0x45ca24 LDR	D24, [X21, X0,LSL #3]

    (863) 0x45ca28 LDR	D2, [X20, X28,LSL #3]

    (863) 0x45ca2c LDR	D7, [X20, X13]

    (863) 0x45ca30 FMUL	D3, D24, D2

    (863) 0x45ca34 FADD	D6, D7, D3

    (863) 0x45ca38 FADD	D5, D1, D3

    (863) 0x45ca3c FADD	D4, D25, D3

    (863) 0x45ca40 STR	D6, [X20, X13]

    (863) 0x45ca44 LDR	D29, [X21, X0,LSL #3]

    (863) 0x45ca48 LDR	D20, [X20, X26,LSL #3]

    (863) 0x45ca4c LDR	D16, [X20, X6]

    (863) 0x45ca50 FMUL	D31, D29, D20

    (863) 0x45ca54 FADD	D19, D16, D31

    (863) 0x45ca58 FADD	D29, D5, D31

    (863) 0x45ca5c FADD	D20, D4, D31

    (863) 0x45ca60 STR	D19, [X20, X6]

    (863) 0x45ca64 CMP	X5, X15

    (863) 0x45ca68 B.NE	45c9a4

  (861) 0x45ca6c LDP	X26, X22, [SP, #160]

  (861) 0x45ca70 LDP	X6, X13, [SP, #176]

  (861) 0x45ca74 LDR	X15, [SP, #112]

  (861) 0x45ca78 LDR	X2, [X15, X2]

  (861) 0x45ca7c LDR	X28, [X15, X11]

  (861) 0x45ca80 CMP	X2, X28

  (861) 0x45ca84 B.GE	45c348

  (861) 0x45ca88 SUB	X11, X28, X2

  (861) 0x45ca8c ANDS	X5, X11, #4160

  (861) 0x45ca90 B.EQ	45cb3c

  (861) 0x45ca94 CMP	X5, #1

  (861) 0x45ca98 B.EQ	45cb04

  (861) 0x45ca9c CMP	X5, #2

  (861) 0x45caa0 B.EQ	45cad4

  (861) 0x45caa4 LDR	X15, [X24, X2,LSL #3]

  (861) 0x45caa8 LDR	D22, [X19, X2,LSL #3]

  (861) 0x45caac ADD	X2, X2, #1

  (861) 0x45cab0 LDR	D21, [X21, X0,LSL #3]

  (861) 0x45cab4 LDR	X11, [X22, X15,LSL #3]

  (861) 0x45cab8 FMUL	D23, D21, D22

  (861) 0x45cabc UBFM	X5, X11, #61, #60

  (861) 0x45cac0 LDR	D27, [X19, X5]

  (861) 0x45cac4 FADD	D29, D29, D23

  (861) 0x45cac8 FADD	D20, D20, D23

  (861) 0x45cacc FADD	D30, D27, D23

  (861) 0x45cad0 STR	D30, [X19, X5]

  (861) 0x45cad4 LDR	X15, [X24, X2,LSL #3]

  (861) 0x45cad8 LDR	D28, [X19, X2,LSL #3]

  (861) 0x45cadc ADD	X2, X2, #1

  (861) 0x45cae0 LDR	D31, [X21, X0,LSL #3]

  (861) 0x45cae4 LDR	X11, [X22, X15,LSL #3]

  (861) 0x45cae8 FMUL	D18, D31, D28

  (861) 0x45caec UBFM	X5, X11, #61, #60

  (861) 0x45caf0 LDR	D17, [X19, X5]

  (861) 0x45caf4 FADD	D29, D29, D18

  (861) 0x45caf8 FADD	D20, D20, D18

  (861) 0x45cafc FADD	D0, D17, D18

  (861) 0x45cb00 STR	D0, [X19, X5]

  (861) 0x45cb04 LDR	X15, [X24, X2,LSL #3]

  (861) 0x45cb08 LDR	D1, [X19, X2,LSL #3]

  (861) 0x45cb0c ADD	X2, X2, #1

  (861) 0x45cb10 LDR	D26, [X21, X0,LSL #3]

  (861) 0x45cb14 LDR	X11, [X22, X15,LSL #3]

  (861) 0x45cb18 FMUL	D31, D26, D1

  (861) 0x45cb1c UBFM	X5, X11, #61, #60

  (861) 0x45cb20 LDR	D25, [X19, X5]

  (861) 0x45cb24 FADD	D29, D29, D31

  (861) 0x45cb28 FADD	D20, D20, D31

  (861) 0x45cb2c FADD	D24, D25, D31

  (861) 0x45cb30 STR	D24, [X19, X5]

  (861) 0x45cb34 CMP	X2, X28

  (861) 0x45cb38 B.EQ	45c348

  (861) 0x45cb3c STP	X26, X23, [SP, #160]

    (862) 0x45cb40 ADD	X11, X2, #1

    (862) 0x45cb44 ADD	X23, X2, #3

    (862) 0x45cb48 LDR	X26, [X24, X2,LSL #3]

    (862) 0x45cb4c LDR	D2, [X21, X0,LSL #3]

    (862) 0x45cb50 LDR	D7, [X19, X2,LSL #3]

    (862) 0x45cb54 ADD	X2, X2, #4

    (862) 0x45cb58 LDR	X15, [X22, X26,LSL #3]

    (862) 0x45cb5c ADD	X26, X11, #1

    (862) 0x45cb60 FMUL	D3, D2, D7

    (862) 0x45cb64 UBFM	X5, X15, #61, #60

    (862) 0x45cb68 LDR	X15, [X24, X11,LSL #3]

    (862) 0x45cb6c LDR	D6, [X19, X5]

    (862) 0x45cb70 FADD	D5, D29, D3

    (862) 0x45cb74 LDR	X15, [X22, X15,LSL #3]

    (862) 0x45cb78 FADD	D4, D20, D3

    (862) 0x45cb7c FADD	D29, D6, D3

    (862) 0x45cb80 UBFM	X15, X15, #61, #60

    (862) 0x45cb84 STR	D29, [X19, X5]

    (862) 0x45cb88 LDR	D20, [X21, X0,LSL #3]

    (862) 0x45cb8c LDR	D16, [X19, X11,LSL #3]

    (862) 0x45cb90 LDR	D19, [X19, X15]

    (862) 0x45cb94 LDR	X11, [X24, X26,LSL #3]

    (862) 0x45cb98 FMUL	D21, D20, D16

    (862) 0x45cb9c LDR	X5, [X24, X23,LSL #3]

    (862) 0x45cba0 LDR	X11, [X22, X11,LSL #3]

    (862) 0x45cba4 LDR	X5, [X22, X5,LSL #3]

    (862) 0x45cba8 FADD	D22, D19, D21

    (862) 0x45cbac FADD	D23, D5, D21

    (862) 0x45cbb0 FADD	D27, D4, D21

    (862) 0x45cbb4 UBFM	X11, X11, #61, #60

    (862) 0x45cbb8 UBFM	X5, X5, #61, #60

    (862) 0x45cbbc STR	D22, [X19, X15]

    (862) 0x45cbc0 LDR	D31, [X19, X26,LSL #3]

    (862) 0x45cbc4 LDR	D30, [X21, X0,LSL #3]

    (862) 0x45cbc8 LDR	D28, [X19, X11]

    (862) 0x45cbcc FMUL	D17, D30, D31

    (862) 0x45cbd0 FADD	D18, D28, D17

    (862) 0x45cbd4 FADD	D0, D23, D17

    (862) 0x45cbd8 FADD	D26, D27, D17

    (862) 0x45cbdc STR	D18, [X19, X11]

    (862) 0x45cbe0 LDR	D1, [X21, X0,LSL #3]

    (862) 0x45cbe4 LDR	D25, [X19, X23,LSL #3]

    (862) 0x45cbe8 LDR	D24, [X19, X5]

    (862) 0x45cbec FMUL	D31, D1, D25

    (862) 0x45cbf0 FADD	D2, D24, D31

    (862) 0x45cbf4 FADD	D29, D0, D31

    (862) 0x45cbf8 FADD	D20, D26, D31

    (862) 0x45cbfc STR	D2, [X19, X5]

    (862) 0x45cc00 CMP	X2, X28

    (862) 0x45cc04 B.NE	45cb40

  (861) 0x45cc08 LDP	X26, X23, [SP, #160]

  (861) 0x45cc0c B	45c348

  (859) 0x45cc10 LDP	X13, X26, [SP, #296]

  (859) 0x45cc14 ADD	X28, X13, X2

  (859) 0x45cc18 LDR	X2, [X26, X2]

  (859) 0x45cc1c LDR	X13, [X28, #8]

  (859) 0x45cc20 ADD	X26, X2, X13

  (859) 0x45cc24 CMP	X2, X26

  (859) 0x45cc28 B.GE	45c3dc

  (859) 0x45cc2c LDR	X28, [SP, #136]

  (859) 0x45cc30 LDR	X13, [SP, #312]

  (859) 0x45cc34 LDR	X13, [X13, X28]

  (859) 0x45cc38 SUB	X28, X26, X2

  (859) 0x45cc3c ANDS	X28, X28, #4160

  (859) 0x45cc40 B.EQ	45cdc0

  (859) 0x45cc44 CMP	X28, #1

  (859) 0x45cc48 B.EQ	45ccbc

  (859) 0x45cc4c CMP	X28, #2

  (859) 0x45cc50 B.EQ	45cc88

  (859) 0x45cc54 LDR	D3, [X17, X0,LSL #3]

  (859) 0x45cc58 LDR	D6, [X14, X2,LSL #3]

  (859) 0x45cc5c LDR	X28, [X13, X2,LSL #3]

  (859) 0x45cc60 FMUL	D16, D3, D6

  (859) 0x45cc64 TBNZ	X28, #63, 45cee4

  (859) 0x45cc68 LDR	X28, [X22, X28,LSL #3]

  (859) 0x45cc6c UBFM	X28, X28, #61, #60

  (859) 0x45cc70 LDR	D5, [X19, X28]

  (859) 0x45cc74 FADD	D4, D5, D16

  (859) 0x45cc78 STR	D4, [X19, X28]

  (859) 0x45cc7c FADD	D29, D29, D16

  (859) 0x45cc80 FADD	D20, D20, D16

  (859) 0x45cc84 ADD	X2, X2, #1

  (859) 0x45cc88 LDR	D22, [X17, X0,LSL #3]

  (859) 0x45cc8c LDR	D23, [X14, X2,LSL #3]

  (859) 0x45cc90 LDR	X28, [X13, X2,LSL #3]

  (859) 0x45cc94 FMUL	D27, D22, D23

  (859) 0x45cc98 TBNZ	X28, #63, 45ceb4

  (859) 0x45cc9c LDR	X28, [X22, X28,LSL #3]

  (859) 0x45cca0 UBFM	X28, X28, #61, #60

  (859) 0x45cca4 LDR	D30, [X19, X28]

  (859) 0x45cca8 FADD	D31, D30, D27

  (859) 0x45ccac STR	D31, [X19, X28]

  (859) 0x45ccb0 FADD	D29, D29, D27

  (859) 0x45ccb4 FADD	D20, D20, D27

  (859) 0x45ccb8 ADD	X2, X2, #1

  (859) 0x45ccbc LDR	D18, [X17, X0,LSL #3]

  (859) 0x45ccc0 LDR	D0, [X14, X2,LSL #3]

  (859) 0x45ccc4 LDR	X28, [X13, X2,LSL #3]

  (859) 0x45ccc8 FMUL	D31, D18, D0

  (859) 0x45cccc TBNZ	X28, #63, 45ce98

  (859) 0x45ccd0 LDR	X28, [X22, X28,LSL #3]

  (859) 0x45ccd4 UBFM	X28, X28, #61, #60

  (859) 0x45ccd8 LDR	D26, [X19, X28]

  (859) 0x45ccdc FADD	D1, D26, D31

  (859) 0x45cce0 STR	D1, [X19, X28]

  (859) 0x45cce4 ADD	X2, X2, #1

  (859) 0x45cce8 FADD	D29, D29, D31

  (859) 0x45ccec FADD	D20, D20, D31

  (859) 0x45ccf0 CMP	X26, X2

  (859) 0x45ccf4 B.NE	45cdc0

  (859) 0x45ccf8 B	45c3dc

    (860) 0x45ccfc LDR	X28, [X22, X28,LSL #3]

    (860) 0x45cd00 ADD	X2, X2, #1

    (860) 0x45cd04 FADD	D29, D29, D3

    (860) 0x45cd08 FADD	D20, D20, D3

    (860) 0x45cd0c UBFM	X28, X28, #61, #60

    (860) 0x45cd10 LDR	D6, [X19, X28]

    (860) 0x45cd14 FADD	D16, D6, D3

    (860) 0x45cd18 STR	D16, [X19, X28]

    (860) 0x45cd1c LDR	D19, [X17, X0,LSL #3]

    (860) 0x45cd20 LDR	D21, [X14, X2,LSL #3]

    (860) 0x45cd24 LDR	X28, [X13, X2,LSL #3]

    (860) 0x45cd28 FMUL	D22, D19, D21

    (860) 0x45cd2c TBNZ	X28, #63, 45ce0c

    (860) 0x45cd30 LDR	X28, [X22, X28,LSL #3]

    (860) 0x45cd34 FADD	D18, D29, D22

    (860) 0x45cd38 FADD	D0, D20, D22

    (860) 0x45cd3c UBFM	X28, X28, #61, #60

    (860) 0x45cd40 LDR	D23, [X19, X28]

    (860) 0x45cd44 FADD	D27, D23, D22

    (860) 0x45cd48 STR	D27, [X19, X28]

    (860) 0x45cd4c ADD	X28, X2, #1

    (860) 0x45cd50 LDR	D17, [X17, X0,LSL #3]

    (860) 0x45cd54 LDR	D28, [X14, X28,LSL #3]

    (860) 0x45cd58 LDR	X28, [X13, X28,LSL #3]

    (860) 0x45cd5c FMUL	D26, D17, D28

    (860) 0x45cd60 TBNZ	X28, #63, 45ce44

    (860) 0x45cd64 LDR	X28, [X22, X28,LSL #3]

    (860) 0x45cd68 FADD	D3, D18, D26

    (860) 0x45cd6c FADD	D6, D0, D26

    (860) 0x45cd70 UBFM	X28, X28, #61, #60

    (860) 0x45cd74 LDR	D1, [X19, X28]

    (860) 0x45cd78 FADD	D25, D1, D26

    (860) 0x45cd7c STR	D25, [X19, X28]

    (860) 0x45cd80 ADD	X28, X2, #2

    (860) 0x45cd84 LDR	D7, [X17, X0,LSL #3]

    (860) 0x45cd88 LDR	D16, [X14, X28,LSL #3]

    (860) 0x45cd8c LDR	X28, [X13, X28,LSL #3]

    (860) 0x45cd90 FMUL	D31, D7, D16

    (860) 0x45cd94 TBNZ	X28, #63, 45ce7c

    (860) 0x45cd98 LDR	X28, [X22, X28,LSL #3]

    (860) 0x45cd9c UBFM	X28, X28, #61, #60

    (860) 0x45cda0 LDR	D5, [X19, X28]

    (860) 0x45cda4 FADD	D4, D5, D31

    (860) 0x45cda8 STR	D4, [X19, X28]

    (860) 0x45cdac ADD	X2, X2, #3

    (860) 0x45cdb0 FADD	D29, D3, D31

    (860) 0x45cdb4 FADD	D20, D6, D31

    (860) 0x45cdb8 CMP	X26, X2

    (860) 0x45cdbc B.EQ	45c3dc

    (860) 0x45cdc0 LDR	D2, [X17, X0,LSL #3]

    (860) 0x45cdc4 LDR	D7, [X14, X2,LSL #3]

    (860) 0x45cdc8 LDR	X28, [X13, X2,LSL #3]

    (860) 0x45cdcc FMUL	D3, D2, D7

    (860) 0x45cdd0 TBZ	X28, #63, 45ccfc

    (860) 0x45cdd4 ORN	X28, XZR, X28

    (860) 0x45cdd8 ADD	X2, X2, #1

    (860) 0x45cddc FADD	D29, D29, D3

    (860) 0x45cde0 FADD	D20, D20, D3

    (860) 0x45cde4 LDR	X28, [X23, X28,LSL #3]

    (860) 0x45cde8 UBFM	X28, X28, #61, #60

    (860) 0x45cdec LDR	D5, [X20, X28]

    (860) 0x45cdf0 FADD	D4, D5, D3

    (860) 0x45cdf4 STR	D4, [X20, X28]

    (860) 0x45cdf8 LDR	D19, [X17, X0,LSL #3]

    (860) 0x45cdfc LDR	D21, [X14, X2,LSL #3]

    (860) 0x45ce00 LDR	X28, [X13, X2,LSL #3]

    (860) 0x45ce04 FMUL	D22, D19, D21

    (860) 0x45ce08 TBZ	X28, #63, 45cd30

    (860) 0x45ce0c ORN	X28, XZR, X28

    (860) 0x45ce10 FADD	D18, D29, D22

    (860) 0x45ce14 FADD	D0, D20, D22

    (860) 0x45ce18 LDR	X28, [X23, X28,LSL #3]

    (860) 0x45ce1c UBFM	X28, X28, #61, #60

    (860) 0x45ce20 LDR	D30, [X20, X28]

    (860) 0x45ce24 FADD	D31, D30, D22

    (860) 0x45ce28 STR	D31, [X20, X28]

    (860) 0x45ce2c ADD	X28, X2, #1

    (860) 0x45ce30 LDR	D17, [X17, X0,LSL #3]

    (860) 0x45ce34 LDR	D28, [X14, X28,LSL #3]

    (860) 0x45ce38 LDR	X28, [X13, X28,LSL #3]

    (860) 0x45ce3c FMUL	D26, D17, D28

    (860) 0x45ce40 TBZ	X28, #63, 45cd64

    (860) 0x45ce44 ORN	X28, XZR, X28

    (860) 0x45ce48 FADD	D3, D18, D26

    (860) 0x45ce4c FADD	D6, D0, D26

    (860) 0x45ce50 LDR	X28, [X23, X28,LSL #3]

    (860) 0x45ce54 UBFM	X28, X28, #61, #60

    (860) 0x45ce58 LDR	D24, [X20, X28]

    (860) 0x45ce5c FADD	D2, D24, D26

    (860) 0x45ce60 STR	D2, [X20, X28]

    (860) 0x45ce64 ADD	X28, X2, #2

    (860) 0x45ce68 LDR	D7, [X17, X0,LSL #3]

    (860) 0x45ce6c LDR	D16, [X14, X28,LSL #3]

    (860) 0x45ce70 LDR	X28, [X13, X28,LSL #3]

    (860) 0x45ce74 FMUL	D31, D7, D16

    (860) 0x45ce78 TBZ	X28, #63, 45cd98

    (860) 0x45ce7c ORN	X28, XZR, X28

    (860) 0x45ce80 LDR	X28, [X23, X28,LSL #3]

    (860) 0x45ce84 UBFM	X28, X28, #61, #60

    (860) 0x45ce88 LDR	D19, [X20, X28]

    (860) 0x45ce8c FADD	D29, D19, D31

    (860) 0x45ce90 STR	D29, [X20, X28]

    (860) 0x45ce94 B	45cdac

  (859) 0x45ce98 ORN	X28, XZR, X28

  (859) 0x45ce9c LDR	X28, [X23, X28,LSL #3]

  (859) 0x45cea0 UBFM	X28, X28, #61, #60

  (859) 0x45cea4 LDR	D25, [X20, X28]

  (859) 0x45cea8 FADD	D24, D25, D31

  (859) 0x45ceac STR	D24, [X20, X28]

  (859) 0x45ceb0 B	45cce4

  (859) 0x45ceb4 ORN	X28, XZR, X28

  (859) 0x45ceb8 LDR	X28, [X23, X28,LSL #3]

  (859) 0x45cebc UBFM	X28, X28, #61, #60

  (859) 0x45cec0 LDR	D28, [X20, X28]

  (859) 0x45cec4 FADD	D17, D28, D27

  (859) 0x45cec8 STR	D17, [X20, X28]

  (859) 0x45cecc B	45ccb0

(856) 0x45ced0 LDR	X2, [SP, #104]

(856) 0x45ced4 STP	X26, X15, [SP, #144]

(856) 0x45ced8 STP	X23, X28, [SP, #160]

(856) 0x45cedc STR	X9, [SP, #176]

(856) 0x45cee0 B	45c1d8

  (859) 0x45cee4 ORN	X28, XZR, X28

  (859) 0x45cee8 LDR	X28, [X23, X28,LSL #3]

  (859) 0x45ceec UBFM	X28, X28, #61, #60

  (859) 0x45cef0 LDR	D19, [X20, X28]

  (859) 0x45cef4 FADD	D21, D19, D16

  (859) 0x45cef8 STR	D21, [X20, X28]

  (859) 0x45cefc B	45cc7c

0x45cf00 ORR	X0, XZR, X22

0x45cf04 STR	X13, [SP, #136]

0x45cf08 STP	X8, X2, [SP, #152]

0x45cf0c STP	X6, X10, [SP, #168]

0x45cf10 STR	X11, [SP, #184]

0x45cf14 STR	X9, [SP, #240]

0x45cf18 STP	X12, X7, [SP, #320]

0x45cf1c B	45bd64

0x45cf20 ORR	X0, XZR, X23

0x45cf24 MOVZ	X1, #8

0x45cf28 STR	X13, [SP, #136]

0x45cf2c STP	X3, X8, [SP, #152]

0x45cf30 STP	X2, X6, [SP, #168]

0x45cf34 STR	X10, [SP, #184]

0x45cf38 STR	X11, [SP, #240]

0x45cf3c STP	X9, X12, [SP, #320]

0x45cf40 STR	X7, [SP, #360]

0x45cf44 BL	546d88

0x45cf48 LDR	X13, [SP, #136]

0x45cf4c ORR	X23, XZR, X0

0x45cf50 LDP	X3, X8, [SP, #152]

0x45cf54 LDP	X2, X6, [SP, #168]

0x45cf58 LDP	X9, X12, [SP, #320]

0x45cf5c LDR	X10, [SP, #184]

0x45cf60 LDR	X11, [SP, #240]

0x45cf64 LDR	X7, [SP, #360]

0x45cf68 B	45bd40

0x45cf6c MOVZ	X1, #8

0x45cf70 STR	X3, [SP, #136]

0x45cf74 STP	X8, X2, [SP, #152]

0x45cf78 STP	X6, X10, [SP, #168]

0x45cf7c STR	X11, [SP, #184]

0x45cf80 STR	X9, [SP, #240]

0x45cf84 STP	X12, X7, [SP, #320]

0x45cf88 BL	546d88

0x45cf8c LDR	X3, [SP, #136]

0x45cf90 ORR	X13, XZR, X0

0x45cf94 LDP	X8, X2, [SP, #152]

0x45cf98 LDP	X6, X10, [SP, #168]

0x45cf9c LDP	X12, X7, [SP, #320]

0x45cfa0 LDR	X11, [SP, #184]

0x45cfa4 LDR	X9, [SP, #240]

0x45cfa8 B	45bd3c

0x45cfac ORR	X0, XZR, X2

0x45cfb0 MOVZ	X1, #8

0x45cfb4 STR	X2, [SP, #136]

0x45cfb8 STP	X3, X8, [SP, #152]

0x45cfbc STP	X6, X10, [SP, #168]

0x45cfc0 STR	X11, [SP, #184]

0x45cfc4 STR	X9, [SP, #240]

0x45cfc8 STP	X12, X7, [SP, #320]

0x45cfcc BL	546d88

0x45cfd0 LDR	X2, [SP, #136]

0x45cfd4 ORR	X26, XZR, X0

0x45cfd8 LDP	X3, X8, [SP, #152]

0x45cfdc LDP	X6, X10, [SP, #168]

0x45cfe0 LDP	X12, X7, [SP, #320]

0x45cfe4 LDR	X11, [SP, #184]

0x45cfe8 LDR	X9, [SP, #240]

0x45cfec B	45bd30

Coverage (%)	Name	Source Location	Module
►98.76+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.24+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:1884	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

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Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	par_multi_interp.c:1737-1881
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1737,1746-1881.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 70% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 53.17 to 41.17 cycles (1.29x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 53.17 to 5.50 cycles (9.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 1008 bytes. The binary function is storing 896 bytes.

General properties

nb instructions	227
loop length	908
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

28.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	11.50	11.50	9.33	9.33	9.33	9.33	9.33	9.33	0.00	0.00	0.00	0.00	53.17	52.83	53.00	40.50	40.50
cycles	11.50	11.50	9.33	9.33	9.33	9.33	9.33	9.33	0.00	0.00	0.00	0.00	53.17	52.83	53.00	40.50	40.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	28.25
Overall L1	53.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 53.17 cycles. At this rate:

19% of peak load performance is reached (18.96 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (16.85 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 45bc60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #656]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X1, X11, [X0, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X1, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X2, X10, [X0, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X2, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X3, X20, [X0, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X3, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X4, X25, [X0, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X4, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X19, X5, [X0, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X5, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X24, X6, [X0, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X6, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X6, X7, [X0, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X7, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X0, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X9, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X12, X13, [X0, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X13, X12, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X14, X15, [X0, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STP X15, X14, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X16, X17, [X0, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X17, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X16, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X18, X21, [X0, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X21, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X18, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X28, X26, [X0, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X2, X23, [X0, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X8, [X0, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X26, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X3, X27, [X0, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X27, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X27, X30, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X7, X12, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X30, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X21, X1, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X1, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X9, X4, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X4, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X0, X5, [X0, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X0, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X5, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBNZ X2, 45cfac <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x134c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X26, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X0, 45cf6c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x130c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X13, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CBNZ X23, 45cf20 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x12c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X3, X22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 45cf00 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x12a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X13, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X8, X2, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X6, X10, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X11, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X7, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
MOVZ X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 546d88 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X15, X1, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ORR X22, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X4, X5, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X18, X6, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X14, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X3, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X8, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 45bdd0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x170>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X2, X1, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X0, XZR, X26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X14, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ W1, #255	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X15, X4, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X5, X3, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X8, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X18, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X6, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4108c0 <@plt_start@+0x140>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X15, X4, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X5, X3, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X8, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X6, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X16, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X16, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 45be18 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X2, X16, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X15, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ W1, #255	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X4, X5, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X3, X8, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X18, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X6, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4108c0 <@plt_start@+0x140>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X14, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X4, X5, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X3, X8, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X18, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X6, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STP X14, X15, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X4, X5, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X3, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X18, X6, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
BL 5499c0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 5499a0 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB X5, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X2, X15, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X9, X6, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
SDIV X3, X14, X0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
LDP X10, X11, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X18, X7, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X13, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
UBFM X1, X13, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X4, [X2, X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X8, X5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
STR X1, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X13, X14, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD X14, X8, X3, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
ADD X0, X3, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, X4, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X2, X0, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CSEL X4, X13, X2, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X4, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 45c864 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc04>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB X30, X24, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X16, X25, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X17, X5, X1,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X3, X5, X4,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X13, X8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X17, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X13, X30, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X17, X30, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X3, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
HINT #0																					N/A
ORR X0, XZR, X26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X15, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 546e20 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 546e20 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 546e20 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #368	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
B 546e20 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X13, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X8, X2, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X6, X10, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X11, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X7, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
B 45bd64 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x104>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X13, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X3, X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X2, X6, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X10, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X11, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X12, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X7, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 546d88 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X23, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X3, X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X2, X6, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X9, X12, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X10, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X11, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X7, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 45bd40 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X3, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X8, X2, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X6, X10, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X11, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X7, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
BL 546d88 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X13, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X8, X2, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X6, X10, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X12, X7, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X11, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 45bd3c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xdc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X2, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X3, X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X6, X10, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X11, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X7, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
BL 546d88 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X26, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X3, X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X6, X10, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X12, X7, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X11, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 45bd30 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	par_multi_interp.c:1737-1881
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1737,1746-1881.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 53.17 to 5.50 cycles (9.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 1008 bytes. The binary function is storing 896 bytes.

General properties

nb instructions	227
loop length	908
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

28.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	11.50	11.50	9.33	9.33	9.33	9.33	9.33	9.33	0.00	0.00	0.00	0.00	53.17	52.83	53.00	40.50	40.50
cycles	11.50	11.50	9.33	9.33	9.33	9.33	9.33	9.33	0.00	0.00	0.00	0.00	53.17	52.83	53.00	40.50	40.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	28.25
Overall L1	53.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 53.17 cycles. At this rate:

19% of peak load performance is reached (18.96 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (16.85 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 45bc60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #656]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X1, X11, [X0, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X1, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X2, X10, [X0, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X2, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X3, X20, [X0, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X3, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X4, X25, [X0, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X4, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X19, X5, [X0, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X5, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X24, X6, [X0, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X6, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X6, X7, [X0, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X7, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X0, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X9, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X12, X13, [X0, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X13, X12, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X14, X15, [X0, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STP X15, X14, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X16, X17, [X0, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X17, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X16, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X18, X21, [X0, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X21, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X18, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X28, X26, [X0, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X2, X23, [X0, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X8, [X0, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X26, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X3, X27, [X0, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X27, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X27, X30, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X7, X12, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X30, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X21, X1, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X1, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X9, X4, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X4, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X0, X5, [X0, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X0, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X5, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBNZ X2, 45cfac <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x134c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X26, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X0, 45cf6c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x130c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X13, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CBNZ X23, 45cf20 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x12c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X3, X22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 45cf00 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x12a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X13, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X8, X2, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X6, X10, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X11, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X7, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
MOVZ X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 546d88 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X15, X1, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ORR X22, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X4, X5, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X18, X6, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X14, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X3, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X8, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 45bdd0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x170>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X2, X1, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X0, XZR, X26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X14, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ W1, #255	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X15, X4, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X5, X3, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X8, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X18, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X6, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4108c0 <@plt_start@+0x140>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X15, X4, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X5, X3, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X8, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X6, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X16, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X16, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 45be18 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X2, X16, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X15, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ W1, #255	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X4, X5, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X3, X8, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X18, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X6, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4108c0 <@plt_start@+0x140>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X14, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X4, X5, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X3, X8, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X18, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X6, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STP X14, X15, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X4, X5, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X3, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X18, X6, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
BL 5499c0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 5499a0 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB X5, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X2, X15, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X9, X6, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
SDIV X3, X14, X0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
LDP X10, X11, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X18, X7, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X13, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
UBFM X1, X13, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X4, [X2, X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X8, X5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
STR X1, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X13, X14, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD X14, X8, X3, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
ADD X0, X3, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, X4, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X2, X0, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CSEL X4, X13, X2, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X4, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 45c864 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc04>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB X30, X24, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X16, X25, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X17, X5, X1,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X3, X5, X4,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X13, X8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X17, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X13, X30, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X17, X30, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X3, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
HINT #0																					N/A
ORR X0, XZR, X26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X15, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 546e20 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 546e20 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 546e20 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #368	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
B 546e20 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X13, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X8, X2, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X6, X10, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X11, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X7, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
B 45bd64 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x104>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X13, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X3, X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X2, X6, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X10, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X11, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X12, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X7, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 546d88 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X23, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X3, X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X2, X6, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X9, X12, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X10, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X11, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X7, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 45bd40 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X3, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X8, X2, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X6, X10, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X11, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X7, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
BL 546d88 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X13, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X8, X2, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X6, X10, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X12, X7, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X11, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 45bd3c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xdc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X2, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X3, X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X6, X10, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X11, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X7, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
BL 546d88 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X26, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X3, X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X6, X10, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X12, X7, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X11, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 45bd30 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGBuildMultipass._omp_fn.10–	1.28	0.21
▼Loop 856 - par_multi_interp.c:1774-1876 - exec–	0.25	0.03
▼Loop 861 - par_multi_interp.c:1811-1837 - exec–	0.75	0.09
○Loop 863 - par_multi_interp.c:1816-1822 - exec	0.00	0.00
○Loop 862 - par_multi_interp.c:1824-1830 - exec	0.00	0.00
○Loop 865 - par_multi_interp.c:1799-1803 - exec	0.28	0.03
○Loop 858 - par_multi_interp.c:1873-1874 - exec	0.00	0.00
○Loop 867 - par_multi_interp.c:1782-1787 - exec	0.00	0.00
○Loop 866 - par_multi_interp.c:1792-1797 - exec	0.00	0.00
▼Loop 859 - par_multi_interp.c:1840-1867 - exec–	0.00	0.00
○Loop 860 - par_multi_interp.c:1851-1860 - exec	0.00	0.00
○Loop 864 - par_multi_interp.c:1805-1809 - exec	0.00	0.00
○Loop 857 - par_multi_interp.c:1875-1876 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code