OV - exec - Function hypre_BoomerAMGCoarsenPMIS._omp

	Function: hypre_BoomerAMGCoarsenPMIS._omp_fn.2	Module: exec	Source: par_coarsen.c:2132-2136	Coverage (incl. loops): 0.70% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c: 2132 - 2136

--------------------------------------------------------------------------------

2132: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

2133:    for (i=0; i < S_diag_i[num_variables]; i++)

2134:    {

2135: #pragma omp atomic

2136:       measure_array_temp[S_diag_j[i]]++;

0x429520 STP	X29, X30, [SP, #976]!

0x429524 ADD	X29, SP, #0

0x429528 STP	X19, X20, [SP, #16]

0x42952c ORR	X20, XZR, X0

0x429530 LDR	X0, [X0]

0x429534 LDR	X1, [X20, #16]

0x429538 STR	X21, [SP, #32]

0x42953c LDR	X21, [X0, X1,LSL #3]

0x429540 BL	410930

0x429544 SBFM	X19, X0, #0, #31

0x429548 BL	410940

0x42954c SBFM	X4, X0, #0, #31

0x429550 SDIV	X3, X21, X19

0x429554 MSUB	X2, X3, X19, X21

0x429558 CMP	X4, X2

0x42955c B.LT	4296a8

(203) 0x429560 MADD	X6, X3, X4, X2

(203) 0x429564 ADD	X7, X3, X6

(203) 0x429568 CMP	X6, X7

(203) 0x42956c B.GE	429698

(203) 0x429570 LDR	X5, [X20, #8]

(203) 0x429574 MOVZ	X8, #1

(203) 0x429578 LDR	X9, [X20, #24]

(203) 0x42957c ADD	X0, X5, X6,LSL #3

(203) 0x429580 ADD	X10, X5, X7,LSL #3

(203) 0x429584 SUB	X11, X10, X0

(203) 0x429588 SUB	X12, X11, #8

(203) 0x42958c UBFM	X13, X12, #3, #63

(203) 0x429590 ADD	X14, X13, X8

(203) 0x429594 ANDS	X15, X14, #4224

(203) 0x429598 B.EQ	429628

(203) 0x42959c CMP	X15, X8

(203) 0x4295a0 B.EQ	429614

(203) 0x4295a4 CMP	X15, #2

(203) 0x4295a8 B.EQ	429608

(203) 0x4295ac CMP	X15, #3

(203) 0x4295b0 B.EQ	4295fc

(203) 0x4295b4 CMP	X15, #4

(203) 0x4295b8 B.EQ	4295f0

(203) 0x4295bc CMP	X15, #5

(203) 0x4295c0 B.EQ	4295e4

(203) 0x4295c4 CMP	X15, #6

(203) 0x4295c8 B.EQ	4295d8

(203) 0x4295cc LDR	X16, [X0], #8

(203) 0x4295d0 ADD	X17, X9, X16,LSL #3

(203) 0x4295d4 LDADD	X8, X1, [X17]

(203) 0x4295d8 LDR	X18, [X0], #8

(203) 0x4295dc ADD	X30, X9, X18,LSL #3

(203) 0x4295e0 LDADD	X8, X1, [X30]

(203) 0x4295e4 LDR	X20, [X0], #8

(203) 0x4295e8 ADD	X1, X9, X20,LSL #3

(203) 0x4295ec LDADD	X8, X1, [X1]

(203) 0x4295f0 LDR	X21, [X0], #8

(203) 0x4295f4 ADD	X19, X9, X21,LSL #3

(203) 0x4295f8 LDADD	X8, X1, [X19]

(203) 0x4295fc LDR	X4, [X0], #8

(203) 0x429600 ADD	X3, X9, X4,LSL #3

(203) 0x429604 LDADD	X8, X1, [X3]

(203) 0x429608 LDR	X2, [X0], #8

(203) 0x42960c ADD	X6, X9, X2,LSL #3

(203) 0x429610 LDADD	X8, X1, [X6]

(203) 0x429614 LDR	X7, [X0], #8

(203) 0x429618 ADD	X5, X9, X7,LSL #3

(203) 0x42961c LDADD	X8, X1, [X5]

(203) 0x429620 CMP	X10, X0

(203) 0x429624 B.EQ	429698

  (204) 0x429628 ORR	X11, XZR, X0

  (204) 0x42962c LDR	X12, [X11], #8

  (204) 0x429630 ADD	X13, X9, X12,LSL #3

  (204) 0x429634 LDADD	X8, X1, [X13]

  (204) 0x429638 LDR	X14, [X0, #8]

  (204) 0x42963c ADD	X15, X9, X14,LSL #3

  (204) 0x429640 LDADD	X8, X1, [X15]

  (204) 0x429644 LDR	X16, [X11, #8]

  (204) 0x429648 ADD	X17, X9, X16,LSL #3

  (204) 0x42964c LDADD	X8, X1, [X17]

  (204) 0x429650 LDR	X18, [X0, #24]

  (204) 0x429654 ADD	X30, X9, X18,LSL #3

  (204) 0x429658 LDADD	X8, X1, [X30]

  (204) 0x42965c LDR	X20, [X0, #32]

  (204) 0x429660 ADD	X1, X9, X20,LSL #3

  (204) 0x429664 LDADD	X8, X1, [X1]

  (204) 0x429668 LDR	X21, [X0, #40]

  (204) 0x42966c ADD	X19, X9, X21,LSL #3

  (204) 0x429670 LDADD	X8, X1, [X19]

  (204) 0x429674 LDR	X4, [X0, #48]

  (204) 0x429678 ADD	X3, X9, X4,LSL #3

  (204) 0x42967c LDADD	X8, X1, [X3]

  (204) 0x429680 LDR	X2, [X0, #56]

  (204) 0x429684 ADD	X6, X9, X2,LSL #3

  (204) 0x429688 LDADD	X8, X1, [X6]

  (204) 0x42968c ADD	X0, X0, #64

  (204) 0x429690 CMP	X10, X0

  (204) 0x429694 B.NE	429628

(203) 0x429698 LDR	X21, [SP, #32]

(203) 0x42969c LDP	X19, X20, [SP, #16]

(203) 0x4296a0 LDP	X29, X30, [SP], #48

(203) 0x4296a4 RET

(203) 0x4296a8 ADD	X3, X3, #1

(203) 0x4296ac MOVZ	X2, #0

(203) 0x4296b0 B	429560

0x4296b4 HINT	#0

0x4296b8 HINT	#0

0x4296bc HINT	#0

Coverage (%)	Name	Source Location	Module
►98.86+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.08+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	hypre_BoomerAMGCoarsenPMIS	par_coarsen.c:2132	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:612	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	par_coarsen.c:2132-2136
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2132-2136.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 71% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 20.00 to 10.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 24 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	19
loop length	76
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50
cycles	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	2.00
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

1% of peak load performance is reached (1.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 429520

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X0, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X21, [X0, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 410930 <@plt_start@+0x1b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X19, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
BL 410940 <@plt_start@+0x1c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X4, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SDIV X3, X21, X19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
MSUB X2, X3, X19, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP X4, X2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 4296a8 <hypre_BoomerAMGCoarsenPMIS._omp_fn.2+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	par_coarsen.c:2132-2136
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2132-2136.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 24 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	19
loop length	76
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50
cycles	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	2.00
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

1% of peak load performance is reached (1.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 429520

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X0, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X21, [X0, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 410930 <@plt_start@+0x1b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X19, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
BL 410940 <@plt_start@+0x1c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X4, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SDIV X3, X21, X19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
MSUB X2, X3, X19, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP X4, X2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 4296a8 <hypre_BoomerAMGCoarsenPMIS._omp_fn.2+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGCoarsenPMIS._omp_fn.2–	0.70	0.11
▼Loop 203 - par_coarsen.c:2132-2136 - exec–	0.00	0.00
○Loop 204 - par_coarsen.c:2135-2136 - exec	0.70	0.09

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code