OV - exec - Function hypre_BoomerAMGCoarsenPMIS._omp

	Function: hypre_BoomerAMGCoarsenPMIS._omp_fn.7	Module: exec	Source: par_coarsen.c:2435-2477 [...]	Coverage (incl. loops): 0.61% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c: 2435 - 2477

--------------------------------------------------------------------------------

2435: #pragma omp parallel for private(ig, i, jS, j) HYPRE_SMP_SCHEDULE

[...]

2446:        if(measure_array[i]<1.) CF_marker[i]= F_PT;

[...]

2453:        if (CF_marker[i] > 0) CF_marker[i] = C_PT;

[...]

2465: 	 for (jS = S_diag_i[i]; jS < S_diag_i[i+1]; jS++)

2466:          {

2467: 	   /* j is the column number, or the local number of the point influencing i */

2468: 	   j = S_diag_j[jS];

2469: 	   if (CF_marker[j] > 0) /* j is a C-point */

2470: 	     CF_marker[i] = F_PT;

2471: 	 }

2472: 	 /* now the external part */

2473: 	 for (jS = S_offd_i[i]; jS < S_offd_i[i+1]; jS++)

2474: 	 {

2475: 	   j = S_offd_j[jS];

2476: 	   if (CF_marker_offd[j] > 0) /* j is a C-point */

2477: 	     CF_marker[i] = F_PT;

0x428384 STP	X29, X30, [SP, #976]!

0x428388 ADD	X29, SP, #0

0x42838c STP	X19, X20, [SP, #16]

0x428390 ORR	X20, XZR, X0

0x428394 LDR	X0, [X0, #64]

0x428398 STR	X21, [SP, #32]

0x42839c LDR	X21, [X0]

0x4283a0 BL	410930

0x4283a4 SBFM	X19, X0, #0, #31

0x4283a8 BL	410940

0x4283ac SBFM	X1, X0, #0, #31

0x4283b0 SDIV	X7, X21, X19

0x4283b4 MSUB	X2, X7, X19, X21

0x4283b8 CMP	X1, X2

0x4283bc B.LT	4284ec

0x4283c0 MADD	X3, X7, X1, X2

0x4283c4 ADD	X4, X7, X3

0x4283c8 CMP	X3, X4

0x4283cc B.GE	4284cc

0x4283d0 LDP	X13, X5, [X20, #48]

0x4283d4 FMOV	D31, #1.0000000

0x4283d8 MOVN	X8, #0

0x4283dc MOVZ	X15, #1

0x4283e0 LDP	X17, X11, [X20]

0x4283e4 ADD	X1, X5, X3,LSL #3

0x4283e8 LDP	X16, X10, [X20, #16]

0x4283ec ADD	X7, X5, X4,LSL #3

0x4283f0 LDP	X3, X9, [X20, #32]

0x4283f4 B	428414

        (181) 0x4283f8 LDR	X12, [X3, X18]

        (181) 0x4283fc CMP	X12, #0

        (181) 0x428400 B.LE	428430

        (181) 0x428404 STR	X15, [X3, X18]

        (181) 0x428408 ADD	X1, X1, #8

        (181) 0x42840c CMP	X7, X1

        (181) 0x428410 B.EQ	4284cc

        (181) 0x428414 LDR	X6, [X1]

        (181) 0x428418 UBFM	X18, X6, #61, #60

        (181) 0x42841c ADD	X30, X3, X6,LSL #3

        (181) 0x428420 LDR	D30, [X13, X18]

        (181) 0x428424 FCMPE	D30, D31

        (181) 0x428428 B.GE	4283f8

      (180) 0x42842c STR	X8, [X3, X18]

      (180) 0x428430 ADD	X14, X18, #8

      (180) 0x428434 LDR	X0, [X17, X18]

      (180) 0x428438 ADD	X20, X17, X14

      (180) 0x42843c LDR	X2, [X17, X14]

      (180) 0x428440 CMP	X0, X2

      (180) 0x428444 B.GE	42846c

    (178) 0x428448 LDR	X21, [X11, X0,LSL #3]

    (178) 0x42844c LDR	X19, [X3, X21,LSL #3]

    (178) 0x428450 CMP	X19, #0

    (178) 0x428454 B.LE	4284dc

    (178) 0x428458 STR	X8, [X30]

    (178) 0x42845c ADD	X0, X0, #1

    (178) 0x428460 LDR	X2, [X20]

    (178) 0x428464 CMP	X2, X0

    (178) 0x428468 B.GT	428448

      (180) 0x42846c LDR	X12, [X16, X18]

      (180) 0x428470 ADD	X6, X16, X14

      (180) 0x428474 LDR	X5, [X16, X14]

      (180) 0x428478 CMP	X12, X5

      (180) 0x42847c B.GE	428408

        (182) 0x428480 LDR	X4, [X10, X12,LSL #3]

        (182) 0x428484 LDR	X18, [X9, X4,LSL #3]

        (182) 0x428488 CMP	X18, #0

        (182) 0x42848c B.LE	4284b4

        (183) 0x428490 STR	X8, [X30]

        (183) 0x428494 ADD	X12, X12, #1

        (183) 0x428498 LDR	X5, [X6]

        (183) 0x42849c CMP	X12, X5

        (183) 0x4284a0 B.GE	428408

        (183) 0x4284a4 LDR	X4, [X10, X12,LSL #3]

        (183) 0x4284a8 LDR	X18, [X9, X4,LSL #3]

        (183) 0x4284ac CMP	X18, #0

        (183) 0x4284b0 B.GT	428490

        (182) 0x4284b4 ADD	X12, X12, #1

        (182) 0x4284b8 CMP	X12, X5

        (182) 0x4284bc B.LT	428480

      (180) 0x4284c0 ADD	X1, X1, #8

      (180) 0x4284c4 CMP	X7, X1

      (180) 0x4284c8 B.NE	428414

(179) 0x4284cc LDR	X21, [SP, #32]

(179) 0x4284d0 LDP	X19, X20, [SP, #16]

(179) 0x4284d4 LDP	X29, X30, [SP], #48

(179) 0x4284d8 RET

  (177) 0x4284dc ADD	X0, X0, #1

  (177) 0x4284e0 CMP	X0, X2

  (177) 0x4284e4 B.LT	428448

  (177) 0x4284e8 B	42846c

0x4284ec ADD	X7, X7, #1

0x4284f0 MOVZ	X2, #0

0x4284f4 B	4283c0

0x4284f8 HINT	#0

0x4284fc HINT	#0

Coverage (%)	Name	Source Location	Module
►99.03+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	par_coarsen.c:2435-2477
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2435,2446,2453,2465-2477.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 69% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 80 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	34
loop length	136
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.00	3.00	3.17	3.25	3.17	3.17	3.17	3.08	0.25	0.25	0.25	0.25	3.17	2.83	3.00	1.50	1.50
cycles	3.00	3.00	3.17	3.25	3.17	3.17	3.17	3.08	0.25	0.25	0.25	0.25	3.17	2.83	3.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	4.00
Overall L1	5.00-20.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

4% of peak load performance is reached (4.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 428384

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X0, [X0, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X21, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 410930 <@plt_start@+0x1b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X19, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
BL 410940 <@plt_start@+0x1c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X1, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
SDIV X7, X21, X19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MSUB X2, X7, X19, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
CMP X1, X2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 4284ec <hypre_BoomerAMGCoarsenPMIS._omp_fn.7+0x168>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X3, X7, X1, X2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
ADD X4, X7, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X3, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4284cc <hypre_BoomerAMGCoarsenPMIS._omp_fn.7+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X13, X5, [X20, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
FMOV D31, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MOVN X8, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ X15, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X17, X11, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
ADD X1, X5, X3,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X16, X10, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
ADD X7, X5, X4,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X3, X9, [X20, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
B 428414 <hypre_BoomerAMGCoarsenPMIS._omp_fn.7+0x90>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X7, X7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ X2, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 4283c0 <hypre_BoomerAMGCoarsenPMIS._omp_fn.7+0x3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	par_coarsen.c:2435-2477
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2435,2446,2453,2465-2477.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 69% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 80 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	34
loop length	136
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.00	3.00	3.17	3.25	3.17	3.17	3.17	3.08	0.25	0.25	0.25	0.25	3.17	2.83	3.00	1.50	1.50
cycles	3.00	3.00	3.17	3.25	3.17	3.17	3.17	3.08	0.25	0.25	0.25	0.25	3.17	2.83	3.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	4.00
Overall L1	5.00-20.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

4% of peak load performance is reached (4.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 428384

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X0, [X0, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X21, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 410930 <@plt_start@+0x1b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X19, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
BL 410940 <@plt_start@+0x1c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X1, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
SDIV X7, X21, X19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MSUB X2, X7, X19, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
CMP X1, X2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 4284ec <hypre_BoomerAMGCoarsenPMIS._omp_fn.7+0x168>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X3, X7, X1, X2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
ADD X4, X7, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X3, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4284cc <hypre_BoomerAMGCoarsenPMIS._omp_fn.7+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X13, X5, [X20, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
FMOV D31, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MOVN X8, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ X15, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X17, X11, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
ADD X1, X5, X3,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X16, X10, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
ADD X7, X5, X4,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X3, X9, [X20, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
B 428414 <hypre_BoomerAMGCoarsenPMIS._omp_fn.7+0x90>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X7, X7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ X2, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 4283c0 <hypre_BoomerAMGCoarsenPMIS._omp_fn.7+0x3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGCoarsenPMIS._omp_fn.7–	0.61	0.10
▼Loop 179 - par_coarsen.c:2435-2477 - exec–	0.00	0.00
▼Loop 177 - par_coarsen.c:2446-2477 - exec–	0.04	0.01
▼Loop 178 - par_coarsen.c:2446-2477 - exec–	0.52	0.06
▼Loop 180 - par_coarsen.c:2446-2477 - exec–	0.02	0.01
○Loop 181 - par_coarsen.c:2446-2453 - exec	0.03	0.01
○Loop 183 - par_coarsen.c:2473-2477 - exec	0.00	0.00
○Loop 182 - par_coarsen.c:2473-2476 - exec	0.00	0.00

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ASM code

Vectorization

Details

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code