OV - exec - Function hypre_BoomerAMGCoarsenPMIS._omp

	Function: hypre_BoomerAMGCoarsenPMIS._omp_fn.4	Module: exec	Source: par_coarsen.c:2327-2334	Coverage (incl. loops): 0.07% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c: 2327 - 2334

--------------------------------------------------------------------------------

2327: #pragma omp parallel for private(ig, i) HYPRE_SMP_SCHEDULE

2328: #endif

2329:         for (ig = 0; ig < graph_size; ig++)

2330:         {

2331:            i = graph_array[ig];

2332:            if (measure_array[i] > 1)

2333:            {

2334:               CF_marker[i] = 1;

0x428120 STP	X29, X30, [SP, #976]!

0x428124 ADD	X29, SP, #0

0x428128 STP	X19, X20, [SP, #16]

0x42812c ORR	X20, XZR, X0

0x428130 LDR	X0, [X0, #24]

0x428134 STR	X21, [SP, #32]

0x428138 LDR	X21, [X0]

0x42813c BL	410930

0x428140 SBFM	X19, X0, #0, #31

0x428144 BL	410940

0x428148 SBFM	X1, X0, #0, #31

0x42814c SDIV	X3, X21, X19

0x428150 MSUB	X2, X3, X19, X21

0x428154 CMP	X1, X2

0x428158 B.LT	428378

(175) 0x42815c MADD	X7, X3, X1, X2

(175) 0x428160 ADD	X8, X3, X7

(175) 0x428164 CMP	X7, X8

(175) 0x428168 B.GE	428368

(175) 0x42816c LDR	X6, [X20, #16]

(175) 0x428170 MOVZ	X5, #1

(175) 0x428174 FMOV	D31, #1.0000000

(175) 0x428178 LDP	X4, X9, [X20]

(175) 0x42817c ADD	X0, X6, X7,LSL #3

(175) 0x428180 ADD	X10, X6, X8,LSL #3

(175) 0x428184 SUB	X11, X10, X0

(175) 0x428188 SUB	X12, X11, #8

(175) 0x42818c UBFM	X13, X12, #3, #63

(175) 0x428190 ADD	X14, X13, X5

(175) 0x428194 ANDS	X15, X14, #4224

(175) 0x428198 B.EQ	428298

(175) 0x42819c CMP	X15, X5

(175) 0x4281a0 B.EQ	428274

(175) 0x4281a4 CMP	X15, #2

(175) 0x4281a8 B.EQ	428258

(175) 0x4281ac CMP	X15, #3

(175) 0x4281b0 B.EQ	42823c

(175) 0x4281b4 CMP	X15, #4

(175) 0x4281b8 B.EQ	428220

(175) 0x4281bc CMP	X15, #5

(175) 0x4281c0 B.EQ	428204

(175) 0x4281c4 CMP	X15, #6

(175) 0x4281c8 B.EQ	4281e8

(175) 0x4281cc LDR	X16, [X0]

(175) 0x4281d0 UBFM	X17, X16, #61, #60

(175) 0x4281d4 LDR	D21, [X9, X17]

(175) 0x4281d8 FCMPE	D21, D31

(175) 0x4281dc B.LS	4281e4

(175) 0x4281e0 STR	X5, [X4, X17]

(175) 0x4281e4 ADD	X0, X0, #8

(175) 0x4281e8 LDR	X18, [X0]

(175) 0x4281ec UBFM	X30, X18, #61, #60

(175) 0x4281f0 LDR	D20, [X9, X30]

(175) 0x4281f4 FCMPE	D20, D31

(175) 0x4281f8 B.LS	428200

(175) 0x4281fc STR	X5, [X4, X30]

(175) 0x428200 ADD	X0, X0, #8

(175) 0x428204 LDR	X20, [X0]

(175) 0x428208 UBFM	X21, X20, #61, #60

(175) 0x42820c LDR	D19, [X9, X21]

(175) 0x428210 FCMPE	D19, D31

(175) 0x428214 B.LS	42821c

(175) 0x428218 STR	X5, [X4, X21]

(175) 0x42821c ADD	X0, X0, #8

(175) 0x428220 LDR	X19, [X0]

(175) 0x428224 UBFM	X1, X19, #61, #60

(175) 0x428228 LDR	D18, [X9, X1]

(175) 0x42822c FCMPE	D18, D31

(175) 0x428230 B.LS	428238

(175) 0x428234 STR	X5, [X4, X1]

(175) 0x428238 ADD	X0, X0, #8

(175) 0x42823c LDR	X3, [X0]

(175) 0x428240 UBFM	X2, X3, #61, #60

(175) 0x428244 LDR	D17, [X9, X2]

(175) 0x428248 FCMPE	D17, D31

(175) 0x42824c B.LS	428254

(175) 0x428250 STR	X5, [X4, X2]

(175) 0x428254 ADD	X0, X0, #8

(175) 0x428258 LDR	X7, [X0]

(175) 0x42825c UBFM	X8, X7, #61, #60

(175) 0x428260 LDR	D16, [X9, X8]

(175) 0x428264 FCMPE	D16, D31

(175) 0x428268 B.LS	428270

(175) 0x42826c STR	X5, [X4, X8]

(175) 0x428270 ADD	X0, X0, #8

(175) 0x428274 LDR	X6, [X0]

(175) 0x428278 UBFM	X11, X6, #61, #60

(175) 0x42827c LDR	D7, [X9, X11]

(175) 0x428280 FCMPE	D7, D31

(175) 0x428284 B.LS	42828c

(175) 0x428288 STR	X5, [X4, X11]

(175) 0x42828c ADD	X0, X0, #8

(175) 0x428290 CMP	X10, X0

(175) 0x428294 B.EQ	428368

  (176) 0x428298 LDR	X12, [X0]

  (176) 0x42829c UBFM	X13, X12, #61, #60

  (176) 0x4282a0 LDR	D6, [X9, X13]

  (176) 0x4282a4 FCMPE	D6, D31

  (176) 0x4282a8 B.LS	4282b0

  (176) 0x4282ac STR	X5, [X4, X13]

  (176) 0x4282b0 LDR	X14, [X0, #8]

  (176) 0x4282b4 ADD	X0, X0, #8

  (176) 0x4282b8 UBFM	X15, X14, #61, #60

  (176) 0x4282bc LDR	D5, [X9, X15]

  (176) 0x4282c0 FCMPE	D5, D31

  (176) 0x4282c4 B.LS	4282cc

  (176) 0x4282c8 STR	X5, [X4, X15]

  (176) 0x4282cc LDR	X16, [X0, #8]

  (176) 0x4282d0 UBFM	X17, X16, #61, #60

  (176) 0x4282d4 LDR	D4, [X9, X17]

  (176) 0x4282d8 FCMPE	D4, D31

  (176) 0x4282dc B.LS	4282e4

  (176) 0x4282e0 STR	X5, [X4, X17]

  (176) 0x4282e4 LDR	X18, [X0, #16]

  (176) 0x4282e8 UBFM	X30, X18, #61, #60

  (176) 0x4282ec LDR	D3, [X9, X30]

  (176) 0x4282f0 FCMPE	D3, D31

  (176) 0x4282f4 B.LS	4282fc

  (176) 0x4282f8 STR	X5, [X4, X30]

  (176) 0x4282fc LDR	X20, [X0, #24]

  (176) 0x428300 UBFM	X21, X20, #61, #60

  (176) 0x428304 LDR	D2, [X9, X21]

  (176) 0x428308 FCMPE	D2, D31

  (176) 0x42830c B.LS	428314

  (176) 0x428310 STR	X5, [X4, X21]

  (176) 0x428314 LDR	X19, [X0, #32]

  (176) 0x428318 UBFM	X1, X19, #61, #60

  (176) 0x42831c LDR	D1, [X9, X1]

  (176) 0x428320 FCMPE	D1, D31

  (176) 0x428324 B.LS	42832c

  (176) 0x428328 STR	X5, [X4, X1]

  (176) 0x42832c LDR	X3, [X0, #40]

  (176) 0x428330 UBFM	X2, X3, #61, #60

  (176) 0x428334 LDR	D0, [X9, X2]

  (176) 0x428338 FCMPE	D0, D31

  (176) 0x42833c B.LS	428344

  (176) 0x428340 STR	X5, [X4, X2]

  (176) 0x428344 LDR	X7, [X0, #48]

  (176) 0x428348 UBFM	X8, X7, #61, #60

  (176) 0x42834c LDR	D30, [X9, X8]

  (176) 0x428350 FCMPE	D30, D31

  (176) 0x428354 B.LS	42835c

  (176) 0x428358 STR	X5, [X4, X8]

  (176) 0x42835c ADD	X0, X0, #56

  (176) 0x428360 CMP	X10, X0

  (176) 0x428364 B.NE	428298

(175) 0x428368 LDR	X21, [SP, #32]

(175) 0x42836c LDP	X19, X20, [SP, #16]

(175) 0x428370 LDP	X29, X30, [SP], #48

(175) 0x428374 RET

(175) 0x428378 ADD	X3, X3, #1

(175) 0x42837c MOVZ	X2, #0

(175) 0x428380 B	42815c

Coverage (%)	Name	Source Location	Module
►98.84+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.16+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	hypre_BoomerAMGCoarsenPMIS	par_coarsen.c:2338	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:612	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	par_coarsen.c:2327-2334
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2327-2334.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 68% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 20.00 to 10.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	15
loop length	60
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.83	1.50	1.67	1.50	1.50
cycles	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.83	1.50	1.67	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.88
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 428120

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [X0, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X21, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 410930 <@plt_start@+0x1b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X19, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (100.0%)
BL 410940 <@plt_start@+0x1c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X1, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SDIV X3, X21, X19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
MSUB X2, X3, X19, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP X1, X2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.LT 428378 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x258>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	par_coarsen.c:2327-2334
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2327-2334.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	15
loop length	60
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.83	1.50	1.67	1.50	1.50
cycles	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.83	1.50	1.67	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.88
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 428120

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [X0, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X21, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 410930 <@plt_start@+0x1b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X19, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (100.0%)
BL 410940 <@plt_start@+0x1c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X1, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SDIV X3, X21, X19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
MSUB X2, X3, X19, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP X1, X2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.LT 428378 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x258>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGCoarsenPMIS._omp_fn.4–	0.07	0.01
▼Loop 175 - par_coarsen.c:2327-2334 - exec–	0.00	0.00
○Loop 176 - par_coarsen.c:2332-2334 - exec	0.07	0.01

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code