OV - exec - Function hypre_BoomerAMGCoarsenPMIS._omp

	Function: hypre_BoomerAMGCoarsenPMIS._omp_fn.6	Module: exec	Source: par_coarsen.c:2354-2381	Coverage (incl. loops): 1.00% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c: 2354 - 2381

--------------------------------------------------------------------------------

2354: #pragma omp parallel for private(ig, i, jS, j, jj) HYPRE_SMP_SCHEDULE

2355: #endif

2356:         for (ig = 0; ig < graph_size; ig++)

2357:         {

2358:            i = graph_array[ig];

2359:            if (measure_array[i] > 1)

2360:            {

2361:               for (jS = S_diag_i[i]; jS < S_diag_i[i+1]; jS++)

2362:               {

2363:                  j = S_diag_j[jS];

2364:                  if (measure_array[j] > 1)

2365:                  {

2366:                     if (measure_array[i] > measure_array[j])

2367:                        CF_marker[j] = 0;

2368:                     else if (measure_array[j] > measure_array[i])

2369:                        CF_marker[i] = 0;

2370:                  }

2371:               } /* for each local neighbor j of i */

2372:               for (jS = S_offd_i[i]; jS < S_offd_i[i+1]; jS++)

2373:               {

2374:                  jj = S_offd_j[jS];

2375:                  j = num_variables+jj;

2376:                  if (measure_array[j] > 1)

2377:                  {

2378:                     if (measure_array[i] > measure_array[j])

2379:                        CF_marker_offd[jj] = 0;

2380:                     else if (measure_array[j] > measure_array[i])

2381:                        CF_marker[i] = 0;

0x427d40 STP	X29, X30, [SP, #976]!

0x427d44 ADD	X29, SP, #0

0x427d48 STP	X19, X20, [SP, #16]

0x427d4c ORR	X19, XZR, X0

0x427d50 LDR	X0, [X0, #72]

0x427d54 STR	X21, [SP, #32]

0x427d58 LDR	X21, [X0]

0x427d5c BL	410930

0x427d60 SBFM	X20, X0, #0, #31

0x427d64 BL	410940

0x427d68 SBFM	X3, X0, #0, #31

0x427d6c SDIV	X10, X21, X20

0x427d70 MSUB	X1, X10, X20, X21

0x427d74 CMP	X3, X1

0x427d78 B.LT	427ea4

(169) 0x427d7c MADD	X4, X10, X3, X1

(169) 0x427d80 ADD	X5, X10, X4

(169) 0x427d84 CMP	X4, X5

(169) 0x427d88 B.GE	427e94

(169) 0x427d8c LDR	X6, [X19, #64]

(169) 0x427d90 FMOV	D31, #1.0000000

(169) 0x427d94 LDP	X14, X9, [X19]

(169) 0x427d98 LDP	X13, X8, [X19, #16]

(169) 0x427d9c ADD	X3, X6, X4,LSL #3

(169) 0x427da0 ADD	X16, X6, X5,LSL #3

(169) 0x427da4 LDP	X7, X11, [X19, #32]

(169) 0x427da8 LDP	X15, X2, [X19, #48]

(169) 0x427dac B	427dbc

  (170) 0x427db0 ADD	X3, X3, #8

  (170) 0x427db4 CMP	X16, X3

  (170) 0x427db8 B.EQ	427e94

  (170) 0x427dbc LDR	X12, [X3]

  (170) 0x427dc0 UBFM	X17, X12, #61, #60

  (170) 0x427dc4 LDR	D30, [X2, X17]

  (170) 0x427dc8 FCMPE	D30, D31

  (170) 0x427dcc B.LS	427db0

  (170) 0x427dd0 ADD	X18, X17, #8

  (170) 0x427dd4 LDR	X20, [X14, X17]

  (170) 0x427dd8 ADD	X30, X14, X18

  (170) 0x427ddc LDR	X21, [X14, X18]

  (170) 0x427de0 CMP	X20, X21

  (170) 0x427de4 B.LT	427e04

  (170) 0x427de8 B	427e34

    (172) 0x427dec B.GE	427df8

    (172) 0x427df0 STR	XZR, [X11, X17]

    (172) 0x427df4 LDR	X21, [X30]

    (172) 0x427df8 ADD	X20, X20, #1

    (172) 0x427dfc CMP	X20, X21

    (172) 0x427e00 B.GE	427e34

    (172) 0x427e04 LDR	X19, [X9, X20,LSL #3]

    (172) 0x427e08 UBFM	X0, X19, #61, #60

    (172) 0x427e0c LDR	D0, [X2, X0]

    (172) 0x427e10 FCMPE	D0, D31

    (172) 0x427e14 B.LS	427df8

    (172) 0x427e18 FCMPE	D30, D0

    (172) 0x427e1c B.LS	427dec

    (172) 0x427e20 STR	XZR, [X11, X0]

    (172) 0x427e24 ADD	X20, X20, #1

    (172) 0x427e28 LDR	X21, [X30]

    (172) 0x427e2c CMP	X20, X21

    (172) 0x427e30 B.LT	427e04

  (170) 0x427e34 LDR	X6, [X13, X17]

  (170) 0x427e38 ADD	X10, X13, X18

  (170) 0x427e3c LDR	X5, [X13, X18]

  (170) 0x427e40 CMP	X6, X5

  (170) 0x427e44 B.LT	427e6c

  (170) 0x427e48 B	427db0

    (171) 0x427e4c B.GE	427e60

    (171) 0x427e50 STR	XZR, [X11, X17]

    (171) 0x427e54 LDR	X5, [X10]

    (171) 0x427e58 HINT	#0

    (171) 0x427e5c HINT	#0

    (171) 0x427e60 ADD	X6, X6, #1

    (171) 0x427e64 CMP	X6, X5

    (171) 0x427e68 B.GE	427db0

    (171) 0x427e6c LDR	X1, [X8, X6,LSL #3]

    (171) 0x427e70 ADD	X4, X7, X1

    (171) 0x427e74 LDR	D29, [X2, X4,LSL #3]

    (171) 0x427e78 FCMPE	D29, D31

    (171) 0x427e7c B.LS	427e60

    (171) 0x427e80 FCMPE	D30, D29

    (171) 0x427e84 B.LS	427e4c

    (171) 0x427e88 STR	XZR, [X15, X1,LSL #3]

    (171) 0x427e8c LDR	X5, [X10]

    (171) 0x427e90 B	427e60

(169) 0x427e94 LDR	X21, [SP, #32]

(169) 0x427e98 LDP	X19, X20, [SP, #16]

(169) 0x427e9c LDP	X29, X30, [SP], #48

(169) 0x427ea0 RET

(169) 0x427ea4 ADD	X10, X10, #1

(169) 0x427ea8 MOVZ	X1, #0

(169) 0x427eac B	427d7c

Coverage (%)	Name	Source Location	Module
►99.25+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	par_coarsen.c:2354-2381
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2354-2381.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 68% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 20.00 to 10.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	15
loop length	60
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.83	1.50	1.67	1.50	1.50
cycles	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.83	1.50	1.67	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.88
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 427d40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [X0, #72]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X21, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 410930 <@plt_start@+0x1b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X20, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (100.0%)
BL 410940 <@plt_start@+0x1c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X3, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SDIV X10, X21, X20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
MSUB X1, X10, X20, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP X3, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.LT 427ea4 <hypre_BoomerAMGCoarsenPMIS._omp_fn.6+0x164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	par_coarsen.c:2354-2381
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2354-2381.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	15
loop length	60
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.83	1.50	1.67	1.50	1.50
cycles	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.83	1.50	1.67	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.88
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 427d40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [X0, #72]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X21, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 410930 <@plt_start@+0x1b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X20, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (100.0%)
BL 410940 <@plt_start@+0x1c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X3, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SDIV X10, X21, X20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
MSUB X1, X10, X20, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP X3, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.LT 427ea4 <hypre_BoomerAMGCoarsenPMIS._omp_fn.6+0x164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGCoarsenPMIS._omp_fn.6–	1.00	0.16
▼Loop 169 - par_coarsen.c:2354-2381 - exec–	0.00	0.00
▼Loop 170 - par_coarsen.c:2354-2381 - exec–	0.05	0.01
○Loop 172 - par_coarsen.c:2361-2369 - exec	0.95	0.12
○Loop 171 - par_coarsen.c:2372-2381 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code